2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
29 #include "intel_drv.h"
31 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
32 * them for both DP and FDI transports, allowing those ports to
33 * automatically adapt to HDMI connections as well
35 static const u32 hsw_ddi_translations_dp
[] = {
36 0x00FFFFFF, 0x0006000E, /* DP parameters */
37 0x00D75FFF, 0x0005000A,
38 0x00C30FFF, 0x00040006,
39 0x80AAAFFF, 0x000B0000,
40 0x00FFFFFF, 0x0005000A,
41 0x00D75FFF, 0x000C0004,
42 0x80C30FFF, 0x000B0000,
43 0x00FFFFFF, 0x00040006,
44 0x80D75FFF, 0x000B0000,
45 0x00FFFFFF, 0x00040006 /* HDMI parameters */
48 static const u32 hsw_ddi_translations_fdi
[] = {
49 0x00FFFFFF, 0x0007000E, /* FDI parameters */
50 0x00D75FFF, 0x000F000A,
51 0x00C30FFF, 0x00060006,
52 0x00AAAFFF, 0x001E0000,
53 0x00FFFFFF, 0x000F000A,
54 0x00D75FFF, 0x00160004,
55 0x00C30FFF, 0x001E0000,
56 0x00FFFFFF, 0x00060006,
57 0x00D75FFF, 0x001E0000,
58 0x00FFFFFF, 0x00040006 /* HDMI parameters */
61 static enum port
intel_ddi_get_encoder_port(struct intel_encoder
*intel_encoder
)
63 struct drm_encoder
*encoder
= &intel_encoder
->base
;
64 int type
= intel_encoder
->type
;
66 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
||
67 type
== INTEL_OUTPUT_HDMI
|| type
== INTEL_OUTPUT_UNKNOWN
) {
68 struct intel_digital_port
*intel_dig_port
=
69 enc_to_dig_port(encoder
);
70 return intel_dig_port
->port
;
72 } else if (type
== INTEL_OUTPUT_ANALOG
) {
76 DRM_ERROR("Invalid DDI encoder type %d\n", type
);
81 /* On Haswell, DDI port buffers must be programmed with correct values
82 * in advance. The buffer values are different for FDI and DP modes,
83 * but the HDMI/DVI fields are shared among those. So we program the DDI
84 * in either FDI or DP modes only, as HDMI connections will work with both
87 static void intel_prepare_ddi_buffers(struct drm_device
*dev
, enum port port
,
90 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 const u32
*ddi_translations
= ((use_fdi_mode
) ?
94 hsw_ddi_translations_fdi
:
95 hsw_ddi_translations_dp
);
97 DRM_DEBUG_DRIVER("Initializing DDI buffers for port %c in %s mode\n",
99 use_fdi_mode
? "FDI" : "DP");
101 WARN((use_fdi_mode
&& (port
!= PORT_E
)),
102 "Programming port %c in FDI mode, this probably will not work.\n",
105 for (i
=0, reg
=DDI_BUF_TRANS(port
); i
< ARRAY_SIZE(hsw_ddi_translations_fdi
); i
++) {
106 I915_WRITE(reg
, ddi_translations
[i
]);
111 /* Program DDI buffers translations for DP. By default, program ports A-D in DP
112 * mode and port E for FDI.
114 void intel_prepare_ddi(struct drm_device
*dev
)
121 for (port
= PORT_A
; port
< PORT_E
; port
++)
122 intel_prepare_ddi_buffers(dev
, port
, false);
124 /* DDI E is the suggested one to work in FDI mode, so program is as such
125 * by default. It will have to be re-programmed in case a digital DP
126 * output will be detected on it
128 intel_prepare_ddi_buffers(dev
, PORT_E
, true);
131 static const long hsw_ddi_buf_ctl_values
[] = {
132 DDI_BUF_EMP_400MV_0DB_HSW
,
133 DDI_BUF_EMP_400MV_3_5DB_HSW
,
134 DDI_BUF_EMP_400MV_6DB_HSW
,
135 DDI_BUF_EMP_400MV_9_5DB_HSW
,
136 DDI_BUF_EMP_600MV_0DB_HSW
,
137 DDI_BUF_EMP_600MV_3_5DB_HSW
,
138 DDI_BUF_EMP_600MV_6DB_HSW
,
139 DDI_BUF_EMP_800MV_0DB_HSW
,
140 DDI_BUF_EMP_800MV_3_5DB_HSW
143 static void intel_wait_ddi_buf_idle(struct drm_i915_private
*dev_priv
,
146 uint32_t reg
= DDI_BUF_CTL(port
);
149 for (i
= 0; i
< 8; i
++) {
151 if (I915_READ(reg
) & DDI_BUF_IS_IDLE
)
154 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port
));
157 /* Starting with Haswell, different DDI ports can work in FDI mode for
158 * connection to the PCH-located connectors. For this, it is necessary to train
159 * both the DDI port and PCH receiver for the desired DDI buffer settings.
161 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
162 * please note that when FDI mode is active on DDI E, it shares 2 lines with
163 * DDI A (which is used for eDP)
166 void hsw_fdi_link_train(struct drm_crtc
*crtc
)
168 struct drm_device
*dev
= crtc
->dev
;
169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
170 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
171 u32 temp
, i
, rx_ctl_val
;
173 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
174 * mode set "sequence for CRT port" document:
175 * - TP1 to TP2 time with the default value
178 I915_WRITE(_FDI_RXA_MISC
, FDI_RX_PWRDN_LANE1_VAL(2) |
179 FDI_RX_PWRDN_LANE0_VAL(2) |
180 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
182 /* Enable the PCH Receiver FDI PLL */
183 rx_ctl_val
= FDI_RX_PLL_ENABLE
| FDI_RX_ENHANCE_FRAME_ENABLE
|
184 ((intel_crtc
->fdi_lanes
- 1) << 19);
185 if (dev_priv
->fdi_rx_polarity_reversed
)
186 rx_ctl_val
|= FDI_RX_POLARITY_REVERSED_LPT
;
187 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
188 POSTING_READ(_FDI_RXA_CTL
);
191 /* Switch from Rawclk to PCDclk */
192 rx_ctl_val
|= FDI_PCDCLK
;
193 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
195 /* Configure Port Clock Select */
196 I915_WRITE(PORT_CLK_SEL(PORT_E
), intel_crtc
->ddi_pll_sel
);
198 /* Start the training iterating through available voltages and emphasis,
199 * testing each value twice. */
200 for (i
= 0; i
< ARRAY_SIZE(hsw_ddi_buf_ctl_values
) * 2; i
++) {
201 /* Configure DP_TP_CTL with auto-training */
202 I915_WRITE(DP_TP_CTL(PORT_E
),
203 DP_TP_CTL_FDI_AUTOTRAIN
|
204 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
205 DP_TP_CTL_LINK_TRAIN_PAT1
|
208 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage */
209 I915_WRITE(DDI_BUF_CTL(PORT_E
),
211 ((intel_crtc
->fdi_lanes
- 1) << 1) |
212 hsw_ddi_buf_ctl_values
[i
/ 2]);
213 POSTING_READ(DDI_BUF_CTL(PORT_E
));
217 /* Program PCH FDI Receiver TU */
218 I915_WRITE(_FDI_RXA_TUSIZE1
, TU_SIZE(64));
220 /* Enable PCH FDI Receiver with auto-training */
221 rx_ctl_val
|= FDI_RX_ENABLE
| FDI_LINK_TRAIN_AUTO
;
222 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
223 POSTING_READ(_FDI_RXA_CTL
);
225 /* Wait for FDI receiver lane calibration */
228 /* Unset FDI_RX_MISC pwrdn lanes */
229 temp
= I915_READ(_FDI_RXA_MISC
);
230 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
231 I915_WRITE(_FDI_RXA_MISC
, temp
);
232 POSTING_READ(_FDI_RXA_MISC
);
234 /* Wait for FDI auto training time */
237 temp
= I915_READ(DP_TP_STATUS(PORT_E
));
238 if (temp
& DP_TP_STATUS_AUTOTRAIN_DONE
) {
239 DRM_DEBUG_KMS("FDI link training done on step %d\n", i
);
241 /* Enable normal pixel sending for FDI */
242 I915_WRITE(DP_TP_CTL(PORT_E
),
243 DP_TP_CTL_FDI_AUTOTRAIN
|
244 DP_TP_CTL_LINK_TRAIN_NORMAL
|
245 DP_TP_CTL_ENHANCED_FRAME_ENABLE
|
251 temp
= I915_READ(DDI_BUF_CTL(PORT_E
));
252 temp
&= ~DDI_BUF_CTL_ENABLE
;
253 I915_WRITE(DDI_BUF_CTL(PORT_E
), temp
);
254 POSTING_READ(DDI_BUF_CTL(PORT_E
));
256 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
257 temp
= I915_READ(DP_TP_CTL(PORT_E
));
258 temp
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
259 temp
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
260 I915_WRITE(DP_TP_CTL(PORT_E
), temp
);
261 POSTING_READ(DP_TP_CTL(PORT_E
));
263 intel_wait_ddi_buf_idle(dev_priv
, PORT_E
);
265 rx_ctl_val
&= ~FDI_RX_ENABLE
;
266 I915_WRITE(_FDI_RXA_CTL
, rx_ctl_val
);
267 POSTING_READ(_FDI_RXA_CTL
);
269 /* Reset FDI_RX_MISC pwrdn lanes */
270 temp
= I915_READ(_FDI_RXA_MISC
);
271 temp
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
272 temp
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
273 I915_WRITE(_FDI_RXA_MISC
, temp
);
274 POSTING_READ(_FDI_RXA_MISC
);
277 DRM_ERROR("FDI link training failed!\n");
280 /* WRPLL clock dividers */
281 struct wrpll_tmds_clock
{
283 u16 p
; /* Post divider */
284 u16 n2
; /* Feedback divider */
285 u16 r2
; /* Reference divider */
288 /* Table of matching values for WRPLL clocks programming for each frequency.
289 * The code assumes this table is sorted. */
290 static const struct wrpll_tmds_clock wrpll_tmds_clock_table
[] = {
305 {27027, 18, 100, 111},
333 {40541, 22, 147, 89},
343 {44900, 20, 108, 65},
359 {54054, 16, 173, 108},
411 {81081, 6, 100, 111},
456 {108108, 8, 173, 108},
463 {111264, 8, 150, 91},
507 {135250, 6, 167, 111},
530 {148352, 4, 100, 91},
552 {162162, 4, 131, 109},
560 {169000, 4, 104, 83},
607 {202000, 4, 112, 75},
609 {203000, 4, 146, 97},
666 static void intel_ddi_mode_set(struct drm_encoder
*encoder
,
667 struct drm_display_mode
*mode
,
668 struct drm_display_mode
*adjusted_mode
)
670 struct drm_crtc
*crtc
= encoder
->crtc
;
671 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
672 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
673 int port
= intel_ddi_get_encoder_port(intel_encoder
);
674 int pipe
= intel_crtc
->pipe
;
675 int type
= intel_encoder
->type
;
677 DRM_DEBUG_KMS("Preparing DDI mode for Haswell on port %c, pipe %c\n",
678 port_name(port
), pipe_name(pipe
));
680 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
681 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
683 intel_dp
->DP
= DDI_BUF_CTL_ENABLE
| DDI_BUF_EMP_400MV_0DB_HSW
;
684 switch (intel_dp
->lane_count
) {
686 intel_dp
->DP
|= DDI_PORT_WIDTH_X1
;
689 intel_dp
->DP
|= DDI_PORT_WIDTH_X2
;
692 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
695 intel_dp
->DP
|= DDI_PORT_WIDTH_X4
;
696 WARN(1, "Unexpected DP lane count %d\n",
697 intel_dp
->lane_count
);
701 if (intel_dp
->has_audio
) {
702 DRM_DEBUG_DRIVER("DP audio on pipe %c on DDI\n",
703 pipe_name(intel_crtc
->pipe
));
706 DRM_DEBUG_DRIVER("DP audio: write eld information\n");
707 intel_write_eld(encoder
, adjusted_mode
);
710 intel_dp_init_link_config(intel_dp
);
712 } else if (type
== INTEL_OUTPUT_HDMI
) {
713 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
715 if (intel_hdmi
->has_audio
) {
716 /* Proper support for digital audio needs a new logic
717 * and a new set of registers, so we leave it for future
720 DRM_DEBUG_DRIVER("HDMI audio on pipe %c on DDI\n",
721 pipe_name(intel_crtc
->pipe
));
724 DRM_DEBUG_DRIVER("HDMI audio: write eld information\n");
725 intel_write_eld(encoder
, adjusted_mode
);
728 intel_hdmi
->set_infoframes(encoder
, adjusted_mode
);
732 static struct intel_encoder
*
733 intel_ddi_get_crtc_encoder(struct drm_crtc
*crtc
)
735 struct drm_device
*dev
= crtc
->dev
;
736 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
737 struct intel_encoder
*intel_encoder
, *ret
= NULL
;
738 int num_encoders
= 0;
740 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
745 if (num_encoders
!= 1)
746 WARN(1, "%d encoders on crtc for pipe %d\n", num_encoders
,
753 void intel_ddi_put_crtc_pll(struct drm_crtc
*crtc
)
755 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
756 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
757 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
760 switch (intel_crtc
->ddi_pll_sel
) {
761 case PORT_CLK_SEL_SPLL
:
762 plls
->spll_refcount
--;
763 if (plls
->spll_refcount
== 0) {
764 DRM_DEBUG_KMS("Disabling SPLL\n");
765 val
= I915_READ(SPLL_CTL
);
766 WARN_ON(!(val
& SPLL_PLL_ENABLE
));
767 I915_WRITE(SPLL_CTL
, val
& ~SPLL_PLL_ENABLE
);
768 POSTING_READ(SPLL_CTL
);
771 case PORT_CLK_SEL_WRPLL1
:
772 plls
->wrpll1_refcount
--;
773 if (plls
->wrpll1_refcount
== 0) {
774 DRM_DEBUG_KMS("Disabling WRPLL 1\n");
775 val
= I915_READ(WRPLL_CTL1
);
776 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
777 I915_WRITE(WRPLL_CTL1
, val
& ~WRPLL_PLL_ENABLE
);
778 POSTING_READ(WRPLL_CTL1
);
781 case PORT_CLK_SEL_WRPLL2
:
782 plls
->wrpll2_refcount
--;
783 if (plls
->wrpll2_refcount
== 0) {
784 DRM_DEBUG_KMS("Disabling WRPLL 2\n");
785 val
= I915_READ(WRPLL_CTL2
);
786 WARN_ON(!(val
& WRPLL_PLL_ENABLE
));
787 I915_WRITE(WRPLL_CTL2
, val
& ~WRPLL_PLL_ENABLE
);
788 POSTING_READ(WRPLL_CTL2
);
793 WARN(plls
->spll_refcount
< 0, "Invalid SPLL refcount\n");
794 WARN(plls
->wrpll1_refcount
< 0, "Invalid WRPLL1 refcount\n");
795 WARN(plls
->wrpll2_refcount
< 0, "Invalid WRPLL2 refcount\n");
797 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_NONE
;
800 static void intel_ddi_calculate_wrpll(int clock
, int *p
, int *n2
, int *r2
)
804 for (i
= 0; i
< ARRAY_SIZE(wrpll_tmds_clock_table
); i
++)
805 if (clock
<= wrpll_tmds_clock_table
[i
].clock
)
808 if (i
== ARRAY_SIZE(wrpll_tmds_clock_table
))
811 *p
= wrpll_tmds_clock_table
[i
].p
;
812 *n2
= wrpll_tmds_clock_table
[i
].n2
;
813 *r2
= wrpll_tmds_clock_table
[i
].r2
;
815 if (wrpll_tmds_clock_table
[i
].clock
!= clock
)
816 DRM_INFO("WRPLL: using settings for %dKHz on %dKHz mode\n",
817 wrpll_tmds_clock_table
[i
].clock
, clock
);
819 DRM_DEBUG_KMS("WRPLL: %dKHz refresh rate with p=%d, n2=%d r2=%d\n",
820 clock
, *p
, *n2
, *r2
);
823 bool intel_ddi_pll_mode_set(struct drm_crtc
*crtc
, int clock
)
825 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
826 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
827 struct drm_encoder
*encoder
= &intel_encoder
->base
;
828 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
829 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
830 int type
= intel_encoder
->type
;
831 enum pipe pipe
= intel_crtc
->pipe
;
834 /* TODO: reuse PLLs when possible (compare values) */
836 intel_ddi_put_crtc_pll(crtc
);
838 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
839 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
841 switch (intel_dp
->link_bw
) {
842 case DP_LINK_BW_1_62
:
843 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_810
;
846 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_1350
;
849 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_LCPLL_2700
;
852 DRM_ERROR("Link bandwidth %d unsupported\n",
857 /* We don't need to turn any PLL on because we'll use LCPLL. */
860 } else if (type
== INTEL_OUTPUT_HDMI
) {
863 if (plls
->wrpll1_refcount
== 0) {
864 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
866 plls
->wrpll1_refcount
++;
868 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL1
;
869 } else if (plls
->wrpll2_refcount
== 0) {
870 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
872 plls
->wrpll2_refcount
++;
874 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_WRPLL2
;
876 DRM_ERROR("No WRPLLs available!\n");
880 WARN(I915_READ(reg
) & WRPLL_PLL_ENABLE
,
881 "WRPLL already enabled\n");
883 intel_ddi_calculate_wrpll(clock
, &p
, &n2
, &r2
);
885 val
= WRPLL_PLL_ENABLE
| WRPLL_PLL_SELECT_LCPLL_2700
|
886 WRPLL_DIVIDER_REFERENCE(r2
) | WRPLL_DIVIDER_FEEDBACK(n2
) |
887 WRPLL_DIVIDER_POST(p
);
889 } else if (type
== INTEL_OUTPUT_ANALOG
) {
890 if (plls
->spll_refcount
== 0) {
891 DRM_DEBUG_KMS("Using SPLL on pipe %c\n",
893 plls
->spll_refcount
++;
895 intel_crtc
->ddi_pll_sel
= PORT_CLK_SEL_SPLL
;
898 WARN(I915_READ(reg
) & SPLL_PLL_ENABLE
,
899 "SPLL already enabled\n");
901 val
= SPLL_PLL_ENABLE
| SPLL_PLL_FREQ_1350MHz
| SPLL_PLL_SSC
;
904 WARN(1, "Invalid DDI encoder type %d\n", type
);
908 I915_WRITE(reg
, val
);
914 void intel_ddi_set_pipe_settings(struct drm_crtc
*crtc
)
916 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
917 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
918 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
919 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
920 int type
= intel_encoder
->type
;
923 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
925 temp
= TRANS_MSA_SYNC_CLK
;
926 switch (intel_crtc
->bpp
) {
928 temp
|= TRANS_MSA_6_BPC
;
931 temp
|= TRANS_MSA_8_BPC
;
934 temp
|= TRANS_MSA_10_BPC
;
937 temp
|= TRANS_MSA_12_BPC
;
940 temp
|= TRANS_MSA_8_BPC
;
941 WARN(1, "%d bpp unsupported by DDI function\n",
944 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder
), temp
);
948 void intel_ddi_enable_pipe_func(struct drm_crtc
*crtc
)
950 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
951 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
952 struct drm_encoder
*encoder
= &intel_encoder
->base
;
953 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
954 enum pipe pipe
= intel_crtc
->pipe
;
955 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
956 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
957 int type
= intel_encoder
->type
;
960 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
961 temp
= TRANS_DDI_FUNC_ENABLE
;
962 temp
|= TRANS_DDI_SELECT_PORT(port
);
964 switch (intel_crtc
->bpp
) {
966 temp
|= TRANS_DDI_BPC_6
;
969 temp
|= TRANS_DDI_BPC_8
;
972 temp
|= TRANS_DDI_BPC_10
;
975 temp
|= TRANS_DDI_BPC_12
;
978 WARN(1, "%d bpp unsupported by transcoder DDI function\n",
982 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
983 temp
|= TRANS_DDI_PVSYNC
;
984 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
985 temp
|= TRANS_DDI_PHSYNC
;
987 if (cpu_transcoder
== TRANSCODER_EDP
) {
990 temp
|= TRANS_DDI_EDP_INPUT_A_ONOFF
;
993 temp
|= TRANS_DDI_EDP_INPUT_B_ONOFF
;
996 temp
|= TRANS_DDI_EDP_INPUT_C_ONOFF
;
1004 if (type
== INTEL_OUTPUT_HDMI
) {
1005 struct intel_hdmi
*intel_hdmi
= enc_to_intel_hdmi(encoder
);
1007 if (intel_hdmi
->has_hdmi_sink
)
1008 temp
|= TRANS_DDI_MODE_SELECT_HDMI
;
1010 temp
|= TRANS_DDI_MODE_SELECT_DVI
;
1012 } else if (type
== INTEL_OUTPUT_ANALOG
) {
1013 temp
|= TRANS_DDI_MODE_SELECT_FDI
;
1014 temp
|= (intel_crtc
->fdi_lanes
- 1) << 1;
1016 } else if (type
== INTEL_OUTPUT_DISPLAYPORT
||
1017 type
== INTEL_OUTPUT_EDP
) {
1018 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1020 temp
|= TRANS_DDI_MODE_SELECT_DP_SST
;
1022 switch (intel_dp
->lane_count
) {
1024 temp
|= TRANS_DDI_PORT_WIDTH_X1
;
1027 temp
|= TRANS_DDI_PORT_WIDTH_X2
;
1030 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
1033 temp
|= TRANS_DDI_PORT_WIDTH_X4
;
1034 WARN(1, "Unsupported lane count %d\n",
1035 intel_dp
->lane_count
);
1039 WARN(1, "Invalid encoder type %d for pipe %d\n",
1040 intel_encoder
->type
, pipe
);
1043 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder
), temp
);
1046 void intel_ddi_disable_transcoder_func(struct drm_i915_private
*dev_priv
,
1047 enum transcoder cpu_transcoder
)
1049 uint32_t reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1050 uint32_t val
= I915_READ(reg
);
1052 val
&= ~(TRANS_DDI_FUNC_ENABLE
| TRANS_DDI_PORT_MASK
);
1053 val
|= TRANS_DDI_PORT_NONE
;
1054 I915_WRITE(reg
, val
);
1057 bool intel_ddi_connector_get_hw_state(struct intel_connector
*intel_connector
)
1059 struct drm_device
*dev
= intel_connector
->base
.dev
;
1060 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1061 struct intel_encoder
*intel_encoder
= intel_connector
->encoder
;
1062 int type
= intel_connector
->base
.connector_type
;
1063 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1065 enum transcoder cpu_transcoder
;
1068 if (!intel_encoder
->get_hw_state(intel_encoder
, &pipe
))
1072 cpu_transcoder
= TRANSCODER_EDP
;
1074 cpu_transcoder
= (enum transcoder
) pipe
;
1076 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1078 switch (tmp
& TRANS_DDI_MODE_SELECT_MASK
) {
1079 case TRANS_DDI_MODE_SELECT_HDMI
:
1080 case TRANS_DDI_MODE_SELECT_DVI
:
1081 return (type
== DRM_MODE_CONNECTOR_HDMIA
);
1083 case TRANS_DDI_MODE_SELECT_DP_SST
:
1084 if (type
== DRM_MODE_CONNECTOR_eDP
)
1086 case TRANS_DDI_MODE_SELECT_DP_MST
:
1087 return (type
== DRM_MODE_CONNECTOR_DisplayPort
);
1089 case TRANS_DDI_MODE_SELECT_FDI
:
1090 return (type
== DRM_MODE_CONNECTOR_VGA
);
1097 bool intel_ddi_get_hw_state(struct intel_encoder
*encoder
,
1100 struct drm_device
*dev
= encoder
->base
.dev
;
1101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1102 enum port port
= intel_ddi_get_encoder_port(encoder
);
1106 tmp
= I915_READ(DDI_BUF_CTL(port
));
1108 if (!(tmp
& DDI_BUF_CTL_ENABLE
))
1111 if (port
== PORT_A
) {
1112 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
1114 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
1115 case TRANS_DDI_EDP_INPUT_A_ON
:
1116 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
1119 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
1122 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
1129 for (i
= TRANSCODER_A
; i
<= TRANSCODER_C
; i
++) {
1130 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(i
));
1132 if ((tmp
& TRANS_DDI_PORT_MASK
)
1133 == TRANS_DDI_SELECT_PORT(port
)) {
1140 DRM_DEBUG_KMS("No pipe for ddi port %i found\n", port
);
1145 static uint32_t intel_ddi_get_crtc_pll(struct drm_i915_private
*dev_priv
,
1150 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1154 if (cpu_transcoder
== TRANSCODER_EDP
) {
1157 temp
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1158 temp
&= TRANS_DDI_PORT_MASK
;
1160 for (i
= PORT_B
; i
<= PORT_E
; i
++)
1161 if (temp
== TRANS_DDI_SELECT_PORT(i
))
1165 ret
= I915_READ(PORT_CLK_SEL(port
));
1167 DRM_DEBUG_KMS("Pipe %c connected to port %c using clock 0x%08x\n",
1168 pipe_name(pipe
), port_name(port
), ret
);
1173 void intel_ddi_setup_hw_pll_state(struct drm_device
*dev
)
1175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1177 struct intel_crtc
*intel_crtc
;
1179 for_each_pipe(pipe
) {
1181 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1183 if (!intel_crtc
->active
)
1186 intel_crtc
->ddi_pll_sel
= intel_ddi_get_crtc_pll(dev_priv
,
1189 switch (intel_crtc
->ddi_pll_sel
) {
1190 case PORT_CLK_SEL_SPLL
:
1191 dev_priv
->ddi_plls
.spll_refcount
++;
1193 case PORT_CLK_SEL_WRPLL1
:
1194 dev_priv
->ddi_plls
.wrpll1_refcount
++;
1196 case PORT_CLK_SEL_WRPLL2
:
1197 dev_priv
->ddi_plls
.wrpll2_refcount
++;
1203 void intel_ddi_enable_pipe_clock(struct intel_crtc
*intel_crtc
)
1205 struct drm_crtc
*crtc
= &intel_crtc
->base
;
1206 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1207 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1208 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1209 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
1211 if (cpu_transcoder
!= TRANSCODER_EDP
)
1212 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1213 TRANS_CLK_SEL_PORT(port
));
1216 void intel_ddi_disable_pipe_clock(struct intel_crtc
*intel_crtc
)
1218 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1219 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
1221 if (cpu_transcoder
!= TRANSCODER_EDP
)
1222 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder
),
1223 TRANS_CLK_SEL_DISABLED
);
1226 static void intel_ddi_pre_enable(struct intel_encoder
*intel_encoder
)
1228 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1229 struct drm_crtc
*crtc
= encoder
->crtc
;
1230 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1231 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1232 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1233 int type
= intel_encoder
->type
;
1235 if (type
== INTEL_OUTPUT_EDP
) {
1236 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1237 ironlake_edp_panel_vdd_on(intel_dp
);
1238 ironlake_edp_panel_on(intel_dp
);
1239 ironlake_edp_panel_vdd_off(intel_dp
, true);
1242 WARN_ON(intel_crtc
->ddi_pll_sel
== PORT_CLK_SEL_NONE
);
1243 I915_WRITE(PORT_CLK_SEL(port
), intel_crtc
->ddi_pll_sel
);
1245 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
) {
1246 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1248 intel_dp_sink_dpms(intel_dp
, DRM_MODE_DPMS_ON
);
1249 intel_dp_start_link_train(intel_dp
);
1250 intel_dp_complete_link_train(intel_dp
);
1254 static void intel_ddi_post_disable(struct intel_encoder
*intel_encoder
)
1256 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1257 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1258 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1259 int type
= intel_encoder
->type
;
1263 val
= I915_READ(DDI_BUF_CTL(port
));
1264 if (val
& DDI_BUF_CTL_ENABLE
) {
1265 val
&= ~DDI_BUF_CTL_ENABLE
;
1266 I915_WRITE(DDI_BUF_CTL(port
), val
);
1270 val
= I915_READ(DP_TP_CTL(port
));
1271 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1272 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1273 I915_WRITE(DP_TP_CTL(port
), val
);
1276 intel_wait_ddi_buf_idle(dev_priv
, port
);
1278 if (type
== INTEL_OUTPUT_EDP
) {
1279 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1280 ironlake_edp_panel_vdd_on(intel_dp
);
1281 ironlake_edp_panel_off(intel_dp
);
1284 I915_WRITE(PORT_CLK_SEL(port
), PORT_CLK_SEL_NONE
);
1287 static void intel_enable_ddi(struct intel_encoder
*intel_encoder
)
1289 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1290 struct drm_device
*dev
= encoder
->dev
;
1291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1292 enum port port
= intel_ddi_get_encoder_port(intel_encoder
);
1293 int type
= intel_encoder
->type
;
1295 if (type
== INTEL_OUTPUT_HDMI
) {
1296 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1297 * are ignored so nothing special needs to be done besides
1298 * enabling the port.
1300 I915_WRITE(DDI_BUF_CTL(port
), DDI_BUF_CTL_ENABLE
);
1301 } else if (type
== INTEL_OUTPUT_EDP
) {
1302 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1304 ironlake_edp_backlight_on(intel_dp
);
1308 static void intel_disable_ddi(struct intel_encoder
*intel_encoder
)
1310 struct drm_encoder
*encoder
= &intel_encoder
->base
;
1311 int type
= intel_encoder
->type
;
1313 if (type
== INTEL_OUTPUT_EDP
) {
1314 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1316 ironlake_edp_backlight_off(intel_dp
);
1320 int intel_ddi_get_cdclk_freq(struct drm_i915_private
*dev_priv
)
1322 if (I915_READ(HSW_FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
1324 else if ((I915_READ(LCPLL_CTL
) & LCPLL_CLK_FREQ_MASK
) ==
1327 else if (IS_ULT(dev_priv
->dev
))
1333 void intel_ddi_pll_init(struct drm_device
*dev
)
1335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1336 uint32_t val
= I915_READ(LCPLL_CTL
);
1338 /* The LCPLL register should be turned on by the BIOS. For now let's
1339 * just check its state and print errors in case something is wrong.
1340 * Don't even try to turn it on.
1343 DRM_DEBUG_KMS("CDCLK running at %dMHz\n",
1344 intel_ddi_get_cdclk_freq(dev_priv
));
1346 if (val
& LCPLL_CD_SOURCE_FCLK
)
1347 DRM_ERROR("CDCLK source is not LCPLL\n");
1349 if (val
& LCPLL_PLL_DISABLE
)
1350 DRM_ERROR("LCPLL is disabled\n");
1353 void intel_ddi_prepare_link_retrain(struct drm_encoder
*encoder
)
1355 struct intel_digital_port
*intel_dig_port
= enc_to_dig_port(encoder
);
1356 struct intel_dp
*intel_dp
= &intel_dig_port
->dp
;
1357 struct drm_i915_private
*dev_priv
= encoder
->dev
->dev_private
;
1358 enum port port
= intel_dig_port
->port
;
1362 if (I915_READ(DP_TP_CTL(port
)) & DP_TP_CTL_ENABLE
) {
1363 val
= I915_READ(DDI_BUF_CTL(port
));
1364 if (val
& DDI_BUF_CTL_ENABLE
) {
1365 val
&= ~DDI_BUF_CTL_ENABLE
;
1366 I915_WRITE(DDI_BUF_CTL(port
), val
);
1370 val
= I915_READ(DP_TP_CTL(port
));
1371 val
&= ~(DP_TP_CTL_ENABLE
| DP_TP_CTL_LINK_TRAIN_MASK
);
1372 val
|= DP_TP_CTL_LINK_TRAIN_PAT1
;
1373 I915_WRITE(DP_TP_CTL(port
), val
);
1374 POSTING_READ(DP_TP_CTL(port
));
1377 intel_wait_ddi_buf_idle(dev_priv
, port
);
1380 val
= DP_TP_CTL_ENABLE
| DP_TP_CTL_MODE_SST
|
1381 DP_TP_CTL_LINK_TRAIN_PAT1
| DP_TP_CTL_SCRAMBLE_DISABLE
;
1382 if (intel_dp
->link_configuration
[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN
)
1383 val
|= DP_TP_CTL_ENHANCED_FRAME_ENABLE
;
1384 I915_WRITE(DP_TP_CTL(port
), val
);
1385 POSTING_READ(DP_TP_CTL(port
));
1387 intel_dp
->DP
|= DDI_BUF_CTL_ENABLE
;
1388 I915_WRITE(DDI_BUF_CTL(port
), intel_dp
->DP
);
1389 POSTING_READ(DDI_BUF_CTL(port
));
1394 void intel_ddi_fdi_disable(struct drm_crtc
*crtc
)
1396 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1397 struct intel_encoder
*intel_encoder
= intel_ddi_get_crtc_encoder(crtc
);
1400 intel_ddi_post_disable(intel_encoder
);
1402 val
= I915_READ(_FDI_RXA_CTL
);
1403 val
&= ~FDI_RX_ENABLE
;
1404 I915_WRITE(_FDI_RXA_CTL
, val
);
1406 val
= I915_READ(_FDI_RXA_MISC
);
1407 val
&= ~(FDI_RX_PWRDN_LANE1_MASK
| FDI_RX_PWRDN_LANE0_MASK
);
1408 val
|= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1409 I915_WRITE(_FDI_RXA_MISC
, val
);
1411 val
= I915_READ(_FDI_RXA_CTL
);
1413 I915_WRITE(_FDI_RXA_CTL
, val
);
1415 val
= I915_READ(_FDI_RXA_CTL
);
1416 val
&= ~FDI_RX_PLL_ENABLE
;
1417 I915_WRITE(_FDI_RXA_CTL
, val
);
1420 static void intel_ddi_hot_plug(struct intel_encoder
*intel_encoder
)
1422 struct intel_dp
*intel_dp
= enc_to_intel_dp(&intel_encoder
->base
);
1423 int type
= intel_encoder
->type
;
1425 if (type
== INTEL_OUTPUT_DISPLAYPORT
|| type
== INTEL_OUTPUT_EDP
)
1426 intel_dp_check_link_status(intel_dp
);
1429 static void intel_ddi_destroy(struct drm_encoder
*encoder
)
1431 /* HDMI has nothing special to destroy, so we can go with this. */
1432 intel_dp_encoder_destroy(encoder
);
1435 static bool intel_ddi_mode_fixup(struct drm_encoder
*encoder
,
1436 const struct drm_display_mode
*mode
,
1437 struct drm_display_mode
*adjusted_mode
)
1439 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
1440 int type
= intel_encoder
->type
;
1442 WARN(type
== INTEL_OUTPUT_UNKNOWN
, "mode_fixup() on unknown output!\n");
1444 if (type
== INTEL_OUTPUT_HDMI
)
1445 return intel_hdmi_mode_fixup(encoder
, mode
, adjusted_mode
);
1447 return intel_dp_mode_fixup(encoder
, mode
, adjusted_mode
);
1450 static const struct drm_encoder_funcs intel_ddi_funcs
= {
1451 .destroy
= intel_ddi_destroy
,
1454 static const struct drm_encoder_helper_funcs intel_ddi_helper_funcs
= {
1455 .mode_fixup
= intel_ddi_mode_fixup
,
1456 .mode_set
= intel_ddi_mode_set
,
1457 .disable
= intel_encoder_noop
,
1460 void intel_ddi_init(struct drm_device
*dev
, enum port port
)
1462 struct intel_digital_port
*intel_dig_port
;
1463 struct intel_encoder
*intel_encoder
;
1464 struct drm_encoder
*encoder
;
1465 struct intel_connector
*hdmi_connector
= NULL
;
1466 struct intel_connector
*dp_connector
= NULL
;
1468 intel_dig_port
= kzalloc(sizeof(struct intel_digital_port
), GFP_KERNEL
);
1469 if (!intel_dig_port
)
1472 dp_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1473 if (!dp_connector
) {
1474 kfree(intel_dig_port
);
1478 if (port
!= PORT_A
) {
1479 hdmi_connector
= kzalloc(sizeof(struct intel_connector
),
1481 if (!hdmi_connector
) {
1482 kfree(dp_connector
);
1483 kfree(intel_dig_port
);
1488 intel_encoder
= &intel_dig_port
->base
;
1489 encoder
= &intel_encoder
->base
;
1491 drm_encoder_init(dev
, encoder
, &intel_ddi_funcs
,
1492 DRM_MODE_ENCODER_TMDS
);
1493 drm_encoder_helper_add(encoder
, &intel_ddi_helper_funcs
);
1495 intel_encoder
->enable
= intel_enable_ddi
;
1496 intel_encoder
->pre_enable
= intel_ddi_pre_enable
;
1497 intel_encoder
->disable
= intel_disable_ddi
;
1498 intel_encoder
->post_disable
= intel_ddi_post_disable
;
1499 intel_encoder
->get_hw_state
= intel_ddi_get_hw_state
;
1501 intel_dig_port
->port
= port
;
1503 intel_dig_port
->hdmi
.sdvox_reg
= DDI_BUF_CTL(port
);
1505 intel_dig_port
->hdmi
.sdvox_reg
= 0;
1506 intel_dig_port
->dp
.output_reg
= DDI_BUF_CTL(port
);
1508 intel_encoder
->type
= INTEL_OUTPUT_UNKNOWN
;
1509 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1) | (1 << 2);
1510 intel_encoder
->cloneable
= false;
1511 intel_encoder
->hot_plug
= intel_ddi_hot_plug
;
1514 intel_hdmi_init_connector(intel_dig_port
, hdmi_connector
);
1515 intel_dp_init_connector(intel_dig_port
, dp_connector
);