1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include "drm_crtc_helper.h"
40 static int i915_modeset
= -1;
41 module_param_named(modeset
, i915_modeset
, int, 0400);
43 unsigned int i915_fbpercrtc
= 0;
44 module_param_named(fbpercrtc
, i915_fbpercrtc
, int, 0400);
46 int i915_panel_ignore_lid
= 0;
47 module_param_named(panel_ignore_lid
, i915_panel_ignore_lid
, int, 0600);
49 unsigned int i915_powersave
= 1;
50 module_param_named(powersave
, i915_powersave
, int, 0600);
52 unsigned int i915_semaphores
= 0;
53 module_param_named(semaphores
, i915_semaphores
, int, 0600);
55 unsigned int i915_enable_rc6
= 1;
56 module_param_named(i915_enable_rc6
, i915_enable_rc6
, int, 0600);
58 unsigned int i915_enable_fbc
= 0;
59 module_param_named(i915_enable_fbc
, i915_enable_fbc
, int, 0600);
61 unsigned int i915_lvds_downclock
= 0;
62 module_param_named(lvds_downclock
, i915_lvds_downclock
, int, 0400);
64 unsigned int i915_panel_use_ssc
= 1;
65 module_param_named(lvds_use_ssc
, i915_panel_use_ssc
, int, 0600);
67 int i915_vbt_sdvo_panel_type
= -1;
68 module_param_named(vbt_sdvo_panel_type
, i915_vbt_sdvo_panel_type
, int, 0600);
70 static bool i915_try_reset
= true;
71 module_param_named(reset
, i915_try_reset
, bool, 0600);
73 static struct drm_driver driver
;
74 extern int intel_agp_enabled
;
76 #define INTEL_VGA_DEVICE(id, info) { \
77 .class = PCI_CLASS_DISPLAY_VGA << 8, \
78 .class_mask = 0xff0000, \
81 .subvendor = PCI_ANY_ID, \
82 .subdevice = PCI_ANY_ID, \
83 .driver_data = (unsigned long) info }
85 static const struct intel_device_info intel_i830_info
= {
86 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1,
87 .has_overlay
= 1, .overlay_needs_physical
= 1,
90 static const struct intel_device_info intel_845g_info
= {
92 .has_overlay
= 1, .overlay_needs_physical
= 1,
95 static const struct intel_device_info intel_i85x_info
= {
96 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1,
97 .cursor_needs_physical
= 1,
98 .has_overlay
= 1, .overlay_needs_physical
= 1,
101 static const struct intel_device_info intel_i865g_info
= {
103 .has_overlay
= 1, .overlay_needs_physical
= 1,
106 static const struct intel_device_info intel_i915g_info
= {
107 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1,
108 .has_overlay
= 1, .overlay_needs_physical
= 1,
110 static const struct intel_device_info intel_i915gm_info
= {
111 .gen
= 3, .is_mobile
= 1,
112 .cursor_needs_physical
= 1,
113 .has_overlay
= 1, .overlay_needs_physical
= 1,
116 static const struct intel_device_info intel_i945g_info
= {
117 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1,
118 .has_overlay
= 1, .overlay_needs_physical
= 1,
120 static const struct intel_device_info intel_i945gm_info
= {
121 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1,
122 .has_hotplug
= 1, .cursor_needs_physical
= 1,
123 .has_overlay
= 1, .overlay_needs_physical
= 1,
127 static const struct intel_device_info intel_i965g_info
= {
128 .gen
= 4, .is_broadwater
= 1,
133 static const struct intel_device_info intel_i965gm_info
= {
134 .gen
= 4, .is_crestline
= 1,
135 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
140 static const struct intel_device_info intel_g33_info
= {
141 .gen
= 3, .is_g33
= 1,
142 .need_gfx_hws
= 1, .has_hotplug
= 1,
146 static const struct intel_device_info intel_g45_info
= {
147 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1,
148 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
152 static const struct intel_device_info intel_gm45_info
= {
153 .gen
= 4, .is_g4x
= 1,
154 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
155 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
160 static const struct intel_device_info intel_pineview_info
= {
161 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1,
162 .need_gfx_hws
= 1, .has_hotplug
= 1,
166 static const struct intel_device_info intel_ironlake_d_info
= {
168 .need_gfx_hws
= 1, .has_pipe_cxsr
= 1, .has_hotplug
= 1,
172 static const struct intel_device_info intel_ironlake_m_info
= {
173 .gen
= 5, .is_mobile
= 1,
174 .need_gfx_hws
= 1, .has_hotplug
= 1,
179 static const struct intel_device_info intel_sandybridge_d_info
= {
181 .need_gfx_hws
= 1, .has_hotplug
= 1,
186 static const struct intel_device_info intel_sandybridge_m_info
= {
187 .gen
= 6, .is_mobile
= 1,
188 .need_gfx_hws
= 1, .has_hotplug
= 1,
194 static const struct intel_device_info intel_ivybridge_d_info
= {
195 .is_ivybridge
= 1, .gen
= 7,
196 .need_gfx_hws
= 1, .has_hotplug
= 1,
201 static const struct intel_device_info intel_ivybridge_m_info
= {
202 .is_ivybridge
= 1, .gen
= 7, .is_mobile
= 1,
203 .need_gfx_hws
= 1, .has_hotplug
= 1,
204 .has_fbc
= 0, /* FBC is not enabled on Ivybridge mobile yet */
209 static const struct pci_device_id pciidlist
[] = { /* aka */
210 INTEL_VGA_DEVICE(0x3577, &intel_i830_info
), /* I830_M */
211 INTEL_VGA_DEVICE(0x2562, &intel_845g_info
), /* 845_G */
212 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info
), /* I855_GM */
213 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info
),
214 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info
), /* I865_G */
215 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info
), /* I915_G */
216 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info
), /* E7221_G */
217 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info
), /* I915_GM */
218 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info
), /* I945_G */
219 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info
), /* I945_GM */
220 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info
), /* I945_GME */
221 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info
), /* I946_GZ */
222 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info
), /* G35_G */
223 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info
), /* I965_Q */
224 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info
), /* I965_G */
225 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info
), /* Q35_G */
226 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info
), /* G33_G */
227 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info
), /* Q33_G */
228 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info
), /* I965_GM */
229 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info
), /* I965_GME */
230 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info
), /* GM45_G */
231 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info
), /* IGD_E_G */
232 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info
), /* Q45_G */
233 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info
), /* G45_G */
234 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info
), /* G41_G */
235 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info
), /* B43_G */
236 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info
), /* B43_G.1 */
237 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info
),
238 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info
),
239 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info
),
240 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info
),
241 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info
),
242 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info
),
243 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info
),
244 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info
),
245 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info
),
246 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info
),
247 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info
),
248 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info
), /* GT1 mobile */
249 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info
), /* GT2 mobile */
250 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info
), /* GT1 desktop */
251 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info
), /* GT2 desktop */
252 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info
), /* GT1 server */
256 #if defined(CONFIG_DRM_I915_KMS)
257 MODULE_DEVICE_TABLE(pci
, pciidlist
);
260 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
261 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
262 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
263 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
265 void intel_detect_pch (struct drm_device
*dev
)
267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
271 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
272 * make graphics device passthrough work easy for VMM, that only
273 * need to expose ISA bridge to let driver know the real hardware
274 * underneath. This is a requirement from virtualization team.
276 pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
278 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
280 id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
282 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
283 dev_priv
->pch_type
= PCH_IBX
;
284 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
285 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
286 dev_priv
->pch_type
= PCH_CPT
;
287 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
288 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
289 /* PantherPoint is CPT compatible */
290 dev_priv
->pch_type
= PCH_CPT
;
291 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
298 static void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
303 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
306 I915_WRITE_NOTRACE(FORCEWAKE
, 1);
307 POSTING_READ(FORCEWAKE
);
310 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1) == 0)
315 * Generally this is called implicitly by the register read function. However,
316 * if some sequence requires the GT to not power down then this function should
317 * be called at the beginning of the sequence followed by a call to
318 * gen6_gt_force_wake_put() at the end of the sequence.
320 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
322 WARN_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
324 /* Forcewake is atomic in case we get in here without the lock */
325 if (atomic_add_return(1, &dev_priv
->forcewake_count
) == 1)
326 __gen6_gt_force_wake_get(dev_priv
);
329 static void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
331 I915_WRITE_NOTRACE(FORCEWAKE
, 0);
332 POSTING_READ(FORCEWAKE
);
336 * see gen6_gt_force_wake_get()
338 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
340 WARN_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
342 if (atomic_dec_and_test(&dev_priv
->forcewake_count
))
343 __gen6_gt_force_wake_put(dev_priv
);
346 void __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
349 u32 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
350 while (fifo
< 20 && loop
--) {
352 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
356 static int i915_drm_freeze(struct drm_device
*dev
)
358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
360 drm_kms_helper_poll_disable(dev
);
362 pci_save_state(dev
->pdev
);
364 /* If KMS is active, we do the leavevt stuff here */
365 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
366 int error
= i915_gem_idle(dev
);
368 dev_err(&dev
->pdev
->dev
,
369 "GEM idle failed, resume might fail\n");
372 drm_irq_uninstall(dev
);
375 i915_save_state(dev
);
377 intel_opregion_fini(dev
);
379 /* Modeset on resume, not lid events */
380 dev_priv
->modeset_on_lid
= 0;
385 int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
389 if (!dev
|| !dev
->dev_private
) {
390 DRM_ERROR("dev: %p\n", dev
);
391 DRM_ERROR("DRM not initialized, aborting suspend.\n");
395 if (state
.event
== PM_EVENT_PRETHAW
)
399 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
402 error
= i915_drm_freeze(dev
);
406 if (state
.event
== PM_EVENT_SUSPEND
) {
407 /* Shut down the device */
408 pci_disable_device(dev
->pdev
);
409 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
415 static int i915_drm_thaw(struct drm_device
*dev
)
417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
420 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
421 mutex_lock(&dev
->struct_mutex
);
422 i915_gem_restore_gtt_mappings(dev
);
423 mutex_unlock(&dev
->struct_mutex
);
426 i915_restore_state(dev
);
427 intel_opregion_setup(dev
);
429 /* KMS EnterVT equivalent */
430 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
431 mutex_lock(&dev
->struct_mutex
);
432 dev_priv
->mm
.suspended
= 0;
434 error
= i915_gem_init_ringbuffer(dev
);
435 mutex_unlock(&dev
->struct_mutex
);
437 drm_mode_config_reset(dev
);
438 drm_irq_install(dev
);
440 /* Resume the modeset for every activated CRTC */
441 drm_helper_resume_force_mode(dev
);
443 if (IS_IRONLAKE_M(dev
))
444 ironlake_enable_rc6(dev
);
447 intel_opregion_init(dev
);
449 dev_priv
->modeset_on_lid
= 0;
454 int i915_resume(struct drm_device
*dev
)
458 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
461 if (pci_enable_device(dev
->pdev
))
464 pci_set_master(dev
->pdev
);
466 ret
= i915_drm_thaw(dev
);
470 drm_kms_helper_poll_enable(dev
);
474 static int i8xx_do_reset(struct drm_device
*dev
, u8 flags
)
476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
481 I915_WRITE(D_STATE
, I915_READ(D_STATE
) | DSTATE_GFX_RESET_I830
);
482 POSTING_READ(D_STATE
);
484 if (IS_I830(dev
) || IS_845G(dev
)) {
485 I915_WRITE(DEBUG_RESET_I830
,
486 DEBUG_RESET_DISPLAY
|
489 POSTING_READ(DEBUG_RESET_I830
);
492 I915_WRITE(DEBUG_RESET_I830
, 0);
493 POSTING_READ(DEBUG_RESET_I830
);
498 I915_WRITE(D_STATE
, I915_READ(D_STATE
) & ~DSTATE_GFX_RESET_I830
);
499 POSTING_READ(D_STATE
);
504 static int i965_reset_complete(struct drm_device
*dev
)
507 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
511 static int i965_do_reset(struct drm_device
*dev
, u8 flags
)
516 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
517 * well as the reset bit (GR/bit 0). Setting the GR bit
518 * triggers the reset; when done, the hardware will clear it.
520 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
521 pci_write_config_byte(dev
->pdev
, I965_GDRST
, gdrst
| flags
| 0x1);
523 return wait_for(i965_reset_complete(dev
), 500);
526 static int ironlake_do_reset(struct drm_device
*dev
, u8 flags
)
528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
529 u32 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
530 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
, gdrst
| flags
| 0x1);
531 return wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
534 static int gen6_do_reset(struct drm_device
*dev
, u8 flags
)
536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
538 I915_WRITE(GEN6_GDRST
, GEN6_GRDOM_FULL
);
539 return wait_for((I915_READ(GEN6_GDRST
) & GEN6_GRDOM_FULL
) == 0, 500);
543 * i965_reset - reset chip after a hang
544 * @dev: drm device to reset
545 * @flags: reset domains
547 * Reset the chip. Useful if a hang is detected. Returns zero on successful
548 * reset or otherwise an error code.
550 * Procedure is fairly simple:
551 * - reset the chip using the reset reg
552 * - re-init context state
553 * - re-init hardware status page
554 * - re-init ring buffer
555 * - re-init interrupt state
558 int i915_reset(struct drm_device
*dev
, u8 flags
)
560 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
562 * We really should only reset the display subsystem if we actually
565 bool need_display
= true;
571 if (!mutex_trylock(&dev
->struct_mutex
))
577 if (get_seconds() - dev_priv
->last_gpu_reset
< 5) {
578 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
579 } else switch (INTEL_INFO(dev
)->gen
) {
581 ret
= gen6_do_reset(dev
, flags
);
584 ret
= ironlake_do_reset(dev
, flags
);
587 ret
= i965_do_reset(dev
, flags
);
590 ret
= i8xx_do_reset(dev
, flags
);
593 dev_priv
->last_gpu_reset
= get_seconds();
595 DRM_ERROR("Failed to reset chip.\n");
596 mutex_unlock(&dev
->struct_mutex
);
600 /* Ok, now get things going again... */
603 * Everything depends on having the GTT running, so we need to start
604 * there. Fortunately we don't need to do this unless we reset the
605 * chip at a PCI level.
607 * Next we need to restore the context, but we don't use those
610 * Ring buffer needs to be re-initialized in the KMS case, or if X
611 * was running at the time of the reset (i.e. we weren't VT
614 if (drm_core_check_feature(dev
, DRIVER_MODESET
) ||
615 !dev_priv
->mm
.suspended
) {
616 dev_priv
->mm
.suspended
= 0;
618 dev_priv
->ring
[RCS
].init(&dev_priv
->ring
[RCS
]);
620 dev_priv
->ring
[VCS
].init(&dev_priv
->ring
[VCS
]);
622 dev_priv
->ring
[BCS
].init(&dev_priv
->ring
[BCS
]);
624 mutex_unlock(&dev
->struct_mutex
);
625 drm_irq_uninstall(dev
);
626 drm_mode_config_reset(dev
);
627 drm_irq_install(dev
);
628 mutex_lock(&dev
->struct_mutex
);
631 mutex_unlock(&dev
->struct_mutex
);
634 * Perform a full modeset as on later generations, e.g. Ironlake, we may
635 * need to retrain the display link and cannot just restore the register
639 mutex_lock(&dev
->mode_config
.mutex
);
640 drm_helper_resume_force_mode(dev
);
641 mutex_unlock(&dev
->mode_config
.mutex
);
649 i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
651 /* Only bind to function 0 of the device. Early generations
652 * used function 1 as a placeholder for multi-head. This causes
653 * us confusion instead, especially on the systems where both
654 * functions have the same PCI-ID!
656 if (PCI_FUNC(pdev
->devfn
))
659 return drm_get_pci_dev(pdev
, ent
, &driver
);
663 i915_pci_remove(struct pci_dev
*pdev
)
665 struct drm_device
*dev
= pci_get_drvdata(pdev
);
670 static int i915_pm_suspend(struct device
*dev
)
672 struct pci_dev
*pdev
= to_pci_dev(dev
);
673 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
676 if (!drm_dev
|| !drm_dev
->dev_private
) {
677 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
681 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
684 error
= i915_drm_freeze(drm_dev
);
688 pci_disable_device(pdev
);
689 pci_set_power_state(pdev
, PCI_D3hot
);
694 static int i915_pm_resume(struct device
*dev
)
696 struct pci_dev
*pdev
= to_pci_dev(dev
);
697 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
699 return i915_resume(drm_dev
);
702 static int i915_pm_freeze(struct device
*dev
)
704 struct pci_dev
*pdev
= to_pci_dev(dev
);
705 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
707 if (!drm_dev
|| !drm_dev
->dev_private
) {
708 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
712 return i915_drm_freeze(drm_dev
);
715 static int i915_pm_thaw(struct device
*dev
)
717 struct pci_dev
*pdev
= to_pci_dev(dev
);
718 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
720 return i915_drm_thaw(drm_dev
);
723 static int i915_pm_poweroff(struct device
*dev
)
725 struct pci_dev
*pdev
= to_pci_dev(dev
);
726 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
728 return i915_drm_freeze(drm_dev
);
731 static const struct dev_pm_ops i915_pm_ops
= {
732 .suspend
= i915_pm_suspend
,
733 .resume
= i915_pm_resume
,
734 .freeze
= i915_pm_freeze
,
735 .thaw
= i915_pm_thaw
,
736 .poweroff
= i915_pm_poweroff
,
737 .restore
= i915_pm_resume
,
740 static struct vm_operations_struct i915_gem_vm_ops
= {
741 .fault
= i915_gem_fault
,
742 .open
= drm_gem_vm_open
,
743 .close
= drm_gem_vm_close
,
746 static struct drm_driver driver
= {
747 /* don't use mtrr's here, the Xserver or user space app should
748 * deal with them for intel hardware.
751 DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
| /* DRIVER_USE_MTRR |*/
752 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
,
753 .load
= i915_driver_load
,
754 .unload
= i915_driver_unload
,
755 .open
= i915_driver_open
,
756 .lastclose
= i915_driver_lastclose
,
757 .preclose
= i915_driver_preclose
,
758 .postclose
= i915_driver_postclose
,
760 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
761 .suspend
= i915_suspend
,
762 .resume
= i915_resume
,
764 .device_is_agp
= i915_driver_device_is_agp
,
765 .enable_vblank
= i915_enable_vblank
,
766 .disable_vblank
= i915_disable_vblank
,
767 .get_vblank_timestamp
= i915_get_vblank_timestamp
,
768 .get_scanout_position
= i915_get_crtc_scanoutpos
,
769 .irq_preinstall
= i915_driver_irq_preinstall
,
770 .irq_postinstall
= i915_driver_irq_postinstall
,
771 .irq_uninstall
= i915_driver_irq_uninstall
,
772 .irq_handler
= i915_driver_irq_handler
,
773 .reclaim_buffers
= drm_core_reclaim_buffers
,
774 .master_create
= i915_master_create
,
775 .master_destroy
= i915_master_destroy
,
776 #if defined(CONFIG_DEBUG_FS)
777 .debugfs_init
= i915_debugfs_init
,
778 .debugfs_cleanup
= i915_debugfs_cleanup
,
780 .gem_init_object
= i915_gem_init_object
,
781 .gem_free_object
= i915_gem_free_object
,
782 .gem_vm_ops
= &i915_gem_vm_ops
,
783 .dumb_create
= i915_gem_dumb_create
,
784 .dumb_map_offset
= i915_gem_mmap_gtt
,
785 .dumb_destroy
= i915_gem_dumb_destroy
,
786 .ioctls
= i915_ioctls
,
788 .owner
= THIS_MODULE
,
790 .release
= drm_release
,
791 .unlocked_ioctl
= drm_ioctl
,
792 .mmap
= drm_gem_mmap
,
794 .fasync
= drm_fasync
,
797 .compat_ioctl
= i915_compat_ioctl
,
799 .llseek
= noop_llseek
,
805 .major
= DRIVER_MAJOR
,
806 .minor
= DRIVER_MINOR
,
807 .patchlevel
= DRIVER_PATCHLEVEL
,
810 static struct pci_driver i915_pci_driver
= {
812 .id_table
= pciidlist
,
813 .probe
= i915_pci_probe
,
814 .remove
= i915_pci_remove
,
815 .driver
.pm
= &i915_pm_ops
,
818 static int __init
i915_init(void)
820 if (!intel_agp_enabled
) {
821 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
825 driver
.num_ioctls
= i915_max_ioctl
;
828 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
829 * explicitly disabled with the module pararmeter.
831 * Otherwise, just follow the parameter (defaulting to off).
833 * Allow optional vga_text_mode_force boot option to override
834 * the default behavior.
836 #if defined(CONFIG_DRM_I915_KMS)
837 if (i915_modeset
!= 0)
838 driver
.driver_features
|= DRIVER_MODESET
;
840 if (i915_modeset
== 1)
841 driver
.driver_features
|= DRIVER_MODESET
;
843 #ifdef CONFIG_VGA_CONSOLE
844 if (vgacon_text_force() && i915_modeset
== -1)
845 driver
.driver_features
&= ~DRIVER_MODESET
;
848 if (!(driver
.driver_features
& DRIVER_MODESET
))
849 driver
.get_vblank_timestamp
= NULL
;
851 return drm_pci_init(&driver
, &i915_pci_driver
);
854 static void __exit
i915_exit(void)
856 drm_pci_exit(&driver
, &i915_pci_driver
);
859 module_init(i915_init
);
860 module_exit(i915_exit
);
862 MODULE_AUTHOR(DRIVER_AUTHOR
);
863 MODULE_DESCRIPTION(DRIVER_DESC
);
864 MODULE_LICENSE("GPL and additional rights");