d3464f35f427b8d040d60f8afc51449b5626e3e5
2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 * The above copyright notice and this permission notice (including the
21 * next paragraph) shall be included in all copies or substantial portions
26 * Authors: Dave Airlie <airlied@redhat.com>
32 #include "ast_dram_tables.h"
34 static void ast_init_dram_2300(struct drm_device
*dev
);
37 ast_enable_vga(struct drm_device
*dev
)
39 struct ast_private
*ast
= dev
->dev_private
;
41 ast_io_write8(ast
, 0x43, 0x01);
42 ast_io_write8(ast
, 0x42, 0x01);
45 #if 0 /* will use later */
47 ast_is_vga_enabled(struct drm_device
*dev
)
49 struct ast_private
*ast
= dev
->dev_private
;
52 if (ast
->chip
== AST1180
) {
55 ch
= ast_io_read8(ast
, 0x43);
62 static const u8 extreginfo
[] = { 0x0f, 0x04, 0x1c, 0xff };
63 static const u8 extreginfo_ast2300a0
[] = { 0x0f, 0x04, 0x1c, 0xff };
64 static const u8 extreginfo_ast2300
[] = { 0x0f, 0x04, 0x1f, 0xff };
67 ast_set_def_ext_reg(struct drm_device
*dev
)
69 struct ast_private
*ast
= dev
->dev_private
;
71 const u8
*ext_reg_info
;
74 for (i
= 0x81; i
<= 0x8f; i
++)
75 ast_set_index_reg(ast
, AST_IO_CRTC_PORT
, i
, 0x00);
77 if (ast
->chip
== AST2300
) {
78 if (dev
->pdev
->revision
>= 0x20)
79 ext_reg_info
= extreginfo_ast2300
;
81 ext_reg_info
= extreginfo_ast2300a0
;
83 ext_reg_info
= extreginfo
;
86 while (*ext_reg_info
!= 0xff) {
87 ast_set_index_reg_mask(ast
, AST_IO_CRTC_PORT
, index
, 0x00, *ext_reg_info
);
92 /* disable standard IO/MEM decode if secondary */
93 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
95 /* Set Ext. Default */
96 ast_set_index_reg_mask(ast
, AST_IO_CRTC_PORT
, 0x8c, 0x00, 0x01);
97 ast_set_index_reg_mask(ast
, AST_IO_CRTC_PORT
, 0xb7, 0x00, 0x00);
99 /* Enable RAMDAC for A1 */
101 if (ast
->chip
== AST2300
)
103 ast_set_index_reg_mask(ast
, AST_IO_CRTC_PORT
, 0xb6, 0xff, reg
);
106 static inline u32
mindwm(struct ast_private
*ast
, u32 r
)
108 ast_write32(ast
, 0xf004, r
& 0xffff0000);
109 ast_write32(ast
, 0xf000, 0x1);
111 return ast_read32(ast
, 0x10000 + (r
& 0x0000ffff));
114 static inline void moutdwm(struct ast_private
*ast
, u32 r
, u32 v
)
116 ast_write32(ast
, 0xf004, r
& 0xffff0000);
117 ast_write32(ast
, 0xf000, 0x1);
118 ast_write32(ast
, 0x10000 + (r
& 0x0000ffff), v
);
122 * AST2100/2150 DLL CBR Setting
124 #define CBR_SIZE_AST2150 ((16 << 10) - 1)
125 #define CBR_PASSNUM_AST2150 5
126 #define CBR_THRESHOLD_AST2150 10
127 #define CBR_THRESHOLD2_AST2150 10
128 #define TIMEOUT_AST2150 5000000
130 #define CBR_PATNUM_AST2150 8
132 static const u32 pattern_AST2150
[14] = {
149 static u32
mmctestburst2_ast2150(struct ast_private
*ast
, u32 datagen
)
153 moutdwm(ast
, 0x1e6e0070, 0x00000000);
154 moutdwm(ast
, 0x1e6e0070, 0x00000001 | (datagen
<< 3));
157 data
= mindwm(ast
, 0x1e6e0070) & 0x40;
158 if (++timeout
> TIMEOUT_AST2150
) {
159 moutdwm(ast
, 0x1e6e0070, 0x00000000);
163 moutdwm(ast
, 0x1e6e0070, 0x00000000);
164 moutdwm(ast
, 0x1e6e0070, 0x00000003 | (datagen
<< 3));
167 data
= mindwm(ast
, 0x1e6e0070) & 0x40;
168 if (++timeout
> TIMEOUT_AST2150
) {
169 moutdwm(ast
, 0x1e6e0070, 0x00000000);
173 data
= (mindwm(ast
, 0x1e6e0070) & 0x80) >> 7;
174 moutdwm(ast
, 0x1e6e0070, 0x00000000);
178 #if 0 /* unused in DDX driver - here for completeness */
179 static u32
mmctestsingle2_ast2150(struct ast_private
*ast
, u32 datagen
)
183 moutdwm(ast
, 0x1e6e0070, 0x00000000);
184 moutdwm(ast
, 0x1e6e0070, 0x00000005 | (datagen
<< 3));
187 data
= mindwm(ast
, 0x1e6e0070) & 0x40;
188 if (++timeout
> TIMEOUT_AST2150
) {
189 moutdwm(ast
, 0x1e6e0070, 0x00000000);
193 data
= (mindwm(ast
, 0x1e6e0070) & 0x80) >> 7;
194 moutdwm(ast
, 0x1e6e0070, 0x00000000);
199 static int cbrtest_ast2150(struct ast_private
*ast
)
203 for (i
= 0; i
< 8; i
++)
204 if (mmctestburst2_ast2150(ast
, i
))
209 static int cbrscan_ast2150(struct ast_private
*ast
, int busw
)
213 for (patcnt
= 0; patcnt
< CBR_PATNUM_AST2150
; patcnt
++) {
214 moutdwm(ast
, 0x1e6e007c, pattern_AST2150
[patcnt
]);
215 for (loop
= 0; loop
< CBR_PASSNUM_AST2150
; loop
++) {
216 if (cbrtest_ast2150(ast
))
219 if (loop
== CBR_PASSNUM_AST2150
)
226 static void cbrdlli_ast2150(struct ast_private
*ast
, int busw
)
228 u32 dll_min
[4], dll_max
[4], dlli
, data
, passcnt
;
231 dll_min
[0] = dll_min
[1] = dll_min
[2] = dll_min
[3] = 0xff;
232 dll_max
[0] = dll_max
[1] = dll_max
[2] = dll_max
[3] = 0x0;
235 for (dlli
= 0; dlli
< 100; dlli
++) {
236 moutdwm(ast
, 0x1e6e0068, dlli
| (dlli
<< 8) | (dlli
<< 16) | (dlli
<< 24));
237 data
= cbrscan_ast2150(ast
, busw
);
240 if (dll_min
[0] > dlli
)
242 if (dll_max
[0] < dlli
)
246 } else if (passcnt
>= CBR_THRESHOLD_AST2150
)
249 if (dll_max
[0] == 0 || (dll_max
[0]-dll_min
[0]) < CBR_THRESHOLD_AST2150
)
252 dlli
= dll_min
[0] + (((dll_max
[0] - dll_min
[0]) * 7) >> 4);
253 moutdwm(ast
, 0x1e6e0068, dlli
| (dlli
<< 8) | (dlli
<< 16) | (dlli
<< 24));
258 static void ast_init_dram_reg(struct drm_device
*dev
)
260 struct ast_private
*ast
= dev
->dev_private
;
263 const struct ast_dramstruct
*dram_reg_info
;
265 j
= ast_get_index_reg_mask(ast
, AST_IO_CRTC_PORT
, 0xd0, 0xff);
267 if ((j
& 0x80) == 0) { /* VGA only */
268 if (ast
->chip
== AST2000
) {
269 dram_reg_info
= ast2000_dram_table_data
;
270 ast_write32(ast
, 0xf004, 0x1e6e0000);
271 ast_write32(ast
, 0xf000, 0x1);
272 ast_write32(ast
, 0x10100, 0xa8);
276 } while (ast_read32(ast
, 0x10100) != 0xa8);
277 } else {/* AST2100/1100 */
278 if (ast
->chip
== AST2100
|| ast
->chip
== 2200)
279 dram_reg_info
= ast2100_dram_table_data
;
281 dram_reg_info
= ast1100_dram_table_data
;
283 ast_write32(ast
, 0xf004, 0x1e6e0000);
284 ast_write32(ast
, 0xf000, 0x1);
285 ast_write32(ast
, 0x12000, 0x1688A8A8);
288 } while (ast_read32(ast
, 0x12000) != 0x01);
290 ast_write32(ast
, 0x10000, 0xfc600309);
293 } while (ast_read32(ast
, 0x10000) != 0x01);
296 while (dram_reg_info
->index
!= 0xffff) {
297 if (dram_reg_info
->index
== 0xff00) {/* delay fn */
298 for (i
= 0; i
< 15; i
++)
299 udelay(dram_reg_info
->data
);
300 } else if (dram_reg_info
->index
== 0x4 && ast
->chip
!= AST2000
) {
301 data
= dram_reg_info
->data
;
302 if (ast
->dram_type
== AST_DRAM_1Gx16
)
304 else if (ast
->dram_type
== AST_DRAM_1Gx32
)
307 temp
= ast_read32(ast
, 0x12070);
310 ast_write32(ast
, 0x10000 + dram_reg_info
->index
, data
| temp
);
312 ast_write32(ast
, 0x10000 + dram_reg_info
->index
, dram_reg_info
->data
);
316 /* AST 2100/2150 DRAM calibration */
317 data
= ast_read32(ast
, 0x10120);
318 if (data
== 0x5061) { /* 266Mhz */
319 data
= ast_read32(ast
, 0x10004);
321 cbrdlli_ast2150(ast
, 16); /* 16 bits */
323 cbrdlli_ast2150(ast
, 32); /* 32 bits */
328 temp
= ast_read32(ast
, 0x10140);
329 ast_write32(ast
, 0x10140, temp
| 0x40);
335 temp
= ast_read32(ast
, 0x1200c);
336 ast_write32(ast
, 0x1200c, temp
& 0xfffffffd);
337 temp
= ast_read32(ast
, 0x12040);
338 ast_write32(ast
, 0x12040, temp
| 0x40);
347 j
= ast_get_index_reg_mask(ast
, AST_IO_CRTC_PORT
, 0xd0, 0xff);
348 } while ((j
& 0x40) == 0);
351 void ast_post_gpu(struct drm_device
*dev
)
354 struct ast_private
*ast
= dev
->dev_private
;
356 pci_read_config_dword(ast
->dev
->pdev
, 0x04, ®
);
358 pci_write_config_dword(ast
->dev
->pdev
, 0x04, reg
);
362 ast_set_def_ext_reg(dev
);
364 if (ast
->chip
== AST2300
)
365 ast_init_dram_2300(dev
);
367 ast_init_dram_reg(dev
);
370 /* AST 2300 DRAM settings */
374 struct ast2300_dram_param
{
396 u32 dll2_finetune_step
;
400 * DQSI DLL CBR Setting
402 #define CBR_SIZE1 ((4 << 10) - 1)
403 #define CBR_SIZE2 ((64 << 10) - 1)
404 #define CBR_PASSNUM 5
405 #define CBR_PASSNUM2 5
406 #define CBR_THRESHOLD 10
407 #define CBR_THRESHOLD2 10
408 #define TIMEOUT 5000000
411 static const u32 pattern
[8] = {
422 #if 0 /* unused in DDX, included for completeness */
423 static int mmc_test_burst(struct ast_private
*ast
, u32 datagen
)
427 moutdwm(ast
, 0x1e6e0070, 0x00000000);
428 moutdwm(ast
, 0x1e6e0070, 0x000000c1 | (datagen
<< 3));
431 data
= mindwm(ast
, 0x1e6e0070) & 0x3000;
435 if (++timeout
> TIMEOUT
) {
436 moutdwm(ast
, 0x1e6e0070, 0x00000000);
440 moutdwm(ast
, 0x1e6e0070, 0x00000000);
445 static int mmc_test_burst2(struct ast_private
*ast
, u32 datagen
)
449 moutdwm(ast
, 0x1e6e0070, 0x00000000);
450 moutdwm(ast
, 0x1e6e0070, 0x00000041 | (datagen
<< 3));
453 data
= mindwm(ast
, 0x1e6e0070) & 0x1000;
454 if (++timeout
> TIMEOUT
) {
455 moutdwm(ast
, 0x1e6e0070, 0x0);
459 data
= mindwm(ast
, 0x1e6e0078);
460 data
= (data
| (data
>> 16)) & 0xffff;
461 moutdwm(ast
, 0x1e6e0070, 0x0);
465 #if 0 /* Unused in DDX here for completeness */
466 static int mmc_test_single(struct ast_private
*ast
, u32 datagen
)
470 moutdwm(ast
, 0x1e6e0070, 0x00000000);
471 moutdwm(ast
, 0x1e6e0070, 0x000000c5 | (datagen
<< 3));
474 data
= mindwm(ast
, 0x1e6e0070) & 0x3000;
477 if (++timeout
> TIMEOUT
) {
478 moutdwm(ast
, 0x1e6e0070, 0x0);
482 moutdwm(ast
, 0x1e6e0070, 0x0);
487 static int mmc_test_single2(struct ast_private
*ast
, u32 datagen
)
491 moutdwm(ast
, 0x1e6e0070, 0x00000000);
492 moutdwm(ast
, 0x1e6e0070, 0x00000005 | (datagen
<< 3));
495 data
= mindwm(ast
, 0x1e6e0070) & 0x1000;
496 if (++timeout
> TIMEOUT
) {
497 moutdwm(ast
, 0x1e6e0070, 0x0);
501 data
= mindwm(ast
, 0x1e6e0078);
502 data
= (data
| (data
>> 16)) & 0xffff;
503 moutdwm(ast
, 0x1e6e0070, 0x0);
507 static int cbr_test(struct ast_private
*ast
)
511 data
= mmc_test_single2(ast
, 0);
512 if ((data
& 0xff) && (data
& 0xff00))
514 for (i
= 0; i
< 8; i
++) {
515 data
= mmc_test_burst2(ast
, i
);
516 if ((data
& 0xff) && (data
& 0xff00))
521 else if (data
& 0xff)
526 static int cbr_scan(struct ast_private
*ast
)
528 u32 data
, data2
, patcnt
, loop
;
531 for (patcnt
= 0; patcnt
< CBR_PATNUM
; patcnt
++) {
532 moutdwm(ast
, 0x1e6e007c, pattern
[patcnt
]);
533 for (loop
= 0; loop
< CBR_PASSNUM2
; loop
++) {
534 if ((data
= cbr_test(ast
)) != 0) {
541 if (loop
== CBR_PASSNUM2
)
547 static u32
cbr_test2(struct ast_private
*ast
)
551 data
= mmc_test_burst2(ast
, 0);
554 data
|= mmc_test_single2(ast
, 0);
558 return ~data
& 0xffff;
561 static u32
cbr_scan2(struct ast_private
*ast
)
563 u32 data
, data2
, patcnt
, loop
;
566 for (patcnt
= 0; patcnt
< CBR_PATNUM
; patcnt
++) {
567 moutdwm(ast
, 0x1e6e007c, pattern
[patcnt
]);
568 for (loop
= 0; loop
< CBR_PASSNUM2
; loop
++) {
569 if ((data
= cbr_test2(ast
)) != 0) {
576 if (loop
== CBR_PASSNUM2
)
582 #if 0 /* unused in DDX - added for completeness */
583 static void finetuneDQI(struct ast_private
*ast
, struct ast2300_dram_param
*param
)
585 u32 gold_sadj
[2], dllmin
[16], dllmax
[16], dlli
, data
, cnt
, mask
, passcnt
;
587 gold_sadj
[0] = (mindwm(ast
, 0x1E6E0024) >> 16) & 0xffff;
588 gold_sadj
[1] = gold_sadj
[0] >> 8;
589 gold_sadj
[0] = gold_sadj
[0] & 0xff;
590 gold_sadj
[0] = (gold_sadj
[0] + gold_sadj
[1]) >> 1;
591 gold_sadj
[1] = gold_sadj
[0];
593 for (cnt
= 0; cnt
< 16; cnt
++) {
598 for (dlli
= 0; dlli
< 76; dlli
++) {
599 moutdwm(ast
, 0x1E6E0068, 0x00001400 | (dlli
<< 16) | (dlli
<< 24));
600 /* Wait DQSI latch phase calibration */
601 moutdwm(ast
, 0x1E6E0074, 0x00000010);
602 moutdwm(ast
, 0x1E6E0070, 0x00000003);
604 data
= mindwm(ast
, 0x1E6E0070);
605 } while (!(data
& 0x00001000));
606 moutdwm(ast
, 0x1E6E0070, 0x00000000);
608 moutdwm(ast
, 0x1E6E0074, CBR_SIZE1
);
609 data
= cbr_scan2(ast
);
612 for (cnt
= 0; cnt
< 16; cnt
++) {
614 if (dllmin
[cnt
] > dlli
) {
617 if (dllmax
[cnt
] < dlli
) {
624 } else if (passcnt
>= CBR_THRESHOLD
) {
629 for (cnt
= 0; cnt
< 8; cnt
++) {
631 if ((dllmax
[cnt
] > dllmin
[cnt
]) && ((dllmax
[cnt
] - dllmin
[cnt
]) >= CBR_THRESHOLD
)) {
632 dlli
= (dllmin
[cnt
] + dllmax
[cnt
]) >> 1;
633 if (gold_sadj
[0] >= dlli
) {
634 dlli
= (gold_sadj
[0] - dlli
) >> 1;
639 dlli
= (dlli
- gold_sadj
[0]) >> 1;
643 dlli
= (8 - dlli
) & 0x7;
648 moutdwm(ast
, 0x1E6E0080, data
);
651 for (cnt
= 8; cnt
< 16; cnt
++) {
653 if ((dllmax
[cnt
] > dllmin
[cnt
]) && ((dllmax
[cnt
] - dllmin
[cnt
]) >= CBR_THRESHOLD
)) {
654 dlli
= (dllmin
[cnt
] + dllmax
[cnt
]) >> 1;
655 if (gold_sadj
[1] >= dlli
) {
656 dlli
= (gold_sadj
[1] - dlli
) >> 1;
660 dlli
= (dlli
- 1) & 0x7;
663 dlli
= (dlli
- gold_sadj
[1]) >> 1;
668 dlli
= (8 - dlli
) & 0x7;
673 moutdwm(ast
, 0x1E6E0084, data
);
678 static void finetuneDQI_L(struct ast_private
*ast
, struct ast2300_dram_param
*param
)
680 u32 gold_sadj
[2], dllmin
[16], dllmax
[16], dlli
, data
, cnt
, mask
, passcnt
;
683 for (cnt
= 0; cnt
< 16; cnt
++) {
688 for (dlli
= 0; dlli
< 76; dlli
++) {
689 moutdwm(ast
, 0x1E6E0068, 0x00001400 | (dlli
<< 16) | (dlli
<< 24));
690 /* Wait DQSI latch phase calibration */
691 moutdwm(ast
, 0x1E6E0074, 0x00000010);
692 moutdwm(ast
, 0x1E6E0070, 0x00000003);
694 data
= mindwm(ast
, 0x1E6E0070);
695 } while (!(data
& 0x00001000));
696 moutdwm(ast
, 0x1E6E0070, 0x00000000);
698 moutdwm(ast
, 0x1E6E0074, CBR_SIZE1
);
699 data
= cbr_scan2(ast
);
702 for (cnt
= 0; cnt
< 16; cnt
++) {
704 if (dllmin
[cnt
] > dlli
) {
707 if (dllmax
[cnt
] < dlli
) {
714 } else if (passcnt
>= CBR_THRESHOLD2
) {
720 for (cnt
= 0; cnt
< 16; cnt
++) {
721 if ((dllmax
[cnt
] > dllmin
[cnt
]) && ((dllmax
[cnt
] - dllmin
[cnt
]) >= CBR_THRESHOLD2
)) {
722 gold_sadj
[0] += dllmin
[cnt
];
729 gold_sadj
[0] = gold_sadj
[0] >> 4;
730 gold_sadj
[1] = gold_sadj
[0];
733 for (cnt
= 0; cnt
< 8; cnt
++) {
735 if ((dllmax
[cnt
] > dllmin
[cnt
]) && ((dllmax
[cnt
] - dllmin
[cnt
]) >= CBR_THRESHOLD2
)) {
737 if (gold_sadj
[0] >= dlli
) {
738 dlli
= ((gold_sadj
[0] - dlli
) * 19) >> 5;
743 dlli
= ((dlli
- gold_sadj
[0]) * 19) >> 5;
747 dlli
= (8 - dlli
) & 0x7;
752 moutdwm(ast
, 0x1E6E0080, data
);
755 for (cnt
= 8; cnt
< 16; cnt
++) {
757 if ((dllmax
[cnt
] > dllmin
[cnt
]) && ((dllmax
[cnt
] - dllmin
[cnt
]) >= CBR_THRESHOLD2
)) {
759 if (gold_sadj
[1] >= dlli
) {
760 dlli
= ((gold_sadj
[1] - dlli
) * 19) >> 5;
764 dlli
= (dlli
- 1) & 0x7;
767 dlli
= ((dlli
- gold_sadj
[1]) * 19) >> 5;
772 dlli
= (8 - dlli
) & 0x7;
777 moutdwm(ast
, 0x1E6E0084, data
);
779 } /* finetuneDQI_L */
781 static void finetuneDQI_L2(struct ast_private
*ast
, struct ast2300_dram_param
*param
)
783 u32 gold_sadj
[2], dllmin
[16], dllmax
[16], dlli
, data
, cnt
, mask
, passcnt
, data2
;
785 for (cnt
= 0; cnt
< 16; cnt
++) {
790 for (dlli
= 0; dlli
< 76; dlli
++) {
791 moutdwm(ast
, 0x1E6E0068, 0x00001400 | (dlli
<< 16) | (dlli
<< 24));
792 /* Wait DQSI latch phase calibration */
793 moutdwm(ast
, 0x1E6E0074, 0x00000010);
794 moutdwm(ast
, 0x1E6E0070, 0x00000003);
796 data
= mindwm(ast
, 0x1E6E0070);
797 } while (!(data
& 0x00001000));
798 moutdwm(ast
, 0x1E6E0070, 0x00000000);
800 moutdwm(ast
, 0x1E6E0074, CBR_SIZE2
);
801 data
= cbr_scan2(ast
);
804 for (cnt
= 0; cnt
< 16; cnt
++) {
806 if (dllmin
[cnt
] > dlli
) {
809 if (dllmax
[cnt
] < dlli
) {
816 } else if (passcnt
>= CBR_THRESHOLD2
) {
822 for (cnt
= 0; cnt
< 8; cnt
++) {
823 if ((dllmax
[cnt
] > dllmin
[cnt
]) && ((dllmax
[cnt
] - dllmin
[cnt
]) >= CBR_THRESHOLD2
)) {
824 if (gold_sadj
[0] < dllmin
[cnt
]) {
825 gold_sadj
[0] = dllmin
[cnt
];
827 if (gold_sadj
[1] > dllmax
[cnt
]) {
828 gold_sadj
[1] = dllmax
[cnt
];
832 gold_sadj
[0] = (gold_sadj
[1] + gold_sadj
[0]) >> 1;
833 gold_sadj
[1] = mindwm(ast
, 0x1E6E0080);
836 for (cnt
= 0; cnt
< 8; cnt
++) {
838 data2
= gold_sadj
[1] & 0x7;
840 if ((dllmax
[cnt
] > dllmin
[cnt
]) && ((dllmax
[cnt
] - dllmin
[cnt
]) >= CBR_THRESHOLD2
)) {
841 dlli
= (dllmin
[cnt
] + dllmax
[cnt
]) >> 1;
842 if (gold_sadj
[0] >= dlli
) {
843 dlli
= (gold_sadj
[0] - dlli
) >> 1;
848 data2
= (data2
+ dlli
) & 0x7;
851 dlli
= (dlli
- gold_sadj
[0]) >> 1;
856 data2
= (data2
- dlli
) & 0x7;
862 moutdwm(ast
, 0x1E6E0080, data
);
866 for (cnt
= 8; cnt
< 16; cnt
++) {
867 if ((dllmax
[cnt
] > dllmin
[cnt
]) && ((dllmax
[cnt
] - dllmin
[cnt
]) >= CBR_THRESHOLD2
)) {
868 if (gold_sadj
[0] < dllmin
[cnt
]) {
869 gold_sadj
[0] = dllmin
[cnt
];
871 if (gold_sadj
[1] > dllmax
[cnt
]) {
872 gold_sadj
[1] = dllmax
[cnt
];
876 gold_sadj
[0] = (gold_sadj
[1] + gold_sadj
[0]) >> 1;
877 gold_sadj
[1] = mindwm(ast
, 0x1E6E0084);
880 for (cnt
= 8; cnt
< 16; cnt
++) {
882 data2
= gold_sadj
[1] & 0x7;
884 if ((dllmax
[cnt
] > dllmin
[cnt
]) && ((dllmax
[cnt
] - dllmin
[cnt
]) >= CBR_THRESHOLD2
)) {
885 dlli
= (dllmin
[cnt
] + dllmax
[cnt
]) >> 1;
886 if (gold_sadj
[0] >= dlli
) {
887 dlli
= (gold_sadj
[0] - dlli
) >> 1;
892 data2
= (data2
+ dlli
) & 0x7;
895 dlli
= (dlli
- gold_sadj
[0]) >> 1;
900 data2
= (data2
- dlli
) & 0x7;
906 moutdwm(ast
, 0x1E6E0084, data
);
908 } /* finetuneDQI_L2 */
910 static void cbr_dll2(struct ast_private
*ast
, struct ast2300_dram_param
*param
)
912 u32 dllmin
[2], dllmax
[2], dlli
, data
, data2
, passcnt
;
915 finetuneDQI_L(ast
, param
);
916 finetuneDQI_L2(ast
, param
);
919 dllmin
[0] = dllmin
[1] = 0xff;
920 dllmax
[0] = dllmax
[1] = 0x0;
922 for (dlli
= 0; dlli
< 76; dlli
++) {
923 moutdwm(ast
, 0x1E6E0068, 0x00001300 | (dlli
<< 16) | (dlli
<< 24));
924 /* Wait DQSI latch phase calibration */
925 moutdwm(ast
, 0x1E6E0074, 0x00000010);
926 moutdwm(ast
, 0x1E6E0070, 0x00000003);
928 data
= mindwm(ast
, 0x1E6E0070);
929 } while (!(data
& 0x00001000));
930 moutdwm(ast
, 0x1E6E0070, 0x00000000);
932 moutdwm(ast
, 0x1E6E0074, CBR_SIZE2
);
933 data
= cbr_scan(ast
);
936 if (dllmin
[0] > dlli
) {
939 if (dllmax
[0] < dlli
) {
944 if (dllmin
[1] > dlli
) {
947 if (dllmax
[1] < dlli
) {
952 } else if (passcnt
>= CBR_THRESHOLD
) {
956 if (dllmax
[0] == 0 || (dllmax
[0]-dllmin
[0]) < CBR_THRESHOLD
) {
959 if (dllmax
[1] == 0 || (dllmax
[1]-dllmin
[1]) < CBR_THRESHOLD
) {
962 dlli
= (dllmin
[1] + dllmax
[1]) >> 1;
964 dlli
+= (dllmin
[0] + dllmax
[0]) >> 1;
965 moutdwm(ast
, 0x1E6E0068, (mindwm(ast
, 0x1E6E0068) & 0xFFFF) | (dlli
<< 16));
967 data
= (mindwm(ast
, 0x1E6E0080) >> 24) & 0x1F;
968 data2
= (mindwm(ast
, 0x1E6E0018) & 0xff80ffff) | (data
<< 16);
969 moutdwm(ast
, 0x1E6E0018, data2
);
970 moutdwm(ast
, 0x1E6E0024, 0x8001 | (data
<< 1) | (param
->dll2_finetune_step
<< 8));
972 /* Wait DQSI latch phase calibration */
973 moutdwm(ast
, 0x1E6E0074, 0x00000010);
974 moutdwm(ast
, 0x1E6E0070, 0x00000003);
976 data
= mindwm(ast
, 0x1E6E0070);
977 } while (!(data
& 0x00001000));
978 moutdwm(ast
, 0x1E6E0070, 0x00000000);
979 moutdwm(ast
, 0x1E6E0070, 0x00000003);
981 data
= mindwm(ast
, 0x1E6E0070);
982 } while (!(data
& 0x00001000));
983 moutdwm(ast
, 0x1E6E0070, 0x00000000);
986 static void get_ddr3_info(struct ast_private
*ast
, struct ast2300_dram_param
*param
)
988 u32 trap
, trap_AC2
, trap_MRS
;
990 moutdwm(ast
, 0x1E6E2000, 0x1688A8A8);
993 trap
= (mindwm(ast
, 0x1E6E2070) >> 25) & 0x3;
994 trap_AC2
= 0x00020000 + (trap
<< 16);
995 trap_AC2
|= 0x00300000 + ((trap
& 0x2) << 19);
996 trap_MRS
= 0x00000010 + (trap
<< 4);
997 trap_MRS
|= ((trap
& 0x2) << 18);
999 param
->reg_MADJ
= 0x00034C4C;
1000 param
->reg_SADJ
= 0x00001800;
1001 param
->reg_DRV
= 0x000000F0;
1002 param
->reg_PERIOD
= param
->dram_freq
;
1005 switch (param
->dram_freq
) {
1007 moutdwm(ast
, 0x1E6E2020, 0x0190);
1009 param
->reg_AC1
= 0x22202725;
1010 param
->reg_AC2
= 0xAA007613 | trap_AC2
;
1011 param
->reg_DQSIC
= 0x000000BA;
1012 param
->reg_MRS
= 0x04001400 | trap_MRS
;
1013 param
->reg_EMRS
= 0x00000000;
1014 param
->reg_IOZ
= 0x00000034;
1015 param
->reg_DQIDLY
= 0x00000074;
1016 param
->reg_FREQ
= 0x00004DC0;
1017 param
->madj_max
= 96;
1018 param
->dll2_finetune_step
= 3;
1022 moutdwm(ast
, 0x1E6E2020, 0x03F1);
1024 param
->reg_AC1
= 0x33302825;
1025 param
->reg_AC2
= 0xCC009617 | trap_AC2
;
1026 param
->reg_DQSIC
= 0x000000E2;
1027 param
->reg_MRS
= 0x04001600 | trap_MRS
;
1028 param
->reg_EMRS
= 0x00000000;
1029 param
->reg_IOZ
= 0x00000034;
1030 param
->reg_DRV
= 0x000000FA;
1031 param
->reg_DQIDLY
= 0x00000089;
1032 param
->reg_FREQ
= 0x000050C0;
1033 param
->madj_max
= 96;
1034 param
->dll2_finetune_step
= 4;
1036 switch (param
->dram_chipid
) {
1038 case AST_DRAM_512Mx16
:
1039 case AST_DRAM_1Gx16
:
1040 param
->reg_AC2
= 0xCC009617 | trap_AC2
;
1042 case AST_DRAM_2Gx16
:
1043 param
->reg_AC2
= 0xCC009622 | trap_AC2
;
1045 case AST_DRAM_4Gx16
:
1046 param
->reg_AC2
= 0xCC00963F | trap_AC2
;
1052 moutdwm(ast
, 0x1E6E2020, 0x01F0);
1054 param
->reg_AC1
= 0x33302825;
1055 param
->reg_AC2
= 0xCC009617 | trap_AC2
;
1056 param
->reg_DQSIC
= 0x000000E2;
1057 param
->reg_MRS
= 0x04001600 | trap_MRS
;
1058 param
->reg_EMRS
= 0x00000000;
1059 param
->reg_IOZ
= 0x00000034;
1060 param
->reg_DRV
= 0x000000FA;
1061 param
->reg_DQIDLY
= 0x00000089;
1062 param
->reg_FREQ
= 0x000050C0;
1063 param
->madj_max
= 96;
1064 param
->dll2_finetune_step
= 4;
1066 switch (param
->dram_chipid
) {
1068 case AST_DRAM_512Mx16
:
1069 case AST_DRAM_1Gx16
:
1070 param
->reg_AC2
= 0xCC009617 | trap_AC2
;
1072 case AST_DRAM_2Gx16
:
1073 param
->reg_AC2
= 0xCC009622 | trap_AC2
;
1075 case AST_DRAM_4Gx16
:
1076 param
->reg_AC2
= 0xCC00963F | trap_AC2
;
1082 moutdwm(ast
, 0x1E6E2020, 0x0230);
1084 param
->reg_AC1
= 0x33302926;
1085 param
->reg_AC2
= 0xCD44961A;
1086 param
->reg_DQSIC
= 0x000000FC;
1087 param
->reg_MRS
= 0x00081830;
1088 param
->reg_EMRS
= 0x00000000;
1089 param
->reg_IOZ
= 0x00000045;
1090 param
->reg_DQIDLY
= 0x00000097;
1091 param
->reg_FREQ
= 0x000052C0;
1092 param
->madj_max
= 88;
1093 param
->dll2_finetune_step
= 4;
1096 moutdwm(ast
, 0x1E6E2020, 0x0270);
1098 param
->reg_AC1
= 0x33302926;
1099 param
->reg_AC2
= 0xDE44A61D;
1100 param
->reg_DQSIC
= 0x00000117;
1101 param
->reg_MRS
= 0x00081A30;
1102 param
->reg_EMRS
= 0x00000000;
1103 param
->reg_IOZ
= 0x070000BB;
1104 param
->reg_DQIDLY
= 0x000000A0;
1105 param
->reg_FREQ
= 0x000054C0;
1106 param
->madj_max
= 79;
1107 param
->dll2_finetune_step
= 4;
1110 moutdwm(ast
, 0x1E6E2020, 0x0290);
1113 param
->reg_AC1
= 0x33302926;
1114 param
->reg_AC2
= 0xEF44B61E;
1115 param
->reg_DQSIC
= 0x00000125;
1116 param
->reg_MRS
= 0x00081A30;
1117 param
->reg_EMRS
= 0x00000040;
1118 param
->reg_DRV
= 0x000000F5;
1119 param
->reg_IOZ
= 0x00000023;
1120 param
->reg_DQIDLY
= 0x00000088;
1121 param
->reg_FREQ
= 0x000055C0;
1122 param
->madj_max
= 76;
1123 param
->dll2_finetune_step
= 3;
1126 moutdwm(ast
, 0x1E6E2020, 0x0140);
1127 param
->reg_MADJ
= 0x00136868;
1128 param
->reg_SADJ
= 0x00004534;
1131 param
->reg_AC1
= 0x33302A37;
1132 param
->reg_AC2
= 0xEF56B61E;
1133 param
->reg_DQSIC
= 0x0000013F;
1134 param
->reg_MRS
= 0x00101A50;
1135 param
->reg_EMRS
= 0x00000040;
1136 param
->reg_DRV
= 0x000000FA;
1137 param
->reg_IOZ
= 0x00000023;
1138 param
->reg_DQIDLY
= 0x00000078;
1139 param
->reg_FREQ
= 0x000057C0;
1140 param
->madj_max
= 136;
1141 param
->dll2_finetune_step
= 3;
1144 moutdwm(ast
, 0x1E6E2020, 0x02E1);
1145 param
->reg_MADJ
= 0x00136868;
1146 param
->reg_SADJ
= 0x00004534;
1149 param
->reg_AC1
= 0x32302A37;
1150 param
->reg_AC2
= 0xDF56B61F;
1151 param
->reg_DQSIC
= 0x0000014D;
1152 param
->reg_MRS
= 0x00101A50;
1153 param
->reg_EMRS
= 0x00000004;
1154 param
->reg_DRV
= 0x000000F5;
1155 param
->reg_IOZ
= 0x00000023;
1156 param
->reg_DQIDLY
= 0x00000078;
1157 param
->reg_FREQ
= 0x000058C0;
1158 param
->madj_max
= 132;
1159 param
->dll2_finetune_step
= 3;
1162 moutdwm(ast
, 0x1E6E2020, 0x0160);
1163 param
->reg_MADJ
= 0x00136868;
1164 param
->reg_SADJ
= 0x00004534;
1167 param
->reg_AC1
= 0x32302A37;
1168 param
->reg_AC2
= 0xEF56B621;
1169 param
->reg_DQSIC
= 0x0000015A;
1170 param
->reg_MRS
= 0x02101A50;
1171 param
->reg_EMRS
= 0x00000004;
1172 param
->reg_DRV
= 0x000000F5;
1173 param
->reg_IOZ
= 0x00000034;
1174 param
->reg_DQIDLY
= 0x00000078;
1175 param
->reg_FREQ
= 0x000059C0;
1176 param
->madj_max
= 128;
1177 param
->dll2_finetune_step
= 3;
1181 switch (param
->dram_chipid
) {
1182 case AST_DRAM_512Mx16
:
1183 param
->dram_config
= 0x130;
1186 case AST_DRAM_1Gx16
:
1187 param
->dram_config
= 0x131;
1189 case AST_DRAM_2Gx16
:
1190 param
->dram_config
= 0x132;
1192 case AST_DRAM_4Gx16
:
1193 param
->dram_config
= 0x133;
1195 }; /* switch size */
1197 switch (param
->vram_size
) {
1199 case AST_VIDMEM_SIZE_8M
:
1200 param
->dram_config
|= 0x00;
1202 case AST_VIDMEM_SIZE_16M
:
1203 param
->dram_config
|= 0x04;
1205 case AST_VIDMEM_SIZE_32M
:
1206 param
->dram_config
|= 0x08;
1208 case AST_VIDMEM_SIZE_64M
:
1209 param
->dram_config
|= 0x0c;
1215 static void ddr3_init(struct ast_private
*ast
, struct ast2300_dram_param
*param
)
1219 moutdwm(ast
, 0x1E6E0000, 0xFC600309);
1220 moutdwm(ast
, 0x1E6E0018, 0x00000100);
1221 moutdwm(ast
, 0x1E6E0024, 0x00000000);
1222 moutdwm(ast
, 0x1E6E0034, 0x00000000);
1224 moutdwm(ast
, 0x1E6E0064, param
->reg_MADJ
);
1225 moutdwm(ast
, 0x1E6E0068, param
->reg_SADJ
);
1227 moutdwm(ast
, 0x1E6E0064, param
->reg_MADJ
| 0xC0000);
1230 moutdwm(ast
, 0x1E6E0004, param
->dram_config
);
1231 moutdwm(ast
, 0x1E6E0008, 0x90040f);
1232 moutdwm(ast
, 0x1E6E0010, param
->reg_AC1
);
1233 moutdwm(ast
, 0x1E6E0014, param
->reg_AC2
);
1234 moutdwm(ast
, 0x1E6E0020, param
->reg_DQSIC
);
1235 moutdwm(ast
, 0x1E6E0080, 0x00000000);
1236 moutdwm(ast
, 0x1E6E0084, 0x00000000);
1237 moutdwm(ast
, 0x1E6E0088, param
->reg_DQIDLY
);
1238 moutdwm(ast
, 0x1E6E0018, 0x4040A170);
1239 moutdwm(ast
, 0x1E6E0018, 0x20402370);
1240 moutdwm(ast
, 0x1E6E0038, 0x00000000);
1241 moutdwm(ast
, 0x1E6E0040, 0xFF444444);
1242 moutdwm(ast
, 0x1E6E0044, 0x22222222);
1243 moutdwm(ast
, 0x1E6E0048, 0x22222222);
1244 moutdwm(ast
, 0x1E6E004C, 0x00000002);
1245 moutdwm(ast
, 0x1E6E0050, 0x80000000);
1246 moutdwm(ast
, 0x1E6E0050, 0x00000000);
1247 moutdwm(ast
, 0x1E6E0054, 0);
1248 moutdwm(ast
, 0x1E6E0060, param
->reg_DRV
);
1249 moutdwm(ast
, 0x1E6E006C, param
->reg_IOZ
);
1250 moutdwm(ast
, 0x1E6E0070, 0x00000000);
1251 moutdwm(ast
, 0x1E6E0074, 0x00000000);
1252 moutdwm(ast
, 0x1E6E0078, 0x00000000);
1253 moutdwm(ast
, 0x1E6E007C, 0x00000000);
1254 /* Wait MCLK2X lock to MCLK */
1256 data
= mindwm(ast
, 0x1E6E001C);
1257 } while (!(data
& 0x08000000));
1258 moutdwm(ast
, 0x1E6E0034, 0x00000001);
1259 moutdwm(ast
, 0x1E6E000C, 0x00005C04);
1261 moutdwm(ast
, 0x1E6E000C, 0x00000000);
1262 moutdwm(ast
, 0x1E6E0034, 0x00000000);
1263 data
= mindwm(ast
, 0x1E6E001C);
1264 data
= (data
>> 8) & 0xff;
1265 while ((data
& 0x08) || ((data
& 0x7) < 2) || (data
< 4)) {
1266 data2
= (mindwm(ast
, 0x1E6E0064) & 0xfff3ffff) + 4;
1267 if ((data2
& 0xff) > param
->madj_max
) {
1270 moutdwm(ast
, 0x1E6E0064, data2
);
1271 if (data2
& 0x00100000) {
1272 data2
= ((data2
& 0xff) >> 3) + 3;
1274 data2
= ((data2
& 0xff) >> 2) + 5;
1276 data
= mindwm(ast
, 0x1E6E0068) & 0xffff00ff;
1277 data2
+= data
& 0xff;
1278 data
= data
| (data2
<< 8);
1279 moutdwm(ast
, 0x1E6E0068, data
);
1281 moutdwm(ast
, 0x1E6E0064, mindwm(ast
, 0x1E6E0064) | 0xC0000);
1283 data
= mindwm(ast
, 0x1E6E0018) & 0xfffff1ff;
1284 moutdwm(ast
, 0x1E6E0018, data
);
1285 data
= data
| 0x200;
1286 moutdwm(ast
, 0x1E6E0018, data
);
1288 data
= mindwm(ast
, 0x1E6E001C);
1289 } while (!(data
& 0x08000000));
1291 moutdwm(ast
, 0x1E6E0034, 0x00000001);
1292 moutdwm(ast
, 0x1E6E000C, 0x00005C04);
1294 moutdwm(ast
, 0x1E6E000C, 0x00000000);
1295 moutdwm(ast
, 0x1E6E0034, 0x00000000);
1296 data
= mindwm(ast
, 0x1E6E001C);
1297 data
= (data
>> 8) & 0xff;
1299 data
= mindwm(ast
, 0x1E6E0018) | 0xC00;
1300 moutdwm(ast
, 0x1E6E0018, data
);
1302 moutdwm(ast
, 0x1E6E0034, 0x00000001);
1303 moutdwm(ast
, 0x1E6E000C, 0x00000040);
1305 /* Mode Register Setting */
1306 moutdwm(ast
, 0x1E6E002C, param
->reg_MRS
| 0x100);
1307 moutdwm(ast
, 0x1E6E0030, param
->reg_EMRS
);
1308 moutdwm(ast
, 0x1E6E0028, 0x00000005);
1309 moutdwm(ast
, 0x1E6E0028, 0x00000007);
1310 moutdwm(ast
, 0x1E6E0028, 0x00000003);
1311 moutdwm(ast
, 0x1E6E0028, 0x00000001);
1312 moutdwm(ast
, 0x1E6E002C, param
->reg_MRS
);
1313 moutdwm(ast
, 0x1E6E000C, 0x00005C08);
1314 moutdwm(ast
, 0x1E6E0028, 0x00000001);
1316 moutdwm(ast
, 0x1E6E000C, 0x7FFF5C01);
1322 data
= data
| 0x3000 | ((param
->reg_AC2
& 0x60000) >> 3);
1324 moutdwm(ast
, 0x1E6E0034, data
| 0x3);
1326 /* Wait DQI delay lock */
1328 data
= mindwm(ast
, 0x1E6E0080);
1329 } while (!(data
& 0x40000000));
1330 /* Wait DQSI delay lock */
1332 data
= mindwm(ast
, 0x1E6E0020);
1333 } while (!(data
& 0x00000800));
1334 /* Calibrate the DQSI delay */
1335 cbr_dll2(ast
, param
);
1337 moutdwm(ast
, 0x1E6E0120, param
->reg_FREQ
);
1338 /* ECC Memory Initialization */
1340 moutdwm(ast
, 0x1E6E007C, 0x00000000);
1341 moutdwm(ast
, 0x1E6E0070, 0x221);
1343 data
= mindwm(ast
, 0x1E6E0070);
1344 } while (!(data
& 0x00001000));
1345 moutdwm(ast
, 0x1E6E0070, 0x00000000);
1346 moutdwm(ast
, 0x1E6E0050, 0x80000000);
1347 moutdwm(ast
, 0x1E6E0050, 0x00000000);
1353 static void get_ddr2_info(struct ast_private
*ast
, struct ast2300_dram_param
*param
)
1355 u32 trap
, trap_AC2
, trap_MRS
;
1357 moutdwm(ast
, 0x1E6E2000, 0x1688A8A8);
1360 trap
= (mindwm(ast
, 0x1E6E2070) >> 25) & 0x3;
1361 trap_AC2
= (trap
<< 20) | (trap
<< 16);
1362 trap_AC2
+= 0x00110000;
1363 trap_MRS
= 0x00000040 | (trap
<< 4);
1366 param
->reg_MADJ
= 0x00034C4C;
1367 param
->reg_SADJ
= 0x00001800;
1368 param
->reg_DRV
= 0x000000F0;
1369 param
->reg_PERIOD
= param
->dram_freq
;
1372 switch (param
->dram_freq
) {
1374 moutdwm(ast
, 0x1E6E2020, 0x0130);
1376 param
->reg_AC1
= 0x11101513;
1377 param
->reg_AC2
= 0x78117011;
1378 param
->reg_DQSIC
= 0x00000092;
1379 param
->reg_MRS
= 0x00000842;
1380 param
->reg_EMRS
= 0x00000000;
1381 param
->reg_DRV
= 0x000000F0;
1382 param
->reg_IOZ
= 0x00000034;
1383 param
->reg_DQIDLY
= 0x0000005A;
1384 param
->reg_FREQ
= 0x00004AC0;
1385 param
->madj_max
= 138;
1386 param
->dll2_finetune_step
= 3;
1389 moutdwm(ast
, 0x1E6E2020, 0x0190);
1391 param
->reg_AC1
= 0x22202613;
1392 param
->reg_AC2
= 0xAA009016 | trap_AC2
;
1393 param
->reg_DQSIC
= 0x000000BA;
1394 param
->reg_MRS
= 0x00000A02 | trap_MRS
;
1395 param
->reg_EMRS
= 0x00000040;
1396 param
->reg_DRV
= 0x000000FA;
1397 param
->reg_IOZ
= 0x00000034;
1398 param
->reg_DQIDLY
= 0x00000074;
1399 param
->reg_FREQ
= 0x00004DC0;
1400 param
->madj_max
= 96;
1401 param
->dll2_finetune_step
= 3;
1405 moutdwm(ast
, 0x1E6E2020, 0x03F1);
1408 param
->reg_AC1
= 0x33302714;
1409 param
->reg_AC2
= 0xCC00B01B | trap_AC2
;
1410 param
->reg_DQSIC
= 0x000000E2;
1411 param
->reg_MRS
= 0x00000C02 | trap_MRS
;
1412 param
->reg_EMRS
= 0x00000040;
1413 param
->reg_DRV
= 0x000000FA;
1414 param
->reg_IOZ
= 0x00000034;
1415 param
->reg_DQIDLY
= 0x00000089;
1416 param
->reg_FREQ
= 0x000050C0;
1417 param
->madj_max
= 96;
1418 param
->dll2_finetune_step
= 4;
1420 switch (param
->dram_chipid
) {
1421 case AST_DRAM_512Mx16
:
1422 param
->reg_AC2
= 0xCC00B016 | trap_AC2
;
1425 case AST_DRAM_1Gx16
:
1426 param
->reg_AC2
= 0xCC00B01B | trap_AC2
;
1428 case AST_DRAM_2Gx16
:
1429 param
->reg_AC2
= 0xCC00B02B | trap_AC2
;
1431 case AST_DRAM_4Gx16
:
1432 param
->reg_AC2
= 0xCC00B03F | trap_AC2
;
1439 moutdwm(ast
, 0x1E6E2020, 0x01F0);
1442 param
->reg_AC1
= 0x33302714;
1443 param
->reg_AC2
= 0xCC00B01B | trap_AC2
;
1444 param
->reg_DQSIC
= 0x000000E2;
1445 param
->reg_MRS
= 0x00000C02 | trap_MRS
;
1446 param
->reg_EMRS
= 0x00000040;
1447 param
->reg_DRV
= 0x000000FA;
1448 param
->reg_IOZ
= 0x00000034;
1449 param
->reg_DQIDLY
= 0x00000089;
1450 param
->reg_FREQ
= 0x000050C0;
1451 param
->madj_max
= 96;
1452 param
->dll2_finetune_step
= 4;
1454 switch (param
->dram_chipid
) {
1455 case AST_DRAM_512Mx16
:
1456 param
->reg_AC2
= 0xCC00B016 | trap_AC2
;
1459 case AST_DRAM_1Gx16
:
1460 param
->reg_AC2
= 0xCC00B01B | trap_AC2
;
1462 case AST_DRAM_2Gx16
:
1463 param
->reg_AC2
= 0xCC00B02B | trap_AC2
;
1465 case AST_DRAM_4Gx16
:
1466 param
->reg_AC2
= 0xCC00B03F | trap_AC2
;
1472 moutdwm(ast
, 0x1E6E2020, 0x0230);
1474 param
->reg_AC1
= 0x33302815;
1475 param
->reg_AC2
= 0xCD44B01E;
1476 param
->reg_DQSIC
= 0x000000FC;
1477 param
->reg_MRS
= 0x00000E72;
1478 param
->reg_EMRS
= 0x00000000;
1479 param
->reg_DRV
= 0x00000000;
1480 param
->reg_IOZ
= 0x00000034;
1481 param
->reg_DQIDLY
= 0x00000097;
1482 param
->reg_FREQ
= 0x000052C0;
1483 param
->madj_max
= 88;
1484 param
->dll2_finetune_step
= 3;
1487 moutdwm(ast
, 0x1E6E2020, 0x0261);
1490 param
->reg_AC1
= 0x33302815;
1491 param
->reg_AC2
= 0xDE44C022;
1492 param
->reg_DQSIC
= 0x00000117;
1493 param
->reg_MRS
= 0x00000E72;
1494 param
->reg_EMRS
= 0x00000040;
1495 param
->reg_DRV
= 0x0000000A;
1496 param
->reg_IOZ
= 0x00000045;
1497 param
->reg_DQIDLY
= 0x000000A0;
1498 param
->reg_FREQ
= 0x000054C0;
1499 param
->madj_max
= 79;
1500 param
->dll2_finetune_step
= 3;
1503 moutdwm(ast
, 0x1E6E2020, 0x0120);
1506 param
->reg_AC1
= 0x33302815;
1507 param
->reg_AC2
= 0xEF44D024;
1508 param
->reg_DQSIC
= 0x00000125;
1509 param
->reg_MRS
= 0x00000E72;
1510 param
->reg_EMRS
= 0x00000004;
1511 param
->reg_DRV
= 0x000000F9;
1512 param
->reg_IOZ
= 0x00000045;
1513 param
->reg_DQIDLY
= 0x000000A7;
1514 param
->reg_FREQ
= 0x000055C0;
1515 param
->madj_max
= 76;
1516 param
->dll2_finetune_step
= 3;
1519 moutdwm(ast
, 0x1E6E2020, 0x02A1);
1522 param
->reg_AC1
= 0x43402915;
1523 param
->reg_AC2
= 0xFF44E025;
1524 param
->reg_DQSIC
= 0x00000132;
1525 param
->reg_MRS
= 0x00000E72;
1526 param
->reg_EMRS
= 0x00000040;
1527 param
->reg_DRV
= 0x0000000A;
1528 param
->reg_IOZ
= 0x00000045;
1529 param
->reg_DQIDLY
= 0x000000AD;
1530 param
->reg_FREQ
= 0x000056C0;
1531 param
->madj_max
= 76;
1532 param
->dll2_finetune_step
= 3;
1535 moutdwm(ast
, 0x1E6E2020, 0x0140);
1538 param
->reg_AC1
= 0x43402915;
1539 param
->reg_AC2
= 0xFF44E027;
1540 param
->reg_DQSIC
= 0x0000013F;
1541 param
->reg_MRS
= 0x00000E72;
1542 param
->reg_EMRS
= 0x00000004;
1543 param
->reg_DRV
= 0x000000F5;
1544 param
->reg_IOZ
= 0x00000045;
1545 param
->reg_DQIDLY
= 0x000000B3;
1546 param
->reg_FREQ
= 0x000057C0;
1547 param
->madj_max
= 76;
1548 param
->dll2_finetune_step
= 3;
1552 switch (param
->dram_chipid
) {
1553 case AST_DRAM_512Mx16
:
1554 param
->dram_config
= 0x100;
1557 case AST_DRAM_1Gx16
:
1558 param
->dram_config
= 0x121;
1560 case AST_DRAM_2Gx16
:
1561 param
->dram_config
= 0x122;
1563 case AST_DRAM_4Gx16
:
1564 param
->dram_config
= 0x123;
1566 }; /* switch size */
1568 switch (param
->vram_size
) {
1570 case AST_VIDMEM_SIZE_8M
:
1571 param
->dram_config
|= 0x00;
1573 case AST_VIDMEM_SIZE_16M
:
1574 param
->dram_config
|= 0x04;
1576 case AST_VIDMEM_SIZE_32M
:
1577 param
->dram_config
|= 0x08;
1579 case AST_VIDMEM_SIZE_64M
:
1580 param
->dram_config
|= 0x0c;
1585 static void ddr2_init(struct ast_private
*ast
, struct ast2300_dram_param
*param
)
1589 moutdwm(ast
, 0x1E6E0000, 0xFC600309);
1590 moutdwm(ast
, 0x1E6E0018, 0x00000100);
1591 moutdwm(ast
, 0x1E6E0024, 0x00000000);
1592 moutdwm(ast
, 0x1E6E0064, param
->reg_MADJ
);
1593 moutdwm(ast
, 0x1E6E0068, param
->reg_SADJ
);
1595 moutdwm(ast
, 0x1E6E0064, param
->reg_MADJ
| 0xC0000);
1598 moutdwm(ast
, 0x1E6E0004, param
->dram_config
);
1599 moutdwm(ast
, 0x1E6E0008, 0x90040f);
1600 moutdwm(ast
, 0x1E6E0010, param
->reg_AC1
);
1601 moutdwm(ast
, 0x1E6E0014, param
->reg_AC2
);
1602 moutdwm(ast
, 0x1E6E0020, param
->reg_DQSIC
);
1603 moutdwm(ast
, 0x1E6E0080, 0x00000000);
1604 moutdwm(ast
, 0x1E6E0084, 0x00000000);
1605 moutdwm(ast
, 0x1E6E0088, param
->reg_DQIDLY
);
1606 moutdwm(ast
, 0x1E6E0018, 0x4040A130);
1607 moutdwm(ast
, 0x1E6E0018, 0x20402330);
1608 moutdwm(ast
, 0x1E6E0038, 0x00000000);
1609 moutdwm(ast
, 0x1E6E0040, 0xFF808000);
1610 moutdwm(ast
, 0x1E6E0044, 0x88848466);
1611 moutdwm(ast
, 0x1E6E0048, 0x44440008);
1612 moutdwm(ast
, 0x1E6E004C, 0x00000000);
1613 moutdwm(ast
, 0x1E6E0050, 0x80000000);
1614 moutdwm(ast
, 0x1E6E0050, 0x00000000);
1615 moutdwm(ast
, 0x1E6E0054, 0);
1616 moutdwm(ast
, 0x1E6E0060, param
->reg_DRV
);
1617 moutdwm(ast
, 0x1E6E006C, param
->reg_IOZ
);
1618 moutdwm(ast
, 0x1E6E0070, 0x00000000);
1619 moutdwm(ast
, 0x1E6E0074, 0x00000000);
1620 moutdwm(ast
, 0x1E6E0078, 0x00000000);
1621 moutdwm(ast
, 0x1E6E007C, 0x00000000);
1623 /* Wait MCLK2X lock to MCLK */
1625 data
= mindwm(ast
, 0x1E6E001C);
1626 } while (!(data
& 0x08000000));
1627 moutdwm(ast
, 0x1E6E0034, 0x00000001);
1628 moutdwm(ast
, 0x1E6E000C, 0x00005C04);
1630 moutdwm(ast
, 0x1E6E000C, 0x00000000);
1631 moutdwm(ast
, 0x1E6E0034, 0x00000000);
1632 data
= mindwm(ast
, 0x1E6E001C);
1633 data
= (data
>> 8) & 0xff;
1634 while ((data
& 0x08) || ((data
& 0x7) < 2) || (data
< 4)) {
1635 data2
= (mindwm(ast
, 0x1E6E0064) & 0xfff3ffff) + 4;
1636 if ((data2
& 0xff) > param
->madj_max
) {
1639 moutdwm(ast
, 0x1E6E0064, data2
);
1640 if (data2
& 0x00100000) {
1641 data2
= ((data2
& 0xff) >> 3) + 3;
1643 data2
= ((data2
& 0xff) >> 2) + 5;
1645 data
= mindwm(ast
, 0x1E6E0068) & 0xffff00ff;
1646 data2
+= data
& 0xff;
1647 data
= data
| (data2
<< 8);
1648 moutdwm(ast
, 0x1E6E0068, data
);
1650 moutdwm(ast
, 0x1E6E0064, mindwm(ast
, 0x1E6E0064) | 0xC0000);
1652 data
= mindwm(ast
, 0x1E6E0018) & 0xfffff1ff;
1653 moutdwm(ast
, 0x1E6E0018, data
);
1654 data
= data
| 0x200;
1655 moutdwm(ast
, 0x1E6E0018, data
);
1657 data
= mindwm(ast
, 0x1E6E001C);
1658 } while (!(data
& 0x08000000));
1660 moutdwm(ast
, 0x1E6E0034, 0x00000001);
1661 moutdwm(ast
, 0x1E6E000C, 0x00005C04);
1663 moutdwm(ast
, 0x1E6E000C, 0x00000000);
1664 moutdwm(ast
, 0x1E6E0034, 0x00000000);
1665 data
= mindwm(ast
, 0x1E6E001C);
1666 data
= (data
>> 8) & 0xff;
1668 data
= mindwm(ast
, 0x1E6E0018) | 0xC00;
1669 moutdwm(ast
, 0x1E6E0018, data
);
1671 moutdwm(ast
, 0x1E6E0034, 0x00000001);
1672 moutdwm(ast
, 0x1E6E000C, 0x00000000);
1674 /* Mode Register Setting */
1675 moutdwm(ast
, 0x1E6E002C, param
->reg_MRS
| 0x100);
1676 moutdwm(ast
, 0x1E6E0030, param
->reg_EMRS
);
1677 moutdwm(ast
, 0x1E6E0028, 0x00000005);
1678 moutdwm(ast
, 0x1E6E0028, 0x00000007);
1679 moutdwm(ast
, 0x1E6E0028, 0x00000003);
1680 moutdwm(ast
, 0x1E6E0028, 0x00000001);
1682 moutdwm(ast
, 0x1E6E000C, 0x00005C08);
1683 moutdwm(ast
, 0x1E6E002C, param
->reg_MRS
);
1684 moutdwm(ast
, 0x1E6E0028, 0x00000001);
1685 moutdwm(ast
, 0x1E6E0030, param
->reg_EMRS
| 0x380);
1686 moutdwm(ast
, 0x1E6E0028, 0x00000003);
1687 moutdwm(ast
, 0x1E6E0030, param
->reg_EMRS
);
1688 moutdwm(ast
, 0x1E6E0028, 0x00000003);
1690 moutdwm(ast
, 0x1E6E000C, 0x7FFF5C01);
1696 data
= data
| 0x3000 | ((param
->reg_AC2
& 0x60000) >> 3);
1698 moutdwm(ast
, 0x1E6E0034, data
| 0x3);
1699 moutdwm(ast
, 0x1E6E0120, param
->reg_FREQ
);
1701 /* Wait DQI delay lock */
1703 data
= mindwm(ast
, 0x1E6E0080);
1704 } while (!(data
& 0x40000000));
1705 /* Wait DQSI delay lock */
1707 data
= mindwm(ast
, 0x1E6E0020);
1708 } while (!(data
& 0x00000800));
1709 /* Calibrate the DQSI delay */
1710 cbr_dll2(ast
, param
);
1712 /* ECC Memory Initialization */
1714 moutdwm(ast
, 0x1E6E007C, 0x00000000);
1715 moutdwm(ast
, 0x1E6E0070, 0x221);
1717 data
= mindwm(ast
, 0x1E6E0070);
1718 } while (!(data
& 0x00001000));
1719 moutdwm(ast
, 0x1E6E0070, 0x00000000);
1720 moutdwm(ast
, 0x1E6E0050, 0x80000000);
1721 moutdwm(ast
, 0x1E6E0050, 0x00000000);
1726 static void ast_init_dram_2300(struct drm_device
*dev
)
1728 struct ast_private
*ast
= dev
->dev_private
;
1729 struct ast2300_dram_param param
;
1733 reg
= ast_get_index_reg_mask(ast
, AST_IO_CRTC_PORT
, 0xd0, 0xff);
1734 if ((reg
& 0x80) == 0) {/* vga only */
1735 ast_write32(ast
, 0xf004, 0x1e6e0000);
1736 ast_write32(ast
, 0xf000, 0x1);
1737 ast_write32(ast
, 0x12000, 0x1688a8a8);
1740 } while (ast_read32(ast
, 0x12000) != 0x1);
1742 ast_write32(ast
, 0x10000, 0xfc600309);
1745 } while (ast_read32(ast
, 0x10000) != 0x1);
1747 /* Slow down CPU/AHB CLK in VGA only mode */
1748 temp
= ast_read32(ast
, 0x12008);
1750 ast_write32(ast
, 0x12008, temp
);
1752 param
.dram_type
= AST_DDR3
;
1753 if (temp
& 0x01000000)
1754 param
.dram_type
= AST_DDR2
;
1755 param
.dram_chipid
= ast
->dram_type
;
1756 param
.dram_freq
= ast
->mclk
;
1757 param
.vram_size
= ast
->vram_size
;
1759 if (param
.dram_type
== AST_DDR3
) {
1760 get_ddr3_info(ast
, ¶m
);
1761 ddr3_init(ast
, ¶m
);
1763 get_ddr2_info(ast
, ¶m
);
1764 ddr2_init(ast
, ¶m
);
1767 temp
= mindwm(ast
, 0x1e6e2040);
1768 moutdwm(ast
, 0x1e6e2040, temp
| 0x40);
1773 reg
= ast_get_index_reg_mask(ast
, AST_IO_CRTC_PORT
, 0xd0, 0xff);
1774 } while ((reg
& 0x40) == 0);