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ARM: msm: USB_MSM_OTG needs USB_PHY
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-pxa.c
1 /*
2 * linux/arch/arm/plat-pxa/gpio.c
3 *
4 * Generic PXA GPIO handling
5 *
6 * Author: Nicolas Pitre
7 * Created: Jun 15, 2001
8 * Copyright: MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14 #include <linux/module.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio-pxa.h>
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/irqdomain.h>
22 #include <linux/io.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/platform_device.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/slab.h>
28
29 #include <asm/mach/irq.h>
30
31 #include <mach/irqs.h>
32
33 /*
34 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
35 * one set of registers. The register offsets are organized below:
36 *
37 * GPLR GPDR GPSR GPCR GRER GFER GEDR
38 * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
39 * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
40 * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
41 *
42 * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
43 * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
44 * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
45 *
46 * NOTE:
47 * BANK 3 is only available on PXA27x and later processors.
48 * BANK 4 and 5 are only available on PXA935
49 */
50
51 #define GPLR_OFFSET 0x00
52 #define GPDR_OFFSET 0x0C
53 #define GPSR_OFFSET 0x18
54 #define GPCR_OFFSET 0x24
55 #define GRER_OFFSET 0x30
56 #define GFER_OFFSET 0x3C
57 #define GEDR_OFFSET 0x48
58 #define GAFR_OFFSET 0x54
59 #define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
60
61 #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
62
63 int pxa_last_gpio;
64 static int irq_base;
65
66 #ifdef CONFIG_OF
67 static struct irq_domain *domain;
68 static struct device_node *pxa_gpio_of_node;
69 #endif
70
71 struct pxa_gpio_chip {
72 struct gpio_chip chip;
73 void __iomem *regbase;
74 char label[10];
75
76 unsigned long irq_mask;
77 unsigned long irq_edge_rise;
78 unsigned long irq_edge_fall;
79 int (*set_wake)(unsigned int gpio, unsigned int on);
80
81 #ifdef CONFIG_PM
82 unsigned long saved_gplr;
83 unsigned long saved_gpdr;
84 unsigned long saved_grer;
85 unsigned long saved_gfer;
86 #endif
87 };
88
89 enum pxa_gpio_type {
90 PXA25X_GPIO = 0,
91 PXA26X_GPIO,
92 PXA27X_GPIO,
93 PXA3XX_GPIO,
94 PXA93X_GPIO,
95 MMP_GPIO = 0x10,
96 MMP2_GPIO,
97 };
98
99 struct pxa_gpio_id {
100 enum pxa_gpio_type type;
101 int gpio_nums;
102 };
103
104 static DEFINE_SPINLOCK(gpio_lock);
105 static struct pxa_gpio_chip *pxa_gpio_chips;
106 static enum pxa_gpio_type gpio_type;
107 static void __iomem *gpio_reg_base;
108
109 static struct pxa_gpio_id pxa25x_id = {
110 .type = PXA25X_GPIO,
111 .gpio_nums = 85,
112 };
113
114 static struct pxa_gpio_id pxa26x_id = {
115 .type = PXA26X_GPIO,
116 .gpio_nums = 90,
117 };
118
119 static struct pxa_gpio_id pxa27x_id = {
120 .type = PXA27X_GPIO,
121 .gpio_nums = 121,
122 };
123
124 static struct pxa_gpio_id pxa3xx_id = {
125 .type = PXA3XX_GPIO,
126 .gpio_nums = 128,
127 };
128
129 static struct pxa_gpio_id pxa93x_id = {
130 .type = PXA93X_GPIO,
131 .gpio_nums = 192,
132 };
133
134 static struct pxa_gpio_id mmp_id = {
135 .type = MMP_GPIO,
136 .gpio_nums = 128,
137 };
138
139 static struct pxa_gpio_id mmp2_id = {
140 .type = MMP2_GPIO,
141 .gpio_nums = 192,
142 };
143
144 #define for_each_gpio_chip(i, c) \
145 for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
146
147 static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
148 {
149 return container_of(c, struct pxa_gpio_chip, chip)->regbase;
150 }
151
152 static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
153 {
154 return &pxa_gpio_chips[gpio_to_bank(gpio)];
155 }
156
157 static inline int gpio_is_pxa_type(int type)
158 {
159 return (type & MMP_GPIO) == 0;
160 }
161
162 static inline int gpio_is_mmp_type(int type)
163 {
164 return (type & MMP_GPIO) != 0;
165 }
166
167 /* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
168 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
169 */
170 static inline int __gpio_is_inverted(int gpio)
171 {
172 if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
173 return 1;
174 return 0;
175 }
176
177 /*
178 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
179 * function of a GPIO, and GPDRx cannot be altered once configured. It
180 * is attributed as "occupied" here (I know this terminology isn't
181 * accurate, you are welcome to propose a better one :-)
182 */
183 static inline int __gpio_is_occupied(unsigned gpio)
184 {
185 struct pxa_gpio_chip *pxachip;
186 void __iomem *base;
187 unsigned long gafr = 0, gpdr = 0;
188 int ret, af = 0, dir = 0;
189
190 pxachip = gpio_to_pxachip(gpio);
191 base = gpio_chip_base(&pxachip->chip);
192 gpdr = readl_relaxed(base + GPDR_OFFSET);
193
194 switch (gpio_type) {
195 case PXA25X_GPIO:
196 case PXA26X_GPIO:
197 case PXA27X_GPIO:
198 gafr = readl_relaxed(base + GAFR_OFFSET);
199 af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
200 dir = gpdr & GPIO_bit(gpio);
201
202 if (__gpio_is_inverted(gpio))
203 ret = (af != 1) || (dir == 0);
204 else
205 ret = (af != 0) || (dir != 0);
206 break;
207 default:
208 ret = gpdr & GPIO_bit(gpio);
209 break;
210 }
211 return ret;
212 }
213
214 static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
215 {
216 return chip->base + offset + irq_base;
217 }
218
219 int pxa_irq_to_gpio(int irq)
220 {
221 return irq - irq_base;
222 }
223
224 static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
225 {
226 void __iomem *base = gpio_chip_base(chip);
227 uint32_t value, mask = 1 << offset;
228 unsigned long flags;
229
230 spin_lock_irqsave(&gpio_lock, flags);
231
232 value = readl_relaxed(base + GPDR_OFFSET);
233 if (__gpio_is_inverted(chip->base + offset))
234 value |= mask;
235 else
236 value &= ~mask;
237 writel_relaxed(value, base + GPDR_OFFSET);
238
239 spin_unlock_irqrestore(&gpio_lock, flags);
240 return 0;
241 }
242
243 static int pxa_gpio_direction_output(struct gpio_chip *chip,
244 unsigned offset, int value)
245 {
246 void __iomem *base = gpio_chip_base(chip);
247 uint32_t tmp, mask = 1 << offset;
248 unsigned long flags;
249
250 writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
251
252 spin_lock_irqsave(&gpio_lock, flags);
253
254 tmp = readl_relaxed(base + GPDR_OFFSET);
255 if (__gpio_is_inverted(chip->base + offset))
256 tmp &= ~mask;
257 else
258 tmp |= mask;
259 writel_relaxed(tmp, base + GPDR_OFFSET);
260
261 spin_unlock_irqrestore(&gpio_lock, flags);
262 return 0;
263 }
264
265 static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
266 {
267 return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
268 }
269
270 static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
271 {
272 writel_relaxed(1 << offset, gpio_chip_base(chip) +
273 (value ? GPSR_OFFSET : GPCR_OFFSET));
274 }
275
276 #ifdef CONFIG_OF_GPIO
277 static int pxa_gpio_of_xlate(struct gpio_chip *gc,
278 const struct of_phandle_args *gpiospec,
279 u32 *flags)
280 {
281 if (gpiospec->args[0] > pxa_last_gpio)
282 return -EINVAL;
283
284 if (gc != &pxa_gpio_chips[gpiospec->args[0] / 32].chip)
285 return -EINVAL;
286
287 if (flags)
288 *flags = gpiospec->args[1];
289
290 return gpiospec->args[0] % 32;
291 }
292 #endif
293
294 static int pxa_init_gpio_chip(int gpio_end,
295 int (*set_wake)(unsigned int, unsigned int))
296 {
297 int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
298 struct pxa_gpio_chip *chips;
299
300 chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
301 if (chips == NULL) {
302 pr_err("%s: failed to allocate GPIO chips\n", __func__);
303 return -ENOMEM;
304 }
305
306 for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
307 struct gpio_chip *c = &chips[i].chip;
308
309 sprintf(chips[i].label, "gpio-%d", i);
310 chips[i].regbase = gpio_reg_base + BANK_OFF(i);
311 chips[i].set_wake = set_wake;
312
313 c->base = gpio;
314 c->label = chips[i].label;
315
316 c->direction_input = pxa_gpio_direction_input;
317 c->direction_output = pxa_gpio_direction_output;
318 c->get = pxa_gpio_get;
319 c->set = pxa_gpio_set;
320 c->to_irq = pxa_gpio_to_irq;
321 #ifdef CONFIG_OF_GPIO
322 c->of_node = pxa_gpio_of_node;
323 c->of_xlate = pxa_gpio_of_xlate;
324 c->of_gpio_n_cells = 2;
325 #endif
326
327 /* number of GPIOs on last bank may be less than 32 */
328 c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
329 gpiochip_add(c);
330 }
331 pxa_gpio_chips = chips;
332 return 0;
333 }
334
335 /* Update only those GRERx and GFERx edge detection register bits if those
336 * bits are set in c->irq_mask
337 */
338 static inline void update_edge_detect(struct pxa_gpio_chip *c)
339 {
340 uint32_t grer, gfer;
341
342 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
343 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
344 grer |= c->irq_edge_rise & c->irq_mask;
345 gfer |= c->irq_edge_fall & c->irq_mask;
346 writel_relaxed(grer, c->regbase + GRER_OFFSET);
347 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
348 }
349
350 static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
351 {
352 struct pxa_gpio_chip *c;
353 int gpio = pxa_irq_to_gpio(d->irq);
354 unsigned long gpdr, mask = GPIO_bit(gpio);
355
356 c = gpio_to_pxachip(gpio);
357
358 if (type == IRQ_TYPE_PROBE) {
359 /* Don't mess with enabled GPIOs using preconfigured edges or
360 * GPIOs set to alternate function or to output during probe
361 */
362 if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
363 return 0;
364
365 if (__gpio_is_occupied(gpio))
366 return 0;
367
368 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
369 }
370
371 gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
372
373 if (__gpio_is_inverted(gpio))
374 writel_relaxed(gpdr | mask, c->regbase + GPDR_OFFSET);
375 else
376 writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
377
378 if (type & IRQ_TYPE_EDGE_RISING)
379 c->irq_edge_rise |= mask;
380 else
381 c->irq_edge_rise &= ~mask;
382
383 if (type & IRQ_TYPE_EDGE_FALLING)
384 c->irq_edge_fall |= mask;
385 else
386 c->irq_edge_fall &= ~mask;
387
388 update_edge_detect(c);
389
390 pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
391 ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
392 ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
393 return 0;
394 }
395
396 static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
397 {
398 struct pxa_gpio_chip *c;
399 int loop, gpio, gpio_base, n;
400 unsigned long gedr;
401 struct irq_chip *chip = irq_desc_get_chip(desc);
402
403 chained_irq_enter(chip, desc);
404
405 do {
406 loop = 0;
407 for_each_gpio_chip(gpio, c) {
408 gpio_base = c->chip.base;
409
410 gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
411 gedr = gedr & c->irq_mask;
412 writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
413
414 for_each_set_bit(n, &gedr, BITS_PER_LONG) {
415 loop = 1;
416
417 generic_handle_irq(gpio_to_irq(gpio_base + n));
418 }
419 }
420 } while (loop);
421
422 chained_irq_exit(chip, desc);
423 }
424
425 static void pxa_ack_muxed_gpio(struct irq_data *d)
426 {
427 int gpio = pxa_irq_to_gpio(d->irq);
428 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
429
430 writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
431 }
432
433 static void pxa_mask_muxed_gpio(struct irq_data *d)
434 {
435 int gpio = pxa_irq_to_gpio(d->irq);
436 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
437 uint32_t grer, gfer;
438
439 c->irq_mask &= ~GPIO_bit(gpio);
440
441 grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
442 gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
443 writel_relaxed(grer, c->regbase + GRER_OFFSET);
444 writel_relaxed(gfer, c->regbase + GFER_OFFSET);
445 }
446
447 static int pxa_gpio_set_wake(struct irq_data *d, unsigned int on)
448 {
449 int gpio = pxa_irq_to_gpio(d->irq);
450 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
451
452 if (c->set_wake)
453 return c->set_wake(gpio, on);
454 else
455 return 0;
456 }
457
458 static void pxa_unmask_muxed_gpio(struct irq_data *d)
459 {
460 int gpio = pxa_irq_to_gpio(d->irq);
461 struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
462
463 c->irq_mask |= GPIO_bit(gpio);
464 update_edge_detect(c);
465 }
466
467 static struct irq_chip pxa_muxed_gpio_chip = {
468 .name = "GPIO",
469 .irq_ack = pxa_ack_muxed_gpio,
470 .irq_mask = pxa_mask_muxed_gpio,
471 .irq_unmask = pxa_unmask_muxed_gpio,
472 .irq_set_type = pxa_gpio_irq_type,
473 .irq_set_wake = pxa_gpio_set_wake,
474 };
475
476 static int pxa_gpio_nums(struct platform_device *pdev)
477 {
478 const struct platform_device_id *id = platform_get_device_id(pdev);
479 struct pxa_gpio_id *pxa_id = (struct pxa_gpio_id *)id->driver_data;
480 int count = 0;
481
482 switch (pxa_id->type) {
483 case PXA25X_GPIO:
484 case PXA26X_GPIO:
485 case PXA27X_GPIO:
486 case PXA3XX_GPIO:
487 case PXA93X_GPIO:
488 case MMP_GPIO:
489 case MMP2_GPIO:
490 gpio_type = pxa_id->type;
491 count = pxa_id->gpio_nums - 1;
492 break;
493 default:
494 count = -EINVAL;
495 break;
496 }
497 return count;
498 }
499
500 #ifdef CONFIG_OF
501 static struct of_device_id pxa_gpio_dt_ids[] = {
502 { .compatible = "intel,pxa25x-gpio", .data = &pxa25x_id, },
503 { .compatible = "intel,pxa26x-gpio", .data = &pxa26x_id, },
504 { .compatible = "intel,pxa27x-gpio", .data = &pxa27x_id, },
505 { .compatible = "intel,pxa3xx-gpio", .data = &pxa3xx_id, },
506 { .compatible = "marvell,pxa93x-gpio", .data = &pxa93x_id, },
507 { .compatible = "marvell,mmp-gpio", .data = &mmp_id, },
508 { .compatible = "marvell,mmp2-gpio", .data = &mmp2_id, },
509 {}
510 };
511
512 static int pxa_irq_domain_map(struct irq_domain *d, unsigned int irq,
513 irq_hw_number_t hw)
514 {
515 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
516 handle_edge_irq);
517 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
518 return 0;
519 }
520
521 const struct irq_domain_ops pxa_irq_domain_ops = {
522 .map = pxa_irq_domain_map,
523 .xlate = irq_domain_xlate_twocell,
524 };
525
526 static int pxa_gpio_probe_dt(struct platform_device *pdev)
527 {
528 int ret, nr_gpios;
529 struct device_node *prev, *next, *np = pdev->dev.of_node;
530 const struct of_device_id *of_id =
531 of_match_device(pxa_gpio_dt_ids, &pdev->dev);
532 const struct pxa_gpio_id *gpio_id;
533
534 if (!of_id || !of_id->data) {
535 dev_err(&pdev->dev, "Failed to find gpio controller\n");
536 return -EFAULT;
537 }
538 gpio_id = of_id->data;
539 gpio_type = gpio_id->type;
540
541 next = of_get_next_child(np, NULL);
542 prev = next;
543 if (!next) {
544 dev_err(&pdev->dev, "Failed to find child gpio node\n");
545 ret = -EINVAL;
546 goto err;
547 }
548 of_node_put(prev);
549 nr_gpios = gpio_id->gpio_nums;
550 pxa_last_gpio = nr_gpios - 1;
551
552 irq_base = irq_alloc_descs(-1, 0, nr_gpios, 0);
553 if (irq_base < 0) {
554 dev_err(&pdev->dev, "Failed to allocate IRQ numbers\n");
555 goto err;
556 }
557 domain = irq_domain_add_legacy(np, nr_gpios, irq_base, 0,
558 &pxa_irq_domain_ops, NULL);
559 pxa_gpio_of_node = np;
560 return 0;
561 err:
562 iounmap(gpio_reg_base);
563 return ret;
564 }
565 #else
566 #define pxa_gpio_probe_dt(pdev) (-1)
567 #endif
568
569 static int pxa_gpio_probe(struct platform_device *pdev)
570 {
571 struct pxa_gpio_chip *c;
572 struct resource *res;
573 struct clk *clk;
574 struct pxa_gpio_platform_data *info;
575 int gpio, irq, ret, use_of = 0;
576 int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
577
578 info = dev_get_platdata(&pdev->dev);
579 if (info) {
580 irq_base = info->irq_base;
581 if (irq_base <= 0)
582 return -EINVAL;
583 pxa_last_gpio = pxa_gpio_nums(pdev);
584 } else {
585 irq_base = 0;
586 use_of = 1;
587 ret = pxa_gpio_probe_dt(pdev);
588 if (ret < 0)
589 return -EINVAL;
590 }
591
592 if (!pxa_last_gpio)
593 return -EINVAL;
594
595 irq0 = platform_get_irq_byname(pdev, "gpio0");
596 irq1 = platform_get_irq_byname(pdev, "gpio1");
597 irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
598 if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
599 || (irq_mux <= 0))
600 return -EINVAL;
601 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
602 if (!res)
603 return -EINVAL;
604 gpio_reg_base = ioremap(res->start, resource_size(res));
605 if (!gpio_reg_base)
606 return -EINVAL;
607
608 if (irq0 > 0)
609 gpio_offset = 2;
610
611 clk = clk_get(&pdev->dev, NULL);
612 if (IS_ERR(clk)) {
613 dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
614 PTR_ERR(clk));
615 iounmap(gpio_reg_base);
616 return PTR_ERR(clk);
617 }
618 ret = clk_prepare_enable(clk);
619 if (ret) {
620 clk_put(clk);
621 iounmap(gpio_reg_base);
622 return ret;
623 }
624
625 /* Initialize GPIO chips */
626 pxa_init_gpio_chip(pxa_last_gpio, info ? info->gpio_set_wake : NULL);
627
628 /* clear all GPIO edge detects */
629 for_each_gpio_chip(gpio, c) {
630 writel_relaxed(0, c->regbase + GFER_OFFSET);
631 writel_relaxed(0, c->regbase + GRER_OFFSET);
632 writel_relaxed(~0,c->regbase + GEDR_OFFSET);
633 /* unmask GPIO edge detect for AP side */
634 if (gpio_is_mmp_type(gpio_type))
635 writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
636 }
637
638 if (!use_of) {
639 #ifdef CONFIG_ARCH_PXA
640 irq = gpio_to_irq(0);
641 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
642 handle_edge_irq);
643 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
644 irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
645
646 irq = gpio_to_irq(1);
647 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
648 handle_edge_irq);
649 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
650 irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
651 #endif
652
653 for (irq = gpio_to_irq(gpio_offset);
654 irq <= gpio_to_irq(pxa_last_gpio); irq++) {
655 irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
656 handle_edge_irq);
657 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
658 }
659 }
660
661 irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
662 return 0;
663 }
664
665 static const struct platform_device_id gpio_id_table[] = {
666 { "pxa25x-gpio", (unsigned long)&pxa25x_id },
667 { "pxa26x-gpio", (unsigned long)&pxa26x_id },
668 { "pxa27x-gpio", (unsigned long)&pxa27x_id },
669 { "pxa3xx-gpio", (unsigned long)&pxa3xx_id },
670 { "pxa93x-gpio", (unsigned long)&pxa93x_id },
671 { "mmp-gpio", (unsigned long)&mmp_id },
672 { "mmp2-gpio", (unsigned long)&mmp2_id },
673 { },
674 };
675
676 static struct platform_driver pxa_gpio_driver = {
677 .probe = pxa_gpio_probe,
678 .driver = {
679 .name = "pxa-gpio",
680 .of_match_table = of_match_ptr(pxa_gpio_dt_ids),
681 },
682 .id_table = gpio_id_table,
683 };
684 module_platform_driver(pxa_gpio_driver);
685
686 #ifdef CONFIG_PM
687 static int pxa_gpio_suspend(void)
688 {
689 struct pxa_gpio_chip *c;
690 int gpio;
691
692 for_each_gpio_chip(gpio, c) {
693 c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
694 c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
695 c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
696 c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
697
698 /* Clear GPIO transition detect bits */
699 writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
700 }
701 return 0;
702 }
703
704 static void pxa_gpio_resume(void)
705 {
706 struct pxa_gpio_chip *c;
707 int gpio;
708
709 for_each_gpio_chip(gpio, c) {
710 /* restore level with set/clear */
711 writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
712 writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
713
714 writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
715 writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
716 writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
717 }
718 }
719 #else
720 #define pxa_gpio_suspend NULL
721 #define pxa_gpio_resume NULL
722 #endif
723
724 struct syscore_ops pxa_gpio_syscore_ops = {
725 .suspend = pxa_gpio_suspend,
726 .resume = pxa_gpio_resume,
727 };
728
729 static int __init pxa_gpio_sysinit(void)
730 {
731 register_syscore_ops(&pxa_gpio_syscore_ops);
732 return 0;
733 }
734 postcore_initcall(pxa_gpio_sysinit);
kernel source for telekom puls (alcatel/mediatek)