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Merge tag 'v3.10.58' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / dma / ste_dma40.c
1 /*
2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/export.h>
13 #include <linux/dmaengine.h>
14 #include <linux/platform_device.h>
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/err.h>
20 #include <linux/amba/bus.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/platform_data/dma-ste-dma40.h>
23
24 #include "dmaengine.h"
25 #include "ste_dma40_ll.h"
26
27 #define D40_NAME "dma40"
28
29 #define D40_PHY_CHAN -1
30
31 /* For masking out/in 2 bit channel positions */
32 #define D40_CHAN_POS(chan) (2 * (chan / 2))
33 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
34
35 /* Maximum iterations taken before giving up suspending a channel */
36 #define D40_SUSPEND_MAX_IT 500
37
38 /* Milliseconds */
39 #define DMA40_AUTOSUSPEND_DELAY 100
40
41 /* Hardware requirement on LCLA alignment */
42 #define LCLA_ALIGNMENT 0x40000
43
44 /* Max number of links per event group */
45 #define D40_LCLA_LINK_PER_EVENT_GRP 128
46 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
47
48 /* Attempts before giving up to trying to get pages that are aligned */
49 #define MAX_LCLA_ALLOC_ATTEMPTS 256
50
51 /* Bit markings for allocation map */
52 #define D40_ALLOC_FREE (1 << 31)
53 #define D40_ALLOC_PHY (1 << 30)
54 #define D40_ALLOC_LOG_FREE 0
55
56 #define MAX(a, b) (((a) < (b)) ? (b) : (a))
57
58 /**
59 * enum 40_command - The different commands and/or statuses.
60 *
61 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
62 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
63 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
64 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
65 */
66 enum d40_command {
67 D40_DMA_STOP = 0,
68 D40_DMA_RUN = 1,
69 D40_DMA_SUSPEND_REQ = 2,
70 D40_DMA_SUSPENDED = 3
71 };
72
73 /*
74 * enum d40_events - The different Event Enables for the event lines.
75 *
76 * @D40_DEACTIVATE_EVENTLINE: De-activate Event line, stopping the logical chan.
77 * @D40_ACTIVATE_EVENTLINE: Activate the Event line, to start a logical chan.
78 * @D40_SUSPEND_REQ_EVENTLINE: Requesting for suspending a event line.
79 * @D40_ROUND_EVENTLINE: Status check for event line.
80 */
81
82 enum d40_events {
83 D40_DEACTIVATE_EVENTLINE = 0,
84 D40_ACTIVATE_EVENTLINE = 1,
85 D40_SUSPEND_REQ_EVENTLINE = 2,
86 D40_ROUND_EVENTLINE = 3
87 };
88
89 /*
90 * These are the registers that has to be saved and later restored
91 * when the DMA hw is powered off.
92 * TODO: Add save/restore of D40_DREG_GCC on dma40 v3 or later, if that works.
93 */
94 static u32 d40_backup_regs[] = {
95 D40_DREG_LCPA,
96 D40_DREG_LCLA,
97 D40_DREG_PRMSE,
98 D40_DREG_PRMSO,
99 D40_DREG_PRMOE,
100 D40_DREG_PRMOO,
101 };
102
103 #define BACKUP_REGS_SZ ARRAY_SIZE(d40_backup_regs)
104
105 /*
106 * since 9540 and 8540 has the same HW revision
107 * use v4a for 9540 or ealier
108 * use v4b for 8540 or later
109 * HW revision:
110 * DB8500ed has revision 0
111 * DB8500v1 has revision 2
112 * DB8500v2 has revision 3
113 * AP9540v1 has revision 4
114 * DB8540v1 has revision 4
115 * TODO: Check if all these registers have to be saved/restored on dma40 v4a
116 */
117 static u32 d40_backup_regs_v4a[] = {
118 D40_DREG_PSEG1,
119 D40_DREG_PSEG2,
120 D40_DREG_PSEG3,
121 D40_DREG_PSEG4,
122 D40_DREG_PCEG1,
123 D40_DREG_PCEG2,
124 D40_DREG_PCEG3,
125 D40_DREG_PCEG4,
126 D40_DREG_RSEG1,
127 D40_DREG_RSEG2,
128 D40_DREG_RSEG3,
129 D40_DREG_RSEG4,
130 D40_DREG_RCEG1,
131 D40_DREG_RCEG2,
132 D40_DREG_RCEG3,
133 D40_DREG_RCEG4,
134 };
135
136 #define BACKUP_REGS_SZ_V4A ARRAY_SIZE(d40_backup_regs_v4a)
137
138 static u32 d40_backup_regs_v4b[] = {
139 D40_DREG_CPSEG1,
140 D40_DREG_CPSEG2,
141 D40_DREG_CPSEG3,
142 D40_DREG_CPSEG4,
143 D40_DREG_CPSEG5,
144 D40_DREG_CPCEG1,
145 D40_DREG_CPCEG2,
146 D40_DREG_CPCEG3,
147 D40_DREG_CPCEG4,
148 D40_DREG_CPCEG5,
149 D40_DREG_CRSEG1,
150 D40_DREG_CRSEG2,
151 D40_DREG_CRSEG3,
152 D40_DREG_CRSEG4,
153 D40_DREG_CRSEG5,
154 D40_DREG_CRCEG1,
155 D40_DREG_CRCEG2,
156 D40_DREG_CRCEG3,
157 D40_DREG_CRCEG4,
158 D40_DREG_CRCEG5,
159 };
160
161 #define BACKUP_REGS_SZ_V4B ARRAY_SIZE(d40_backup_regs_v4b)
162
163 static u32 d40_backup_regs_chan[] = {
164 D40_CHAN_REG_SSCFG,
165 D40_CHAN_REG_SSELT,
166 D40_CHAN_REG_SSPTR,
167 D40_CHAN_REG_SSLNK,
168 D40_CHAN_REG_SDCFG,
169 D40_CHAN_REG_SDELT,
170 D40_CHAN_REG_SDPTR,
171 D40_CHAN_REG_SDLNK,
172 };
173
174 /**
175 * struct d40_interrupt_lookup - lookup table for interrupt handler
176 *
177 * @src: Interrupt mask register.
178 * @clr: Interrupt clear register.
179 * @is_error: true if this is an error interrupt.
180 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
181 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
182 */
183 struct d40_interrupt_lookup {
184 u32 src;
185 u32 clr;
186 bool is_error;
187 int offset;
188 };
189
190
191 static struct d40_interrupt_lookup il_v4a[] = {
192 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
193 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
194 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
195 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
196 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
197 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
198 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
199 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
200 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
201 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
202 };
203
204 static struct d40_interrupt_lookup il_v4b[] = {
205 {D40_DREG_CLCTIS1, D40_DREG_CLCICR1, false, 0},
206 {D40_DREG_CLCTIS2, D40_DREG_CLCICR2, false, 32},
207 {D40_DREG_CLCTIS3, D40_DREG_CLCICR3, false, 64},
208 {D40_DREG_CLCTIS4, D40_DREG_CLCICR4, false, 96},
209 {D40_DREG_CLCTIS5, D40_DREG_CLCICR5, false, 128},
210 {D40_DREG_CLCEIS1, D40_DREG_CLCICR1, true, 0},
211 {D40_DREG_CLCEIS2, D40_DREG_CLCICR2, true, 32},
212 {D40_DREG_CLCEIS3, D40_DREG_CLCICR3, true, 64},
213 {D40_DREG_CLCEIS4, D40_DREG_CLCICR4, true, 96},
214 {D40_DREG_CLCEIS5, D40_DREG_CLCICR5, true, 128},
215 {D40_DREG_CPCTIS, D40_DREG_CPCICR, false, D40_PHY_CHAN},
216 {D40_DREG_CPCEIS, D40_DREG_CPCICR, true, D40_PHY_CHAN},
217 };
218
219 /**
220 * struct d40_reg_val - simple lookup struct
221 *
222 * @reg: The register.
223 * @val: The value that belongs to the register in reg.
224 */
225 struct d40_reg_val {
226 unsigned int reg;
227 unsigned int val;
228 };
229
230 static __initdata struct d40_reg_val dma_init_reg_v4a[] = {
231 /* Clock every part of the DMA block from start */
232 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
233
234 /* Interrupts on all logical channels */
235 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
236 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
237 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
238 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
239 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
240 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
241 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
242 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
243 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
244 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
245 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
246 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
247 };
248 static __initdata struct d40_reg_val dma_init_reg_v4b[] = {
249 /* Clock every part of the DMA block from start */
250 { .reg = D40_DREG_GCC, .val = D40_DREG_GCC_ENABLE_ALL},
251
252 /* Interrupts on all logical channels */
253 { .reg = D40_DREG_CLCMIS1, .val = 0xFFFFFFFF},
254 { .reg = D40_DREG_CLCMIS2, .val = 0xFFFFFFFF},
255 { .reg = D40_DREG_CLCMIS3, .val = 0xFFFFFFFF},
256 { .reg = D40_DREG_CLCMIS4, .val = 0xFFFFFFFF},
257 { .reg = D40_DREG_CLCMIS5, .val = 0xFFFFFFFF},
258 { .reg = D40_DREG_CLCICR1, .val = 0xFFFFFFFF},
259 { .reg = D40_DREG_CLCICR2, .val = 0xFFFFFFFF},
260 { .reg = D40_DREG_CLCICR3, .val = 0xFFFFFFFF},
261 { .reg = D40_DREG_CLCICR4, .val = 0xFFFFFFFF},
262 { .reg = D40_DREG_CLCICR5, .val = 0xFFFFFFFF},
263 { .reg = D40_DREG_CLCTIS1, .val = 0xFFFFFFFF},
264 { .reg = D40_DREG_CLCTIS2, .val = 0xFFFFFFFF},
265 { .reg = D40_DREG_CLCTIS3, .val = 0xFFFFFFFF},
266 { .reg = D40_DREG_CLCTIS4, .val = 0xFFFFFFFF},
267 { .reg = D40_DREG_CLCTIS5, .val = 0xFFFFFFFF}
268 };
269
270 /**
271 * struct d40_lli_pool - Structure for keeping LLIs in memory
272 *
273 * @base: Pointer to memory area when the pre_alloc_lli's are not large
274 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
275 * pre_alloc_lli is used.
276 * @dma_addr: DMA address, if mapped
277 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
278 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
279 * one buffer to one buffer.
280 */
281 struct d40_lli_pool {
282 void *base;
283 int size;
284 dma_addr_t dma_addr;
285 /* Space for dst and src, plus an extra for padding */
286 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
287 };
288
289 /**
290 * struct d40_desc - A descriptor is one DMA job.
291 *
292 * @lli_phy: LLI settings for physical channel. Both src and dst=
293 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
294 * lli_len equals one.
295 * @lli_log: Same as above but for logical channels.
296 * @lli_pool: The pool with two entries pre-allocated.
297 * @lli_len: Number of llis of current descriptor.
298 * @lli_current: Number of transferred llis.
299 * @lcla_alloc: Number of LCLA entries allocated.
300 * @txd: DMA engine struct. Used for among other things for communication
301 * during a transfer.
302 * @node: List entry.
303 * @is_in_client_list: true if the client owns this descriptor.
304 * @cyclic: true if this is a cyclic job
305 *
306 * This descriptor is used for both logical and physical transfers.
307 */
308 struct d40_desc {
309 /* LLI physical */
310 struct d40_phy_lli_bidir lli_phy;
311 /* LLI logical */
312 struct d40_log_lli_bidir lli_log;
313
314 struct d40_lli_pool lli_pool;
315 int lli_len;
316 int lli_current;
317 int lcla_alloc;
318
319 struct dma_async_tx_descriptor txd;
320 struct list_head node;
321
322 bool is_in_client_list;
323 bool cyclic;
324 };
325
326 /**
327 * struct d40_lcla_pool - LCLA pool settings and data.
328 *
329 * @base: The virtual address of LCLA. 18 bit aligned.
330 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
331 * This pointer is only there for clean-up on error.
332 * @pages: The number of pages needed for all physical channels.
333 * Only used later for clean-up on error
334 * @lock: Lock to protect the content in this struct.
335 * @alloc_map: big map over which LCLA entry is own by which job.
336 */
337 struct d40_lcla_pool {
338 void *base;
339 dma_addr_t dma_addr;
340 void *base_unaligned;
341 int pages;
342 spinlock_t lock;
343 struct d40_desc **alloc_map;
344 };
345
346 /**
347 * struct d40_phy_res - struct for handling eventlines mapped to physical
348 * channels.
349 *
350 * @lock: A lock protection this entity.
351 * @reserved: True if used by secure world or otherwise.
352 * @num: The physical channel number of this entity.
353 * @allocated_src: Bit mapped to show which src event line's are mapped to
354 * this physical channel. Can also be free or physically allocated.
355 * @allocated_dst: Same as for src but is dst.
356 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
357 * event line number.
358 * @use_soft_lli: To mark if the linked lists of channel are managed by SW.
359 */
360 struct d40_phy_res {
361 spinlock_t lock;
362 bool reserved;
363 int num;
364 u32 allocated_src;
365 u32 allocated_dst;
366 bool use_soft_lli;
367 };
368
369 struct d40_base;
370
371 /**
372 * struct d40_chan - Struct that describes a channel.
373 *
374 * @lock: A spinlock to protect this struct.
375 * @log_num: The logical number, if any of this channel.
376 * @pending_tx: The number of pending transfers. Used between interrupt handler
377 * and tasklet.
378 * @busy: Set to true when transfer is ongoing on this channel.
379 * @phy_chan: Pointer to physical channel which this instance runs on. If this
380 * point is NULL, then the channel is not allocated.
381 * @chan: DMA engine handle.
382 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
383 * transfer and call client callback.
384 * @client: Cliented owned descriptor list.
385 * @pending_queue: Submitted jobs, to be issued by issue_pending()
386 * @active: Active descriptor.
387 * @done: Completed jobs
388 * @queue: Queued jobs.
389 * @prepare_queue: Prepared jobs.
390 * @dma_cfg: The client configuration of this dma channel.
391 * @configured: whether the dma_cfg configuration is valid
392 * @base: Pointer to the device instance struct.
393 * @src_def_cfg: Default cfg register setting for src.
394 * @dst_def_cfg: Default cfg register setting for dst.
395 * @log_def: Default logical channel settings.
396 * @lcpa: Pointer to dst and src lcpa settings.
397 * @runtime_addr: runtime configured address.
398 * @runtime_direction: runtime configured direction.
399 *
400 * This struct can either "be" a logical or a physical channel.
401 */
402 struct d40_chan {
403 spinlock_t lock;
404 int log_num;
405 int pending_tx;
406 bool busy;
407 struct d40_phy_res *phy_chan;
408 struct dma_chan chan;
409 struct tasklet_struct tasklet;
410 struct list_head client;
411 struct list_head pending_queue;
412 struct list_head active;
413 struct list_head done;
414 struct list_head queue;
415 struct list_head prepare_queue;
416 struct stedma40_chan_cfg dma_cfg;
417 bool configured;
418 struct d40_base *base;
419 /* Default register configurations */
420 u32 src_def_cfg;
421 u32 dst_def_cfg;
422 struct d40_def_lcsp log_def;
423 struct d40_log_lli_full *lcpa;
424 /* Runtime reconfiguration */
425 dma_addr_t runtime_addr;
426 enum dma_transfer_direction runtime_direction;
427 };
428
429 /**
430 * struct d40_gen_dmac - generic values to represent u8500/u8540 DMA
431 * controller
432 *
433 * @backup: the pointer to the registers address array for backup
434 * @backup_size: the size of the registers address array for backup
435 * @realtime_en: the realtime enable register
436 * @realtime_clear: the realtime clear register
437 * @high_prio_en: the high priority enable register
438 * @high_prio_clear: the high priority clear register
439 * @interrupt_en: the interrupt enable register
440 * @interrupt_clear: the interrupt clear register
441 * @il: the pointer to struct d40_interrupt_lookup
442 * @il_size: the size of d40_interrupt_lookup array
443 * @init_reg: the pointer to the struct d40_reg_val
444 * @init_reg_size: the size of d40_reg_val array
445 */
446 struct d40_gen_dmac {
447 u32 *backup;
448 u32 backup_size;
449 u32 realtime_en;
450 u32 realtime_clear;
451 u32 high_prio_en;
452 u32 high_prio_clear;
453 u32 interrupt_en;
454 u32 interrupt_clear;
455 struct d40_interrupt_lookup *il;
456 u32 il_size;
457 struct d40_reg_val *init_reg;
458 u32 init_reg_size;
459 };
460
461 /**
462 * struct d40_base - The big global struct, one for each probe'd instance.
463 *
464 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
465 * @execmd_lock: Lock for execute command usage since several channels share
466 * the same physical register.
467 * @dev: The device structure.
468 * @virtbase: The virtual base address of the DMA's register.
469 * @rev: silicon revision detected.
470 * @clk: Pointer to the DMA clock structure.
471 * @phy_start: Physical memory start of the DMA registers.
472 * @phy_size: Size of the DMA register map.
473 * @irq: The IRQ number.
474 * @num_phy_chans: The number of physical channels. Read from HW. This
475 * is the number of available channels for this driver, not counting "Secure
476 * mode" allocated physical channels.
477 * @num_log_chans: The number of logical channels. Calculated from
478 * num_phy_chans.
479 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
480 * @dma_slave: dma_device channels that can do only do slave transfers.
481 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
482 * @phy_chans: Room for all possible physical channels in system.
483 * @log_chans: Room for all possible logical channels in system.
484 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
485 * to log_chans entries.
486 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
487 * to phy_chans entries.
488 * @plat_data: Pointer to provided platform_data which is the driver
489 * configuration.
490 * @lcpa_regulator: Pointer to hold the regulator for the esram bank for lcla.
491 * @phy_res: Vector containing all physical channels.
492 * @lcla_pool: lcla pool settings and data.
493 * @lcpa_base: The virtual mapped address of LCPA.
494 * @phy_lcpa: The physical address of the LCPA.
495 * @lcpa_size: The size of the LCPA area.
496 * @desc_slab: cache for descriptors.
497 * @reg_val_backup: Here the values of some hardware registers are stored
498 * before the DMA is powered off. They are restored when the power is back on.
499 * @reg_val_backup_v4: Backup of registers that only exits on dma40 v3 and
500 * later
501 * @reg_val_backup_chan: Backup data for standard channel parameter registers.
502 * @gcc_pwr_off_mask: Mask to maintain the channels that can be turned off.
503 * @initialized: true if the dma has been initialized
504 * @gen_dmac: the struct for generic registers values to represent u8500/8540
505 * DMA controller
506 */
507 struct d40_base {
508 spinlock_t interrupt_lock;
509 spinlock_t execmd_lock;
510 struct device *dev;
511 void __iomem *virtbase;
512 u8 rev:4;
513 struct clk *clk;
514 phys_addr_t phy_start;
515 resource_size_t phy_size;
516 int irq;
517 int num_phy_chans;
518 int num_log_chans;
519 struct device_dma_parameters dma_parms;
520 struct dma_device dma_both;
521 struct dma_device dma_slave;
522 struct dma_device dma_memcpy;
523 struct d40_chan *phy_chans;
524 struct d40_chan *log_chans;
525 struct d40_chan **lookup_log_chans;
526 struct d40_chan **lookup_phy_chans;
527 struct stedma40_platform_data *plat_data;
528 struct regulator *lcpa_regulator;
529 /* Physical half channels */
530 struct d40_phy_res *phy_res;
531 struct d40_lcla_pool lcla_pool;
532 void *lcpa_base;
533 dma_addr_t phy_lcpa;
534 resource_size_t lcpa_size;
535 struct kmem_cache *desc_slab;
536 u32 reg_val_backup[BACKUP_REGS_SZ];
537 u32 reg_val_backup_v4[MAX(BACKUP_REGS_SZ_V4A, BACKUP_REGS_SZ_V4B)];
538 u32 *reg_val_backup_chan;
539 u16 gcc_pwr_off_mask;
540 bool initialized;
541 struct d40_gen_dmac gen_dmac;
542 };
543
544 static struct device *chan2dev(struct d40_chan *d40c)
545 {
546 return &d40c->chan.dev->device;
547 }
548
549 static bool chan_is_physical(struct d40_chan *chan)
550 {
551 return chan->log_num == D40_PHY_CHAN;
552 }
553
554 static bool chan_is_logical(struct d40_chan *chan)
555 {
556 return !chan_is_physical(chan);
557 }
558
559 static void __iomem *chan_base(struct d40_chan *chan)
560 {
561 return chan->base->virtbase + D40_DREG_PCBASE +
562 chan->phy_chan->num * D40_DREG_PCDELTA;
563 }
564
565 #define d40_err(dev, format, arg...) \
566 dev_err(dev, "[%s] " format, __func__, ## arg)
567
568 #define chan_err(d40c, format, arg...) \
569 d40_err(chan2dev(d40c), format, ## arg)
570
571 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
572 int lli_len)
573 {
574 bool is_log = chan_is_logical(d40c);
575 u32 align;
576 void *base;
577
578 if (is_log)
579 align = sizeof(struct d40_log_lli);
580 else
581 align = sizeof(struct d40_phy_lli);
582
583 if (lli_len == 1) {
584 base = d40d->lli_pool.pre_alloc_lli;
585 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
586 d40d->lli_pool.base = NULL;
587 } else {
588 d40d->lli_pool.size = lli_len * 2 * align;
589
590 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
591 d40d->lli_pool.base = base;
592
593 if (d40d->lli_pool.base == NULL)
594 return -ENOMEM;
595 }
596
597 if (is_log) {
598 d40d->lli_log.src = PTR_ALIGN(base, align);
599 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
600
601 d40d->lli_pool.dma_addr = 0;
602 } else {
603 d40d->lli_phy.src = PTR_ALIGN(base, align);
604 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
605
606 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
607 d40d->lli_phy.src,
608 d40d->lli_pool.size,
609 DMA_TO_DEVICE);
610
611 if (dma_mapping_error(d40c->base->dev,
612 d40d->lli_pool.dma_addr)) {
613 kfree(d40d->lli_pool.base);
614 d40d->lli_pool.base = NULL;
615 d40d->lli_pool.dma_addr = 0;
616 return -ENOMEM;
617 }
618 }
619
620 return 0;
621 }
622
623 static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
624 {
625 if (d40d->lli_pool.dma_addr)
626 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
627 d40d->lli_pool.size, DMA_TO_DEVICE);
628
629 kfree(d40d->lli_pool.base);
630 d40d->lli_pool.base = NULL;
631 d40d->lli_pool.size = 0;
632 d40d->lli_log.src = NULL;
633 d40d->lli_log.dst = NULL;
634 d40d->lli_phy.src = NULL;
635 d40d->lli_phy.dst = NULL;
636 }
637
638 static int d40_lcla_alloc_one(struct d40_chan *d40c,
639 struct d40_desc *d40d)
640 {
641 unsigned long flags;
642 int i;
643 int ret = -EINVAL;
644
645 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
646
647 /*
648 * Allocate both src and dst at the same time, therefore the half
649 * start on 1 since 0 can't be used since zero is used as end marker.
650 */
651 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
652 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
653
654 if (!d40c->base->lcla_pool.alloc_map[idx]) {
655 d40c->base->lcla_pool.alloc_map[idx] = d40d;
656 d40d->lcla_alloc++;
657 ret = i;
658 break;
659 }
660 }
661
662 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
663
664 return ret;
665 }
666
667 static int d40_lcla_free_all(struct d40_chan *d40c,
668 struct d40_desc *d40d)
669 {
670 unsigned long flags;
671 int i;
672 int ret = -EINVAL;
673
674 if (chan_is_physical(d40c))
675 return 0;
676
677 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
678
679 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
680 int idx = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP + i;
681
682 if (d40c->base->lcla_pool.alloc_map[idx] == d40d) {
683 d40c->base->lcla_pool.alloc_map[idx] = NULL;
684 d40d->lcla_alloc--;
685 if (d40d->lcla_alloc == 0) {
686 ret = 0;
687 break;
688 }
689 }
690 }
691
692 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
693
694 return ret;
695
696 }
697
698 static void d40_desc_remove(struct d40_desc *d40d)
699 {
700 list_del(&d40d->node);
701 }
702
703 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
704 {
705 struct d40_desc *desc = NULL;
706
707 if (!list_empty(&d40c->client)) {
708 struct d40_desc *d;
709 struct d40_desc *_d;
710
711 list_for_each_entry_safe(d, _d, &d40c->client, node) {
712 if (async_tx_test_ack(&d->txd)) {
713 d40_desc_remove(d);
714 desc = d;
715 memset(desc, 0, sizeof(*desc));
716 break;
717 }
718 }
719 }
720
721 if (!desc)
722 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
723
724 if (desc)
725 INIT_LIST_HEAD(&desc->node);
726
727 return desc;
728 }
729
730 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
731 {
732
733 d40_pool_lli_free(d40c, d40d);
734 d40_lcla_free_all(d40c, d40d);
735 kmem_cache_free(d40c->base->desc_slab, d40d);
736 }
737
738 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
739 {
740 list_add_tail(&desc->node, &d40c->active);
741 }
742
743 static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
744 {
745 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
746 struct d40_phy_lli *lli_src = desc->lli_phy.src;
747 void __iomem *base = chan_base(chan);
748
749 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
750 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
751 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
752 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
753
754 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
755 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
756 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
757 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
758 }
759
760 static void d40_desc_done(struct d40_chan *d40c, struct d40_desc *desc)
761 {
762 list_add_tail(&desc->node, &d40c->done);
763 }
764
765 static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
766 {
767 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
768 struct d40_log_lli_bidir *lli = &desc->lli_log;
769 int lli_current = desc->lli_current;
770 int lli_len = desc->lli_len;
771 bool cyclic = desc->cyclic;
772 int curr_lcla = -EINVAL;
773 int first_lcla = 0;
774 bool use_esram_lcla = chan->base->plat_data->use_esram_lcla;
775 bool linkback;
776
777 /*
778 * We may have partially running cyclic transfers, in case we did't get
779 * enough LCLA entries.
780 */
781 linkback = cyclic && lli_current == 0;
782
783 /*
784 * For linkback, we need one LCLA even with only one link, because we
785 * can't link back to the one in LCPA space
786 */
787 if (linkback || (lli_len - lli_current > 1)) {
788 /*
789 * If the channel is expected to use only soft_lli don't
790 * allocate a lcla. This is to avoid a HW issue that exists
791 * in some controller during a peripheral to memory transfer
792 * that uses linked lists.
793 */
794 if (!(chan->phy_chan->use_soft_lli &&
795 chan->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM))
796 curr_lcla = d40_lcla_alloc_one(chan, desc);
797
798 first_lcla = curr_lcla;
799 }
800
801 /*
802 * For linkback, we normally load the LCPA in the loop since we need to
803 * link it to the second LCLA and not the first. However, if we
804 * couldn't even get a first LCLA, then we have to run in LCPA and
805 * reload manually.
806 */
807 if (!linkback || curr_lcla == -EINVAL) {
808 unsigned int flags = 0;
809
810 if (curr_lcla == -EINVAL)
811 flags |= LLI_TERM_INT;
812
813 d40_log_lli_lcpa_write(chan->lcpa,
814 &lli->dst[lli_current],
815 &lli->src[lli_current],
816 curr_lcla,
817 flags);
818 lli_current++;
819 }
820
821 if (curr_lcla < 0)
822 goto out;
823
824 for (; lli_current < lli_len; lli_current++) {
825 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
826 8 * curr_lcla * 2;
827 struct d40_log_lli *lcla = pool->base + lcla_offset;
828 unsigned int flags = 0;
829 int next_lcla;
830
831 if (lli_current + 1 < lli_len)
832 next_lcla = d40_lcla_alloc_one(chan, desc);
833 else
834 next_lcla = linkback ? first_lcla : -EINVAL;
835
836 if (cyclic || next_lcla == -EINVAL)
837 flags |= LLI_TERM_INT;
838
839 if (linkback && curr_lcla == first_lcla) {
840 /* First link goes in both LCPA and LCLA */
841 d40_log_lli_lcpa_write(chan->lcpa,
842 &lli->dst[lli_current],
843 &lli->src[lli_current],
844 next_lcla, flags);
845 }
846
847 /*
848 * One unused LCLA in the cyclic case if the very first
849 * next_lcla fails...
850 */
851 d40_log_lli_lcla_write(lcla,
852 &lli->dst[lli_current],
853 &lli->src[lli_current],
854 next_lcla, flags);
855
856 /*
857 * Cache maintenance is not needed if lcla is
858 * mapped in esram
859 */
860 if (!use_esram_lcla) {
861 dma_sync_single_range_for_device(chan->base->dev,
862 pool->dma_addr, lcla_offset,
863 2 * sizeof(struct d40_log_lli),
864 DMA_TO_DEVICE);
865 }
866 curr_lcla = next_lcla;
867
868 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
869 lli_current++;
870 break;
871 }
872 }
873
874 out:
875 desc->lli_current = lli_current;
876 }
877
878 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
879 {
880 if (chan_is_physical(d40c)) {
881 d40_phy_lli_load(d40c, d40d);
882 d40d->lli_current = d40d->lli_len;
883 } else
884 d40_log_lli_to_lcxa(d40c, d40d);
885 }
886
887 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
888 {
889 struct d40_desc *d;
890
891 if (list_empty(&d40c->active))
892 return NULL;
893
894 d = list_first_entry(&d40c->active,
895 struct d40_desc,
896 node);
897 return d;
898 }
899
900 /* remove desc from current queue and add it to the pending_queue */
901 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
902 {
903 d40_desc_remove(desc);
904 desc->is_in_client_list = false;
905 list_add_tail(&desc->node, &d40c->pending_queue);
906 }
907
908 static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
909 {
910 struct d40_desc *d;
911
912 if (list_empty(&d40c->pending_queue))
913 return NULL;
914
915 d = list_first_entry(&d40c->pending_queue,
916 struct d40_desc,
917 node);
918 return d;
919 }
920
921 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
922 {
923 struct d40_desc *d;
924
925 if (list_empty(&d40c->queue))
926 return NULL;
927
928 d = list_first_entry(&d40c->queue,
929 struct d40_desc,
930 node);
931 return d;
932 }
933
934 static struct d40_desc *d40_first_done(struct d40_chan *d40c)
935 {
936 if (list_empty(&d40c->done))
937 return NULL;
938
939 return list_first_entry(&d40c->done, struct d40_desc, node);
940 }
941
942 static int d40_psize_2_burst_size(bool is_log, int psize)
943 {
944 if (is_log) {
945 if (psize == STEDMA40_PSIZE_LOG_1)
946 return 1;
947 } else {
948 if (psize == STEDMA40_PSIZE_PHY_1)
949 return 1;
950 }
951
952 return 2 << psize;
953 }
954
955 /*
956 * The dma only supports transmitting packages up to
957 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
958 * dma elements required to send the entire sg list
959 */
960 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
961 {
962 int dmalen;
963 u32 max_w = max(data_width1, data_width2);
964 u32 min_w = min(data_width1, data_width2);
965 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
966
967 if (seg_max > STEDMA40_MAX_SEG_SIZE)
968 seg_max -= (1 << max_w);
969
970 if (!IS_ALIGNED(size, 1 << max_w))
971 return -EINVAL;
972
973 if (size <= seg_max)
974 dmalen = 1;
975 else {
976 dmalen = size / seg_max;
977 if (dmalen * seg_max < size)
978 dmalen++;
979 }
980 return dmalen;
981 }
982
983 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
984 u32 data_width1, u32 data_width2)
985 {
986 struct scatterlist *sg;
987 int i;
988 int len = 0;
989 int ret;
990
991 for_each_sg(sgl, sg, sg_len, i) {
992 ret = d40_size_2_dmalen(sg_dma_len(sg),
993 data_width1, data_width2);
994 if (ret < 0)
995 return ret;
996 len += ret;
997 }
998 return len;
999 }
1000
1001
1002 #ifdef CONFIG_PM
1003 static void dma40_backup(void __iomem *baseaddr, u32 *backup,
1004 u32 *regaddr, int num, bool save)
1005 {
1006 int i;
1007
1008 for (i = 0; i < num; i++) {
1009 void __iomem *addr = baseaddr + regaddr[i];
1010
1011 if (save)
1012 backup[i] = readl_relaxed(addr);
1013 else
1014 writel_relaxed(backup[i], addr);
1015 }
1016 }
1017
1018 static void d40_save_restore_registers(struct d40_base *base, bool save)
1019 {
1020 int i;
1021
1022 /* Save/Restore channel specific registers */
1023 for (i = 0; i < base->num_phy_chans; i++) {
1024 void __iomem *addr;
1025 int idx;
1026
1027 if (base->phy_res[i].reserved)
1028 continue;
1029
1030 addr = base->virtbase + D40_DREG_PCBASE + i * D40_DREG_PCDELTA;
1031 idx = i * ARRAY_SIZE(d40_backup_regs_chan);
1032
1033 dma40_backup(addr, &base->reg_val_backup_chan[idx],
1034 d40_backup_regs_chan,
1035 ARRAY_SIZE(d40_backup_regs_chan),
1036 save);
1037 }
1038
1039 /* Save/Restore global registers */
1040 dma40_backup(base->virtbase, base->reg_val_backup,
1041 d40_backup_regs, ARRAY_SIZE(d40_backup_regs),
1042 save);
1043
1044 /* Save/Restore registers only existing on dma40 v3 and later */
1045 if (base->gen_dmac.backup)
1046 dma40_backup(base->virtbase, base->reg_val_backup_v4,
1047 base->gen_dmac.backup,
1048 base->gen_dmac.backup_size,
1049 save);
1050 }
1051 #else
1052 static void d40_save_restore_registers(struct d40_base *base, bool save)
1053 {
1054 }
1055 #endif
1056
1057 static int __d40_execute_command_phy(struct d40_chan *d40c,
1058 enum d40_command command)
1059 {
1060 u32 status;
1061 int i;
1062 void __iomem *active_reg;
1063 int ret = 0;
1064 unsigned long flags;
1065 u32 wmask;
1066
1067 if (command == D40_DMA_STOP) {
1068 ret = __d40_execute_command_phy(d40c, D40_DMA_SUSPEND_REQ);
1069 if (ret)
1070 return ret;
1071 }
1072
1073 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
1074
1075 if (d40c->phy_chan->num % 2 == 0)
1076 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1077 else
1078 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1079
1080 if (command == D40_DMA_SUSPEND_REQ) {
1081 status = (readl(active_reg) &
1082 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1083 D40_CHAN_POS(d40c->phy_chan->num);
1084
1085 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1086 goto done;
1087 }
1088
1089 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
1090 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
1091 active_reg);
1092
1093 if (command == D40_DMA_SUSPEND_REQ) {
1094
1095 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
1096 status = (readl(active_reg) &
1097 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1098 D40_CHAN_POS(d40c->phy_chan->num);
1099
1100 cpu_relax();
1101 /*
1102 * Reduce the number of bus accesses while
1103 * waiting for the DMA to suspend.
1104 */
1105 udelay(3);
1106
1107 if (status == D40_DMA_STOP ||
1108 status == D40_DMA_SUSPENDED)
1109 break;
1110 }
1111
1112 if (i == D40_SUSPEND_MAX_IT) {
1113 chan_err(d40c,
1114 "unable to suspend the chl %d (log: %d) status %x\n",
1115 d40c->phy_chan->num, d40c->log_num,
1116 status);
1117 dump_stack();
1118 ret = -EBUSY;
1119 }
1120
1121 }
1122 done:
1123 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
1124 return ret;
1125 }
1126
1127 static void d40_term_all(struct d40_chan *d40c)
1128 {
1129 struct d40_desc *d40d;
1130 struct d40_desc *_d;
1131
1132 /* Release completed descriptors */
1133 while ((d40d = d40_first_done(d40c))) {
1134 d40_desc_remove(d40d);
1135 d40_desc_free(d40c, d40d);
1136 }
1137
1138 /* Release active descriptors */
1139 while ((d40d = d40_first_active_get(d40c))) {
1140 d40_desc_remove(d40d);
1141 d40_desc_free(d40c, d40d);
1142 }
1143
1144 /* Release queued descriptors waiting for transfer */
1145 while ((d40d = d40_first_queued(d40c))) {
1146 d40_desc_remove(d40d);
1147 d40_desc_free(d40c, d40d);
1148 }
1149
1150 /* Release pending descriptors */
1151 while ((d40d = d40_first_pending(d40c))) {
1152 d40_desc_remove(d40d);
1153 d40_desc_free(d40c, d40d);
1154 }
1155
1156 /* Release client owned descriptors */
1157 if (!list_empty(&d40c->client))
1158 list_for_each_entry_safe(d40d, _d, &d40c->client, node) {
1159 d40_desc_remove(d40d);
1160 d40_desc_free(d40c, d40d);
1161 }
1162
1163 /* Release descriptors in prepare queue */
1164 if (!list_empty(&d40c->prepare_queue))
1165 list_for_each_entry_safe(d40d, _d,
1166 &d40c->prepare_queue, node) {
1167 d40_desc_remove(d40d);
1168 d40_desc_free(d40c, d40d);
1169 }
1170
1171 d40c->pending_tx = 0;
1172 }
1173
1174 static void __d40_config_set_event(struct d40_chan *d40c,
1175 enum d40_events event_type, u32 event,
1176 int reg)
1177 {
1178 void __iomem *addr = chan_base(d40c) + reg;
1179 int tries;
1180 u32 status;
1181
1182 switch (event_type) {
1183
1184 case D40_DEACTIVATE_EVENTLINE:
1185
1186 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
1187 | ~D40_EVENTLINE_MASK(event), addr);
1188 break;
1189
1190 case D40_SUSPEND_REQ_EVENTLINE:
1191 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1192 D40_EVENTLINE_POS(event);
1193
1194 if (status == D40_DEACTIVATE_EVENTLINE ||
1195 status == D40_SUSPEND_REQ_EVENTLINE)
1196 break;
1197
1198 writel((D40_SUSPEND_REQ_EVENTLINE << D40_EVENTLINE_POS(event))
1199 | ~D40_EVENTLINE_MASK(event), addr);
1200
1201 for (tries = 0 ; tries < D40_SUSPEND_MAX_IT; tries++) {
1202
1203 status = (readl(addr) & D40_EVENTLINE_MASK(event)) >>
1204 D40_EVENTLINE_POS(event);
1205
1206 cpu_relax();
1207 /*
1208 * Reduce the number of bus accesses while
1209 * waiting for the DMA to suspend.
1210 */
1211 udelay(3);
1212
1213 if (status == D40_DEACTIVATE_EVENTLINE)
1214 break;
1215 }
1216
1217 if (tries == D40_SUSPEND_MAX_IT) {
1218 chan_err(d40c,
1219 "unable to stop the event_line chl %d (log: %d)"
1220 "status %x\n", d40c->phy_chan->num,
1221 d40c->log_num, status);
1222 }
1223 break;
1224
1225 case D40_ACTIVATE_EVENTLINE:
1226 /*
1227 * The hardware sometimes doesn't register the enable when src and dst
1228 * event lines are active on the same logical channel. Retry to ensure
1229 * it does. Usually only one retry is sufficient.
1230 */
1231 tries = 100;
1232 while (--tries) {
1233 writel((D40_ACTIVATE_EVENTLINE <<
1234 D40_EVENTLINE_POS(event)) |
1235 ~D40_EVENTLINE_MASK(event), addr);
1236
1237 if (readl(addr) & D40_EVENTLINE_MASK(event))
1238 break;
1239 }
1240
1241 if (tries != 99)
1242 dev_dbg(chan2dev(d40c),
1243 "[%s] workaround enable S%cLNK (%d tries)\n",
1244 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
1245 100 - tries);
1246
1247 WARN_ON(!tries);
1248 break;
1249
1250 case D40_ROUND_EVENTLINE:
1251 BUG();
1252 break;
1253
1254 }
1255 }
1256
1257 static void d40_config_set_event(struct d40_chan *d40c,
1258 enum d40_events event_type)
1259 {
1260 /* Enable event line connected to device (or memcpy) */
1261 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1262 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
1263 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1264
1265 __d40_config_set_event(d40c, event_type, event,
1266 D40_CHAN_REG_SSLNK);
1267 }
1268
1269 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
1270 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1271
1272 __d40_config_set_event(d40c, event_type, event,
1273 D40_CHAN_REG_SDLNK);
1274 }
1275 }
1276
1277 static u32 d40_chan_has_events(struct d40_chan *d40c)
1278 {
1279 void __iomem *chanbase = chan_base(d40c);
1280 u32 val;
1281
1282 val = readl(chanbase + D40_CHAN_REG_SSLNK);
1283 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
1284
1285 return val;
1286 }
1287
1288 static int
1289 __d40_execute_command_log(struct d40_chan *d40c, enum d40_command command)
1290 {
1291 unsigned long flags;
1292 int ret = 0;
1293 u32 active_status;
1294 void __iomem *active_reg;
1295
1296 if (d40c->phy_chan->num % 2 == 0)
1297 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1298 else
1299 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1300
1301
1302 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
1303
1304 switch (command) {
1305 case D40_DMA_STOP:
1306 case D40_DMA_SUSPEND_REQ:
1307
1308 active_status = (readl(active_reg) &
1309 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1310 D40_CHAN_POS(d40c->phy_chan->num);
1311
1312 if (active_status == D40_DMA_RUN)
1313 d40_config_set_event(d40c, D40_SUSPEND_REQ_EVENTLINE);
1314 else
1315 d40_config_set_event(d40c, D40_DEACTIVATE_EVENTLINE);
1316
1317 if (!d40_chan_has_events(d40c) && (command == D40_DMA_STOP))
1318 ret = __d40_execute_command_phy(d40c, command);
1319
1320 break;
1321
1322 case D40_DMA_RUN:
1323
1324 d40_config_set_event(d40c, D40_ACTIVATE_EVENTLINE);
1325 ret = __d40_execute_command_phy(d40c, command);
1326 break;
1327
1328 case D40_DMA_SUSPENDED:
1329 BUG();
1330 break;
1331 }
1332
1333 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
1334 return ret;
1335 }
1336
1337 static int d40_channel_execute_command(struct d40_chan *d40c,
1338 enum d40_command command)
1339 {
1340 if (chan_is_logical(d40c))
1341 return __d40_execute_command_log(d40c, command);
1342 else
1343 return __d40_execute_command_phy(d40c, command);
1344 }
1345
1346 static u32 d40_get_prmo(struct d40_chan *d40c)
1347 {
1348 static const unsigned int phy_map[] = {
1349 [STEDMA40_PCHAN_BASIC_MODE]
1350 = D40_DREG_PRMO_PCHAN_BASIC,
1351 [STEDMA40_PCHAN_MODULO_MODE]
1352 = D40_DREG_PRMO_PCHAN_MODULO,
1353 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
1354 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
1355 };
1356 static const unsigned int log_map[] = {
1357 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
1358 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
1359 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
1360 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
1361 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
1362 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
1363 };
1364
1365 if (chan_is_physical(d40c))
1366 return phy_map[d40c->dma_cfg.mode_opt];
1367 else
1368 return log_map[d40c->dma_cfg.mode_opt];
1369 }
1370
1371 static void d40_config_write(struct d40_chan *d40c)
1372 {
1373 u32 addr_base;
1374 u32 var;
1375
1376 /* Odd addresses are even addresses + 4 */
1377 addr_base = (d40c->phy_chan->num % 2) * 4;
1378 /* Setup channel mode to logical or physical */
1379 var = ((u32)(chan_is_logical(d40c)) + 1) <<
1380 D40_CHAN_POS(d40c->phy_chan->num);
1381 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
1382
1383 /* Setup operational mode option register */
1384 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
1385
1386 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
1387
1388 if (chan_is_logical(d40c)) {
1389 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
1390 & D40_SREG_ELEM_LOG_LIDX_MASK;
1391 void __iomem *chanbase = chan_base(d40c);
1392
1393 /* Set default config for CFG reg */
1394 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
1395 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
1396
1397 /* Set LIDX for lcla */
1398 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
1399 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
1400
1401 /* Clear LNK which will be used by d40_chan_has_events() */
1402 writel(0, chanbase + D40_CHAN_REG_SSLNK);
1403 writel(0, chanbase + D40_CHAN_REG_SDLNK);
1404 }
1405 }
1406
1407 static u32 d40_residue(struct d40_chan *d40c)
1408 {
1409 u32 num_elt;
1410
1411 if (chan_is_logical(d40c))
1412 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
1413 >> D40_MEM_LCSP2_ECNT_POS;
1414 else {
1415 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
1416 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
1417 >> D40_SREG_ELEM_PHY_ECNT_POS;
1418 }
1419
1420 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
1421 }
1422
1423 static bool d40_tx_is_linked(struct d40_chan *d40c)
1424 {
1425 bool is_link;
1426
1427 if (chan_is_logical(d40c))
1428 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
1429 else
1430 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
1431 & D40_SREG_LNK_PHYS_LNK_MASK;
1432
1433 return is_link;
1434 }
1435
1436 static int d40_pause(struct d40_chan *d40c)
1437 {
1438 int res = 0;
1439 unsigned long flags;
1440
1441 if (!d40c->busy)
1442 return 0;
1443
1444 pm_runtime_get_sync(d40c->base->dev);
1445 spin_lock_irqsave(&d40c->lock, flags);
1446
1447 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1448
1449 pm_runtime_mark_last_busy(d40c->base->dev);
1450 pm_runtime_put_autosuspend(d40c->base->dev);
1451 spin_unlock_irqrestore(&d40c->lock, flags);
1452 return res;
1453 }
1454
1455 static int d40_resume(struct d40_chan *d40c)
1456 {
1457 int res = 0;
1458 unsigned long flags;
1459
1460 if (!d40c->busy)
1461 return 0;
1462
1463 spin_lock_irqsave(&d40c->lock, flags);
1464 pm_runtime_get_sync(d40c->base->dev);
1465
1466 /* If bytes left to transfer or linked tx resume job */
1467 if (d40_residue(d40c) || d40_tx_is_linked(d40c))
1468 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1469
1470 pm_runtime_mark_last_busy(d40c->base->dev);
1471 pm_runtime_put_autosuspend(d40c->base->dev);
1472 spin_unlock_irqrestore(&d40c->lock, flags);
1473 return res;
1474 }
1475
1476 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1477 {
1478 struct d40_chan *d40c = container_of(tx->chan,
1479 struct d40_chan,
1480 chan);
1481 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1482 unsigned long flags;
1483 dma_cookie_t cookie;
1484
1485 spin_lock_irqsave(&d40c->lock, flags);
1486 cookie = dma_cookie_assign(tx);
1487 d40_desc_queue(d40c, d40d);
1488 spin_unlock_irqrestore(&d40c->lock, flags);
1489
1490 return cookie;
1491 }
1492
1493 static int d40_start(struct d40_chan *d40c)
1494 {
1495 return d40_channel_execute_command(d40c, D40_DMA_RUN);
1496 }
1497
1498 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1499 {
1500 struct d40_desc *d40d;
1501 int err;
1502
1503 /* Start queued jobs, if any */
1504 d40d = d40_first_queued(d40c);
1505
1506 if (d40d != NULL) {
1507 if (!d40c->busy) {
1508 d40c->busy = true;
1509 pm_runtime_get_sync(d40c->base->dev);
1510 }
1511
1512 /* Remove from queue */
1513 d40_desc_remove(d40d);
1514
1515 /* Add to active queue */
1516 d40_desc_submit(d40c, d40d);
1517
1518 /* Initiate DMA job */
1519 d40_desc_load(d40c, d40d);
1520
1521 /* Start dma job */
1522 err = d40_start(d40c);
1523
1524 if (err)
1525 return NULL;
1526 }
1527
1528 return d40d;
1529 }
1530
1531 /* called from interrupt context */
1532 static void dma_tc_handle(struct d40_chan *d40c)
1533 {
1534 struct d40_desc *d40d;
1535
1536 /* Get first active entry from list */
1537 d40d = d40_first_active_get(d40c);
1538
1539 if (d40d == NULL)
1540 return;
1541
1542 if (d40d->cyclic) {
1543 /*
1544 * If this was a paritially loaded list, we need to reloaded
1545 * it, and only when the list is completed. We need to check
1546 * for done because the interrupt will hit for every link, and
1547 * not just the last one.
1548 */
1549 if (d40d->lli_current < d40d->lli_len
1550 && !d40_tx_is_linked(d40c)
1551 && !d40_residue(d40c)) {
1552 d40_lcla_free_all(d40c, d40d);
1553 d40_desc_load(d40c, d40d);
1554 (void) d40_start(d40c);
1555
1556 if (d40d->lli_current == d40d->lli_len)
1557 d40d->lli_current = 0;
1558 }
1559 } else {
1560 d40_lcla_free_all(d40c, d40d);
1561
1562 if (d40d->lli_current < d40d->lli_len) {
1563 d40_desc_load(d40c, d40d);
1564 /* Start dma job */
1565 (void) d40_start(d40c);
1566 return;
1567 }
1568
1569 if (d40_queue_start(d40c) == NULL) {
1570 d40c->busy = false;
1571
1572 pm_runtime_mark_last_busy(d40c->base->dev);
1573 pm_runtime_put_autosuspend(d40c->base->dev);
1574 }
1575
1576 d40_desc_remove(d40d);
1577 d40_desc_done(d40c, d40d);
1578 }
1579
1580 d40c->pending_tx++;
1581 tasklet_schedule(&d40c->tasklet);
1582
1583 }
1584
1585 static void dma_tasklet(unsigned long data)
1586 {
1587 struct d40_chan *d40c = (struct d40_chan *) data;
1588 struct d40_desc *d40d;
1589 unsigned long flags;
1590 bool callback_active;
1591 dma_async_tx_callback callback;
1592 void *callback_param;
1593
1594 spin_lock_irqsave(&d40c->lock, flags);
1595
1596 /* Get first entry from the done list */
1597 d40d = d40_first_done(d40c);
1598 if (d40d == NULL) {
1599 /* Check if we have reached here for cyclic job */
1600 d40d = d40_first_active_get(d40c);
1601 if (d40d == NULL || !d40d->cyclic)
1602 goto err;
1603 }
1604
1605 if (!d40d->cyclic)
1606 dma_cookie_complete(&d40d->txd);
1607
1608 /*
1609 * If terminating a channel pending_tx is set to zero.
1610 * This prevents any finished active jobs to return to the client.
1611 */
1612 if (d40c->pending_tx == 0) {
1613 spin_unlock_irqrestore(&d40c->lock, flags);
1614 return;
1615 }
1616
1617 /* Callback to client */
1618 callback_active = !!(d40d->txd.flags & DMA_PREP_INTERRUPT);
1619 callback = d40d->txd.callback;
1620 callback_param = d40d->txd.callback_param;
1621
1622 if (!d40d->cyclic) {
1623 if (async_tx_test_ack(&d40d->txd)) {
1624 d40_desc_remove(d40d);
1625 d40_desc_free(d40c, d40d);
1626 } else if (!d40d->is_in_client_list) {
1627 d40_desc_remove(d40d);
1628 d40_lcla_free_all(d40c, d40d);
1629 list_add_tail(&d40d->node, &d40c->client);
1630 d40d->is_in_client_list = true;
1631 }
1632 }
1633
1634 d40c->pending_tx--;
1635
1636 if (d40c->pending_tx)
1637 tasklet_schedule(&d40c->tasklet);
1638
1639 spin_unlock_irqrestore(&d40c->lock, flags);
1640
1641 if (callback_active && callback)
1642 callback(callback_param);
1643
1644 return;
1645
1646 err:
1647 /* Rescue manouver if receiving double interrupts */
1648 if (d40c->pending_tx > 0)
1649 d40c->pending_tx--;
1650 spin_unlock_irqrestore(&d40c->lock, flags);
1651 }
1652
1653 static irqreturn_t d40_handle_interrupt(int irq, void *data)
1654 {
1655 int i;
1656 u32 idx;
1657 u32 row;
1658 long chan = -1;
1659 struct d40_chan *d40c;
1660 unsigned long flags;
1661 struct d40_base *base = data;
1662 u32 regs[base->gen_dmac.il_size];
1663 struct d40_interrupt_lookup *il = base->gen_dmac.il;
1664 u32 il_size = base->gen_dmac.il_size;
1665
1666 spin_lock_irqsave(&base->interrupt_lock, flags);
1667
1668 /* Read interrupt status of both logical and physical channels */
1669 for (i = 0; i < il_size; i++)
1670 regs[i] = readl(base->virtbase + il[i].src);
1671
1672 for (;;) {
1673
1674 chan = find_next_bit((unsigned long *)regs,
1675 BITS_PER_LONG * il_size, chan + 1);
1676
1677 /* No more set bits found? */
1678 if (chan == BITS_PER_LONG * il_size)
1679 break;
1680
1681 row = chan / BITS_PER_LONG;
1682 idx = chan & (BITS_PER_LONG - 1);
1683
1684 if (il[row].offset == D40_PHY_CHAN)
1685 d40c = base->lookup_phy_chans[idx];
1686 else
1687 d40c = base->lookup_log_chans[il[row].offset + idx];
1688
1689 if (!d40c) {
1690 /*
1691 * No error because this can happen if something else
1692 * in the system is using the channel.
1693 */
1694 continue;
1695 }
1696
1697 /* ACK interrupt */
1698 writel(1 << idx, base->virtbase + il[row].clr);
1699
1700 spin_lock(&d40c->lock);
1701
1702 if (!il[row].is_error)
1703 dma_tc_handle(d40c);
1704 else
1705 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1706 chan, il[row].offset, idx);
1707
1708 spin_unlock(&d40c->lock);
1709 }
1710
1711 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1712
1713 return IRQ_HANDLED;
1714 }
1715
1716 static int d40_validate_conf(struct d40_chan *d40c,
1717 struct stedma40_chan_cfg *conf)
1718 {
1719 int res = 0;
1720 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1721 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
1722 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1723
1724 if (!conf->dir) {
1725 chan_err(d40c, "Invalid direction.\n");
1726 res = -EINVAL;
1727 }
1728
1729 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1730 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1731 d40c->runtime_addr == 0) {
1732
1733 chan_err(d40c, "Invalid TX channel address (%d)\n",
1734 conf->dst_dev_type);
1735 res = -EINVAL;
1736 }
1737
1738 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1739 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1740 d40c->runtime_addr == 0) {
1741 chan_err(d40c, "Invalid RX channel address (%d)\n",
1742 conf->src_dev_type);
1743 res = -EINVAL;
1744 }
1745
1746 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
1747 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
1748 chan_err(d40c, "Invalid dst\n");
1749 res = -EINVAL;
1750 }
1751
1752 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
1753 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
1754 chan_err(d40c, "Invalid src\n");
1755 res = -EINVAL;
1756 }
1757
1758 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1759 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
1760 chan_err(d40c, "No event line\n");
1761 res = -EINVAL;
1762 }
1763
1764 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1765 (src_event_group != dst_event_group)) {
1766 chan_err(d40c, "Invalid event group\n");
1767 res = -EINVAL;
1768 }
1769
1770 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1771 /*
1772 * DMAC HW supports it. Will be added to this driver,
1773 * in case any dma client requires it.
1774 */
1775 chan_err(d40c, "periph to periph not supported\n");
1776 res = -EINVAL;
1777 }
1778
1779 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1780 (1 << conf->src_info.data_width) !=
1781 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1782 (1 << conf->dst_info.data_width)) {
1783 /*
1784 * The DMAC hardware only supports
1785 * src (burst x width) == dst (burst x width)
1786 */
1787
1788 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
1789 res = -EINVAL;
1790 }
1791
1792 return res;
1793 }
1794
1795 static bool d40_alloc_mask_set(struct d40_phy_res *phy,
1796 bool is_src, int log_event_line, bool is_log,
1797 bool *first_user)
1798 {
1799 unsigned long flags;
1800 spin_lock_irqsave(&phy->lock, flags);
1801
1802 *first_user = ((phy->allocated_src | phy->allocated_dst)
1803 == D40_ALLOC_FREE);
1804
1805 if (!is_log) {
1806 /* Physical interrupts are masked per physical full channel */
1807 if (phy->allocated_src == D40_ALLOC_FREE &&
1808 phy->allocated_dst == D40_ALLOC_FREE) {
1809 phy->allocated_dst = D40_ALLOC_PHY;
1810 phy->allocated_src = D40_ALLOC_PHY;
1811 goto found;
1812 } else
1813 goto not_found;
1814 }
1815
1816 /* Logical channel */
1817 if (is_src) {
1818 if (phy->allocated_src == D40_ALLOC_PHY)
1819 goto not_found;
1820
1821 if (phy->allocated_src == D40_ALLOC_FREE)
1822 phy->allocated_src = D40_ALLOC_LOG_FREE;
1823
1824 if (!(phy->allocated_src & (1 << log_event_line))) {
1825 phy->allocated_src |= 1 << log_event_line;
1826 goto found;
1827 } else
1828 goto not_found;
1829 } else {
1830 if (phy->allocated_dst == D40_ALLOC_PHY)
1831 goto not_found;
1832
1833 if (phy->allocated_dst == D40_ALLOC_FREE)
1834 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1835
1836 if (!(phy->allocated_dst & (1 << log_event_line))) {
1837 phy->allocated_dst |= 1 << log_event_line;
1838 goto found;
1839 } else
1840 goto not_found;
1841 }
1842
1843 not_found:
1844 spin_unlock_irqrestore(&phy->lock, flags);
1845 return false;
1846 found:
1847 spin_unlock_irqrestore(&phy->lock, flags);
1848 return true;
1849 }
1850
1851 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1852 int log_event_line)
1853 {
1854 unsigned long flags;
1855 bool is_free = false;
1856
1857 spin_lock_irqsave(&phy->lock, flags);
1858 if (!log_event_line) {
1859 phy->allocated_dst = D40_ALLOC_FREE;
1860 phy->allocated_src = D40_ALLOC_FREE;
1861 is_free = true;
1862 goto out;
1863 }
1864
1865 /* Logical channel */
1866 if (is_src) {
1867 phy->allocated_src &= ~(1 << log_event_line);
1868 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1869 phy->allocated_src = D40_ALLOC_FREE;
1870 } else {
1871 phy->allocated_dst &= ~(1 << log_event_line);
1872 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1873 phy->allocated_dst = D40_ALLOC_FREE;
1874 }
1875
1876 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1877 D40_ALLOC_FREE);
1878
1879 out:
1880 spin_unlock_irqrestore(&phy->lock, flags);
1881
1882 return is_free;
1883 }
1884
1885 static int d40_allocate_channel(struct d40_chan *d40c, bool *first_phy_user)
1886 {
1887 int dev_type;
1888 int event_group;
1889 int event_line;
1890 struct d40_phy_res *phys;
1891 int i;
1892 int j;
1893 int log_num;
1894 int num_phy_chans;
1895 bool is_src;
1896 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1897
1898 phys = d40c->base->phy_res;
1899 num_phy_chans = d40c->base->num_phy_chans;
1900
1901 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1902 dev_type = d40c->dma_cfg.src_dev_type;
1903 log_num = 2 * dev_type;
1904 is_src = true;
1905 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1906 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1907 /* dst event lines are used for logical memcpy */
1908 dev_type = d40c->dma_cfg.dst_dev_type;
1909 log_num = 2 * dev_type + 1;
1910 is_src = false;
1911 } else
1912 return -EINVAL;
1913
1914 event_group = D40_TYPE_TO_GROUP(dev_type);
1915 event_line = D40_TYPE_TO_EVENT(dev_type);
1916
1917 if (!is_log) {
1918 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1919 /* Find physical half channel */
1920 if (d40c->dma_cfg.use_fixed_channel) {
1921 i = d40c->dma_cfg.phy_channel;
1922 if (d40_alloc_mask_set(&phys[i], is_src,
1923 0, is_log,
1924 first_phy_user))
1925 goto found_phy;
1926 } else {
1927 for (i = 0; i < num_phy_chans; i++) {
1928 if (d40_alloc_mask_set(&phys[i], is_src,
1929 0, is_log,
1930 first_phy_user))
1931 goto found_phy;
1932 }
1933 }
1934 } else
1935 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1936 int phy_num = j + event_group * 2;
1937 for (i = phy_num; i < phy_num + 2; i++) {
1938 if (d40_alloc_mask_set(&phys[i],
1939 is_src,
1940 0,
1941 is_log,
1942 first_phy_user))
1943 goto found_phy;
1944 }
1945 }
1946 return -EINVAL;
1947 found_phy:
1948 d40c->phy_chan = &phys[i];
1949 d40c->log_num = D40_PHY_CHAN;
1950 goto out;
1951 }
1952 if (dev_type == -1)
1953 return -EINVAL;
1954
1955 /* Find logical channel */
1956 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1957 int phy_num = j + event_group * 2;
1958
1959 if (d40c->dma_cfg.use_fixed_channel) {
1960 i = d40c->dma_cfg.phy_channel;
1961
1962 if ((i != phy_num) && (i != phy_num + 1)) {
1963 dev_err(chan2dev(d40c),
1964 "invalid fixed phy channel %d\n", i);
1965 return -EINVAL;
1966 }
1967
1968 if (d40_alloc_mask_set(&phys[i], is_src, event_line,
1969 is_log, first_phy_user))
1970 goto found_log;
1971
1972 dev_err(chan2dev(d40c),
1973 "could not allocate fixed phy channel %d\n", i);
1974 return -EINVAL;
1975 }
1976
1977 /*
1978 * Spread logical channels across all available physical rather
1979 * than pack every logical channel at the first available phy
1980 * channels.
1981 */
1982 if (is_src) {
1983 for (i = phy_num; i < phy_num + 2; i++) {
1984 if (d40_alloc_mask_set(&phys[i], is_src,
1985 event_line, is_log,
1986 first_phy_user))
1987 goto found_log;
1988 }
1989 } else {
1990 for (i = phy_num + 1; i >= phy_num; i--) {
1991 if (d40_alloc_mask_set(&phys[i], is_src,
1992 event_line, is_log,
1993 first_phy_user))
1994 goto found_log;
1995 }
1996 }
1997 }
1998 return -EINVAL;
1999
2000 found_log:
2001 d40c->phy_chan = &phys[i];
2002 d40c->log_num = log_num;
2003 out:
2004
2005 if (is_log)
2006 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
2007 else
2008 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
2009
2010 return 0;
2011
2012 }
2013
2014 static int d40_config_memcpy(struct d40_chan *d40c)
2015 {
2016 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
2017
2018 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
2019 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
2020 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
2021 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
2022 memcpy[d40c->chan.chan_id];
2023
2024 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
2025 dma_has_cap(DMA_SLAVE, cap)) {
2026 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
2027 } else {
2028 chan_err(d40c, "No memcpy\n");
2029 return -EINVAL;
2030 }
2031
2032 return 0;
2033 }
2034
2035 static int d40_free_dma(struct d40_chan *d40c)
2036 {
2037
2038 int res = 0;
2039 u32 event;
2040 struct d40_phy_res *phy = d40c->phy_chan;
2041 bool is_src;
2042
2043 /* Terminate all queued and active transfers */
2044 d40_term_all(d40c);
2045
2046 if (phy == NULL) {
2047 chan_err(d40c, "phy == null\n");
2048 return -EINVAL;
2049 }
2050
2051 if (phy->allocated_src == D40_ALLOC_FREE &&
2052 phy->allocated_dst == D40_ALLOC_FREE) {
2053 chan_err(d40c, "channel already free\n");
2054 return -EINVAL;
2055 }
2056
2057 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
2058 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
2059 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
2060 is_src = false;
2061 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
2062 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
2063 is_src = true;
2064 } else {
2065 chan_err(d40c, "Unknown direction\n");
2066 return -EINVAL;
2067 }
2068
2069 pm_runtime_get_sync(d40c->base->dev);
2070 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
2071 if (res) {
2072 chan_err(d40c, "stop failed\n");
2073 goto out;
2074 }
2075
2076 d40_alloc_mask_free(phy, is_src, chan_is_logical(d40c) ? event : 0);
2077
2078 if (chan_is_logical(d40c))
2079 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
2080 else
2081 d40c->base->lookup_phy_chans[phy->num] = NULL;
2082
2083 if (d40c->busy) {
2084 pm_runtime_mark_last_busy(d40c->base->dev);
2085 pm_runtime_put_autosuspend(d40c->base->dev);
2086 }
2087
2088 d40c->busy = false;
2089 d40c->phy_chan = NULL;
2090 d40c->configured = false;
2091 out:
2092
2093 pm_runtime_mark_last_busy(d40c->base->dev);
2094 pm_runtime_put_autosuspend(d40c->base->dev);
2095 return res;
2096 }
2097
2098 static bool d40_is_paused(struct d40_chan *d40c)
2099 {
2100 void __iomem *chanbase = chan_base(d40c);
2101 bool is_paused = false;
2102 unsigned long flags;
2103 void __iomem *active_reg;
2104 u32 status;
2105 u32 event;
2106
2107 spin_lock_irqsave(&d40c->lock, flags);
2108
2109 if (chan_is_physical(d40c)) {
2110 if (d40c->phy_chan->num % 2 == 0)
2111 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
2112 else
2113 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
2114
2115 status = (readl(active_reg) &
2116 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
2117 D40_CHAN_POS(d40c->phy_chan->num);
2118 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
2119 is_paused = true;
2120
2121 goto _exit;
2122 }
2123
2124 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
2125 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
2126 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
2127 status = readl(chanbase + D40_CHAN_REG_SDLNK);
2128 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
2129 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
2130 status = readl(chanbase + D40_CHAN_REG_SSLNK);
2131 } else {
2132 chan_err(d40c, "Unknown direction\n");
2133 goto _exit;
2134 }
2135
2136 status = (status & D40_EVENTLINE_MASK(event)) >>
2137 D40_EVENTLINE_POS(event);
2138
2139 if (status != D40_DMA_RUN)
2140 is_paused = true;
2141 _exit:
2142 spin_unlock_irqrestore(&d40c->lock, flags);
2143 return is_paused;
2144
2145 }
2146
2147 static u32 stedma40_residue(struct dma_chan *chan)
2148 {
2149 struct d40_chan *d40c =
2150 container_of(chan, struct d40_chan, chan);
2151 u32 bytes_left;
2152 unsigned long flags;
2153
2154 spin_lock_irqsave(&d40c->lock, flags);
2155 bytes_left = d40_residue(d40c);
2156 spin_unlock_irqrestore(&d40c->lock, flags);
2157
2158 return bytes_left;
2159 }
2160
2161 static int
2162 d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
2163 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2164 unsigned int sg_len, dma_addr_t src_dev_addr,
2165 dma_addr_t dst_dev_addr)
2166 {
2167 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2168 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2169 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2170 int ret;
2171
2172 ret = d40_log_sg_to_lli(sg_src, sg_len,
2173 src_dev_addr,
2174 desc->lli_log.src,
2175 chan->log_def.lcsp1,
2176 src_info->data_width,
2177 dst_info->data_width);
2178
2179 ret = d40_log_sg_to_lli(sg_dst, sg_len,
2180 dst_dev_addr,
2181 desc->lli_log.dst,
2182 chan->log_def.lcsp3,
2183 dst_info->data_width,
2184 src_info->data_width);
2185
2186 return ret < 0 ? ret : 0;
2187 }
2188
2189 static int
2190 d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
2191 struct scatterlist *sg_src, struct scatterlist *sg_dst,
2192 unsigned int sg_len, dma_addr_t src_dev_addr,
2193 dma_addr_t dst_dev_addr)
2194 {
2195 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2196 struct stedma40_half_channel_info *src_info = &cfg->src_info;
2197 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
2198 unsigned long flags = 0;
2199 int ret;
2200
2201 if (desc->cyclic)
2202 flags |= LLI_CYCLIC | LLI_TERM_INT;
2203
2204 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
2205 desc->lli_phy.src,
2206 virt_to_phys(desc->lli_phy.src),
2207 chan->src_def_cfg,
2208 src_info, dst_info, flags);
2209
2210 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
2211 desc->lli_phy.dst,
2212 virt_to_phys(desc->lli_phy.dst),
2213 chan->dst_def_cfg,
2214 dst_info, src_info, flags);
2215
2216 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
2217 desc->lli_pool.size, DMA_TO_DEVICE);
2218
2219 return ret < 0 ? ret : 0;
2220 }
2221
2222 static struct d40_desc *
2223 d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
2224 unsigned int sg_len, unsigned long dma_flags)
2225 {
2226 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2227 struct d40_desc *desc;
2228 int ret;
2229
2230 desc = d40_desc_get(chan);
2231 if (!desc)
2232 return NULL;
2233
2234 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
2235 cfg->dst_info.data_width);
2236 if (desc->lli_len < 0) {
2237 chan_err(chan, "Unaligned size\n");
2238 goto err;
2239 }
2240
2241 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
2242 if (ret < 0) {
2243 chan_err(chan, "Could not allocate lli\n");
2244 goto err;
2245 }
2246
2247 desc->lli_current = 0;
2248 desc->txd.flags = dma_flags;
2249 desc->txd.tx_submit = d40_tx_submit;
2250
2251 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
2252
2253 return desc;
2254
2255 err:
2256 d40_desc_free(chan, desc);
2257 return NULL;
2258 }
2259
2260 static dma_addr_t
2261 d40_get_dev_addr(struct d40_chan *chan, enum dma_transfer_direction direction)
2262 {
2263 struct stedma40_platform_data *plat = chan->base->plat_data;
2264 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2265 dma_addr_t addr = 0;
2266
2267 if (chan->runtime_addr)
2268 return chan->runtime_addr;
2269
2270 if (direction == DMA_DEV_TO_MEM)
2271 addr = plat->dev_rx[cfg->src_dev_type];
2272 else if (direction == DMA_MEM_TO_DEV)
2273 addr = plat->dev_tx[cfg->dst_dev_type];
2274
2275 return addr;
2276 }
2277
2278 static struct dma_async_tx_descriptor *
2279 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
2280 struct scatterlist *sg_dst, unsigned int sg_len,
2281 enum dma_transfer_direction direction, unsigned long dma_flags)
2282 {
2283 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
2284 dma_addr_t src_dev_addr = 0;
2285 dma_addr_t dst_dev_addr = 0;
2286 struct d40_desc *desc;
2287 unsigned long flags;
2288 int ret;
2289
2290 if (!chan->phy_chan) {
2291 chan_err(chan, "Cannot prepare unallocated channel\n");
2292 return NULL;
2293 }
2294
2295 spin_lock_irqsave(&chan->lock, flags);
2296
2297 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
2298 if (desc == NULL)
2299 goto err;
2300
2301 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
2302 desc->cyclic = true;
2303
2304 if (direction != DMA_TRANS_NONE) {
2305 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
2306
2307 if (direction == DMA_DEV_TO_MEM)
2308 src_dev_addr = dev_addr;
2309 else if (direction == DMA_MEM_TO_DEV)
2310 dst_dev_addr = dev_addr;
2311 }
2312
2313 if (chan_is_logical(chan))
2314 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
2315 sg_len, src_dev_addr, dst_dev_addr);
2316 else
2317 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
2318 sg_len, src_dev_addr, dst_dev_addr);
2319
2320 if (ret) {
2321 chan_err(chan, "Failed to prepare %s sg job: %d\n",
2322 chan_is_logical(chan) ? "log" : "phy", ret);
2323 goto err;
2324 }
2325
2326 /*
2327 * add descriptor to the prepare queue in order to be able
2328 * to free them later in terminate_all
2329 */
2330 list_add_tail(&desc->node, &chan->prepare_queue);
2331
2332 spin_unlock_irqrestore(&chan->lock, flags);
2333
2334 return &desc->txd;
2335
2336 err:
2337 if (desc)
2338 d40_desc_free(chan, desc);
2339 spin_unlock_irqrestore(&chan->lock, flags);
2340 return NULL;
2341 }
2342
2343 bool stedma40_filter(struct dma_chan *chan, void *data)
2344 {
2345 struct stedma40_chan_cfg *info = data;
2346 struct d40_chan *d40c =
2347 container_of(chan, struct d40_chan, chan);
2348 int err;
2349
2350 if (data) {
2351 err = d40_validate_conf(d40c, info);
2352 if (!err)
2353 d40c->dma_cfg = *info;
2354 } else
2355 err = d40_config_memcpy(d40c);
2356
2357 if (!err)
2358 d40c->configured = true;
2359
2360 return err == 0;
2361 }
2362 EXPORT_SYMBOL(stedma40_filter);
2363
2364 static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
2365 {
2366 bool realtime = d40c->dma_cfg.realtime;
2367 bool highprio = d40c->dma_cfg.high_priority;
2368 u32 rtreg;
2369 u32 event = D40_TYPE_TO_EVENT(dev_type);
2370 u32 group = D40_TYPE_TO_GROUP(dev_type);
2371 u32 bit = 1 << event;
2372 u32 prioreg;
2373 struct d40_gen_dmac *dmac = &d40c->base->gen_dmac;
2374
2375 rtreg = realtime ? dmac->realtime_en : dmac->realtime_clear;
2376 /*
2377 * Due to a hardware bug, in some cases a logical channel triggered by
2378 * a high priority destination event line can generate extra packet
2379 * transactions.
2380 *
2381 * The workaround is to not set the high priority level for the
2382 * destination event lines that trigger logical channels.
2383 */
2384 if (!src && chan_is_logical(d40c))
2385 highprio = false;
2386
2387 prioreg = highprio ? dmac->high_prio_en : dmac->high_prio_clear;
2388
2389 /* Destination event lines are stored in the upper halfword */
2390 if (!src)
2391 bit <<= 16;
2392
2393 writel(bit, d40c->base->virtbase + prioreg + group * 4);
2394 writel(bit, d40c->base->virtbase + rtreg + group * 4);
2395 }
2396
2397 static void d40_set_prio_realtime(struct d40_chan *d40c)
2398 {
2399 if (d40c->base->rev < 3)
2400 return;
2401
2402 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
2403 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2404 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
2405
2406 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
2407 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
2408 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
2409 }
2410
2411 /* DMA ENGINE functions */
2412 static int d40_alloc_chan_resources(struct dma_chan *chan)
2413 {
2414 int err;
2415 unsigned long flags;
2416 struct d40_chan *d40c =
2417 container_of(chan, struct d40_chan, chan);
2418 bool is_free_phy;
2419 spin_lock_irqsave(&d40c->lock, flags);
2420
2421 dma_cookie_init(chan);
2422
2423 /* If no dma configuration is set use default configuration (memcpy) */
2424 if (!d40c->configured) {
2425 err = d40_config_memcpy(d40c);
2426 if (err) {
2427 chan_err(d40c, "Failed to configure memcpy channel\n");
2428 goto fail;
2429 }
2430 }
2431
2432 err = d40_allocate_channel(d40c, &is_free_phy);
2433 if (err) {
2434 chan_err(d40c, "Failed to allocate channel\n");
2435 d40c->configured = false;
2436 goto fail;
2437 }
2438
2439 pm_runtime_get_sync(d40c->base->dev);
2440 /* Fill in basic CFG register values */
2441 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
2442 &d40c->dst_def_cfg, chan_is_logical(d40c));
2443
2444 d40_set_prio_realtime(d40c);
2445
2446 if (chan_is_logical(d40c)) {
2447 d40_log_cfg(&d40c->dma_cfg,
2448 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2449
2450 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
2451 d40c->lcpa = d40c->base->lcpa_base +
2452 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
2453 else
2454 d40c->lcpa = d40c->base->lcpa_base +
2455 d40c->dma_cfg.dst_dev_type *
2456 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2457 }
2458
2459 dev_dbg(chan2dev(d40c), "allocated %s channel (phy %d%s)\n",
2460 chan_is_logical(d40c) ? "logical" : "physical",
2461 d40c->phy_chan->num,
2462 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2463
2464
2465 /*
2466 * Only write channel configuration to the DMA if the physical
2467 * resource is free. In case of multiple logical channels
2468 * on the same physical resource, only the first write is necessary.
2469 */
2470 if (is_free_phy)
2471 d40_config_write(d40c);
2472 fail:
2473 pm_runtime_mark_last_busy(d40c->base->dev);
2474 pm_runtime_put_autosuspend(d40c->base->dev);
2475 spin_unlock_irqrestore(&d40c->lock, flags);
2476 return err;
2477 }
2478
2479 static void d40_free_chan_resources(struct dma_chan *chan)
2480 {
2481 struct d40_chan *d40c =
2482 container_of(chan, struct d40_chan, chan);
2483 int err;
2484 unsigned long flags;
2485
2486 if (d40c->phy_chan == NULL) {
2487 chan_err(d40c, "Cannot free unallocated channel\n");
2488 return;
2489 }
2490
2491 spin_lock_irqsave(&d40c->lock, flags);
2492
2493 err = d40_free_dma(d40c);
2494
2495 if (err)
2496 chan_err(d40c, "Failed to free channel\n");
2497 spin_unlock_irqrestore(&d40c->lock, flags);
2498 }
2499
2500 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2501 dma_addr_t dst,
2502 dma_addr_t src,
2503 size_t size,
2504 unsigned long dma_flags)
2505 {
2506 struct scatterlist dst_sg;
2507 struct scatterlist src_sg;
2508
2509 sg_init_table(&dst_sg, 1);
2510 sg_init_table(&src_sg, 1);
2511
2512 sg_dma_address(&dst_sg) = dst;
2513 sg_dma_address(&src_sg) = src;
2514
2515 sg_dma_len(&dst_sg) = size;
2516 sg_dma_len(&src_sg) = size;
2517
2518 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
2519 }
2520
2521 static struct dma_async_tx_descriptor *
2522 d40_prep_memcpy_sg(struct dma_chan *chan,
2523 struct scatterlist *dst_sg, unsigned int dst_nents,
2524 struct scatterlist *src_sg, unsigned int src_nents,
2525 unsigned long dma_flags)
2526 {
2527 if (dst_nents != src_nents)
2528 return NULL;
2529
2530 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
2531 }
2532
2533 static struct dma_async_tx_descriptor *
2534 d40_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
2535 unsigned int sg_len, enum dma_transfer_direction direction,
2536 unsigned long dma_flags, void *context)
2537 {
2538 if (!is_slave_direction(direction))
2539 return NULL;
2540
2541 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
2542 }
2543
2544 static struct dma_async_tx_descriptor *
2545 dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2546 size_t buf_len, size_t period_len,
2547 enum dma_transfer_direction direction, unsigned long flags,
2548 void *context)
2549 {
2550 unsigned int periods = buf_len / period_len;
2551 struct dma_async_tx_descriptor *txd;
2552 struct scatterlist *sg;
2553 int i;
2554
2555 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
2556 for (i = 0; i < periods; i++) {
2557 sg_dma_address(&sg[i]) = dma_addr;
2558 sg_dma_len(&sg[i]) = period_len;
2559 dma_addr += period_len;
2560 }
2561
2562 sg[periods].offset = 0;
2563 sg_dma_len(&sg[periods]) = 0;
2564 sg[periods].page_link =
2565 ((unsigned long)sg | 0x01) & ~0x02;
2566
2567 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2568 DMA_PREP_INTERRUPT);
2569
2570 kfree(sg);
2571
2572 return txd;
2573 }
2574
2575 static enum dma_status d40_tx_status(struct dma_chan *chan,
2576 dma_cookie_t cookie,
2577 struct dma_tx_state *txstate)
2578 {
2579 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2580 enum dma_status ret;
2581
2582 if (d40c->phy_chan == NULL) {
2583 chan_err(d40c, "Cannot read status of unallocated channel\n");
2584 return -EINVAL;
2585 }
2586
2587 ret = dma_cookie_status(chan, cookie, txstate);
2588 if (ret != DMA_SUCCESS)
2589 dma_set_residue(txstate, stedma40_residue(chan));
2590
2591 if (d40_is_paused(d40c))
2592 ret = DMA_PAUSED;
2593
2594 return ret;
2595 }
2596
2597 static void d40_issue_pending(struct dma_chan *chan)
2598 {
2599 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2600 unsigned long flags;
2601
2602 if (d40c->phy_chan == NULL) {
2603 chan_err(d40c, "Channel is not allocated!\n");
2604 return;
2605 }
2606
2607 spin_lock_irqsave(&d40c->lock, flags);
2608
2609 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2610
2611 /* Busy means that queued jobs are already being processed */
2612 if (!d40c->busy)
2613 (void) d40_queue_start(d40c);
2614
2615 spin_unlock_irqrestore(&d40c->lock, flags);
2616 }
2617
2618 static void d40_terminate_all(struct dma_chan *chan)
2619 {
2620 unsigned long flags;
2621 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2622 int ret;
2623
2624 spin_lock_irqsave(&d40c->lock, flags);
2625
2626 pm_runtime_get_sync(d40c->base->dev);
2627 ret = d40_channel_execute_command(d40c, D40_DMA_STOP);
2628 if (ret)
2629 chan_err(d40c, "Failed to stop channel\n");
2630
2631 d40_term_all(d40c);
2632 pm_runtime_mark_last_busy(d40c->base->dev);
2633 pm_runtime_put_autosuspend(d40c->base->dev);
2634 if (d40c->busy) {
2635 pm_runtime_mark_last_busy(d40c->base->dev);
2636 pm_runtime_put_autosuspend(d40c->base->dev);
2637 }
2638 d40c->busy = false;
2639
2640 spin_unlock_irqrestore(&d40c->lock, flags);
2641 }
2642
2643 static int
2644 dma40_config_to_halfchannel(struct d40_chan *d40c,
2645 struct stedma40_half_channel_info *info,
2646 enum dma_slave_buswidth width,
2647 u32 maxburst)
2648 {
2649 enum stedma40_periph_data_width addr_width;
2650 int psize;
2651
2652 switch (width) {
2653 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2654 addr_width = STEDMA40_BYTE_WIDTH;
2655 break;
2656 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2657 addr_width = STEDMA40_HALFWORD_WIDTH;
2658 break;
2659 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2660 addr_width = STEDMA40_WORD_WIDTH;
2661 break;
2662 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2663 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2664 break;
2665 default:
2666 dev_err(d40c->base->dev,
2667 "illegal peripheral address width "
2668 "requested (%d)\n",
2669 width);
2670 return -EINVAL;
2671 }
2672
2673 if (chan_is_logical(d40c)) {
2674 if (maxburst >= 16)
2675 psize = STEDMA40_PSIZE_LOG_16;
2676 else if (maxburst >= 8)
2677 psize = STEDMA40_PSIZE_LOG_8;
2678 else if (maxburst >= 4)
2679 psize = STEDMA40_PSIZE_LOG_4;
2680 else
2681 psize = STEDMA40_PSIZE_LOG_1;
2682 } else {
2683 if (maxburst >= 16)
2684 psize = STEDMA40_PSIZE_PHY_16;
2685 else if (maxburst >= 8)
2686 psize = STEDMA40_PSIZE_PHY_8;
2687 else if (maxburst >= 4)
2688 psize = STEDMA40_PSIZE_PHY_4;
2689 else
2690 psize = STEDMA40_PSIZE_PHY_1;
2691 }
2692
2693 info->data_width = addr_width;
2694 info->psize = psize;
2695 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2696
2697 return 0;
2698 }
2699
2700 /* Runtime reconfiguration extension */
2701 static int d40_set_runtime_config(struct dma_chan *chan,
2702 struct dma_slave_config *config)
2703 {
2704 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2705 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2706 enum dma_slave_buswidth src_addr_width, dst_addr_width;
2707 dma_addr_t config_addr;
2708 u32 src_maxburst, dst_maxburst;
2709 int ret;
2710
2711 src_addr_width = config->src_addr_width;
2712 src_maxburst = config->src_maxburst;
2713 dst_addr_width = config->dst_addr_width;
2714 dst_maxburst = config->dst_maxburst;
2715
2716 if (config->direction == DMA_DEV_TO_MEM) {
2717 dma_addr_t dev_addr_rx =
2718 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2719
2720 config_addr = config->src_addr;
2721 if (dev_addr_rx)
2722 dev_dbg(d40c->base->dev,
2723 "channel has a pre-wired RX address %08x "
2724 "overriding with %08x\n",
2725 dev_addr_rx, config_addr);
2726 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2727 dev_dbg(d40c->base->dev,
2728 "channel was not configured for peripheral "
2729 "to memory transfer (%d) overriding\n",
2730 cfg->dir);
2731 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2732
2733 /* Configure the memory side */
2734 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2735 dst_addr_width = src_addr_width;
2736 if (dst_maxburst == 0)
2737 dst_maxburst = src_maxburst;
2738
2739 } else if (config->direction == DMA_MEM_TO_DEV) {
2740 dma_addr_t dev_addr_tx =
2741 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2742
2743 config_addr = config->dst_addr;
2744 if (dev_addr_tx)
2745 dev_dbg(d40c->base->dev,
2746 "channel has a pre-wired TX address %08x "
2747 "overriding with %08x\n",
2748 dev_addr_tx, config_addr);
2749 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2750 dev_dbg(d40c->base->dev,
2751 "channel was not configured for memory "
2752 "to peripheral transfer (%d) overriding\n",
2753 cfg->dir);
2754 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2755
2756 /* Configure the memory side */
2757 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2758 src_addr_width = dst_addr_width;
2759 if (src_maxburst == 0)
2760 src_maxburst = dst_maxburst;
2761 } else {
2762 dev_err(d40c->base->dev,
2763 "unrecognized channel direction %d\n",
2764 config->direction);
2765 return -EINVAL;
2766 }
2767
2768 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
2769 dev_err(d40c->base->dev,
2770 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2771 src_maxburst,
2772 src_addr_width,
2773 dst_maxburst,
2774 dst_addr_width);
2775 return -EINVAL;
2776 }
2777
2778 if (src_maxburst > 16) {
2779 src_maxburst = 16;
2780 dst_maxburst = src_maxburst * src_addr_width / dst_addr_width;
2781 } else if (dst_maxburst > 16) {
2782 dst_maxburst = 16;
2783 src_maxburst = dst_maxburst * dst_addr_width / src_addr_width;
2784 }
2785
2786 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2787 src_addr_width,
2788 src_maxburst);
2789 if (ret)
2790 return ret;
2791
2792 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2793 dst_addr_width,
2794 dst_maxburst);
2795 if (ret)
2796 return ret;
2797
2798 /* Fill in register values */
2799 if (chan_is_logical(d40c))
2800 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2801 else
2802 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2803 &d40c->dst_def_cfg, false);
2804
2805 /* These settings will take precedence later */
2806 d40c->runtime_addr = config_addr;
2807 d40c->runtime_direction = config->direction;
2808 dev_dbg(d40c->base->dev,
2809 "configured channel %s for %s, data width %d/%d, "
2810 "maxburst %d/%d elements, LE, no flow control\n",
2811 dma_chan_name(chan),
2812 (config->direction == DMA_DEV_TO_MEM) ? "RX" : "TX",
2813 src_addr_width, dst_addr_width,
2814 src_maxburst, dst_maxburst);
2815
2816 return 0;
2817 }
2818
2819 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2820 unsigned long arg)
2821 {
2822 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2823
2824 if (d40c->phy_chan == NULL) {
2825 chan_err(d40c, "Channel is not allocated!\n");
2826 return -EINVAL;
2827 }
2828
2829 switch (cmd) {
2830 case DMA_TERMINATE_ALL:
2831 d40_terminate_all(chan);
2832 return 0;
2833 case DMA_PAUSE:
2834 return d40_pause(d40c);
2835 case DMA_RESUME:
2836 return d40_resume(d40c);
2837 case DMA_SLAVE_CONFIG:
2838 return d40_set_runtime_config(chan,
2839 (struct dma_slave_config *) arg);
2840 default:
2841 break;
2842 }
2843
2844 /* Other commands are unimplemented */
2845 return -ENXIO;
2846 }
2847
2848 /* Initialization functions */
2849
2850 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2851 struct d40_chan *chans, int offset,
2852 int num_chans)
2853 {
2854 int i = 0;
2855 struct d40_chan *d40c;
2856
2857 INIT_LIST_HEAD(&dma->channels);
2858
2859 for (i = offset; i < offset + num_chans; i++) {
2860 d40c = &chans[i];
2861 d40c->base = base;
2862 d40c->chan.device = dma;
2863
2864 spin_lock_init(&d40c->lock);
2865
2866 d40c->log_num = D40_PHY_CHAN;
2867
2868 INIT_LIST_HEAD(&d40c->done);
2869 INIT_LIST_HEAD(&d40c->active);
2870 INIT_LIST_HEAD(&d40c->queue);
2871 INIT_LIST_HEAD(&d40c->pending_queue);
2872 INIT_LIST_HEAD(&d40c->client);
2873 INIT_LIST_HEAD(&d40c->prepare_queue);
2874
2875 tasklet_init(&d40c->tasklet, dma_tasklet,
2876 (unsigned long) d40c);
2877
2878 list_add_tail(&d40c->chan.device_node,
2879 &dma->channels);
2880 }
2881 }
2882
2883 static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2884 {
2885 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2886 dev->device_prep_slave_sg = d40_prep_slave_sg;
2887
2888 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2889 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2890
2891 /*
2892 * This controller can only access address at even
2893 * 32bit boundaries, i.e. 2^2
2894 */
2895 dev->copy_align = 2;
2896 }
2897
2898 if (dma_has_cap(DMA_SG, dev->cap_mask))
2899 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2900
2901 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2902 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2903
2904 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2905 dev->device_free_chan_resources = d40_free_chan_resources;
2906 dev->device_issue_pending = d40_issue_pending;
2907 dev->device_tx_status = d40_tx_status;
2908 dev->device_control = d40_control;
2909 dev->dev = base->dev;
2910 }
2911
2912 static int __init d40_dmaengine_init(struct d40_base *base,
2913 int num_reserved_chans)
2914 {
2915 int err ;
2916
2917 d40_chan_init(base, &base->dma_slave, base->log_chans,
2918 0, base->num_log_chans);
2919
2920 dma_cap_zero(base->dma_slave.cap_mask);
2921 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2922 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2923
2924 d40_ops_init(base, &base->dma_slave);
2925
2926 err = dma_async_device_register(&base->dma_slave);
2927
2928 if (err) {
2929 d40_err(base->dev, "Failed to register slave channels\n");
2930 goto failure1;
2931 }
2932
2933 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2934 base->num_log_chans, base->plat_data->memcpy_len);
2935
2936 dma_cap_zero(base->dma_memcpy.cap_mask);
2937 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2938 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2939
2940 d40_ops_init(base, &base->dma_memcpy);
2941
2942 err = dma_async_device_register(&base->dma_memcpy);
2943
2944 if (err) {
2945 d40_err(base->dev,
2946 "Failed to regsiter memcpy only channels\n");
2947 goto failure2;
2948 }
2949
2950 d40_chan_init(base, &base->dma_both, base->phy_chans,
2951 0, num_reserved_chans);
2952
2953 dma_cap_zero(base->dma_both.cap_mask);
2954 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2955 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2956 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
2957 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2958
2959 d40_ops_init(base, &base->dma_both);
2960 err = dma_async_device_register(&base->dma_both);
2961
2962 if (err) {
2963 d40_err(base->dev,
2964 "Failed to register logical and physical capable channels\n");
2965 goto failure3;
2966 }
2967 return 0;
2968 failure3:
2969 dma_async_device_unregister(&base->dma_memcpy);
2970 failure2:
2971 dma_async_device_unregister(&base->dma_slave);
2972 failure1:
2973 return err;
2974 }
2975
2976 /* Suspend resume functionality */
2977 #ifdef CONFIG_PM
2978 static int dma40_pm_suspend(struct device *dev)
2979 {
2980 struct platform_device *pdev = to_platform_device(dev);
2981 struct d40_base *base = platform_get_drvdata(pdev);
2982 int ret = 0;
2983
2984 if (base->lcpa_regulator)
2985 ret = regulator_disable(base->lcpa_regulator);
2986 return ret;
2987 }
2988
2989 static int dma40_runtime_suspend(struct device *dev)
2990 {
2991 struct platform_device *pdev = to_platform_device(dev);
2992 struct d40_base *base = platform_get_drvdata(pdev);
2993
2994 d40_save_restore_registers(base, true);
2995
2996 /* Don't disable/enable clocks for v1 due to HW bugs */
2997 if (base->rev != 1)
2998 writel_relaxed(base->gcc_pwr_off_mask,
2999 base->virtbase + D40_DREG_GCC);
3000
3001 return 0;
3002 }
3003
3004 static int dma40_runtime_resume(struct device *dev)
3005 {
3006 struct platform_device *pdev = to_platform_device(dev);
3007 struct d40_base *base = platform_get_drvdata(pdev);
3008
3009 if (base->initialized)
3010 d40_save_restore_registers(base, false);
3011
3012 writel_relaxed(D40_DREG_GCC_ENABLE_ALL,
3013 base->virtbase + D40_DREG_GCC);
3014 return 0;
3015 }
3016
3017 static int dma40_resume(struct device *dev)
3018 {
3019 struct platform_device *pdev = to_platform_device(dev);
3020 struct d40_base *base = platform_get_drvdata(pdev);
3021 int ret = 0;
3022
3023 if (base->lcpa_regulator)
3024 ret = regulator_enable(base->lcpa_regulator);
3025
3026 return ret;
3027 }
3028
3029 static const struct dev_pm_ops dma40_pm_ops = {
3030 .suspend = dma40_pm_suspend,
3031 .runtime_suspend = dma40_runtime_suspend,
3032 .runtime_resume = dma40_runtime_resume,
3033 .resume = dma40_resume,
3034 };
3035 #define DMA40_PM_OPS (&dma40_pm_ops)
3036 #else
3037 #define DMA40_PM_OPS NULL
3038 #endif
3039
3040 /* Initialization functions. */
3041
3042 static int __init d40_phy_res_init(struct d40_base *base)
3043 {
3044 int i;
3045 int num_phy_chans_avail = 0;
3046 u32 val[2];
3047 int odd_even_bit = -2;
3048 int gcc = D40_DREG_GCC_ENA;
3049
3050 val[0] = readl(base->virtbase + D40_DREG_PRSME);
3051 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
3052
3053 for (i = 0; i < base->num_phy_chans; i++) {
3054 base->phy_res[i].num = i;
3055 odd_even_bit += 2 * ((i % 2) == 0);
3056 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
3057 /* Mark security only channels as occupied */
3058 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
3059 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
3060 base->phy_res[i].reserved = true;
3061 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3062 D40_DREG_GCC_SRC);
3063 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(i),
3064 D40_DREG_GCC_DST);
3065
3066
3067 } else {
3068 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
3069 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
3070 base->phy_res[i].reserved = false;
3071 num_phy_chans_avail++;
3072 }
3073 spin_lock_init(&base->phy_res[i].lock);
3074 }
3075
3076 /* Mark disabled channels as occupied */
3077 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
3078 int chan = base->plat_data->disabled_channels[i];
3079
3080 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
3081 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
3082 base->phy_res[chan].reserved = true;
3083 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3084 D40_DREG_GCC_SRC);
3085 gcc |= D40_DREG_GCC_EVTGRP_ENA(D40_PHYS_TO_GROUP(chan),
3086 D40_DREG_GCC_DST);
3087 num_phy_chans_avail--;
3088 }
3089
3090 /* Mark soft_lli channels */
3091 for (i = 0; i < base->plat_data->num_of_soft_lli_chans; i++) {
3092 int chan = base->plat_data->soft_lli_chans[i];
3093
3094 base->phy_res[chan].use_soft_lli = true;
3095 }
3096
3097 dev_info(base->dev, "%d of %d physical DMA channels available\n",
3098 num_phy_chans_avail, base->num_phy_chans);
3099
3100 /* Verify settings extended vs standard */
3101 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
3102
3103 for (i = 0; i < base->num_phy_chans; i++) {
3104
3105 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
3106 (val[0] & 0x3) != 1)
3107 dev_info(base->dev,
3108 "[%s] INFO: channel %d is misconfigured (%d)\n",
3109 __func__, i, val[0] & 0x3);
3110
3111 val[0] = val[0] >> 2;
3112 }
3113
3114 /*
3115 * To keep things simple, Enable all clocks initially.
3116 * The clocks will get managed later post channel allocation.
3117 * The clocks for the event lines on which reserved channels exists
3118 * are not managed here.
3119 */
3120 writel(D40_DREG_GCC_ENABLE_ALL, base->virtbase + D40_DREG_GCC);
3121 base->gcc_pwr_off_mask = gcc;
3122
3123 return num_phy_chans_avail;
3124 }
3125
3126 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
3127 {
3128 struct stedma40_platform_data *plat_data;
3129 struct clk *clk = NULL;
3130 void __iomem *virtbase = NULL;
3131 struct resource *res = NULL;
3132 struct d40_base *base = NULL;
3133 int num_log_chans = 0;
3134 int num_phy_chans;
3135 int clk_ret = -EINVAL;
3136 int i;
3137 u32 pid;
3138 u32 cid;
3139 u8 rev;
3140
3141 clk = clk_get(&pdev->dev, NULL);
3142 if (IS_ERR(clk)) {
3143 d40_err(&pdev->dev, "No matching clock found\n");
3144 goto failure;
3145 }
3146
3147 clk_ret = clk_prepare_enable(clk);
3148 if (clk_ret) {
3149 d40_err(&pdev->dev, "Failed to prepare/enable clock\n");
3150 goto failure;
3151 }
3152
3153 /* Get IO for DMAC base address */
3154 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
3155 if (!res)
3156 goto failure;
3157
3158 if (request_mem_region(res->start, resource_size(res),
3159 D40_NAME " I/O base") == NULL)
3160 goto failure;
3161
3162 virtbase = ioremap(res->start, resource_size(res));
3163 if (!virtbase)
3164 goto failure;
3165
3166 /* This is just a regular AMBA PrimeCell ID actually */
3167 for (pid = 0, i = 0; i < 4; i++)
3168 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
3169 & 255) << (i * 8);
3170 for (cid = 0, i = 0; i < 4; i++)
3171 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
3172 & 255) << (i * 8);
3173
3174 if (cid != AMBA_CID) {
3175 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
3176 goto failure;
3177 }
3178 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
3179 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
3180 AMBA_MANF_BITS(pid),
3181 AMBA_VENDOR_ST);
3182 goto failure;
3183 }
3184 /*
3185 * HW revision:
3186 * DB8500ed has revision 0
3187 * ? has revision 1
3188 * DB8500v1 has revision 2
3189 * DB8500v2 has revision 3
3190 * AP9540v1 has revision 4
3191 * DB8540v1 has revision 4
3192 */
3193 rev = AMBA_REV_BITS(pid);
3194
3195 plat_data = pdev->dev.platform_data;
3196
3197 /* The number of physical channels on this HW */
3198 if (plat_data->num_of_phy_chans)
3199 num_phy_chans = plat_data->num_of_phy_chans;
3200 else
3201 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
3202
3203 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x with %d physical channels\n",
3204 rev, res->start, num_phy_chans);
3205
3206 if (rev < 2) {
3207 d40_err(&pdev->dev, "hardware revision: %d is not supported",
3208 rev);
3209 goto failure;
3210 }
3211
3212 /* Count the number of logical channels in use */
3213 for (i = 0; i < plat_data->dev_len; i++)
3214 if (plat_data->dev_rx[i] != 0)
3215 num_log_chans++;
3216
3217 for (i = 0; i < plat_data->dev_len; i++)
3218 if (plat_data->dev_tx[i] != 0)
3219 num_log_chans++;
3220
3221 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
3222 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
3223 sizeof(struct d40_chan), GFP_KERNEL);
3224
3225 if (base == NULL) {
3226 d40_err(&pdev->dev, "Out of memory\n");
3227 goto failure;
3228 }
3229
3230 base->rev = rev;
3231 base->clk = clk;
3232 base->num_phy_chans = num_phy_chans;
3233 base->num_log_chans = num_log_chans;
3234 base->phy_start = res->start;
3235 base->phy_size = resource_size(res);
3236 base->virtbase = virtbase;
3237 base->plat_data = plat_data;
3238 base->dev = &pdev->dev;
3239 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
3240 base->log_chans = &base->phy_chans[num_phy_chans];
3241
3242 if (base->plat_data->num_of_phy_chans == 14) {
3243 base->gen_dmac.backup = d40_backup_regs_v4b;
3244 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4B;
3245 base->gen_dmac.interrupt_en = D40_DREG_CPCMIS;
3246 base->gen_dmac.interrupt_clear = D40_DREG_CPCICR;
3247 base->gen_dmac.realtime_en = D40_DREG_CRSEG1;
3248 base->gen_dmac.realtime_clear = D40_DREG_CRCEG1;
3249 base->gen_dmac.high_prio_en = D40_DREG_CPSEG1;
3250 base->gen_dmac.high_prio_clear = D40_DREG_CPCEG1;
3251 base->gen_dmac.il = il_v4b;
3252 base->gen_dmac.il_size = ARRAY_SIZE(il_v4b);
3253 base->gen_dmac.init_reg = dma_init_reg_v4b;
3254 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4b);
3255 } else {
3256 if (base->rev >= 3) {
3257 base->gen_dmac.backup = d40_backup_regs_v4a;
3258 base->gen_dmac.backup_size = BACKUP_REGS_SZ_V4A;
3259 }
3260 base->gen_dmac.interrupt_en = D40_DREG_PCMIS;
3261 base->gen_dmac.interrupt_clear = D40_DREG_PCICR;
3262 base->gen_dmac.realtime_en = D40_DREG_RSEG1;
3263 base->gen_dmac.realtime_clear = D40_DREG_RCEG1;
3264 base->gen_dmac.high_prio_en = D40_DREG_PSEG1;
3265 base->gen_dmac.high_prio_clear = D40_DREG_PCEG1;
3266 base->gen_dmac.il = il_v4a;
3267 base->gen_dmac.il_size = ARRAY_SIZE(il_v4a);
3268 base->gen_dmac.init_reg = dma_init_reg_v4a;
3269 base->gen_dmac.init_reg_size = ARRAY_SIZE(dma_init_reg_v4a);
3270 }
3271
3272 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
3273 GFP_KERNEL);
3274 if (!base->phy_res)
3275 goto failure;
3276
3277 base->lookup_phy_chans = kzalloc(num_phy_chans *
3278 sizeof(struct d40_chan *),
3279 GFP_KERNEL);
3280 if (!base->lookup_phy_chans)
3281 goto failure;
3282
3283 if (num_log_chans + plat_data->memcpy_len) {
3284 /*
3285 * The max number of logical channels are event lines for all
3286 * src devices and dst devices
3287 */
3288 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
3289 sizeof(struct d40_chan *),
3290 GFP_KERNEL);
3291 if (!base->lookup_log_chans)
3292 goto failure;
3293 }
3294
3295 base->reg_val_backup_chan = kmalloc(base->num_phy_chans *
3296 sizeof(d40_backup_regs_chan),
3297 GFP_KERNEL);
3298 if (!base->reg_val_backup_chan)
3299 goto failure;
3300
3301 base->lcla_pool.alloc_map =
3302 kzalloc(num_phy_chans * sizeof(struct d40_desc *)
3303 * D40_LCLA_LINK_PER_EVENT_GRP, GFP_KERNEL);
3304 if (!base->lcla_pool.alloc_map)
3305 goto failure;
3306
3307 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
3308 0, SLAB_HWCACHE_ALIGN,
3309 NULL);
3310 if (base->desc_slab == NULL)
3311 goto failure;
3312
3313 return base;
3314
3315 failure:
3316 if (!clk_ret)
3317 clk_disable_unprepare(clk);
3318 if (!IS_ERR(clk))
3319 clk_put(clk);
3320 if (virtbase)
3321 iounmap(virtbase);
3322 if (res)
3323 release_mem_region(res->start,
3324 resource_size(res));
3325 if (virtbase)
3326 iounmap(virtbase);
3327
3328 if (base) {
3329 kfree(base->lcla_pool.alloc_map);
3330 kfree(base->reg_val_backup_chan);
3331 kfree(base->lookup_log_chans);
3332 kfree(base->lookup_phy_chans);
3333 kfree(base->phy_res);
3334 kfree(base);
3335 }
3336
3337 return NULL;
3338 }
3339
3340 static void __init d40_hw_init(struct d40_base *base)
3341 {
3342
3343 int i;
3344 u32 prmseo[2] = {0, 0};
3345 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
3346 u32 pcmis = 0;
3347 u32 pcicr = 0;
3348 struct d40_reg_val *dma_init_reg = base->gen_dmac.init_reg;
3349 u32 reg_size = base->gen_dmac.init_reg_size;
3350
3351 for (i = 0; i < reg_size; i++)
3352 writel(dma_init_reg[i].val,
3353 base->virtbase + dma_init_reg[i].reg);
3354
3355 /* Configure all our dma channels to default settings */
3356 for (i = 0; i < base->num_phy_chans; i++) {
3357
3358 activeo[i % 2] = activeo[i % 2] << 2;
3359
3360 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
3361 == D40_ALLOC_PHY) {
3362 activeo[i % 2] |= 3;
3363 continue;
3364 }
3365
3366 /* Enable interrupt # */
3367 pcmis = (pcmis << 1) | 1;
3368
3369 /* Clear interrupt # */
3370 pcicr = (pcicr << 1) | 1;
3371
3372 /* Set channel to physical mode */
3373 prmseo[i % 2] = prmseo[i % 2] << 2;
3374 prmseo[i % 2] |= 1;
3375
3376 }
3377
3378 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
3379 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
3380 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
3381 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
3382
3383 /* Write which interrupt to enable */
3384 writel(pcmis, base->virtbase + base->gen_dmac.interrupt_en);
3385
3386 /* Write which interrupt to clear */
3387 writel(pcicr, base->virtbase + base->gen_dmac.interrupt_clear);
3388
3389 /* These are __initdata and cannot be accessed after init */
3390 base->gen_dmac.init_reg = NULL;
3391 base->gen_dmac.init_reg_size = 0;
3392 }
3393
3394 static int __init d40_lcla_allocate(struct d40_base *base)
3395 {
3396 struct d40_lcla_pool *pool = &base->lcla_pool;
3397 unsigned long *page_list;
3398 int i, j;
3399 int ret = 0;
3400
3401 /*
3402 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
3403 * To full fill this hardware requirement without wasting 256 kb
3404 * we allocate pages until we get an aligned one.
3405 */
3406 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
3407 GFP_KERNEL);
3408
3409 if (!page_list) {
3410 ret = -ENOMEM;
3411 goto failure;
3412 }
3413
3414 /* Calculating how many pages that are required */
3415 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
3416
3417 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
3418 page_list[i] = __get_free_pages(GFP_KERNEL,
3419 base->lcla_pool.pages);
3420 if (!page_list[i]) {
3421
3422 d40_err(base->dev, "Failed to allocate %d pages.\n",
3423 base->lcla_pool.pages);
3424
3425 for (j = 0; j < i; j++)
3426 free_pages(page_list[j], base->lcla_pool.pages);
3427 goto failure;
3428 }
3429
3430 if ((virt_to_phys((void *)page_list[i]) &
3431 (LCLA_ALIGNMENT - 1)) == 0)
3432 break;
3433 }
3434
3435 for (j = 0; j < i; j++)
3436 free_pages(page_list[j], base->lcla_pool.pages);
3437
3438 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
3439 base->lcla_pool.base = (void *)page_list[i];
3440 } else {
3441 /*
3442 * After many attempts and no succees with finding the correct
3443 * alignment, try with allocating a big buffer.
3444 */
3445 dev_warn(base->dev,
3446 "[%s] Failed to get %d pages @ 18 bit align.\n",
3447 __func__, base->lcla_pool.pages);
3448 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
3449 base->num_phy_chans +
3450 LCLA_ALIGNMENT,
3451 GFP_KERNEL);
3452 if (!base->lcla_pool.base_unaligned) {
3453 ret = -ENOMEM;
3454 goto failure;
3455 }
3456
3457 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
3458 LCLA_ALIGNMENT);
3459 }
3460
3461 pool->dma_addr = dma_map_single(base->dev, pool->base,
3462 SZ_1K * base->num_phy_chans,
3463 DMA_TO_DEVICE);
3464 if (dma_mapping_error(base->dev, pool->dma_addr)) {
3465 pool->dma_addr = 0;
3466 ret = -ENOMEM;
3467 goto failure;
3468 }
3469
3470 writel(virt_to_phys(base->lcla_pool.base),
3471 base->virtbase + D40_DREG_LCLA);
3472 failure:
3473 kfree(page_list);
3474 return ret;
3475 }
3476
3477 static int __init d40_probe(struct platform_device *pdev)
3478 {
3479 int err;
3480 int ret = -ENOENT;
3481 struct d40_base *base;
3482 struct resource *res = NULL;
3483 int num_reserved_chans;
3484 u32 val;
3485
3486 base = d40_hw_detect_init(pdev);
3487
3488 if (!base)
3489 goto failure;
3490
3491 num_reserved_chans = d40_phy_res_init(base);
3492
3493 platform_set_drvdata(pdev, base);
3494
3495 spin_lock_init(&base->interrupt_lock);
3496 spin_lock_init(&base->execmd_lock);
3497
3498 /* Get IO for logical channel parameter address */
3499 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
3500 if (!res) {
3501 ret = -ENOENT;
3502 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
3503 goto failure;
3504 }
3505 base->lcpa_size = resource_size(res);
3506 base->phy_lcpa = res->start;
3507
3508 if (request_mem_region(res->start, resource_size(res),
3509 D40_NAME " I/O lcpa") == NULL) {
3510 ret = -EBUSY;
3511 d40_err(&pdev->dev,
3512 "Failed to request LCPA region 0x%x-0x%x\n",
3513 res->start, res->end);
3514 goto failure;
3515 }
3516
3517 /* We make use of ESRAM memory for this. */
3518 val = readl(base->virtbase + D40_DREG_LCPA);
3519 if (res->start != val && val != 0) {
3520 dev_warn(&pdev->dev,
3521 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
3522 __func__, val, res->start);
3523 } else
3524 writel(res->start, base->virtbase + D40_DREG_LCPA);
3525
3526 base->lcpa_base = ioremap(res->start, resource_size(res));
3527 if (!base->lcpa_base) {
3528 ret = -ENOMEM;
3529 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
3530 goto failure;
3531 }
3532 /* If lcla has to be located in ESRAM we don't need to allocate */
3533 if (base->plat_data->use_esram_lcla) {
3534 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
3535 "lcla_esram");
3536 if (!res) {
3537 ret = -ENOENT;
3538 d40_err(&pdev->dev,
3539 "No \"lcla_esram\" memory resource\n");
3540 goto failure;
3541 }
3542 base->lcla_pool.base = ioremap(res->start,
3543 resource_size(res));
3544 if (!base->lcla_pool.base) {
3545 ret = -ENOMEM;
3546 d40_err(&pdev->dev, "Failed to ioremap LCLA region\n");
3547 goto failure;
3548 }
3549 writel(res->start, base->virtbase + D40_DREG_LCLA);
3550
3551 } else {
3552 ret = d40_lcla_allocate(base);
3553 if (ret) {
3554 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
3555 goto failure;
3556 }
3557 }
3558
3559 spin_lock_init(&base->lcla_pool.lock);
3560
3561 base->irq = platform_get_irq(pdev, 0);
3562
3563 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
3564 if (ret) {
3565 d40_err(&pdev->dev, "No IRQ defined\n");
3566 goto failure;
3567 }
3568
3569 pm_runtime_irq_safe(base->dev);
3570 pm_runtime_set_autosuspend_delay(base->dev, DMA40_AUTOSUSPEND_DELAY);
3571 pm_runtime_use_autosuspend(base->dev);
3572 pm_runtime_enable(base->dev);
3573 pm_runtime_resume(base->dev);
3574
3575 if (base->plat_data->use_esram_lcla) {
3576
3577 base->lcpa_regulator = regulator_get(base->dev, "lcla_esram");
3578 if (IS_ERR(base->lcpa_regulator)) {
3579 d40_err(&pdev->dev, "Failed to get lcpa_regulator\n");
3580 base->lcpa_regulator = NULL;
3581 goto failure;
3582 }
3583
3584 ret = regulator_enable(base->lcpa_regulator);
3585 if (ret) {
3586 d40_err(&pdev->dev,
3587 "Failed to enable lcpa_regulator\n");
3588 regulator_put(base->lcpa_regulator);
3589 base->lcpa_regulator = NULL;
3590 goto failure;
3591 }
3592 }
3593
3594 base->initialized = true;
3595 err = d40_dmaengine_init(base, num_reserved_chans);
3596 if (err)
3597 goto failure;
3598
3599 base->dev->dma_parms = &base->dma_parms;
3600 err = dma_set_max_seg_size(base->dev, STEDMA40_MAX_SEG_SIZE);
3601 if (err) {
3602 d40_err(&pdev->dev, "Failed to set dma max seg size\n");
3603 goto failure;
3604 }
3605
3606 d40_hw_init(base);
3607
3608 dev_info(base->dev, "initialized\n");
3609 return 0;
3610
3611 failure:
3612 if (base) {
3613 if (base->desc_slab)
3614 kmem_cache_destroy(base->desc_slab);
3615 if (base->virtbase)
3616 iounmap(base->virtbase);
3617
3618 if (base->lcla_pool.base && base->plat_data->use_esram_lcla) {
3619 iounmap(base->lcla_pool.base);
3620 base->lcla_pool.base = NULL;
3621 }
3622
3623 if (base->lcla_pool.dma_addr)
3624 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
3625 SZ_1K * base->num_phy_chans,
3626 DMA_TO_DEVICE);
3627
3628 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
3629 free_pages((unsigned long)base->lcla_pool.base,
3630 base->lcla_pool.pages);
3631
3632 kfree(base->lcla_pool.base_unaligned);
3633
3634 if (base->phy_lcpa)
3635 release_mem_region(base->phy_lcpa,
3636 base->lcpa_size);
3637 if (base->phy_start)
3638 release_mem_region(base->phy_start,
3639 base->phy_size);
3640 if (base->clk) {
3641 clk_disable_unprepare(base->clk);
3642 clk_put(base->clk);
3643 }
3644
3645 if (base->lcpa_regulator) {
3646 regulator_disable(base->lcpa_regulator);
3647 regulator_put(base->lcpa_regulator);
3648 }
3649
3650 kfree(base->lcla_pool.alloc_map);
3651 kfree(base->lookup_log_chans);
3652 kfree(base->lookup_phy_chans);
3653 kfree(base->phy_res);
3654 kfree(base);
3655 }
3656
3657 d40_err(&pdev->dev, "probe failed\n");
3658 return ret;
3659 }
3660
3661 static struct platform_driver d40_driver = {
3662 .driver = {
3663 .owner = THIS_MODULE,
3664 .name = D40_NAME,
3665 .pm = DMA40_PM_OPS,
3666 },
3667 };
3668
3669 static int __init stedma40_init(void)
3670 {
3671 return platform_driver_probe(&d40_driver, d40_probe);
3672 }
3673 subsys_initcall(stedma40_init);
kernel source for telekom puls (alcatel/mediatek)