drivers/clocksource/clksrc-dbx500-prcmu.c

   1 /*
   2  * Copyright (C) ST-Ericsson SA 2011
   3  *
   4  * License Terms: GNU General Public License v2
   5  * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson
   6  * Author: Sundar Iyer for ST-Ericsson
   7  * sched_clock implementation is based on:
   8  * plat-nomadik/timer.c Linus Walleij <linus.walleij@stericsson.com>
   9  *
  10  * DBx500-PRCMU Timer
  11  * The PRCMU has 5 timers which are available in a always-on
  12  * power domain.  We use the Timer 4 for our always-on clock
  13  * source on DB8500 and Timer 3 on DB5500.
  14  */
  15 #include <linux/clockchips.h>
  16 #include <linux/clksrc-dbx500-prcmu.h>
  17
  18 #include <asm/sched_clock.h>
  19
  20 #define RATE_32K                32768
  21
  22 #define TIMER_MODE_CONTINOUS    0x1
  23 #define TIMER_DOWNCOUNT_VAL     0xffffffff
  24
  25 #define PRCMU_TIMER_REF         0
  26 #define PRCMU_TIMER_DOWNCOUNT   0x4
  27 #define PRCMU_TIMER_MODE        0x8
  28
  29 #define SCHED_CLOCK_MIN_WRAP 131072 /* 2^32 / 32768 */
  30
  31 static void __iomem *clksrc_dbx500_timer_base;
  32
  33 static cycle_t clksrc_dbx500_prcmu_read(struct clocksource *cs)
  34 {
  35         u32 count, count2;
  36
  37         do {
  38                 count = readl(clksrc_dbx500_timer_base +
  39                               PRCMU_TIMER_DOWNCOUNT);
  40                 count2 = readl(clksrc_dbx500_timer_base +
  41                                PRCMU_TIMER_DOWNCOUNT);
  42         } while (count2 != count);
  43
  44         /* Negate because the timer is a decrementing counter */
  45         return ~count;
  46 }
  47
  48 static struct clocksource clocksource_dbx500_prcmu = {
  49         .name           = "dbx500-prcmu-timer",
  50         .rating         = 300,
  51         .read           = clksrc_dbx500_prcmu_read,
  52         .mask           = CLOCKSOURCE_MASK(32),
  53         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  54 };
  55
  56 #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
  57
  58 static u32 notrace dbx500_prcmu_sched_clock_read(void)
  59 {
  60         if (unlikely(!clksrc_dbx500_timer_base))
  61                 return 0;
  62
  63         return clksrc_dbx500_prcmu_read(&clocksource_dbx500_prcmu);
  64 }
  65
  66 #endif
  67
  68 void __init clksrc_dbx500_prcmu_init(void __iomem *base)
  69 {
  70         clksrc_dbx500_timer_base = base;
  71
  72         /*
  73          * The A9 sub system expects the timer to be configured as
  74          * a continous looping timer.
  75          * The PRCMU should configure it but if it for some reason
  76          * don't we do it here.
  77          */
  78         if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
  79             TIMER_MODE_CONTINOUS) {
  80                 writel(TIMER_MODE_CONTINOUS,
  81                        clksrc_dbx500_timer_base + PRCMU_TIMER_MODE);
  82                 writel(TIMER_DOWNCOUNT_VAL,
  83                        clksrc_dbx500_timer_base + PRCMU_TIMER_REF);
  84         }
  85 #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK
  86         setup_sched_clock(dbx500_prcmu_sched_clock_read,
  87                          32, RATE_32K);
  88 #endif
  89         clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
  90 }