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bus: mvebu-mbus: allow several windows with the same target/attribute
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / bus / mvebu-mbus.c
1 /*
2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
13 *
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
18 * attribute).
19 *
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
23 *
24 * This driver:
25 *
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
35 *
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
38 * device accesses. This API is mvebu_mbus_add_window(),
39 * mvebu_mbus_add_window_remap_flags() and
40 * mvebu_mbus_del_window(). Since the (target, attribute) values
41 * differ from one SoC family to another, the API uses a 'const char
42 * *' string to identify devices, and this driver is responsible for
43 * knowing the mapping between the name of a device and its
44 * corresponding (target, attribute) in the current SoC family.
45 *
46 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
47 * see the list of CPU -> SDRAM windows and their configuration
48 * (file 'sdram') and the list of CPU -> devices windows and their
49 * configuration (file 'devices').
50 */
51
52 #include <linux/kernel.h>
53 #include <linux/module.h>
54 #include <linux/init.h>
55 #include <linux/mbus.h>
56 #include <linux/io.h>
57 #include <linux/ioport.h>
58 #include <linux/of.h>
59 #include <linux/of_address.h>
60 #include <linux/debugfs.h>
61
62 /*
63 * DDR target is the same on all platforms.
64 */
65 #define TARGET_DDR 0
66
67 /*
68 * CPU Address Decode Windows registers
69 */
70 #define WIN_CTRL_OFF 0x0000
71 #define WIN_CTRL_ENABLE BIT(0)
72 #define WIN_CTRL_TGT_MASK 0xf0
73 #define WIN_CTRL_TGT_SHIFT 4
74 #define WIN_CTRL_ATTR_MASK 0xff00
75 #define WIN_CTRL_ATTR_SHIFT 8
76 #define WIN_CTRL_SIZE_MASK 0xffff0000
77 #define WIN_CTRL_SIZE_SHIFT 16
78 #define WIN_BASE_OFF 0x0004
79 #define WIN_BASE_LOW 0xffff0000
80 #define WIN_BASE_HIGH 0xf
81 #define WIN_REMAP_LO_OFF 0x0008
82 #define WIN_REMAP_LOW 0xffff0000
83 #define WIN_REMAP_HI_OFF 0x000c
84
85 #define ATTR_HW_COHERENCY (0x1 << 4)
86
87 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
88 #define DDR_BASE_CS_HIGH_MASK 0xf
89 #define DDR_BASE_CS_LOW_MASK 0xff000000
90 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
91 #define DDR_SIZE_ENABLED BIT(0)
92 #define DDR_SIZE_CS_MASK 0x1c
93 #define DDR_SIZE_CS_SHIFT 2
94 #define DDR_SIZE_MASK 0xff000000
95
96 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
97
98 struct mvebu_mbus_mapping {
99 const char *name;
100 u8 target;
101 u8 attr;
102 u8 attrmask;
103 };
104
105 /*
106 * Masks used for the 'attrmask' field of mvebu_mbus_mapping. They
107 * allow to get the real attribute value, discarding the special bits
108 * used to select a PCI MEM region or a PCI WA region. This allows the
109 * debugfs code to reverse-match the name of a device from its
110 * target/attr values.
111 *
112 * For all devices except PCI, all bits of 'attr' must be
113 * considered. For most SoCs, only bit 3 should be ignored (it allows
114 * to select between PCI MEM and PCI I/O). On Orion5x however, there
115 * is the special bit 5 to select a PCI WA region.
116 */
117 #define MAPDEF_NOMASK 0xff
118 #define MAPDEF_PCIMASK 0xf7
119 #define MAPDEF_ORIONPCIMASK 0xd7
120
121 /* Macro used to define one mvebu_mbus_mapping entry */
122 #define MAPDEF(__n, __t, __a, __m) \
123 { .name = __n, .target = __t, .attr = __a, .attrmask = __m }
124
125 struct mvebu_mbus_state;
126
127 struct mvebu_mbus_soc_data {
128 unsigned int num_wins;
129 unsigned int num_remappable_wins;
130 unsigned int (*win_cfg_offset)(const int win);
131 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
132 int (*show_cpu_target)(struct mvebu_mbus_state *s,
133 struct seq_file *seq, void *v);
134 const struct mvebu_mbus_mapping *map;
135 };
136
137 struct mvebu_mbus_state {
138 void __iomem *mbuswins_base;
139 void __iomem *sdramwins_base;
140 struct dentry *debugfs_root;
141 struct dentry *debugfs_sdram;
142 struct dentry *debugfs_devs;
143 const struct mvebu_mbus_soc_data *soc;
144 int hw_io_coherency;
145 };
146
147 static struct mvebu_mbus_state mbus_state;
148
149 static struct mbus_dram_target_info mvebu_mbus_dram_info;
150 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
151 {
152 return &mvebu_mbus_dram_info;
153 }
154 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
155
156 /*
157 * Functions to manipulate the address decoding windows
158 */
159
160 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
161 int win, int *enabled, u64 *base,
162 u32 *size, u8 *target, u8 *attr,
163 u64 *remap)
164 {
165 void __iomem *addr = mbus->mbuswins_base +
166 mbus->soc->win_cfg_offset(win);
167 u32 basereg = readl(addr + WIN_BASE_OFF);
168 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
169
170 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
171 *enabled = 0;
172 return;
173 }
174
175 *enabled = 1;
176 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
177 *base |= (basereg & WIN_BASE_LOW);
178 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
179
180 if (target)
181 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
182
183 if (attr)
184 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
185
186 if (remap) {
187 if (win < mbus->soc->num_remappable_wins) {
188 u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
189 u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
190 *remap = ((u64)remap_hi << 32) | remap_low;
191 } else
192 *remap = 0;
193 }
194 }
195
196 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
197 int win)
198 {
199 void __iomem *addr;
200
201 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
202
203 writel(0, addr + WIN_BASE_OFF);
204 writel(0, addr + WIN_CTRL_OFF);
205 if (win < mbus->soc->num_remappable_wins) {
206 writel(0, addr + WIN_REMAP_LO_OFF);
207 writel(0, addr + WIN_REMAP_HI_OFF);
208 }
209 }
210
211 /* Checks whether the given window number is available */
212 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
213 const int win)
214 {
215 void __iomem *addr = mbus->mbuswins_base +
216 mbus->soc->win_cfg_offset(win);
217 u32 ctrl = readl(addr + WIN_CTRL_OFF);
218 return !(ctrl & WIN_CTRL_ENABLE);
219 }
220
221 /*
222 * Checks whether the given (base, base+size) area doesn't overlap an
223 * existing region
224 */
225 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
226 phys_addr_t base, size_t size,
227 u8 target, u8 attr)
228 {
229 u64 end = (u64)base + size;
230 int win;
231
232 for (win = 0; win < mbus->soc->num_wins; win++) {
233 u64 wbase, wend;
234 u32 wsize;
235 u8 wtarget, wattr;
236 int enabled;
237
238 mvebu_mbus_read_window(mbus, win,
239 &enabled, &wbase, &wsize,
240 &wtarget, &wattr, NULL);
241
242 if (!enabled)
243 continue;
244
245 wend = wbase + wsize;
246
247 /*
248 * Check if the current window overlaps with the
249 * proposed physical range
250 */
251 if ((u64)base < wend && end > wbase)
252 return 0;
253 }
254
255 return 1;
256 }
257
258 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
259 phys_addr_t base, size_t size)
260 {
261 int win;
262
263 for (win = 0; win < mbus->soc->num_wins; win++) {
264 u64 wbase;
265 u32 wsize;
266 int enabled;
267
268 mvebu_mbus_read_window(mbus, win,
269 &enabled, &wbase, &wsize,
270 NULL, NULL, NULL);
271
272 if (!enabled)
273 continue;
274
275 if (base == wbase && size == wsize)
276 return win;
277 }
278
279 return -ENODEV;
280 }
281
282 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
283 int win, phys_addr_t base, size_t size,
284 phys_addr_t remap, u8 target,
285 u8 attr)
286 {
287 void __iomem *addr = mbus->mbuswins_base +
288 mbus->soc->win_cfg_offset(win);
289 u32 ctrl, remap_addr;
290
291 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
292 (attr << WIN_CTRL_ATTR_SHIFT) |
293 (target << WIN_CTRL_TGT_SHIFT) |
294 WIN_CTRL_ENABLE;
295
296 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
297 writel(ctrl, addr + WIN_CTRL_OFF);
298 if (win < mbus->soc->num_remappable_wins) {
299 if (remap == MVEBU_MBUS_NO_REMAP)
300 remap_addr = base;
301 else
302 remap_addr = remap;
303 writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
304 writel(0, addr + WIN_REMAP_HI_OFF);
305 }
306
307 return 0;
308 }
309
310 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
311 phys_addr_t base, size_t size,
312 phys_addr_t remap, u8 target,
313 u8 attr)
314 {
315 int win;
316
317 if (remap == MVEBU_MBUS_NO_REMAP) {
318 for (win = mbus->soc->num_remappable_wins;
319 win < mbus->soc->num_wins; win++)
320 if (mvebu_mbus_window_is_free(mbus, win))
321 return mvebu_mbus_setup_window(mbus, win, base,
322 size, remap,
323 target, attr);
324 }
325
326
327 for (win = 0; win < mbus->soc->num_wins; win++)
328 if (mvebu_mbus_window_is_free(mbus, win))
329 return mvebu_mbus_setup_window(mbus, win, base, size,
330 remap, target, attr);
331
332 return -ENOMEM;
333 }
334
335 /*
336 * Debugfs debugging
337 */
338
339 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
340 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
341 struct seq_file *seq, void *v)
342 {
343 int i;
344
345 for (i = 0; i < 4; i++) {
346 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
347 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
348 u64 base;
349 u32 size;
350
351 if (!(sizereg & DDR_SIZE_ENABLED)) {
352 seq_printf(seq, "[%d] disabled\n", i);
353 continue;
354 }
355
356 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
357 base |= basereg & DDR_BASE_CS_LOW_MASK;
358 size = (sizereg | ~DDR_SIZE_MASK);
359
360 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
361 i, (unsigned long long)base,
362 (unsigned long long)base + size + 1,
363 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
364 }
365
366 return 0;
367 }
368
369 /* Special function for Dove */
370 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
371 struct seq_file *seq, void *v)
372 {
373 int i;
374
375 for (i = 0; i < 2; i++) {
376 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
377 u64 base;
378 u32 size;
379
380 if (!(map & 1)) {
381 seq_printf(seq, "[%d] disabled\n", i);
382 continue;
383 }
384
385 base = map & 0xff800000;
386 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
387
388 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
389 i, (unsigned long long)base,
390 (unsigned long long)base + size, i);
391 }
392
393 return 0;
394 }
395
396 static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
397 {
398 struct mvebu_mbus_state *mbus = &mbus_state;
399 return mbus->soc->show_cpu_target(mbus, seq, v);
400 }
401
402 static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
403 {
404 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
405 }
406
407 static const struct file_operations mvebu_sdram_debug_fops = {
408 .open = mvebu_sdram_debug_open,
409 .read = seq_read,
410 .llseek = seq_lseek,
411 .release = single_release,
412 };
413
414 static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
415 {
416 struct mvebu_mbus_state *mbus = &mbus_state;
417 int win;
418
419 for (win = 0; win < mbus->soc->num_wins; win++) {
420 u64 wbase, wremap;
421 u32 wsize;
422 u8 wtarget, wattr;
423 int enabled, i;
424 const char *name;
425
426 mvebu_mbus_read_window(mbus, win,
427 &enabled, &wbase, &wsize,
428 &wtarget, &wattr, &wremap);
429
430 if (!enabled) {
431 seq_printf(seq, "[%02d] disabled\n", win);
432 continue;
433 }
434
435
436 for (i = 0; mbus->soc->map[i].name; i++)
437 if (mbus->soc->map[i].target == wtarget &&
438 mbus->soc->map[i].attr ==
439 (wattr & mbus->soc->map[i].attrmask))
440 break;
441
442 name = mbus->soc->map[i].name ?: "unknown";
443
444 seq_printf(seq, "[%02d] %016llx - %016llx : %s",
445 win, (unsigned long long)wbase,
446 (unsigned long long)(wbase + wsize), name);
447
448 if (win < mbus->soc->num_remappable_wins) {
449 seq_printf(seq, " (remap %016llx)\n",
450 (unsigned long long)wremap);
451 } else
452 seq_printf(seq, "\n");
453 }
454
455 return 0;
456 }
457
458 static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
459 {
460 return single_open(file, mvebu_devs_debug_show, inode->i_private);
461 }
462
463 static const struct file_operations mvebu_devs_debug_fops = {
464 .open = mvebu_devs_debug_open,
465 .read = seq_read,
466 .llseek = seq_lseek,
467 .release = single_release,
468 };
469
470 /*
471 * SoC-specific functions and definitions
472 */
473
474 static unsigned int orion_mbus_win_offset(int win)
475 {
476 return win << 4;
477 }
478
479 static unsigned int armada_370_xp_mbus_win_offset(int win)
480 {
481 /* The register layout is a bit annoying and the below code
482 * tries to cope with it.
483 * - At offset 0x0, there are the registers for the first 8
484 * windows, with 4 registers of 32 bits per window (ctrl,
485 * base, remap low, remap high)
486 * - Then at offset 0x80, there is a hole of 0x10 bytes for
487 * the internal registers base address and internal units
488 * sync barrier register.
489 * - Then at offset 0x90, there the registers for 12
490 * windows, with only 2 registers of 32 bits per window
491 * (ctrl, base).
492 */
493 if (win < 8)
494 return win << 4;
495 else
496 return 0x90 + ((win - 8) << 3);
497 }
498
499 static unsigned int mv78xx0_mbus_win_offset(int win)
500 {
501 if (win < 8)
502 return win << 4;
503 else
504 return 0x900 + ((win - 8) << 4);
505 }
506
507 static void __init
508 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
509 {
510 int i;
511 int cs;
512
513 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
514
515 for (i = 0, cs = 0; i < 4; i++) {
516 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
517 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
518
519 /*
520 * We only take care of entries for which the chip
521 * select is enabled, and that don't have high base
522 * address bits set (devices can only access the first
523 * 32 bits of the memory).
524 */
525 if ((size & DDR_SIZE_ENABLED) &&
526 !(base & DDR_BASE_CS_HIGH_MASK)) {
527 struct mbus_dram_window *w;
528
529 w = &mvebu_mbus_dram_info.cs[cs++];
530 w->cs_index = i;
531 w->mbus_attr = 0xf & ~(1 << i);
532 if (mbus->hw_io_coherency)
533 w->mbus_attr |= ATTR_HW_COHERENCY;
534 w->base = base & DDR_BASE_CS_LOW_MASK;
535 w->size = (size | ~DDR_SIZE_MASK) + 1;
536 }
537 }
538 mvebu_mbus_dram_info.num_cs = cs;
539 }
540
541 static void __init
542 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
543 {
544 int i;
545 int cs;
546
547 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
548
549 for (i = 0, cs = 0; i < 2; i++) {
550 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
551
552 /*
553 * Chip select enabled?
554 */
555 if (map & 1) {
556 struct mbus_dram_window *w;
557
558 w = &mvebu_mbus_dram_info.cs[cs++];
559 w->cs_index = i;
560 w->mbus_attr = 0; /* CS address decoding done inside */
561 /* the DDR controller, no need to */
562 /* provide attributes */
563 w->base = map & 0xff800000;
564 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
565 }
566 }
567
568 mvebu_mbus_dram_info.num_cs = cs;
569 }
570
571 static const struct mvebu_mbus_mapping armada_370_map[] = {
572 MAPDEF("bootrom", 1, 0xe0, MAPDEF_NOMASK),
573 MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
574 MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
575 MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
576 MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
577 MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
578 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
579 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
580 {},
581 };
582
583 static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
584 .num_wins = 20,
585 .num_remappable_wins = 8,
586 .win_cfg_offset = armada_370_xp_mbus_win_offset,
587 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
588 .show_cpu_target = mvebu_sdram_debug_show_orion,
589 .map = armada_370_map,
590 };
591
592 static const struct mvebu_mbus_mapping armada_xp_map[] = {
593 MAPDEF("bootrom", 1, 0x1d, MAPDEF_NOMASK),
594 MAPDEF("devbus-boot", 1, 0x2f, MAPDEF_NOMASK),
595 MAPDEF("devbus-cs0", 1, 0x3e, MAPDEF_NOMASK),
596 MAPDEF("devbus-cs1", 1, 0x3d, MAPDEF_NOMASK),
597 MAPDEF("devbus-cs2", 1, 0x3b, MAPDEF_NOMASK),
598 MAPDEF("devbus-cs3", 1, 0x37, MAPDEF_NOMASK),
599 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
600 MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
601 MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
602 MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
603 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
604 MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
605 MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
606 MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
607 MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
608 MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
609 {},
610 };
611
612 static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
613 .num_wins = 20,
614 .num_remappable_wins = 8,
615 .win_cfg_offset = armada_370_xp_mbus_win_offset,
616 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
617 .show_cpu_target = mvebu_sdram_debug_show_orion,
618 .map = armada_xp_map,
619 };
620
621 static const struct mvebu_mbus_mapping kirkwood_map[] = {
622 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
623 MAPDEF("pcie1.0", 4, 0xd0, MAPDEF_PCIMASK),
624 MAPDEF("sram", 3, 0x01, MAPDEF_NOMASK),
625 MAPDEF("nand", 1, 0x2f, MAPDEF_NOMASK),
626 {},
627 };
628
629 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
630 .num_wins = 8,
631 .num_remappable_wins = 4,
632 .win_cfg_offset = orion_mbus_win_offset,
633 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
634 .show_cpu_target = mvebu_sdram_debug_show_orion,
635 .map = kirkwood_map,
636 };
637
638 static const struct mvebu_mbus_mapping dove_map[] = {
639 MAPDEF("pcie0.0", 0x4, 0xe0, MAPDEF_PCIMASK),
640 MAPDEF("pcie1.0", 0x8, 0xe0, MAPDEF_PCIMASK),
641 MAPDEF("cesa", 0x3, 0x01, MAPDEF_NOMASK),
642 MAPDEF("bootrom", 0x1, 0xfd, MAPDEF_NOMASK),
643 MAPDEF("scratchpad", 0xd, 0x0, MAPDEF_NOMASK),
644 {},
645 };
646
647 static const struct mvebu_mbus_soc_data dove_mbus_data = {
648 .num_wins = 8,
649 .num_remappable_wins = 4,
650 .win_cfg_offset = orion_mbus_win_offset,
651 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
652 .show_cpu_target = mvebu_sdram_debug_show_dove,
653 .map = dove_map,
654 };
655
656 static const struct mvebu_mbus_mapping orion5x_map[] = {
657 MAPDEF("pcie0.0", 4, 0x51, MAPDEF_ORIONPCIMASK),
658 MAPDEF("pci0.0", 3, 0x51, MAPDEF_ORIONPCIMASK),
659 MAPDEF("devbus-boot", 1, 0x0f, MAPDEF_NOMASK),
660 MAPDEF("devbus-cs0", 1, 0x1e, MAPDEF_NOMASK),
661 MAPDEF("devbus-cs1", 1, 0x1d, MAPDEF_NOMASK),
662 MAPDEF("devbus-cs2", 1, 0x1b, MAPDEF_NOMASK),
663 MAPDEF("sram", 0, 0x00, MAPDEF_NOMASK),
664 {},
665 };
666
667 /*
668 * Some variants of Orion5x have 4 remappable windows, some other have
669 * only two of them.
670 */
671 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
672 .num_wins = 8,
673 .num_remappable_wins = 4,
674 .win_cfg_offset = orion_mbus_win_offset,
675 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
676 .show_cpu_target = mvebu_sdram_debug_show_orion,
677 .map = orion5x_map,
678 };
679
680 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
681 .num_wins = 8,
682 .num_remappable_wins = 2,
683 .win_cfg_offset = orion_mbus_win_offset,
684 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
685 .show_cpu_target = mvebu_sdram_debug_show_orion,
686 .map = orion5x_map,
687 };
688
689 static const struct mvebu_mbus_mapping mv78xx0_map[] = {
690 MAPDEF("pcie0.0", 4, 0xe0, MAPDEF_PCIMASK),
691 MAPDEF("pcie0.1", 4, 0xd0, MAPDEF_PCIMASK),
692 MAPDEF("pcie0.2", 4, 0xb0, MAPDEF_PCIMASK),
693 MAPDEF("pcie0.3", 4, 0x70, MAPDEF_PCIMASK),
694 MAPDEF("pcie1.0", 8, 0xe0, MAPDEF_PCIMASK),
695 MAPDEF("pcie1.1", 8, 0xd0, MAPDEF_PCIMASK),
696 MAPDEF("pcie1.2", 8, 0xb0, MAPDEF_PCIMASK),
697 MAPDEF("pcie1.3", 8, 0x70, MAPDEF_PCIMASK),
698 MAPDEF("pcie2.0", 4, 0xf0, MAPDEF_PCIMASK),
699 MAPDEF("pcie3.0", 8, 0xf0, MAPDEF_PCIMASK),
700 {},
701 };
702
703 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
704 .num_wins = 14,
705 .num_remappable_wins = 8,
706 .win_cfg_offset = mv78xx0_mbus_win_offset,
707 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
708 .show_cpu_target = mvebu_sdram_debug_show_orion,
709 .map = mv78xx0_map,
710 };
711
712 /*
713 * The driver doesn't yet have a DT binding because the details of
714 * this DT binding still need to be sorted out. However, as a
715 * preparation, we already use of_device_id to match a SoC description
716 * string against the SoC specific details of this driver.
717 */
718 static const struct of_device_id of_mvebu_mbus_ids[] = {
719 { .compatible = "marvell,armada370-mbus",
720 .data = &armada_370_mbus_data, },
721 { .compatible = "marvell,armadaxp-mbus",
722 .data = &armada_xp_mbus_data, },
723 { .compatible = "marvell,kirkwood-mbus",
724 .data = &kirkwood_mbus_data, },
725 { .compatible = "marvell,dove-mbus",
726 .data = &dove_mbus_data, },
727 { .compatible = "marvell,orion5x-88f5281-mbus",
728 .data = &orion5x_4win_mbus_data, },
729 { .compatible = "marvell,orion5x-88f5182-mbus",
730 .data = &orion5x_2win_mbus_data, },
731 { .compatible = "marvell,orion5x-88f5181-mbus",
732 .data = &orion5x_2win_mbus_data, },
733 { .compatible = "marvell,orion5x-88f6183-mbus",
734 .data = &orion5x_4win_mbus_data, },
735 { .compatible = "marvell,mv78xx0-mbus",
736 .data = &mv78xx0_mbus_data, },
737 { },
738 };
739
740 /*
741 * Public API of the driver
742 */
743 int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
744 size_t size, phys_addr_t remap,
745 unsigned int flags)
746 {
747 struct mvebu_mbus_state *s = &mbus_state;
748 u8 target, attr;
749 int i;
750
751 if (!s->soc->map)
752 return -ENODEV;
753
754 for (i = 0; s->soc->map[i].name; i++)
755 if (!strcmp(s->soc->map[i].name, devname))
756 break;
757
758 if (!s->soc->map[i].name) {
759 pr_err("mvebu-mbus: unknown device '%s'\n", devname);
760 return -ENODEV;
761 }
762
763 target = s->soc->map[i].target;
764 attr = s->soc->map[i].attr;
765
766 if (flags == MVEBU_MBUS_PCI_MEM)
767 attr |= 0x8;
768 else if (flags == MVEBU_MBUS_PCI_WA)
769 attr |= 0x28;
770
771 if (!mvebu_mbus_window_conflicts(s, base, size, target, attr)) {
772 pr_err("mvebu-mbus: cannot add window '%s', conflicts with another window\n",
773 devname);
774 return -EINVAL;
775 }
776
777 return mvebu_mbus_alloc_window(s, base, size, remap, target, attr);
778
779 }
780
781 int mvebu_mbus_add_window(const char *devname, phys_addr_t base, size_t size)
782 {
783 return mvebu_mbus_add_window_remap_flags(devname, base, size,
784 MVEBU_MBUS_NO_REMAP, 0);
785 }
786
787 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
788 {
789 int win;
790
791 win = mvebu_mbus_find_window(&mbus_state, base, size);
792 if (win < 0)
793 return win;
794
795 mvebu_mbus_disable_window(&mbus_state, win);
796 return 0;
797 }
798
799 static __init int mvebu_mbus_debugfs_init(void)
800 {
801 struct mvebu_mbus_state *s = &mbus_state;
802
803 /*
804 * If no base has been initialized, doesn't make sense to
805 * register the debugfs entries. We may be on a multiplatform
806 * kernel that isn't running a Marvell EBU SoC.
807 */
808 if (!s->mbuswins_base)
809 return 0;
810
811 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
812 if (s->debugfs_root) {
813 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
814 s->debugfs_root, NULL,
815 &mvebu_sdram_debug_fops);
816 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
817 s->debugfs_root, NULL,
818 &mvebu_devs_debug_fops);
819 }
820
821 return 0;
822 }
823 fs_initcall(mvebu_mbus_debugfs_init);
824
825 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
826 size_t mbuswins_size,
827 phys_addr_t sdramwins_phys_base,
828 size_t sdramwins_size)
829 {
830 struct mvebu_mbus_state *mbus = &mbus_state;
831 const struct of_device_id *of_id;
832 int win;
833
834 for (of_id = of_mvebu_mbus_ids; of_id->compatible; of_id++)
835 if (!strcmp(of_id->compatible, soc))
836 break;
837
838 if (!of_id->compatible) {
839 pr_err("mvebu-mbus: could not find a matching SoC family\n");
840 return -ENODEV;
841 }
842
843 mbus->soc = of_id->data;
844
845 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
846 if (!mbus->mbuswins_base)
847 return -ENOMEM;
848
849 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
850 if (!mbus->sdramwins_base) {
851 iounmap(mbus_state.mbuswins_base);
852 return -ENOMEM;
853 }
854
855 if (of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric"))
856 mbus->hw_io_coherency = 1;
857
858 for (win = 0; win < mbus->soc->num_wins; win++)
859 mvebu_mbus_disable_window(mbus, win);
860
861 mbus->soc->setup_cpu_target(mbus);
862
863 return 0;
864 }
kernel source for telekom puls (alcatel/mediatek)