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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / pdc_adma.c
1 /*
2 * pdc_adma.c - Pacific Digital Corporation ADMA
3 *
4 * Maintained by: Mark Lord <mlord@pobox.com>
5 *
6 * Copyright 2005 Mark Lord
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 *
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
25 *
26 *
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
29 *
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/gfp.h>
38 #include <linux/pci.h>
39 #include <linux/init.h>
40 #include <linux/blkdev.h>
41 #include <linux/delay.h>
42 #include <linux/interrupt.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <linux/libata.h>
46
47 #define DRV_NAME "pdc_adma"
48 #define DRV_VERSION "1.0"
49
50 /* macro to calculate base address for ATA regs */
51 #define ADMA_ATA_REGS(base, port_no) ((base) + ((port_no) * 0x40))
52
53 /* macro to calculate base address for ADMA regs */
54 #define ADMA_REGS(base, port_no) ((base) + 0x80 + ((port_no) * 0x20))
55
56 /* macro to obtain addresses from ata_port */
57 #define ADMA_PORT_REGS(ap) \
58 ADMA_REGS((ap)->host->iomap[ADMA_MMIO_BAR], ap->port_no)
59
60 enum {
61 ADMA_MMIO_BAR = 4,
62
63 ADMA_PORTS = 2,
64 ADMA_CPB_BYTES = 40,
65 ADMA_PRD_BYTES = LIBATA_MAX_PRD * 16,
66 ADMA_PKT_BYTES = ADMA_CPB_BYTES + ADMA_PRD_BYTES,
67
68 ADMA_DMA_BOUNDARY = 0xffffffff,
69
70 /* global register offsets */
71 ADMA_MODE_LOCK = 0x00c7,
72
73 /* per-channel register offsets */
74 ADMA_CONTROL = 0x0000, /* ADMA control */
75 ADMA_STATUS = 0x0002, /* ADMA status */
76 ADMA_CPB_COUNT = 0x0004, /* CPB count */
77 ADMA_CPB_CURRENT = 0x000c, /* current CPB address */
78 ADMA_CPB_NEXT = 0x000c, /* next CPB address */
79 ADMA_CPB_LOOKUP = 0x0010, /* CPB lookup table */
80 ADMA_FIFO_IN = 0x0014, /* input FIFO threshold */
81 ADMA_FIFO_OUT = 0x0016, /* output FIFO threshold */
82
83 /* ADMA_CONTROL register bits */
84 aNIEN = (1 << 8), /* irq mask: 1==masked */
85 aGO = (1 << 7), /* packet trigger ("Go!") */
86 aRSTADM = (1 << 5), /* ADMA logic reset */
87 aPIOMD4 = 0x0003, /* PIO mode 4 */
88
89 /* ADMA_STATUS register bits */
90 aPSD = (1 << 6),
91 aUIRQ = (1 << 4),
92 aPERR = (1 << 0),
93
94 /* CPB bits */
95 cDONE = (1 << 0),
96 cATERR = (1 << 3),
97
98 cVLD = (1 << 0),
99 cDAT = (1 << 2),
100 cIEN = (1 << 3),
101
102 /* PRD bits */
103 pORD = (1 << 4),
104 pDIRO = (1 << 5),
105 pEND = (1 << 7),
106
107 /* ATA register flags */
108 rIGN = (1 << 5),
109 rEND = (1 << 7),
110
111 /* ATA register addresses */
112 ADMA_REGS_CONTROL = 0x0e,
113 ADMA_REGS_SECTOR_COUNT = 0x12,
114 ADMA_REGS_LBA_LOW = 0x13,
115 ADMA_REGS_LBA_MID = 0x14,
116 ADMA_REGS_LBA_HIGH = 0x15,
117 ADMA_REGS_DEVICE = 0x16,
118 ADMA_REGS_COMMAND = 0x17,
119
120 /* PCI device IDs */
121 board_1841_idx = 0, /* ADMA 2-port controller */
122 };
123
124 typedef enum { adma_state_idle, adma_state_pkt, adma_state_mmio } adma_state_t;
125
126 struct adma_port_priv {
127 u8 *pkt;
128 dma_addr_t pkt_dma;
129 adma_state_t state;
130 };
131
132 static int adma_ata_init_one(struct pci_dev *pdev,
133 const struct pci_device_id *ent);
134 static int adma_port_start(struct ata_port *ap);
135 static void adma_port_stop(struct ata_port *ap);
136 static void adma_qc_prep(struct ata_queued_cmd *qc);
137 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc);
138 static int adma_check_atapi_dma(struct ata_queued_cmd *qc);
139 static void adma_freeze(struct ata_port *ap);
140 static void adma_thaw(struct ata_port *ap);
141 static int adma_prereset(struct ata_link *link, unsigned long deadline);
142
143 static struct scsi_host_template adma_ata_sht = {
144 ATA_BASE_SHT(DRV_NAME),
145 .sg_tablesize = LIBATA_MAX_PRD,
146 .dma_boundary = ADMA_DMA_BOUNDARY,
147 };
148
149 static struct ata_port_operations adma_ata_ops = {
150 .inherits = &ata_sff_port_ops,
151
152 .lost_interrupt = ATA_OP_NULL,
153
154 .check_atapi_dma = adma_check_atapi_dma,
155 .qc_prep = adma_qc_prep,
156 .qc_issue = adma_qc_issue,
157
158 .freeze = adma_freeze,
159 .thaw = adma_thaw,
160 .prereset = adma_prereset,
161
162 .port_start = adma_port_start,
163 .port_stop = adma_port_stop,
164 };
165
166 static struct ata_port_info adma_port_info[] = {
167 /* board_1841_idx */
168 {
169 .flags = ATA_FLAG_SLAVE_POSS |
170 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO |
171 ATA_FLAG_PIO_POLLING,
172 .pio_mask = ATA_PIO4_ONLY,
173 .udma_mask = ATA_UDMA4,
174 .port_ops = &adma_ata_ops,
175 },
176 };
177
178 static const struct pci_device_id adma_ata_pci_tbl[] = {
179 { PCI_VDEVICE(PDC, 0x1841), board_1841_idx },
180
181 { } /* terminate list */
182 };
183
184 static struct pci_driver adma_ata_pci_driver = {
185 .name = DRV_NAME,
186 .id_table = adma_ata_pci_tbl,
187 .probe = adma_ata_init_one,
188 .remove = ata_pci_remove_one,
189 };
190
191 static int adma_check_atapi_dma(struct ata_queued_cmd *qc)
192 {
193 return 1; /* ATAPI DMA not yet supported */
194 }
195
196 static void adma_reset_engine(struct ata_port *ap)
197 {
198 void __iomem *chan = ADMA_PORT_REGS(ap);
199
200 /* reset ADMA to idle state */
201 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
202 udelay(2);
203 writew(aPIOMD4, chan + ADMA_CONTROL);
204 udelay(2);
205 }
206
207 static void adma_reinit_engine(struct ata_port *ap)
208 {
209 struct adma_port_priv *pp = ap->private_data;
210 void __iomem *chan = ADMA_PORT_REGS(ap);
211
212 /* mask/clear ATA interrupts */
213 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
214 ata_sff_check_status(ap);
215
216 /* reset the ADMA engine */
217 adma_reset_engine(ap);
218
219 /* set in-FIFO threshold to 0x100 */
220 writew(0x100, chan + ADMA_FIFO_IN);
221
222 /* set CPB pointer */
223 writel((u32)pp->pkt_dma, chan + ADMA_CPB_NEXT);
224
225 /* set out-FIFO threshold to 0x100 */
226 writew(0x100, chan + ADMA_FIFO_OUT);
227
228 /* set CPB count */
229 writew(1, chan + ADMA_CPB_COUNT);
230
231 /* read/discard ADMA status */
232 readb(chan + ADMA_STATUS);
233 }
234
235 static inline void adma_enter_reg_mode(struct ata_port *ap)
236 {
237 void __iomem *chan = ADMA_PORT_REGS(ap);
238
239 writew(aPIOMD4, chan + ADMA_CONTROL);
240 readb(chan + ADMA_STATUS); /* flush */
241 }
242
243 static void adma_freeze(struct ata_port *ap)
244 {
245 void __iomem *chan = ADMA_PORT_REGS(ap);
246
247 /* mask/clear ATA interrupts */
248 writeb(ATA_NIEN, ap->ioaddr.ctl_addr);
249 ata_sff_check_status(ap);
250
251 /* reset ADMA to idle state */
252 writew(aPIOMD4 | aNIEN | aRSTADM, chan + ADMA_CONTROL);
253 udelay(2);
254 writew(aPIOMD4 | aNIEN, chan + ADMA_CONTROL);
255 udelay(2);
256 }
257
258 static void adma_thaw(struct ata_port *ap)
259 {
260 adma_reinit_engine(ap);
261 }
262
263 static int adma_prereset(struct ata_link *link, unsigned long deadline)
264 {
265 struct ata_port *ap = link->ap;
266 struct adma_port_priv *pp = ap->private_data;
267
268 if (pp->state != adma_state_idle) /* healthy paranoia */
269 pp->state = adma_state_mmio;
270 adma_reinit_engine(ap);
271
272 return ata_sff_prereset(link, deadline);
273 }
274
275 static int adma_fill_sg(struct ata_queued_cmd *qc)
276 {
277 struct scatterlist *sg;
278 struct ata_port *ap = qc->ap;
279 struct adma_port_priv *pp = ap->private_data;
280 u8 *buf = pp->pkt, *last_buf = NULL;
281 int i = (2 + buf[3]) * 8;
282 u8 pFLAGS = pORD | ((qc->tf.flags & ATA_TFLAG_WRITE) ? pDIRO : 0);
283 unsigned int si;
284
285 for_each_sg(qc->sg, sg, qc->n_elem, si) {
286 u32 addr;
287 u32 len;
288
289 addr = (u32)sg_dma_address(sg);
290 *(__le32 *)(buf + i) = cpu_to_le32(addr);
291 i += 4;
292
293 len = sg_dma_len(sg) >> 3;
294 *(__le32 *)(buf + i) = cpu_to_le32(len);
295 i += 4;
296
297 last_buf = &buf[i];
298 buf[i++] = pFLAGS;
299 buf[i++] = qc->dev->dma_mode & 0xf;
300 buf[i++] = 0; /* pPKLW */
301 buf[i++] = 0; /* reserved */
302
303 *(__le32 *)(buf + i) =
304 (pFLAGS & pEND) ? 0 : cpu_to_le32(pp->pkt_dma + i + 4);
305 i += 4;
306
307 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i/4,
308 (unsigned long)addr, len);
309 }
310
311 if (likely(last_buf))
312 *last_buf |= pEND;
313
314 return i;
315 }
316
317 static void adma_qc_prep(struct ata_queued_cmd *qc)
318 {
319 struct adma_port_priv *pp = qc->ap->private_data;
320 u8 *buf = pp->pkt;
321 u32 pkt_dma = (u32)pp->pkt_dma;
322 int i = 0;
323
324 VPRINTK("ENTER\n");
325
326 adma_enter_reg_mode(qc->ap);
327 if (qc->tf.protocol != ATA_PROT_DMA) {
328 ata_sff_qc_prep(qc);
329 return;
330 }
331
332 buf[i++] = 0; /* Response flags */
333 buf[i++] = 0; /* reserved */
334 buf[i++] = cVLD | cDAT | cIEN;
335 i++; /* cLEN, gets filled in below */
336
337 *(__le32 *)(buf+i) = cpu_to_le32(pkt_dma); /* cNCPB */
338 i += 4; /* cNCPB */
339 i += 4; /* cPRD, gets filled in below */
340
341 buf[i++] = 0; /* reserved */
342 buf[i++] = 0; /* reserved */
343 buf[i++] = 0; /* reserved */
344 buf[i++] = 0; /* reserved */
345
346 /* ATA registers; must be a multiple of 4 */
347 buf[i++] = qc->tf.device;
348 buf[i++] = ADMA_REGS_DEVICE;
349 if ((qc->tf.flags & ATA_TFLAG_LBA48)) {
350 buf[i++] = qc->tf.hob_nsect;
351 buf[i++] = ADMA_REGS_SECTOR_COUNT;
352 buf[i++] = qc->tf.hob_lbal;
353 buf[i++] = ADMA_REGS_LBA_LOW;
354 buf[i++] = qc->tf.hob_lbam;
355 buf[i++] = ADMA_REGS_LBA_MID;
356 buf[i++] = qc->tf.hob_lbah;
357 buf[i++] = ADMA_REGS_LBA_HIGH;
358 }
359 buf[i++] = qc->tf.nsect;
360 buf[i++] = ADMA_REGS_SECTOR_COUNT;
361 buf[i++] = qc->tf.lbal;
362 buf[i++] = ADMA_REGS_LBA_LOW;
363 buf[i++] = qc->tf.lbam;
364 buf[i++] = ADMA_REGS_LBA_MID;
365 buf[i++] = qc->tf.lbah;
366 buf[i++] = ADMA_REGS_LBA_HIGH;
367 buf[i++] = 0;
368 buf[i++] = ADMA_REGS_CONTROL;
369 buf[i++] = rIGN;
370 buf[i++] = 0;
371 buf[i++] = qc->tf.command;
372 buf[i++] = ADMA_REGS_COMMAND | rEND;
373
374 buf[3] = (i >> 3) - 2; /* cLEN */
375 *(__le32 *)(buf+8) = cpu_to_le32(pkt_dma + i); /* cPRD */
376
377 i = adma_fill_sg(qc);
378 wmb(); /* flush PRDs and pkt to memory */
379 #if 0
380 /* dump out CPB + PRDs for debug */
381 {
382 int j, len = 0;
383 static char obuf[2048];
384 for (j = 0; j < i; ++j) {
385 len += sprintf(obuf+len, "%02x ", buf[j]);
386 if ((j & 7) == 7) {
387 printk("%s\n", obuf);
388 len = 0;
389 }
390 }
391 if (len)
392 printk("%s\n", obuf);
393 }
394 #endif
395 }
396
397 static inline void adma_packet_start(struct ata_queued_cmd *qc)
398 {
399 struct ata_port *ap = qc->ap;
400 void __iomem *chan = ADMA_PORT_REGS(ap);
401
402 VPRINTK("ENTER, ap %p\n", ap);
403
404 /* fire up the ADMA engine */
405 writew(aPIOMD4 | aGO, chan + ADMA_CONTROL);
406 }
407
408 static unsigned int adma_qc_issue(struct ata_queued_cmd *qc)
409 {
410 struct adma_port_priv *pp = qc->ap->private_data;
411
412 switch (qc->tf.protocol) {
413 case ATA_PROT_DMA:
414 pp->state = adma_state_pkt;
415 adma_packet_start(qc);
416 return 0;
417
418 case ATAPI_PROT_DMA:
419 BUG();
420 break;
421
422 default:
423 break;
424 }
425
426 pp->state = adma_state_mmio;
427 return ata_sff_qc_issue(qc);
428 }
429
430 static inline unsigned int adma_intr_pkt(struct ata_host *host)
431 {
432 unsigned int handled = 0, port_no;
433
434 for (port_no = 0; port_no < host->n_ports; ++port_no) {
435 struct ata_port *ap = host->ports[port_no];
436 struct adma_port_priv *pp;
437 struct ata_queued_cmd *qc;
438 void __iomem *chan = ADMA_PORT_REGS(ap);
439 u8 status = readb(chan + ADMA_STATUS);
440
441 if (status == 0)
442 continue;
443 handled = 1;
444 adma_enter_reg_mode(ap);
445 if (ap->flags & ATA_FLAG_DISABLED)
446 continue;
447 pp = ap->private_data;
448 if (!pp || pp->state != adma_state_pkt)
449 continue;
450 qc = ata_qc_from_tag(ap, ap->link.active_tag);
451 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
452 if (status & aPERR)
453 qc->err_mask |= AC_ERR_HOST_BUS;
454 else if ((status & (aPSD | aUIRQ)))
455 qc->err_mask |= AC_ERR_OTHER;
456
457 if (pp->pkt[0] & cATERR)
458 qc->err_mask |= AC_ERR_DEV;
459 else if (pp->pkt[0] != cDONE)
460 qc->err_mask |= AC_ERR_OTHER;
461
462 if (!qc->err_mask)
463 ata_qc_complete(qc);
464 else {
465 struct ata_eh_info *ehi = &ap->link.eh_info;
466 ata_ehi_clear_desc(ehi);
467 ata_ehi_push_desc(ehi,
468 "ADMA-status 0x%02X", status);
469 ata_ehi_push_desc(ehi,
470 "pkt[0] 0x%02X", pp->pkt[0]);
471
472 if (qc->err_mask == AC_ERR_DEV)
473 ata_port_abort(ap);
474 else
475 ata_port_freeze(ap);
476 }
477 }
478 }
479 return handled;
480 }
481
482 static inline unsigned int adma_intr_mmio(struct ata_host *host)
483 {
484 unsigned int handled = 0, port_no;
485
486 for (port_no = 0; port_no < host->n_ports; ++port_no) {
487 struct ata_port *ap;
488 ap = host->ports[port_no];
489 if (ap && (!(ap->flags & ATA_FLAG_DISABLED))) {
490 struct ata_queued_cmd *qc;
491 struct adma_port_priv *pp = ap->private_data;
492 if (!pp || pp->state != adma_state_mmio)
493 continue;
494 qc = ata_qc_from_tag(ap, ap->link.active_tag);
495 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) {
496
497 /* check main status, clearing INTRQ */
498 u8 status = ata_sff_check_status(ap);
499 if ((status & ATA_BUSY))
500 continue;
501 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
502 ap->print_id, qc->tf.protocol, status);
503
504 /* complete taskfile transaction */
505 pp->state = adma_state_idle;
506 qc->err_mask |= ac_err_mask(status);
507 if (!qc->err_mask)
508 ata_qc_complete(qc);
509 else {
510 struct ata_eh_info *ehi =
511 &ap->link.eh_info;
512 ata_ehi_clear_desc(ehi);
513 ata_ehi_push_desc(ehi,
514 "status 0x%02X", status);
515
516 if (qc->err_mask == AC_ERR_DEV)
517 ata_port_abort(ap);
518 else
519 ata_port_freeze(ap);
520 }
521 handled = 1;
522 }
523 }
524 }
525 return handled;
526 }
527
528 static irqreturn_t adma_intr(int irq, void *dev_instance)
529 {
530 struct ata_host *host = dev_instance;
531 unsigned int handled = 0;
532
533 VPRINTK("ENTER\n");
534
535 spin_lock(&host->lock);
536 handled = adma_intr_pkt(host) | adma_intr_mmio(host);
537 spin_unlock(&host->lock);
538
539 VPRINTK("EXIT\n");
540
541 return IRQ_RETVAL(handled);
542 }
543
544 static void adma_ata_setup_port(struct ata_ioports *port, void __iomem *base)
545 {
546 port->cmd_addr =
547 port->data_addr = base + 0x000;
548 port->error_addr =
549 port->feature_addr = base + 0x004;
550 port->nsect_addr = base + 0x008;
551 port->lbal_addr = base + 0x00c;
552 port->lbam_addr = base + 0x010;
553 port->lbah_addr = base + 0x014;
554 port->device_addr = base + 0x018;
555 port->status_addr =
556 port->command_addr = base + 0x01c;
557 port->altstatus_addr =
558 port->ctl_addr = base + 0x038;
559 }
560
561 static int adma_port_start(struct ata_port *ap)
562 {
563 struct device *dev = ap->host->dev;
564 struct adma_port_priv *pp;
565 int rc;
566
567 rc = ata_port_start(ap);
568 if (rc)
569 return rc;
570 adma_enter_reg_mode(ap);
571 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
572 if (!pp)
573 return -ENOMEM;
574 pp->pkt = dmam_alloc_coherent(dev, ADMA_PKT_BYTES, &pp->pkt_dma,
575 GFP_KERNEL);
576 if (!pp->pkt)
577 return -ENOMEM;
578 /* paranoia? */
579 if ((pp->pkt_dma & 7) != 0) {
580 printk(KERN_ERR "bad alignment for pp->pkt_dma: %08x\n",
581 (u32)pp->pkt_dma);
582 return -ENOMEM;
583 }
584 memset(pp->pkt, 0, ADMA_PKT_BYTES);
585 ap->private_data = pp;
586 adma_reinit_engine(ap);
587 return 0;
588 }
589
590 static void adma_port_stop(struct ata_port *ap)
591 {
592 adma_reset_engine(ap);
593 }
594
595 static void adma_host_init(struct ata_host *host, unsigned int chip_id)
596 {
597 unsigned int port_no;
598
599 /* enable/lock aGO operation */
600 writeb(7, host->iomap[ADMA_MMIO_BAR] + ADMA_MODE_LOCK);
601
602 /* reset the ADMA logic */
603 for (port_no = 0; port_no < ADMA_PORTS; ++port_no)
604 adma_reset_engine(host->ports[port_no]);
605 }
606
607 static int adma_set_dma_masks(struct pci_dev *pdev, void __iomem *mmio_base)
608 {
609 int rc;
610
611 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
612 if (rc) {
613 dev_printk(KERN_ERR, &pdev->dev,
614 "32-bit DMA enable failed\n");
615 return rc;
616 }
617 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
618 if (rc) {
619 dev_printk(KERN_ERR, &pdev->dev,
620 "32-bit consistent DMA enable failed\n");
621 return rc;
622 }
623 return 0;
624 }
625
626 static int adma_ata_init_one(struct pci_dev *pdev,
627 const struct pci_device_id *ent)
628 {
629 static int printed_version;
630 unsigned int board_idx = (unsigned int) ent->driver_data;
631 const struct ata_port_info *ppi[] = { &adma_port_info[board_idx], NULL };
632 struct ata_host *host;
633 void __iomem *mmio_base;
634 int rc, port_no;
635
636 if (!printed_version++)
637 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
638
639 /* alloc host */
640 host = ata_host_alloc_pinfo(&pdev->dev, ppi, ADMA_PORTS);
641 if (!host)
642 return -ENOMEM;
643
644 /* acquire resources and fill host */
645 rc = pcim_enable_device(pdev);
646 if (rc)
647 return rc;
648
649 if ((pci_resource_flags(pdev, 4) & IORESOURCE_MEM) == 0)
650 return -ENODEV;
651
652 rc = pcim_iomap_regions(pdev, 1 << ADMA_MMIO_BAR, DRV_NAME);
653 if (rc)
654 return rc;
655 host->iomap = pcim_iomap_table(pdev);
656 mmio_base = host->iomap[ADMA_MMIO_BAR];
657
658 rc = adma_set_dma_masks(pdev, mmio_base);
659 if (rc)
660 return rc;
661
662 for (port_no = 0; port_no < ADMA_PORTS; ++port_no) {
663 struct ata_port *ap = host->ports[port_no];
664 void __iomem *port_base = ADMA_ATA_REGS(mmio_base, port_no);
665 unsigned int offset = port_base - mmio_base;
666
667 adma_ata_setup_port(&ap->ioaddr, port_base);
668
669 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, -1, "mmio");
670 ata_port_pbar_desc(ap, ADMA_MMIO_BAR, offset, "port");
671 }
672
673 /* initialize adapter */
674 adma_host_init(host, board_idx);
675
676 pci_set_master(pdev);
677 return ata_host_activate(host, pdev->irq, adma_intr, IRQF_SHARED,
678 &adma_ata_sht);
679 }
680
681 static int __init adma_ata_init(void)
682 {
683 return pci_register_driver(&adma_ata_pci_driver);
684 }
685
686 static void __exit adma_ata_exit(void)
687 {
688 pci_unregister_driver(&adma_ata_pci_driver);
689 }
690
691 MODULE_AUTHOR("Mark Lord");
692 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
693 MODULE_LICENSE("GPL");
694 MODULE_DEVICE_TABLE(pci, adma_ata_pci_tbl);
695 MODULE_VERSION(DRV_VERSION);
696
697 module_init(adma_ata_init);
698 module_exit(adma_ata_exit);
kernel source for telekom puls (alcatel/mediatek)