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Merge tag 'v3.10.85' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / libahci.c
1 /*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/gfp.h>
37 #include <linux/module.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
45 #include <scsi/scsi_cmnd.h>
46 #include <linux/libata.h>
47 #include "ahci.h"
48 #include "libata.h"
49
50 static int ahci_skip_host_reset;
51 int ahci_ignore_sss;
52 EXPORT_SYMBOL_GPL(ahci_ignore_sss);
53
54 module_param_named(skip_host_reset, ahci_skip_host_reset, int, 0444);
55 MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)");
56
57 module_param_named(ignore_sss, ahci_ignore_sss, int, 0444);
58 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
59
60 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
61 unsigned hints);
62 static ssize_t ahci_led_show(struct ata_port *ap, char *buf);
63 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
64 size_t size);
65 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
66 ssize_t size);
67
68
69
70 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
71 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
72 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
73 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc);
74 static int ahci_port_start(struct ata_port *ap);
75 static void ahci_port_stop(struct ata_port *ap);
76 static void ahci_qc_prep(struct ata_queued_cmd *qc);
77 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc);
78 static void ahci_freeze(struct ata_port *ap);
79 static void ahci_thaw(struct ata_port *ap);
80 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep);
81 static void ahci_enable_fbs(struct ata_port *ap);
82 static void ahci_disable_fbs(struct ata_port *ap);
83 static void ahci_pmp_attach(struct ata_port *ap);
84 static void ahci_pmp_detach(struct ata_port *ap);
85 static int ahci_softreset(struct ata_link *link, unsigned int *class,
86 unsigned long deadline);
87 static int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static void ahci_postreset(struct ata_link *link, unsigned int *class);
92 static void ahci_error_handler(struct ata_port *ap);
93 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
94 static void ahci_dev_config(struct ata_device *dev);
95 #ifdef CONFIG_PM
96 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg);
97 #endif
98 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf);
99 static ssize_t ahci_activity_store(struct ata_device *dev,
100 enum sw_activity val);
101 static void ahci_init_sw_activity(struct ata_link *link);
102
103 static ssize_t ahci_show_host_caps(struct device *dev,
104 struct device_attribute *attr, char *buf);
105 static ssize_t ahci_show_host_cap2(struct device *dev,
106 struct device_attribute *attr, char *buf);
107 static ssize_t ahci_show_host_version(struct device *dev,
108 struct device_attribute *attr, char *buf);
109 static ssize_t ahci_show_port_cmd(struct device *dev,
110 struct device_attribute *attr, char *buf);
111 static ssize_t ahci_read_em_buffer(struct device *dev,
112 struct device_attribute *attr, char *buf);
113 static ssize_t ahci_store_em_buffer(struct device *dev,
114 struct device_attribute *attr,
115 const char *buf, size_t size);
116 static ssize_t ahci_show_em_supported(struct device *dev,
117 struct device_attribute *attr, char *buf);
118
119 static DEVICE_ATTR(ahci_host_caps, S_IRUGO, ahci_show_host_caps, NULL);
120 static DEVICE_ATTR(ahci_host_cap2, S_IRUGO, ahci_show_host_cap2, NULL);
121 static DEVICE_ATTR(ahci_host_version, S_IRUGO, ahci_show_host_version, NULL);
122 static DEVICE_ATTR(ahci_port_cmd, S_IRUGO, ahci_show_port_cmd, NULL);
123 static DEVICE_ATTR(em_buffer, S_IWUSR | S_IRUGO,
124 ahci_read_em_buffer, ahci_store_em_buffer);
125 static DEVICE_ATTR(em_message_supported, S_IRUGO, ahci_show_em_supported, NULL);
126
127 struct device_attribute *ahci_shost_attrs[] = {
128 &dev_attr_link_power_management_policy,
129 &dev_attr_em_message_type,
130 &dev_attr_em_message,
131 &dev_attr_ahci_host_caps,
132 &dev_attr_ahci_host_cap2,
133 &dev_attr_ahci_host_version,
134 &dev_attr_ahci_port_cmd,
135 &dev_attr_em_buffer,
136 &dev_attr_em_message_supported,
137 NULL
138 };
139 EXPORT_SYMBOL_GPL(ahci_shost_attrs);
140
141 struct device_attribute *ahci_sdev_attrs[] = {
142 &dev_attr_sw_activity,
143 &dev_attr_unload_heads,
144 NULL
145 };
146 EXPORT_SYMBOL_GPL(ahci_sdev_attrs);
147
148 struct ata_port_operations ahci_ops = {
149 .inherits = &sata_pmp_port_ops,
150
151 .qc_defer = ahci_pmp_qc_defer,
152 .qc_prep = ahci_qc_prep,
153 .qc_issue = ahci_qc_issue,
154 .qc_fill_rtf = ahci_qc_fill_rtf,
155
156 .freeze = ahci_freeze,
157 .thaw = ahci_thaw,
158 .softreset = ahci_softreset,
159 .hardreset = ahci_hardreset,
160 .postreset = ahci_postreset,
161 .pmp_softreset = ahci_softreset,
162 .error_handler = ahci_error_handler,
163 .post_internal_cmd = ahci_post_internal_cmd,
164 .dev_config = ahci_dev_config,
165
166 .scr_read = ahci_scr_read,
167 .scr_write = ahci_scr_write,
168 .pmp_attach = ahci_pmp_attach,
169 .pmp_detach = ahci_pmp_detach,
170
171 .set_lpm = ahci_set_lpm,
172 .em_show = ahci_led_show,
173 .em_store = ahci_led_store,
174 .sw_activity_show = ahci_activity_show,
175 .sw_activity_store = ahci_activity_store,
176 #ifdef CONFIG_PM
177 .port_suspend = ahci_port_suspend,
178 .port_resume = ahci_port_resume,
179 #endif
180 .port_start = ahci_port_start,
181 .port_stop = ahci_port_stop,
182 };
183 EXPORT_SYMBOL_GPL(ahci_ops);
184
185 struct ata_port_operations ahci_pmp_retry_srst_ops = {
186 .inherits = &ahci_ops,
187 .softreset = ahci_pmp_retry_softreset,
188 };
189 EXPORT_SYMBOL_GPL(ahci_pmp_retry_srst_ops);
190
191 int ahci_em_messages = 1;
192 EXPORT_SYMBOL_GPL(ahci_em_messages);
193 module_param(ahci_em_messages, int, 0444);
194 /* add other LED protocol types when they become supported */
195 MODULE_PARM_DESC(ahci_em_messages,
196 "AHCI Enclosure Management Message control (0 = off, 1 = on)");
197
198 int devslp_idle_timeout = 1000; /* device sleep idle timeout in ms */
199 module_param(devslp_idle_timeout, int, 0644);
200 MODULE_PARM_DESC(devslp_idle_timeout, "device sleep idle timeout");
201
202 static void ahci_enable_ahci(void __iomem *mmio)
203 {
204 int i;
205 u32 tmp;
206
207 /* turn on AHCI_EN */
208 tmp = readl(mmio + HOST_CTL);
209 if (tmp & HOST_AHCI_EN)
210 return;
211
212 /* Some controllers need AHCI_EN to be written multiple times.
213 * Try a few times before giving up.
214 */
215 for (i = 0; i < 5; i++) {
216 tmp |= HOST_AHCI_EN;
217 writel(tmp, mmio + HOST_CTL);
218 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
219 if (tmp & HOST_AHCI_EN)
220 return;
221 msleep(10);
222 }
223
224 WARN_ON(1);
225 }
226
227 static ssize_t ahci_show_host_caps(struct device *dev,
228 struct device_attribute *attr, char *buf)
229 {
230 struct Scsi_Host *shost = class_to_shost(dev);
231 struct ata_port *ap = ata_shost_to_port(shost);
232 struct ahci_host_priv *hpriv = ap->host->private_data;
233
234 return sprintf(buf, "%x\n", hpriv->cap);
235 }
236
237 static ssize_t ahci_show_host_cap2(struct device *dev,
238 struct device_attribute *attr, char *buf)
239 {
240 struct Scsi_Host *shost = class_to_shost(dev);
241 struct ata_port *ap = ata_shost_to_port(shost);
242 struct ahci_host_priv *hpriv = ap->host->private_data;
243
244 return sprintf(buf, "%x\n", hpriv->cap2);
245 }
246
247 static ssize_t ahci_show_host_version(struct device *dev,
248 struct device_attribute *attr, char *buf)
249 {
250 struct Scsi_Host *shost = class_to_shost(dev);
251 struct ata_port *ap = ata_shost_to_port(shost);
252 struct ahci_host_priv *hpriv = ap->host->private_data;
253 void __iomem *mmio = hpriv->mmio;
254
255 return sprintf(buf, "%x\n", readl(mmio + HOST_VERSION));
256 }
257
258 static ssize_t ahci_show_port_cmd(struct device *dev,
259 struct device_attribute *attr, char *buf)
260 {
261 struct Scsi_Host *shost = class_to_shost(dev);
262 struct ata_port *ap = ata_shost_to_port(shost);
263 void __iomem *port_mmio = ahci_port_base(ap);
264
265 return sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD));
266 }
267
268 static ssize_t ahci_read_em_buffer(struct device *dev,
269 struct device_attribute *attr, char *buf)
270 {
271 struct Scsi_Host *shost = class_to_shost(dev);
272 struct ata_port *ap = ata_shost_to_port(shost);
273 struct ahci_host_priv *hpriv = ap->host->private_data;
274 void __iomem *mmio = hpriv->mmio;
275 void __iomem *em_mmio = mmio + hpriv->em_loc;
276 u32 em_ctl, msg;
277 unsigned long flags;
278 size_t count;
279 int i;
280
281 spin_lock_irqsave(ap->lock, flags);
282
283 em_ctl = readl(mmio + HOST_EM_CTL);
284 if (!(ap->flags & ATA_FLAG_EM) || em_ctl & EM_CTL_XMT ||
285 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO)) {
286 spin_unlock_irqrestore(ap->lock, flags);
287 return -EINVAL;
288 }
289
290 if (!(em_ctl & EM_CTL_MR)) {
291 spin_unlock_irqrestore(ap->lock, flags);
292 return -EAGAIN;
293 }
294
295 if (!(em_ctl & EM_CTL_SMB))
296 em_mmio += hpriv->em_buf_sz;
297
298 count = hpriv->em_buf_sz;
299
300 /* the count should not be larger than PAGE_SIZE */
301 if (count > PAGE_SIZE) {
302 if (printk_ratelimit())
303 ata_port_warn(ap,
304 "EM read buffer size too large: "
305 "buffer size %u, page size %lu\n",
306 hpriv->em_buf_sz, PAGE_SIZE);
307 count = PAGE_SIZE;
308 }
309
310 for (i = 0; i < count; i += 4) {
311 msg = readl(em_mmio + i);
312 buf[i] = msg & 0xff;
313 buf[i + 1] = (msg >> 8) & 0xff;
314 buf[i + 2] = (msg >> 16) & 0xff;
315 buf[i + 3] = (msg >> 24) & 0xff;
316 }
317
318 spin_unlock_irqrestore(ap->lock, flags);
319
320 return i;
321 }
322
323 static ssize_t ahci_store_em_buffer(struct device *dev,
324 struct device_attribute *attr,
325 const char *buf, size_t size)
326 {
327 struct Scsi_Host *shost = class_to_shost(dev);
328 struct ata_port *ap = ata_shost_to_port(shost);
329 struct ahci_host_priv *hpriv = ap->host->private_data;
330 void __iomem *mmio = hpriv->mmio;
331 void __iomem *em_mmio = mmio + hpriv->em_loc;
332 const unsigned char *msg_buf = buf;
333 u32 em_ctl, msg;
334 unsigned long flags;
335 int i;
336
337 /* check size validity */
338 if (!(ap->flags & ATA_FLAG_EM) ||
339 !(hpriv->em_msg_type & EM_MSG_TYPE_SGPIO) ||
340 size % 4 || size > hpriv->em_buf_sz)
341 return -EINVAL;
342
343 spin_lock_irqsave(ap->lock, flags);
344
345 em_ctl = readl(mmio + HOST_EM_CTL);
346 if (em_ctl & EM_CTL_TM) {
347 spin_unlock_irqrestore(ap->lock, flags);
348 return -EBUSY;
349 }
350
351 for (i = 0; i < size; i += 4) {
352 msg = msg_buf[i] | msg_buf[i + 1] << 8 |
353 msg_buf[i + 2] << 16 | msg_buf[i + 3] << 24;
354 writel(msg, em_mmio + i);
355 }
356
357 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
358
359 spin_unlock_irqrestore(ap->lock, flags);
360
361 return size;
362 }
363
364 static ssize_t ahci_show_em_supported(struct device *dev,
365 struct device_attribute *attr, char *buf)
366 {
367 struct Scsi_Host *shost = class_to_shost(dev);
368 struct ata_port *ap = ata_shost_to_port(shost);
369 struct ahci_host_priv *hpriv = ap->host->private_data;
370 void __iomem *mmio = hpriv->mmio;
371 u32 em_ctl;
372
373 em_ctl = readl(mmio + HOST_EM_CTL);
374
375 return sprintf(buf, "%s%s%s%s\n",
376 em_ctl & EM_CTL_LED ? "led " : "",
377 em_ctl & EM_CTL_SAFTE ? "saf-te " : "",
378 em_ctl & EM_CTL_SES ? "ses-2 " : "",
379 em_ctl & EM_CTL_SGPIO ? "sgpio " : "");
380 }
381
382 /**
383 * ahci_save_initial_config - Save and fixup initial config values
384 * @dev: target AHCI device
385 * @hpriv: host private area to store config values
386 * @force_port_map: force port map to a specified value
387 * @mask_port_map: mask out particular bits from port map
388 *
389 * Some registers containing configuration info might be setup by
390 * BIOS and might be cleared on reset. This function saves the
391 * initial values of those registers into @hpriv such that they
392 * can be restored after controller reset.
393 *
394 * If inconsistent, config values are fixed up by this function.
395 *
396 * LOCKING:
397 * None.
398 */
399 void ahci_save_initial_config(struct device *dev,
400 struct ahci_host_priv *hpriv,
401 unsigned int force_port_map,
402 unsigned int mask_port_map)
403 {
404 void __iomem *mmio = hpriv->mmio;
405 u32 cap, cap2, vers, port_map;
406 int i;
407
408 /* make sure AHCI mode is enabled before accessing CAP */
409 ahci_enable_ahci(mmio);
410
411 /* Values prefixed with saved_ are written back to host after
412 * reset. Values without are used for driver operation.
413 */
414 hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
415 hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
416
417 /* CAP2 register is only defined for AHCI 1.2 and later */
418 vers = readl(mmio + HOST_VERSION);
419 if ((vers >> 16) > 1 ||
420 ((vers >> 16) == 1 && (vers & 0xFFFF) >= 0x200))
421 hpriv->saved_cap2 = cap2 = readl(mmio + HOST_CAP2);
422 else
423 hpriv->saved_cap2 = cap2 = 0;
424
425 /* some chips have errata preventing 64bit use */
426 if ((cap & HOST_CAP_64) && (hpriv->flags & AHCI_HFLAG_32BIT_ONLY)) {
427 dev_info(dev, "controller can't do 64bit DMA, forcing 32bit\n");
428 cap &= ~HOST_CAP_64;
429 }
430
431 if ((cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_NO_NCQ)) {
432 dev_info(dev, "controller can't do NCQ, turning off CAP_NCQ\n");
433 cap &= ~HOST_CAP_NCQ;
434 }
435
436 if (!(cap & HOST_CAP_NCQ) && (hpriv->flags & AHCI_HFLAG_YES_NCQ)) {
437 dev_info(dev, "controller can do NCQ, turning on CAP_NCQ\n");
438 cap |= HOST_CAP_NCQ;
439 }
440
441 if ((cap & HOST_CAP_PMP) && (hpriv->flags & AHCI_HFLAG_NO_PMP)) {
442 dev_info(dev, "controller can't do PMP, turning off CAP_PMP\n");
443 cap &= ~HOST_CAP_PMP;
444 }
445
446 if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
447 dev_info(dev,
448 "controller can't do SNTF, turning off CAP_SNTF\n");
449 cap &= ~HOST_CAP_SNTF;
450 }
451
452 if (!(cap & HOST_CAP_FBS) && (hpriv->flags & AHCI_HFLAG_YES_FBS)) {
453 dev_info(dev, "controller can do FBS, turning on CAP_FBS\n");
454 cap |= HOST_CAP_FBS;
455 }
456
457 if (force_port_map && port_map != force_port_map) {
458 dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
459 port_map, force_port_map);
460 port_map = force_port_map;
461 }
462
463 if (mask_port_map) {
464 dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
465 port_map,
466 port_map & mask_port_map);
467 port_map &= mask_port_map;
468 }
469
470 /* cross check port_map and cap.n_ports */
471 if (port_map) {
472 int map_ports = 0;
473
474 for (i = 0; i < AHCI_MAX_PORTS; i++)
475 if (port_map & (1 << i))
476 map_ports++;
477
478 /* If PI has more ports than n_ports, whine, clear
479 * port_map and let it be generated from n_ports.
480 */
481 if (map_ports > ahci_nr_ports(cap)) {
482 dev_warn(dev,
483 "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
484 port_map, ahci_nr_ports(cap));
485 port_map = 0;
486 }
487 }
488
489 /* fabricate port_map from cap.nr_ports */
490 if (!port_map) {
491 port_map = (1 << ahci_nr_ports(cap)) - 1;
492 dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
493
494 /* write the fixed up value to the PI register */
495 hpriv->saved_port_map = port_map;
496 }
497
498 /* record values to use during operation */
499 hpriv->cap = cap;
500 hpriv->cap2 = cap2;
501 hpriv->port_map = port_map;
502 }
503 EXPORT_SYMBOL_GPL(ahci_save_initial_config);
504
505 /**
506 * ahci_restore_initial_config - Restore initial config
507 * @host: target ATA host
508 *
509 * Restore initial config stored by ahci_save_initial_config().
510 *
511 * LOCKING:
512 * None.
513 */
514 static void ahci_restore_initial_config(struct ata_host *host)
515 {
516 struct ahci_host_priv *hpriv = host->private_data;
517 void __iomem *mmio = hpriv->mmio;
518
519 writel(hpriv->saved_cap, mmio + HOST_CAP);
520 if (hpriv->saved_cap2)
521 writel(hpriv->saved_cap2, mmio + HOST_CAP2);
522 writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
523 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
524 }
525
526 static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
527 {
528 static const int offset[] = {
529 [SCR_STATUS] = PORT_SCR_STAT,
530 [SCR_CONTROL] = PORT_SCR_CTL,
531 [SCR_ERROR] = PORT_SCR_ERR,
532 [SCR_ACTIVE] = PORT_SCR_ACT,
533 [SCR_NOTIFICATION] = PORT_SCR_NTF,
534 };
535 struct ahci_host_priv *hpriv = ap->host->private_data;
536
537 if (sc_reg < ARRAY_SIZE(offset) &&
538 (sc_reg != SCR_NOTIFICATION || (hpriv->cap & HOST_CAP_SNTF)))
539 return offset[sc_reg];
540 return 0;
541 }
542
543 static int ahci_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
544 {
545 void __iomem *port_mmio = ahci_port_base(link->ap);
546 int offset = ahci_scr_offset(link->ap, sc_reg);
547
548 if (offset) {
549 *val = readl(port_mmio + offset);
550 return 0;
551 }
552 return -EINVAL;
553 }
554
555 static int ahci_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
556 {
557 void __iomem *port_mmio = ahci_port_base(link->ap);
558 int offset = ahci_scr_offset(link->ap, sc_reg);
559
560 if (offset) {
561 writel(val, port_mmio + offset);
562 return 0;
563 }
564 return -EINVAL;
565 }
566
567 void ahci_start_engine(struct ata_port *ap)
568 {
569 void __iomem *port_mmio = ahci_port_base(ap);
570 u32 tmp;
571
572 /* start DMA */
573 tmp = readl(port_mmio + PORT_CMD);
574 tmp |= PORT_CMD_START;
575 writel(tmp, port_mmio + PORT_CMD);
576 readl(port_mmio + PORT_CMD); /* flush */
577 }
578 EXPORT_SYMBOL_GPL(ahci_start_engine);
579
580 int ahci_stop_engine(struct ata_port *ap)
581 {
582 void __iomem *port_mmio = ahci_port_base(ap);
583 u32 tmp;
584
585 tmp = readl(port_mmio + PORT_CMD);
586
587 /* check if the HBA is idle */
588 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
589 return 0;
590
591 /* setting HBA to idle */
592 tmp &= ~PORT_CMD_START;
593 writel(tmp, port_mmio + PORT_CMD);
594
595 /* wait for engine to stop. This could be as long as 500 msec */
596 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
597 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
598 if (tmp & PORT_CMD_LIST_ON)
599 return -EIO;
600
601 return 0;
602 }
603 EXPORT_SYMBOL_GPL(ahci_stop_engine);
604
605 static void ahci_start_fis_rx(struct ata_port *ap)
606 {
607 void __iomem *port_mmio = ahci_port_base(ap);
608 struct ahci_host_priv *hpriv = ap->host->private_data;
609 struct ahci_port_priv *pp = ap->private_data;
610 u32 tmp;
611
612 /* set FIS registers */
613 if (hpriv->cap & HOST_CAP_64)
614 writel((pp->cmd_slot_dma >> 16) >> 16,
615 port_mmio + PORT_LST_ADDR_HI);
616 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
617
618 if (hpriv->cap & HOST_CAP_64)
619 writel((pp->rx_fis_dma >> 16) >> 16,
620 port_mmio + PORT_FIS_ADDR_HI);
621 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
622
623 /* enable FIS reception */
624 tmp = readl(port_mmio + PORT_CMD);
625 tmp |= PORT_CMD_FIS_RX;
626 writel(tmp, port_mmio + PORT_CMD);
627
628 /* flush */
629 readl(port_mmio + PORT_CMD);
630 }
631
632 static int ahci_stop_fis_rx(struct ata_port *ap)
633 {
634 void __iomem *port_mmio = ahci_port_base(ap);
635 u32 tmp;
636
637 /* disable FIS reception */
638 tmp = readl(port_mmio + PORT_CMD);
639 tmp &= ~PORT_CMD_FIS_RX;
640 writel(tmp, port_mmio + PORT_CMD);
641
642 /* wait for completion, spec says 500ms, give it 1000 */
643 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
644 PORT_CMD_FIS_ON, 10, 1000);
645 if (tmp & PORT_CMD_FIS_ON)
646 return -EBUSY;
647
648 return 0;
649 }
650
651 static void ahci_power_up(struct ata_port *ap)
652 {
653 struct ahci_host_priv *hpriv = ap->host->private_data;
654 void __iomem *port_mmio = ahci_port_base(ap);
655 u32 cmd;
656
657 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
658
659 /* spin up device */
660 if (hpriv->cap & HOST_CAP_SSS) {
661 cmd |= PORT_CMD_SPIN_UP;
662 writel(cmd, port_mmio + PORT_CMD);
663 }
664
665 /* wake up link */
666 writel(cmd | PORT_CMD_ICC_ACTIVE, port_mmio + PORT_CMD);
667 }
668
669 static int ahci_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
670 unsigned int hints)
671 {
672 struct ata_port *ap = link->ap;
673 struct ahci_host_priv *hpriv = ap->host->private_data;
674 struct ahci_port_priv *pp = ap->private_data;
675 void __iomem *port_mmio = ahci_port_base(ap);
676
677 if (policy != ATA_LPM_MAX_POWER) {
678 /*
679 * Disable interrupts on Phy Ready. This keeps us from
680 * getting woken up due to spurious phy ready
681 * interrupts.
682 */
683 pp->intr_mask &= ~PORT_IRQ_PHYRDY;
684 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
685
686 sata_link_scr_lpm(link, policy, false);
687 }
688
689 if (hpriv->cap & HOST_CAP_ALPM) {
690 u32 cmd = readl(port_mmio + PORT_CMD);
691
692 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
693 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
694 cmd |= PORT_CMD_ICC_ACTIVE;
695
696 writel(cmd, port_mmio + PORT_CMD);
697 readl(port_mmio + PORT_CMD);
698
699 /* wait 10ms to be sure we've come out of LPM state */
700 ata_msleep(ap, 10);
701 } else {
702 cmd |= PORT_CMD_ALPE;
703 if (policy == ATA_LPM_MIN_POWER)
704 cmd |= PORT_CMD_ASP;
705
706 /* write out new cmd value */
707 writel(cmd, port_mmio + PORT_CMD);
708 }
709 }
710
711 /* set aggressive device sleep */
712 if ((hpriv->cap2 & HOST_CAP2_SDS) &&
713 (hpriv->cap2 & HOST_CAP2_SADM) &&
714 (link->device->flags & ATA_DFLAG_DEVSLP)) {
715 if (policy == ATA_LPM_MIN_POWER)
716 ahci_set_aggressive_devslp(ap, true);
717 else
718 ahci_set_aggressive_devslp(ap, false);
719 }
720
721 if (policy == ATA_LPM_MAX_POWER) {
722 sata_link_scr_lpm(link, policy, false);
723
724 /* turn PHYRDY IRQ back on */
725 pp->intr_mask |= PORT_IRQ_PHYRDY;
726 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
727 }
728
729 return 0;
730 }
731
732 #ifdef CONFIG_PM
733 static void ahci_power_down(struct ata_port *ap)
734 {
735 struct ahci_host_priv *hpriv = ap->host->private_data;
736 void __iomem *port_mmio = ahci_port_base(ap);
737 u32 cmd, scontrol;
738
739 if (!(hpriv->cap & HOST_CAP_SSS))
740 return;
741
742 /* put device into listen mode, first set PxSCTL.DET to 0 */
743 scontrol = readl(port_mmio + PORT_SCR_CTL);
744 scontrol &= ~0xf;
745 writel(scontrol, port_mmio + PORT_SCR_CTL);
746
747 /* then set PxCMD.SUD to 0 */
748 cmd = readl(port_mmio + PORT_CMD) & ~PORT_CMD_ICC_MASK;
749 cmd &= ~PORT_CMD_SPIN_UP;
750 writel(cmd, port_mmio + PORT_CMD);
751 }
752 #endif
753
754 static void ahci_start_port(struct ata_port *ap)
755 {
756 struct ahci_host_priv *hpriv = ap->host->private_data;
757 struct ahci_port_priv *pp = ap->private_data;
758 struct ata_link *link;
759 struct ahci_em_priv *emp;
760 ssize_t rc;
761 int i;
762
763 /* enable FIS reception */
764 ahci_start_fis_rx(ap);
765
766 /* enable DMA */
767 if (!(hpriv->flags & AHCI_HFLAG_DELAY_ENGINE))
768 ahci_start_engine(ap);
769
770 /* turn on LEDs */
771 if (ap->flags & ATA_FLAG_EM) {
772 ata_for_each_link(link, ap, EDGE) {
773 emp = &pp->em_priv[link->pmp];
774
775 /* EM Transmit bit maybe busy during init */
776 for (i = 0; i < EM_MAX_RETRY; i++) {
777 rc = ahci_transmit_led_message(ap,
778 emp->led_state,
779 4);
780 if (rc == -EBUSY)
781 ata_msleep(ap, 1);
782 else
783 break;
784 }
785 }
786 }
787
788 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
789 ata_for_each_link(link, ap, EDGE)
790 ahci_init_sw_activity(link);
791
792 }
793
794 static int ahci_deinit_port(struct ata_port *ap, const char **emsg)
795 {
796 int rc;
797
798 /* disable DMA */
799 rc = ahci_stop_engine(ap);
800 if (rc) {
801 *emsg = "failed to stop engine";
802 return rc;
803 }
804
805 /* disable FIS reception */
806 rc = ahci_stop_fis_rx(ap);
807 if (rc) {
808 *emsg = "failed stop FIS RX";
809 return rc;
810 }
811
812 return 0;
813 }
814
815 int ahci_reset_controller(struct ata_host *host)
816 {
817 struct ahci_host_priv *hpriv = host->private_data;
818 void __iomem *mmio = hpriv->mmio;
819 u32 tmp;
820
821 /* we must be in AHCI mode, before using anything
822 * AHCI-specific, such as HOST_RESET.
823 */
824 ahci_enable_ahci(mmio);
825
826 /* global controller reset */
827 if (!ahci_skip_host_reset) {
828 tmp = readl(mmio + HOST_CTL);
829 if ((tmp & HOST_RESET) == 0) {
830 writel(tmp | HOST_RESET, mmio + HOST_CTL);
831 readl(mmio + HOST_CTL); /* flush */
832 }
833
834 /*
835 * to perform host reset, OS should set HOST_RESET
836 * and poll until this bit is read to be "0".
837 * reset must complete within 1 second, or
838 * the hardware should be considered fried.
839 */
840 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
841 HOST_RESET, 10, 1000);
842
843 if (tmp & HOST_RESET) {
844 dev_err(host->dev, "controller reset failed (0x%x)\n",
845 tmp);
846 return -EIO;
847 }
848
849 /* turn on AHCI mode */
850 ahci_enable_ahci(mmio);
851
852 /* Some registers might be cleared on reset. Restore
853 * initial values.
854 */
855 ahci_restore_initial_config(host);
856 } else
857 dev_info(host->dev, "skipping global host reset\n");
858
859 return 0;
860 }
861 EXPORT_SYMBOL_GPL(ahci_reset_controller);
862
863 static void ahci_sw_activity(struct ata_link *link)
864 {
865 struct ata_port *ap = link->ap;
866 struct ahci_port_priv *pp = ap->private_data;
867 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
868
869 if (!(link->flags & ATA_LFLAG_SW_ACTIVITY))
870 return;
871
872 emp->activity++;
873 if (!timer_pending(&emp->timer))
874 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(10));
875 }
876
877 static void ahci_sw_activity_blink(unsigned long arg)
878 {
879 struct ata_link *link = (struct ata_link *)arg;
880 struct ata_port *ap = link->ap;
881 struct ahci_port_priv *pp = ap->private_data;
882 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
883 unsigned long led_message = emp->led_state;
884 u32 activity_led_state;
885 unsigned long flags;
886
887 led_message &= EM_MSG_LED_VALUE;
888 led_message |= ap->port_no | (link->pmp << 8);
889
890 /* check to see if we've had activity. If so,
891 * toggle state of LED and reset timer. If not,
892 * turn LED to desired idle state.
893 */
894 spin_lock_irqsave(ap->lock, flags);
895 if (emp->saved_activity != emp->activity) {
896 emp->saved_activity = emp->activity;
897 /* get the current LED state */
898 activity_led_state = led_message & EM_MSG_LED_VALUE_ON;
899
900 if (activity_led_state)
901 activity_led_state = 0;
902 else
903 activity_led_state = 1;
904
905 /* clear old state */
906 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
907
908 /* toggle state */
909 led_message |= (activity_led_state << 16);
910 mod_timer(&emp->timer, jiffies + msecs_to_jiffies(100));
911 } else {
912 /* switch to idle */
913 led_message &= ~EM_MSG_LED_VALUE_ACTIVITY;
914 if (emp->blink_policy == BLINK_OFF)
915 led_message |= (1 << 16);
916 }
917 spin_unlock_irqrestore(ap->lock, flags);
918 ahci_transmit_led_message(ap, led_message, 4);
919 }
920
921 static void ahci_init_sw_activity(struct ata_link *link)
922 {
923 struct ata_port *ap = link->ap;
924 struct ahci_port_priv *pp = ap->private_data;
925 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
926
927 /* init activity stats, setup timer */
928 emp->saved_activity = emp->activity = 0;
929 setup_timer(&emp->timer, ahci_sw_activity_blink, (unsigned long)link);
930
931 /* check our blink policy and set flag for link if it's enabled */
932 if (emp->blink_policy)
933 link->flags |= ATA_LFLAG_SW_ACTIVITY;
934 }
935
936 int ahci_reset_em(struct ata_host *host)
937 {
938 struct ahci_host_priv *hpriv = host->private_data;
939 void __iomem *mmio = hpriv->mmio;
940 u32 em_ctl;
941
942 em_ctl = readl(mmio + HOST_EM_CTL);
943 if ((em_ctl & EM_CTL_TM) || (em_ctl & EM_CTL_RST))
944 return -EINVAL;
945
946 writel(em_ctl | EM_CTL_RST, mmio + HOST_EM_CTL);
947 return 0;
948 }
949 EXPORT_SYMBOL_GPL(ahci_reset_em);
950
951 static ssize_t ahci_transmit_led_message(struct ata_port *ap, u32 state,
952 ssize_t size)
953 {
954 struct ahci_host_priv *hpriv = ap->host->private_data;
955 struct ahci_port_priv *pp = ap->private_data;
956 void __iomem *mmio = hpriv->mmio;
957 u32 em_ctl;
958 u32 message[] = {0, 0};
959 unsigned long flags;
960 int pmp;
961 struct ahci_em_priv *emp;
962
963 /* get the slot number from the message */
964 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
965 if (pmp < EM_MAX_SLOTS)
966 emp = &pp->em_priv[pmp];
967 else
968 return -EINVAL;
969
970 spin_lock_irqsave(ap->lock, flags);
971
972 /*
973 * if we are still busy transmitting a previous message,
974 * do not allow
975 */
976 em_ctl = readl(mmio + HOST_EM_CTL);
977 if (em_ctl & EM_CTL_TM) {
978 spin_unlock_irqrestore(ap->lock, flags);
979 return -EBUSY;
980 }
981
982 if (hpriv->em_msg_type & EM_MSG_TYPE_LED) {
983 /*
984 * create message header - this is all zero except for
985 * the message size, which is 4 bytes.
986 */
987 message[0] |= (4 << 8);
988
989 /* ignore 0:4 of byte zero, fill in port info yourself */
990 message[1] = ((state & ~EM_MSG_LED_HBA_PORT) | ap->port_no);
991
992 /* write message to EM_LOC */
993 writel(message[0], mmio + hpriv->em_loc);
994 writel(message[1], mmio + hpriv->em_loc+4);
995
996 /*
997 * tell hardware to transmit the message
998 */
999 writel(em_ctl | EM_CTL_TM, mmio + HOST_EM_CTL);
1000 }
1001
1002 /* save off new led state for port/slot */
1003 emp->led_state = state;
1004
1005 spin_unlock_irqrestore(ap->lock, flags);
1006 return size;
1007 }
1008
1009 static ssize_t ahci_led_show(struct ata_port *ap, char *buf)
1010 {
1011 struct ahci_port_priv *pp = ap->private_data;
1012 struct ata_link *link;
1013 struct ahci_em_priv *emp;
1014 int rc = 0;
1015
1016 ata_for_each_link(link, ap, EDGE) {
1017 emp = &pp->em_priv[link->pmp];
1018 rc += sprintf(buf, "%lx\n", emp->led_state);
1019 }
1020 return rc;
1021 }
1022
1023 static ssize_t ahci_led_store(struct ata_port *ap, const char *buf,
1024 size_t size)
1025 {
1026 int state;
1027 int pmp;
1028 struct ahci_port_priv *pp = ap->private_data;
1029 struct ahci_em_priv *emp;
1030
1031 state = simple_strtoul(buf, NULL, 0);
1032
1033 /* get the slot number from the message */
1034 pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
1035 if (pmp < EM_MAX_SLOTS)
1036 emp = &pp->em_priv[pmp];
1037 else
1038 return -EINVAL;
1039
1040 /* mask off the activity bits if we are in sw_activity
1041 * mode, user should turn off sw_activity before setting
1042 * activity led through em_message
1043 */
1044 if (emp->blink_policy)
1045 state &= ~EM_MSG_LED_VALUE_ACTIVITY;
1046
1047 return ahci_transmit_led_message(ap, state, size);
1048 }
1049
1050 static ssize_t ahci_activity_store(struct ata_device *dev, enum sw_activity val)
1051 {
1052 struct ata_link *link = dev->link;
1053 struct ata_port *ap = link->ap;
1054 struct ahci_port_priv *pp = ap->private_data;
1055 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1056 u32 port_led_state = emp->led_state;
1057
1058 /* save the desired Activity LED behavior */
1059 if (val == OFF) {
1060 /* clear LFLAG */
1061 link->flags &= ~(ATA_LFLAG_SW_ACTIVITY);
1062
1063 /* set the LED to OFF */
1064 port_led_state &= EM_MSG_LED_VALUE_OFF;
1065 port_led_state |= (ap->port_no | (link->pmp << 8));
1066 ahci_transmit_led_message(ap, port_led_state, 4);
1067 } else {
1068 link->flags |= ATA_LFLAG_SW_ACTIVITY;
1069 if (val == BLINK_OFF) {
1070 /* set LED to ON for idle */
1071 port_led_state &= EM_MSG_LED_VALUE_OFF;
1072 port_led_state |= (ap->port_no | (link->pmp << 8));
1073 port_led_state |= EM_MSG_LED_VALUE_ON; /* check this */
1074 ahci_transmit_led_message(ap, port_led_state, 4);
1075 }
1076 }
1077 emp->blink_policy = val;
1078 return 0;
1079 }
1080
1081 static ssize_t ahci_activity_show(struct ata_device *dev, char *buf)
1082 {
1083 struct ata_link *link = dev->link;
1084 struct ata_port *ap = link->ap;
1085 struct ahci_port_priv *pp = ap->private_data;
1086 struct ahci_em_priv *emp = &pp->em_priv[link->pmp];
1087
1088 /* display the saved value of activity behavior for this
1089 * disk.
1090 */
1091 return sprintf(buf, "%d\n", emp->blink_policy);
1092 }
1093
1094 static void ahci_port_init(struct device *dev, struct ata_port *ap,
1095 int port_no, void __iomem *mmio,
1096 void __iomem *port_mmio)
1097 {
1098 const char *emsg = NULL;
1099 int rc;
1100 u32 tmp;
1101
1102 /* make sure port is not active */
1103 rc = ahci_deinit_port(ap, &emsg);
1104 if (rc)
1105 dev_warn(dev, "%s (%d)\n", emsg, rc);
1106
1107 /* clear SError */
1108 tmp = readl(port_mmio + PORT_SCR_ERR);
1109 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1110 writel(tmp, port_mmio + PORT_SCR_ERR);
1111
1112 /* clear port IRQ */
1113 tmp = readl(port_mmio + PORT_IRQ_STAT);
1114 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1115 if (tmp)
1116 writel(tmp, port_mmio + PORT_IRQ_STAT);
1117
1118 writel(1 << port_no, mmio + HOST_IRQ_STAT);
1119 }
1120
1121 void ahci_init_controller(struct ata_host *host)
1122 {
1123 struct ahci_host_priv *hpriv = host->private_data;
1124 void __iomem *mmio = hpriv->mmio;
1125 int i;
1126 void __iomem *port_mmio;
1127 u32 tmp;
1128
1129 for (i = 0; i < host->n_ports; i++) {
1130 struct ata_port *ap = host->ports[i];
1131
1132 port_mmio = ahci_port_base(ap);
1133 if (ata_port_is_dummy(ap))
1134 continue;
1135
1136 ahci_port_init(host->dev, ap, i, mmio, port_mmio);
1137 }
1138
1139 tmp = readl(mmio + HOST_CTL);
1140 VPRINTK("HOST_CTL 0x%x\n", tmp);
1141 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1142 tmp = readl(mmio + HOST_CTL);
1143 VPRINTK("HOST_CTL 0x%x\n", tmp);
1144 }
1145 EXPORT_SYMBOL_GPL(ahci_init_controller);
1146
1147 static void ahci_dev_config(struct ata_device *dev)
1148 {
1149 struct ahci_host_priv *hpriv = dev->link->ap->host->private_data;
1150
1151 if (hpriv->flags & AHCI_HFLAG_SECT255) {
1152 dev->max_sectors = 255;
1153 ata_dev_info(dev,
1154 "SB600 AHCI: limiting to 255 sectors per cmd\n");
1155 }
1156 }
1157
1158 unsigned int ahci_dev_classify(struct ata_port *ap)
1159 {
1160 void __iomem *port_mmio = ahci_port_base(ap);
1161 struct ata_taskfile tf;
1162 u32 tmp;
1163
1164 tmp = readl(port_mmio + PORT_SIG);
1165 tf.lbah = (tmp >> 24) & 0xff;
1166 tf.lbam = (tmp >> 16) & 0xff;
1167 tf.lbal = (tmp >> 8) & 0xff;
1168 tf.nsect = (tmp) & 0xff;
1169
1170 return ata_dev_classify(&tf);
1171 }
1172 EXPORT_SYMBOL_GPL(ahci_dev_classify);
1173
1174 void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
1175 u32 opts)
1176 {
1177 dma_addr_t cmd_tbl_dma;
1178
1179 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
1180
1181 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
1182 pp->cmd_slot[tag].status = 0;
1183 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
1184 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
1185 }
1186 EXPORT_SYMBOL_GPL(ahci_fill_cmd_slot);
1187
1188 int ahci_kick_engine(struct ata_port *ap)
1189 {
1190 void __iomem *port_mmio = ahci_port_base(ap);
1191 struct ahci_host_priv *hpriv = ap->host->private_data;
1192 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1193 u32 tmp;
1194 int busy, rc;
1195
1196 /* stop engine */
1197 rc = ahci_stop_engine(ap);
1198 if (rc)
1199 goto out_restart;
1200
1201 /* need to do CLO?
1202 * always do CLO if PMP is attached (AHCI-1.3 9.2)
1203 */
1204 busy = status & (ATA_BUSY | ATA_DRQ);
1205 if (!busy && !sata_pmp_attached(ap)) {
1206 rc = 0;
1207 goto out_restart;
1208 }
1209
1210 if (!(hpriv->cap & HOST_CAP_CLO)) {
1211 rc = -EOPNOTSUPP;
1212 goto out_restart;
1213 }
1214
1215 /* perform CLO */
1216 tmp = readl(port_mmio + PORT_CMD);
1217 tmp |= PORT_CMD_CLO;
1218 writel(tmp, port_mmio + PORT_CMD);
1219
1220 rc = 0;
1221 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1222 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1223 if (tmp & PORT_CMD_CLO)
1224 rc = -EIO;
1225
1226 /* restart engine */
1227 out_restart:
1228 ahci_start_engine(ap);
1229 return rc;
1230 }
1231 EXPORT_SYMBOL_GPL(ahci_kick_engine);
1232
1233 static int ahci_exec_polled_cmd(struct ata_port *ap, int pmp,
1234 struct ata_taskfile *tf, int is_cmd, u16 flags,
1235 unsigned long timeout_msec)
1236 {
1237 const u32 cmd_fis_len = 5; /* five dwords */
1238 struct ahci_port_priv *pp = ap->private_data;
1239 void __iomem *port_mmio = ahci_port_base(ap);
1240 u8 *fis = pp->cmd_tbl;
1241 u32 tmp;
1242
1243 /* prep the command */
1244 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1245 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1246
1247 /* issue & wait */
1248 writel(1, port_mmio + PORT_CMD_ISSUE);
1249
1250 if (timeout_msec) {
1251 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1252 0x1, 0x1, 1, timeout_msec);
1253 if (tmp & 0x1) {
1254 ahci_kick_engine(ap);
1255 return -EBUSY;
1256 }
1257 } else
1258 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1259
1260 return 0;
1261 }
1262
1263 int ahci_do_softreset(struct ata_link *link, unsigned int *class,
1264 int pmp, unsigned long deadline,
1265 int (*check_ready)(struct ata_link *link))
1266 {
1267 struct ata_port *ap = link->ap;
1268 struct ahci_host_priv *hpriv = ap->host->private_data;
1269 struct ahci_port_priv *pp = ap->private_data;
1270 const char *reason = NULL;
1271 unsigned long now, msecs;
1272 struct ata_taskfile tf;
1273 bool fbs_disabled = false;
1274 int rc;
1275
1276 DPRINTK("ENTER\n");
1277
1278 /* prepare for SRST (AHCI-1.1 10.4.1) */
1279 rc = ahci_kick_engine(ap);
1280 if (rc && rc != -EOPNOTSUPP)
1281 ata_link_warn(link, "failed to reset engine (errno=%d)\n", rc);
1282
1283 /*
1284 * According to AHCI-1.2 9.3.9: if FBS is enable, software shall
1285 * clear PxFBS.EN to '0' prior to issuing software reset to devices
1286 * that is attached to port multiplier.
1287 */
1288 if (!ata_is_host_link(link) && pp->fbs_enabled) {
1289 ahci_disable_fbs(ap);
1290 fbs_disabled = true;
1291 }
1292
1293 ata_tf_init(link->device, &tf);
1294
1295 /* issue the first D2H Register FIS */
1296 msecs = 0;
1297 now = jiffies;
1298 if (time_after(deadline, now))
1299 msecs = jiffies_to_msecs(deadline - now);
1300
1301 tf.ctl |= ATA_SRST;
1302 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1303 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1304 rc = -EIO;
1305 reason = "1st FIS failed";
1306 goto fail;
1307 }
1308
1309 /* spec says at least 5us, but be generous and sleep for 1ms */
1310 ata_msleep(ap, 1);
1311
1312 /* issue the second D2H Register FIS */
1313 tf.ctl &= ~ATA_SRST;
1314 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1315
1316 /* wait for link to become ready */
1317 rc = ata_wait_after_reset(link, deadline, check_ready);
1318 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {
1319 /*
1320 * Workaround for cases where link online status can't
1321 * be trusted. Treat device readiness timeout as link
1322 * offline.
1323 */
1324 ata_link_info(link, "device not ready, treating as offline\n");
1325 *class = ATA_DEV_NONE;
1326 } else if (rc) {
1327 /* link occupied, -ENODEV too is an error */
1328 reason = "device not ready";
1329 goto fail;
1330 } else
1331 *class = ahci_dev_classify(ap);
1332
1333 /* re-enable FBS if disabled before */
1334 if (fbs_disabled)
1335 ahci_enable_fbs(ap);
1336
1337 DPRINTK("EXIT, class=%u\n", *class);
1338 return 0;
1339
1340 fail:
1341 ata_link_err(link, "softreset failed (%s)\n", reason);
1342 return rc;
1343 }
1344
1345 int ahci_check_ready(struct ata_link *link)
1346 {
1347 void __iomem *port_mmio = ahci_port_base(link->ap);
1348 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1349
1350 return ata_check_ready(status);
1351 }
1352 EXPORT_SYMBOL_GPL(ahci_check_ready);
1353
1354 static int ahci_softreset(struct ata_link *link, unsigned int *class,
1355 unsigned long deadline)
1356 {
1357 int pmp = sata_srst_pmp(link);
1358
1359 DPRINTK("ENTER\n");
1360
1361 return ahci_do_softreset(link, class, pmp, deadline, ahci_check_ready);
1362 }
1363 EXPORT_SYMBOL_GPL(ahci_do_softreset);
1364
1365 static int ahci_bad_pmp_check_ready(struct ata_link *link)
1366 {
1367 void __iomem *port_mmio = ahci_port_base(link->ap);
1368 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
1369 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
1370
1371 /*
1372 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
1373 * which can save timeout delay.
1374 */
1375 if (irq_status & PORT_IRQ_BAD_PMP)
1376 return -EIO;
1377
1378 return ata_check_ready(status);
1379 }
1380
1381 int ahci_pmp_retry_softreset(struct ata_link *link, unsigned int *class,
1382 unsigned long deadline)
1383 {
1384 struct ata_port *ap = link->ap;
1385 void __iomem *port_mmio = ahci_port_base(ap);
1386 int pmp = sata_srst_pmp(link);
1387 int rc;
1388 u32 irq_sts;
1389
1390 DPRINTK("ENTER\n");
1391
1392 rc = ahci_do_softreset(link, class, pmp, deadline,
1393 ahci_bad_pmp_check_ready);
1394
1395 /*
1396 * Soft reset fails with IPMS set when PMP is enabled but
1397 * SATA HDD/ODD is connected to SATA port, do soft reset
1398 * again to port 0.
1399 */
1400 if (rc == -EIO) {
1401 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
1402 if (irq_sts & PORT_IRQ_BAD_PMP) {
1403 ata_link_warn(link,
1404 "applying PMP SRST workaround "
1405 "and retrying\n");
1406 rc = ahci_do_softreset(link, class, 0, deadline,
1407 ahci_check_ready);
1408 }
1409 }
1410
1411 return rc;
1412 }
1413
1414 static int ahci_hardreset(struct ata_link *link, unsigned int *class,
1415 unsigned long deadline)
1416 {
1417 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
1418 struct ata_port *ap = link->ap;
1419 struct ahci_port_priv *pp = ap->private_data;
1420 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
1421 struct ata_taskfile tf;
1422 bool online;
1423 int rc;
1424
1425 DPRINTK("ENTER\n");
1426
1427 ahci_stop_engine(ap);
1428
1429 /* clear D2H reception area to properly wait for D2H FIS */
1430 ata_tf_init(link->device, &tf);
1431 tf.command = 0x80;
1432 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
1433
1434 rc = sata_link_hardreset(link, timing, deadline, &online,
1435 ahci_check_ready);
1436
1437 ahci_start_engine(ap);
1438
1439 if (online)
1440 *class = ahci_dev_classify(ap);
1441
1442 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
1443 return rc;
1444 }
1445
1446 static void ahci_postreset(struct ata_link *link, unsigned int *class)
1447 {
1448 struct ata_port *ap = link->ap;
1449 void __iomem *port_mmio = ahci_port_base(ap);
1450 u32 new_tmp, tmp;
1451
1452 ata_std_postreset(link, class);
1453
1454 /* Make sure port's ATAPI bit is set appropriately */
1455 new_tmp = tmp = readl(port_mmio + PORT_CMD);
1456 if (*class == ATA_DEV_ATAPI)
1457 new_tmp |= PORT_CMD_ATAPI;
1458 else
1459 new_tmp &= ~PORT_CMD_ATAPI;
1460 if (new_tmp != tmp) {
1461 writel(new_tmp, port_mmio + PORT_CMD);
1462 readl(port_mmio + PORT_CMD); /* flush */
1463 }
1464 }
1465
1466 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
1467 {
1468 struct scatterlist *sg;
1469 struct ahci_sg *ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
1470 unsigned int si;
1471
1472 VPRINTK("ENTER\n");
1473
1474 /*
1475 * Next, the S/G list.
1476 */
1477 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1478 dma_addr_t addr = sg_dma_address(sg);
1479 u32 sg_len = sg_dma_len(sg);
1480
1481 ahci_sg[si].addr = cpu_to_le32(addr & 0xffffffff);
1482 ahci_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1483 ahci_sg[si].flags_size = cpu_to_le32(sg_len - 1);
1484 }
1485
1486 return si;
1487 }
1488
1489 static int ahci_pmp_qc_defer(struct ata_queued_cmd *qc)
1490 {
1491 struct ata_port *ap = qc->ap;
1492 struct ahci_port_priv *pp = ap->private_data;
1493
1494 if (!sata_pmp_attached(ap) || pp->fbs_enabled)
1495 return ata_std_qc_defer(qc);
1496 else
1497 return sata_pmp_qc_defer_cmd_switch(qc);
1498 }
1499
1500 static void ahci_qc_prep(struct ata_queued_cmd *qc)
1501 {
1502 struct ata_port *ap = qc->ap;
1503 struct ahci_port_priv *pp = ap->private_data;
1504 int is_atapi = ata_is_atapi(qc->tf.protocol);
1505 void *cmd_tbl;
1506 u32 opts;
1507 const u32 cmd_fis_len = 5; /* five dwords */
1508 unsigned int n_elem;
1509
1510 /*
1511 * Fill in command table information. First, the header,
1512 * a SATA Register - Host to Device command FIS.
1513 */
1514 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
1515
1516 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl);
1517 if (is_atapi) {
1518 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
1519 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
1520 }
1521
1522 n_elem = 0;
1523 if (qc->flags & ATA_QCFLAG_DMAMAP)
1524 n_elem = ahci_fill_sg(qc, cmd_tbl);
1525
1526 /*
1527 * Fill in command slot information.
1528 */
1529 opts = cmd_fis_len | n_elem << 16 | (qc->dev->link->pmp << 12);
1530 if (qc->tf.flags & ATA_TFLAG_WRITE)
1531 opts |= AHCI_CMD_WRITE;
1532 if (is_atapi)
1533 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
1534
1535 ahci_fill_cmd_slot(pp, qc->tag, opts);
1536 }
1537
1538 static void ahci_fbs_dec_intr(struct ata_port *ap)
1539 {
1540 struct ahci_port_priv *pp = ap->private_data;
1541 void __iomem *port_mmio = ahci_port_base(ap);
1542 u32 fbs = readl(port_mmio + PORT_FBS);
1543 int retries = 3;
1544
1545 DPRINTK("ENTER\n");
1546 BUG_ON(!pp->fbs_enabled);
1547
1548 /* time to wait for DEC is not specified by AHCI spec,
1549 * add a retry loop for safety.
1550 */
1551 writel(fbs | PORT_FBS_DEC, port_mmio + PORT_FBS);
1552 fbs = readl(port_mmio + PORT_FBS);
1553 while ((fbs & PORT_FBS_DEC) && retries--) {
1554 udelay(1);
1555 fbs = readl(port_mmio + PORT_FBS);
1556 }
1557
1558 if (fbs & PORT_FBS_DEC)
1559 dev_err(ap->host->dev, "failed to clear device error\n");
1560 }
1561
1562 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
1563 {
1564 struct ahci_host_priv *hpriv = ap->host->private_data;
1565 struct ahci_port_priv *pp = ap->private_data;
1566 struct ata_eh_info *host_ehi = &ap->link.eh_info;
1567 struct ata_link *link = NULL;
1568 struct ata_queued_cmd *active_qc;
1569 struct ata_eh_info *active_ehi;
1570 bool fbs_need_dec = false;
1571 u32 serror;
1572
1573 /* determine active link with error */
1574 if (pp->fbs_enabled) {
1575 void __iomem *port_mmio = ahci_port_base(ap);
1576 u32 fbs = readl(port_mmio + PORT_FBS);
1577 int pmp = fbs >> PORT_FBS_DWE_OFFSET;
1578
1579 if ((fbs & PORT_FBS_SDE) && (pmp < ap->nr_pmp_links)) {
1580 link = &ap->pmp_link[pmp];
1581 fbs_need_dec = true;
1582 }
1583
1584 } else
1585 ata_for_each_link(link, ap, EDGE)
1586 if (ata_link_active(link))
1587 break;
1588
1589 if (!link)
1590 link = &ap->link;
1591
1592 active_qc = ata_qc_from_tag(ap, link->active_tag);
1593 active_ehi = &link->eh_info;
1594
1595 /* record irq stat */
1596 ata_ehi_clear_desc(host_ehi);
1597 ata_ehi_push_desc(host_ehi, "irq_stat 0x%08x", irq_stat);
1598
1599 /* AHCI needs SError cleared; otherwise, it might lock up */
1600 ahci_scr_read(&ap->link, SCR_ERROR, &serror);
1601 ahci_scr_write(&ap->link, SCR_ERROR, serror);
1602 host_ehi->serror |= serror;
1603
1604 /* some controllers set IRQ_IF_ERR on device errors, ignore it */
1605 if (hpriv->flags & AHCI_HFLAG_IGN_IRQ_IF_ERR)
1606 irq_stat &= ~PORT_IRQ_IF_ERR;
1607
1608 if (irq_stat & PORT_IRQ_TF_ERR) {
1609 /* If qc is active, charge it; otherwise, the active
1610 * link. There's no active qc on NCQ errors. It will
1611 * be determined by EH by reading log page 10h.
1612 */
1613 if (active_qc)
1614 active_qc->err_mask |= AC_ERR_DEV;
1615 else
1616 active_ehi->err_mask |= AC_ERR_DEV;
1617
1618 if (hpriv->flags & AHCI_HFLAG_IGN_SERR_INTERNAL)
1619 host_ehi->serror &= ~SERR_INTERNAL;
1620 }
1621
1622 if (irq_stat & PORT_IRQ_UNK_FIS) {
1623 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
1624
1625 active_ehi->err_mask |= AC_ERR_HSM;
1626 active_ehi->action |= ATA_EH_RESET;
1627 ata_ehi_push_desc(active_ehi,
1628 "unknown FIS %08x %08x %08x %08x" ,
1629 unk[0], unk[1], unk[2], unk[3]);
1630 }
1631
1632 if (sata_pmp_attached(ap) && (irq_stat & PORT_IRQ_BAD_PMP)) {
1633 active_ehi->err_mask |= AC_ERR_HSM;
1634 active_ehi->action |= ATA_EH_RESET;
1635 ata_ehi_push_desc(active_ehi, "incorrect PMP");
1636 }
1637
1638 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
1639 host_ehi->err_mask |= AC_ERR_HOST_BUS;
1640 host_ehi->action |= ATA_EH_RESET;
1641 ata_ehi_push_desc(host_ehi, "host bus error");
1642 }
1643
1644 if (irq_stat & PORT_IRQ_IF_ERR) {
1645 if (fbs_need_dec)
1646 active_ehi->err_mask |= AC_ERR_DEV;
1647 else {
1648 host_ehi->err_mask |= AC_ERR_ATA_BUS;
1649 host_ehi->action |= ATA_EH_RESET;
1650 }
1651
1652 ata_ehi_push_desc(host_ehi, "interface fatal error");
1653 }
1654
1655 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
1656 ata_ehi_hotplugged(host_ehi);
1657 ata_ehi_push_desc(host_ehi, "%s",
1658 irq_stat & PORT_IRQ_CONNECT ?
1659 "connection status changed" : "PHY RDY changed");
1660 }
1661
1662 /* okay, let's hand over to EH */
1663
1664 if (irq_stat & PORT_IRQ_FREEZE)
1665 ata_port_freeze(ap);
1666 else if (fbs_need_dec) {
1667 ata_link_abort(link);
1668 ahci_fbs_dec_intr(ap);
1669 } else
1670 ata_port_abort(ap);
1671 }
1672
1673 static void ahci_handle_port_interrupt(struct ata_port *ap,
1674 void __iomem *port_mmio, u32 status)
1675 {
1676 struct ata_eh_info *ehi = &ap->link.eh_info;
1677 struct ahci_port_priv *pp = ap->private_data;
1678 struct ahci_host_priv *hpriv = ap->host->private_data;
1679 int resetting = !!(ap->pflags & ATA_PFLAG_RESETTING);
1680 u32 qc_active = 0;
1681 int rc;
1682
1683 /* ignore BAD_PMP while resetting */
1684 if (unlikely(resetting))
1685 status &= ~PORT_IRQ_BAD_PMP;
1686
1687 if (sata_lpm_ignore_phy_events(&ap->link)) {
1688 status &= ~PORT_IRQ_PHYRDY;
1689 ahci_scr_write(&ap->link, SCR_ERROR, SERR_PHYRDY_CHG);
1690 }
1691
1692 if (unlikely(status & PORT_IRQ_ERROR)) {
1693 ahci_error_intr(ap, status);
1694 return;
1695 }
1696
1697 if (status & PORT_IRQ_SDB_FIS) {
1698 /* If SNotification is available, leave notification
1699 * handling to sata_async_notification(). If not,
1700 * emulate it by snooping SDB FIS RX area.
1701 *
1702 * Snooping FIS RX area is probably cheaper than
1703 * poking SNotification but some constrollers which
1704 * implement SNotification, ICH9 for example, don't
1705 * store AN SDB FIS into receive area.
1706 */
1707 if (hpriv->cap & HOST_CAP_SNTF)
1708 sata_async_notification(ap);
1709 else {
1710 /* If the 'N' bit in word 0 of the FIS is set,
1711 * we just received asynchronous notification.
1712 * Tell libata about it.
1713 *
1714 * Lack of SNotification should not appear in
1715 * ahci 1.2, so the workaround is unnecessary
1716 * when FBS is enabled.
1717 */
1718 if (pp->fbs_enabled)
1719 WARN_ON_ONCE(1);
1720 else {
1721 const __le32 *f = pp->rx_fis + RX_FIS_SDB;
1722 u32 f0 = le32_to_cpu(f[0]);
1723 if (f0 & (1 << 15))
1724 sata_async_notification(ap);
1725 }
1726 }
1727 }
1728
1729 /* pp->active_link is not reliable once FBS is enabled, both
1730 * PORT_SCR_ACT and PORT_CMD_ISSUE should be checked because
1731 * NCQ and non-NCQ commands may be in flight at the same time.
1732 */
1733 if (pp->fbs_enabled) {
1734 if (ap->qc_active) {
1735 qc_active = readl(port_mmio + PORT_SCR_ACT);
1736 qc_active |= readl(port_mmio + PORT_CMD_ISSUE);
1737 }
1738 } else {
1739 /* pp->active_link is valid iff any command is in flight */
1740 if (ap->qc_active && pp->active_link->sactive)
1741 qc_active = readl(port_mmio + PORT_SCR_ACT);
1742 else
1743 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
1744 }
1745
1746
1747 rc = ata_qc_complete_multiple(ap, qc_active);
1748
1749 /* while resetting, invalid completions are expected */
1750 if (unlikely(rc < 0 && !resetting)) {
1751 ehi->err_mask |= AC_ERR_HSM;
1752 ehi->action |= ATA_EH_RESET;
1753 ata_port_freeze(ap);
1754 }
1755 }
1756
1757 void ahci_port_intr(struct ata_port *ap)
1758 {
1759 void __iomem *port_mmio = ahci_port_base(ap);
1760 u32 status;
1761
1762 status = readl(port_mmio + PORT_IRQ_STAT);
1763 writel(status, port_mmio + PORT_IRQ_STAT);
1764
1765 ahci_handle_port_interrupt(ap, port_mmio, status);
1766 }
1767
1768 irqreturn_t ahci_thread_fn(int irq, void *dev_instance)
1769 {
1770 struct ata_port *ap = dev_instance;
1771 struct ahci_port_priv *pp = ap->private_data;
1772 void __iomem *port_mmio = ahci_port_base(ap);
1773 unsigned long flags;
1774 u32 status;
1775
1776 spin_lock_irqsave(&ap->host->lock, flags);
1777 status = pp->intr_status;
1778 if (status)
1779 pp->intr_status = 0;
1780 spin_unlock_irqrestore(&ap->host->lock, flags);
1781
1782 spin_lock_bh(ap->lock);
1783 ahci_handle_port_interrupt(ap, port_mmio, status);
1784 spin_unlock_bh(ap->lock);
1785
1786 return IRQ_HANDLED;
1787 }
1788 EXPORT_SYMBOL_GPL(ahci_thread_fn);
1789
1790 void ahci_hw_port_interrupt(struct ata_port *ap)
1791 {
1792 void __iomem *port_mmio = ahci_port_base(ap);
1793 struct ahci_port_priv *pp = ap->private_data;
1794 u32 status;
1795
1796 status = readl(port_mmio + PORT_IRQ_STAT);
1797 writel(status, port_mmio + PORT_IRQ_STAT);
1798
1799 pp->intr_status |= status;
1800 }
1801
1802 irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance)
1803 {
1804 struct ata_port *ap_this = dev_instance;
1805 struct ahci_port_priv *pp = ap_this->private_data;
1806 struct ata_host *host = ap_this->host;
1807 struct ahci_host_priv *hpriv = host->private_data;
1808 void __iomem *mmio = hpriv->mmio;
1809 unsigned int i;
1810 u32 irq_stat, irq_masked;
1811
1812 VPRINTK("ENTER\n");
1813
1814 spin_lock(&host->lock);
1815
1816 irq_stat = readl(mmio + HOST_IRQ_STAT);
1817
1818 if (!irq_stat) {
1819 u32 status = pp->intr_status;
1820
1821 spin_unlock(&host->lock);
1822
1823 VPRINTK("EXIT\n");
1824
1825 return status ? IRQ_WAKE_THREAD : IRQ_NONE;
1826 }
1827
1828 irq_masked = irq_stat & hpriv->port_map;
1829
1830 for (i = 0; i < host->n_ports; i++) {
1831 struct ata_port *ap;
1832
1833 if (!(irq_masked & (1 << i)))
1834 continue;
1835
1836 ap = host->ports[i];
1837 if (ap) {
1838 ahci_hw_port_interrupt(ap);
1839 VPRINTK("port %u\n", i);
1840 } else {
1841 VPRINTK("port %u (no irq)\n", i);
1842 if (ata_ratelimit())
1843 dev_warn(host->dev,
1844 "interrupt on disabled port %u\n", i);
1845 }
1846 }
1847
1848 writel(irq_stat, mmio + HOST_IRQ_STAT);
1849
1850 spin_unlock(&host->lock);
1851
1852 VPRINTK("EXIT\n");
1853
1854 return IRQ_WAKE_THREAD;
1855 }
1856 EXPORT_SYMBOL_GPL(ahci_hw_interrupt);
1857
1858 irqreturn_t ahci_interrupt(int irq, void *dev_instance)
1859 {
1860 struct ata_host *host = dev_instance;
1861 struct ahci_host_priv *hpriv;
1862 unsigned int i, handled = 0;
1863 void __iomem *mmio;
1864 u32 irq_stat, irq_masked;
1865
1866 VPRINTK("ENTER\n");
1867
1868 hpriv = host->private_data;
1869 mmio = hpriv->mmio;
1870
1871 /* sigh. 0xffffffff is a valid return from h/w */
1872 irq_stat = readl(mmio + HOST_IRQ_STAT);
1873 if (!irq_stat)
1874 return IRQ_NONE;
1875
1876 irq_masked = irq_stat & hpriv->port_map;
1877
1878 spin_lock(&host->lock);
1879
1880 for (i = 0; i < host->n_ports; i++) {
1881 struct ata_port *ap;
1882
1883 if (!(irq_masked & (1 << i)))
1884 continue;
1885
1886 ap = host->ports[i];
1887 if (ap) {
1888 ahci_port_intr(ap);
1889 VPRINTK("port %u\n", i);
1890 } else {
1891 VPRINTK("port %u (no irq)\n", i);
1892 if (ata_ratelimit())
1893 dev_warn(host->dev,
1894 "interrupt on disabled port %u\n", i);
1895 }
1896
1897 handled = 1;
1898 }
1899
1900 /* HOST_IRQ_STAT behaves as level triggered latch meaning that
1901 * it should be cleared after all the port events are cleared;
1902 * otherwise, it will raise a spurious interrupt after each
1903 * valid one. Please read section 10.6.2 of ahci 1.1 for more
1904 * information.
1905 *
1906 * Also, use the unmasked value to clear interrupt as spurious
1907 * pending event on a dummy port might cause screaming IRQ.
1908 */
1909 writel(irq_stat, mmio + HOST_IRQ_STAT);
1910
1911 spin_unlock(&host->lock);
1912
1913 VPRINTK("EXIT\n");
1914
1915 return IRQ_RETVAL(handled);
1916 }
1917 EXPORT_SYMBOL_GPL(ahci_interrupt);
1918
1919 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1920 {
1921 struct ata_port *ap = qc->ap;
1922 void __iomem *port_mmio = ahci_port_base(ap);
1923 struct ahci_port_priv *pp = ap->private_data;
1924
1925 /* Keep track of the currently active link. It will be used
1926 * in completion path to determine whether NCQ phase is in
1927 * progress.
1928 */
1929 pp->active_link = qc->dev->link;
1930
1931 if (qc->tf.protocol == ATA_PROT_NCQ)
1932 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
1933
1934 if (pp->fbs_enabled && pp->fbs_last_dev != qc->dev->link->pmp) {
1935 u32 fbs = readl(port_mmio + PORT_FBS);
1936 fbs &= ~(PORT_FBS_DEV_MASK | PORT_FBS_DEC);
1937 fbs |= qc->dev->link->pmp << PORT_FBS_DEV_OFFSET;
1938 writel(fbs, port_mmio + PORT_FBS);
1939 pp->fbs_last_dev = qc->dev->link->pmp;
1940 }
1941
1942 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
1943
1944 ahci_sw_activity(qc->dev->link);
1945
1946 return 0;
1947 }
1948
1949 static bool ahci_qc_fill_rtf(struct ata_queued_cmd *qc)
1950 {
1951 struct ahci_port_priv *pp = qc->ap->private_data;
1952 u8 *rx_fis = pp->rx_fis;
1953
1954 if (pp->fbs_enabled)
1955 rx_fis += qc->dev->link->pmp * AHCI_RX_FIS_SZ;
1956
1957 /*
1958 * After a successful execution of an ATA PIO data-in command,
1959 * the device doesn't send D2H Reg FIS to update the TF and
1960 * the host should take TF and E_Status from the preceding PIO
1961 * Setup FIS.
1962 */
1963 if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE &&
1964 !(qc->flags & ATA_QCFLAG_FAILED)) {
1965 ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf);
1966 qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15];
1967 } else
1968 ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf);
1969
1970 return true;
1971 }
1972
1973 static void ahci_freeze(struct ata_port *ap)
1974 {
1975 void __iomem *port_mmio = ahci_port_base(ap);
1976
1977 /* turn IRQ off */
1978 writel(0, port_mmio + PORT_IRQ_MASK);
1979 }
1980
1981 static void ahci_thaw(struct ata_port *ap)
1982 {
1983 struct ahci_host_priv *hpriv = ap->host->private_data;
1984 void __iomem *mmio = hpriv->mmio;
1985 void __iomem *port_mmio = ahci_port_base(ap);
1986 u32 tmp;
1987 struct ahci_port_priv *pp = ap->private_data;
1988
1989 /* clear IRQ */
1990 tmp = readl(port_mmio + PORT_IRQ_STAT);
1991 writel(tmp, port_mmio + PORT_IRQ_STAT);
1992 writel(1 << ap->port_no, mmio + HOST_IRQ_STAT);
1993
1994 /* turn IRQ back on */
1995 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
1996 }
1997
1998 static void ahci_error_handler(struct ata_port *ap)
1999 {
2000 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
2001 /* restart engine */
2002 ahci_stop_engine(ap);
2003 ahci_start_engine(ap);
2004 }
2005
2006 sata_pmp_error_handler(ap);
2007
2008 if (!ata_dev_enabled(ap->link.device))
2009 ahci_stop_engine(ap);
2010 }
2011
2012 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
2013 {
2014 struct ata_port *ap = qc->ap;
2015
2016 /* make DMA engine forget about the failed command */
2017 if (qc->flags & ATA_QCFLAG_FAILED)
2018 ahci_kick_engine(ap);
2019 }
2020
2021 static void ahci_set_aggressive_devslp(struct ata_port *ap, bool sleep)
2022 {
2023 void __iomem *port_mmio = ahci_port_base(ap);
2024 struct ata_device *dev = ap->link.device;
2025 u32 devslp, dm, dito, mdat, deto;
2026 int rc;
2027 unsigned int err_mask;
2028
2029 devslp = readl(port_mmio + PORT_DEVSLP);
2030 if (!(devslp & PORT_DEVSLP_DSP)) {
2031 dev_err(ap->host->dev, "port does not support device sleep\n");
2032 return;
2033 }
2034
2035 /* disable device sleep */
2036 if (!sleep) {
2037 if (devslp & PORT_DEVSLP_ADSE) {
2038 writel(devslp & ~PORT_DEVSLP_ADSE,
2039 port_mmio + PORT_DEVSLP);
2040 err_mask = ata_dev_set_feature(dev,
2041 SETFEATURES_SATA_DISABLE,
2042 SATA_DEVSLP);
2043 if (err_mask && err_mask != AC_ERR_DEV)
2044 ata_dev_warn(dev, "failed to disable DEVSLP\n");
2045 }
2046 return;
2047 }
2048
2049 /* device sleep was already enabled */
2050 if (devslp & PORT_DEVSLP_ADSE)
2051 return;
2052
2053 /* set DITO, MDAT, DETO and enable DevSlp, need to stop engine first */
2054 rc = ahci_stop_engine(ap);
2055 if (rc)
2056 return;
2057
2058 dm = (devslp & PORT_DEVSLP_DM_MASK) >> PORT_DEVSLP_DM_OFFSET;
2059 dito = devslp_idle_timeout / (dm + 1);
2060 if (dito > 0x3ff)
2061 dito = 0x3ff;
2062
2063 /* Use the nominal value 10 ms if the read MDAT is zero,
2064 * the nominal value of DETO is 20 ms.
2065 */
2066 if (dev->devslp_timing[ATA_LOG_DEVSLP_VALID] &
2067 ATA_LOG_DEVSLP_VALID_MASK) {
2068 mdat = dev->devslp_timing[ATA_LOG_DEVSLP_MDAT] &
2069 ATA_LOG_DEVSLP_MDAT_MASK;
2070 if (!mdat)
2071 mdat = 10;
2072 deto = dev->devslp_timing[ATA_LOG_DEVSLP_DETO];
2073 if (!deto)
2074 deto = 20;
2075 } else {
2076 mdat = 10;
2077 deto = 20;
2078 }
2079
2080 devslp |= ((dito << PORT_DEVSLP_DITO_OFFSET) |
2081 (mdat << PORT_DEVSLP_MDAT_OFFSET) |
2082 (deto << PORT_DEVSLP_DETO_OFFSET) |
2083 PORT_DEVSLP_ADSE);
2084 writel(devslp, port_mmio + PORT_DEVSLP);
2085
2086 ahci_start_engine(ap);
2087
2088 /* enable device sleep feature for the drive */
2089 err_mask = ata_dev_set_feature(dev,
2090 SETFEATURES_SATA_ENABLE,
2091 SATA_DEVSLP);
2092 if (err_mask && err_mask != AC_ERR_DEV)
2093 ata_dev_warn(dev, "failed to enable DEVSLP\n");
2094 }
2095
2096 static void ahci_enable_fbs(struct ata_port *ap)
2097 {
2098 struct ahci_port_priv *pp = ap->private_data;
2099 void __iomem *port_mmio = ahci_port_base(ap);
2100 u32 fbs;
2101 int rc;
2102
2103 if (!pp->fbs_supported)
2104 return;
2105
2106 fbs = readl(port_mmio + PORT_FBS);
2107 if (fbs & PORT_FBS_EN) {
2108 pp->fbs_enabled = true;
2109 pp->fbs_last_dev = -1; /* initialization */
2110 return;
2111 }
2112
2113 rc = ahci_stop_engine(ap);
2114 if (rc)
2115 return;
2116
2117 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS);
2118 fbs = readl(port_mmio + PORT_FBS);
2119 if (fbs & PORT_FBS_EN) {
2120 dev_info(ap->host->dev, "FBS is enabled\n");
2121 pp->fbs_enabled = true;
2122 pp->fbs_last_dev = -1; /* initialization */
2123 } else
2124 dev_err(ap->host->dev, "Failed to enable FBS\n");
2125
2126 ahci_start_engine(ap);
2127 }
2128
2129 static void ahci_disable_fbs(struct ata_port *ap)
2130 {
2131 struct ahci_port_priv *pp = ap->private_data;
2132 void __iomem *port_mmio = ahci_port_base(ap);
2133 u32 fbs;
2134 int rc;
2135
2136 if (!pp->fbs_supported)
2137 return;
2138
2139 fbs = readl(port_mmio + PORT_FBS);
2140 if ((fbs & PORT_FBS_EN) == 0) {
2141 pp->fbs_enabled = false;
2142 return;
2143 }
2144
2145 rc = ahci_stop_engine(ap);
2146 if (rc)
2147 return;
2148
2149 writel(fbs & ~PORT_FBS_EN, port_mmio + PORT_FBS);
2150 fbs = readl(port_mmio + PORT_FBS);
2151 if (fbs & PORT_FBS_EN)
2152 dev_err(ap->host->dev, "Failed to disable FBS\n");
2153 else {
2154 dev_info(ap->host->dev, "FBS is disabled\n");
2155 pp->fbs_enabled = false;
2156 }
2157
2158 ahci_start_engine(ap);
2159 }
2160
2161 static void ahci_pmp_attach(struct ata_port *ap)
2162 {
2163 void __iomem *port_mmio = ahci_port_base(ap);
2164 struct ahci_port_priv *pp = ap->private_data;
2165 u32 cmd;
2166
2167 cmd = readl(port_mmio + PORT_CMD);
2168 cmd |= PORT_CMD_PMP;
2169 writel(cmd, port_mmio + PORT_CMD);
2170
2171 ahci_enable_fbs(ap);
2172
2173 pp->intr_mask |= PORT_IRQ_BAD_PMP;
2174
2175 /*
2176 * We must not change the port interrupt mask register if the
2177 * port is marked frozen, the value in pp->intr_mask will be
2178 * restored later when the port is thawed.
2179 *
2180 * Note that during initialization, the port is marked as
2181 * frozen since the irq handler is not yet registered.
2182 */
2183 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2184 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2185 }
2186
2187 static void ahci_pmp_detach(struct ata_port *ap)
2188 {
2189 void __iomem *port_mmio = ahci_port_base(ap);
2190 struct ahci_port_priv *pp = ap->private_data;
2191 u32 cmd;
2192
2193 ahci_disable_fbs(ap);
2194
2195 cmd = readl(port_mmio + PORT_CMD);
2196 cmd &= ~PORT_CMD_PMP;
2197 writel(cmd, port_mmio + PORT_CMD);
2198
2199 pp->intr_mask &= ~PORT_IRQ_BAD_PMP;
2200
2201 /* see comment above in ahci_pmp_attach() */
2202 if (!(ap->pflags & ATA_PFLAG_FROZEN))
2203 writel(pp->intr_mask, port_mmio + PORT_IRQ_MASK);
2204 }
2205
2206 int ahci_port_resume(struct ata_port *ap)
2207 {
2208 ahci_power_up(ap);
2209 ahci_start_port(ap);
2210
2211 if (sata_pmp_attached(ap))
2212 ahci_pmp_attach(ap);
2213 else
2214 ahci_pmp_detach(ap);
2215
2216 return 0;
2217 }
2218 EXPORT_SYMBOL_GPL(ahci_port_resume);
2219
2220 #ifdef CONFIG_PM
2221 static int ahci_port_suspend(struct ata_port *ap, pm_message_t mesg)
2222 {
2223 const char *emsg = NULL;
2224 int rc;
2225
2226 rc = ahci_deinit_port(ap, &emsg);
2227 if (rc == 0)
2228 ahci_power_down(ap);
2229 else {
2230 ata_port_err(ap, "%s (%d)\n", emsg, rc);
2231 ata_port_freeze(ap);
2232 }
2233
2234 return rc;
2235 }
2236 #endif
2237
2238 static int ahci_port_start(struct ata_port *ap)
2239 {
2240 struct ahci_host_priv *hpriv = ap->host->private_data;
2241 struct device *dev = ap->host->dev;
2242 struct ahci_port_priv *pp;
2243 void *mem;
2244 dma_addr_t mem_dma;
2245 size_t dma_sz, rx_fis_sz;
2246
2247 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
2248 if (!pp)
2249 return -ENOMEM;
2250
2251 /* check FBS capability */
2252 if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) {
2253 void __iomem *port_mmio = ahci_port_base(ap);
2254 u32 cmd = readl(port_mmio + PORT_CMD);
2255 if (cmd & PORT_CMD_FBSCP)
2256 pp->fbs_supported = true;
2257 else if (hpriv->flags & AHCI_HFLAG_YES_FBS) {
2258 dev_info(dev, "port %d can do FBS, forcing FBSCP\n",
2259 ap->port_no);
2260 pp->fbs_supported = true;
2261 } else
2262 dev_warn(dev, "port %d is not capable of FBS\n",
2263 ap->port_no);
2264 }
2265
2266 if (pp->fbs_supported) {
2267 dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ;
2268 rx_fis_sz = AHCI_RX_FIS_SZ * 16;
2269 } else {
2270 dma_sz = AHCI_PORT_PRIV_DMA_SZ;
2271 rx_fis_sz = AHCI_RX_FIS_SZ;
2272 }
2273
2274 mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL);
2275 if (!mem)
2276 return -ENOMEM;
2277 memset(mem, 0, dma_sz);
2278
2279 /*
2280 * First item in chunk of DMA memory: 32-slot command table,
2281 * 32 bytes each in size
2282 */
2283 pp->cmd_slot = mem;
2284 pp->cmd_slot_dma = mem_dma;
2285
2286 mem += AHCI_CMD_SLOT_SZ;
2287 mem_dma += AHCI_CMD_SLOT_SZ;
2288
2289 /*
2290 * Second item: Received-FIS area
2291 */
2292 pp->rx_fis = mem;
2293 pp->rx_fis_dma = mem_dma;
2294
2295 mem += rx_fis_sz;
2296 mem_dma += rx_fis_sz;
2297
2298 /*
2299 * Third item: data area for storing a single command
2300 * and its scatter-gather table
2301 */
2302 pp->cmd_tbl = mem;
2303 pp->cmd_tbl_dma = mem_dma;
2304
2305 /*
2306 * Save off initial list of interrupts to be enabled.
2307 * This could be changed later
2308 */
2309 pp->intr_mask = DEF_PORT_IRQ;
2310
2311 /*
2312 * Switch to per-port locking in case each port has its own MSI vector.
2313 */
2314 if ((hpriv->flags & AHCI_HFLAG_MULTI_MSI)) {
2315 spin_lock_init(&pp->lock);
2316 ap->lock = &pp->lock;
2317 }
2318
2319 ap->private_data = pp;
2320
2321 /* engage engines, captain */
2322 return ahci_port_resume(ap);
2323 }
2324
2325 static void ahci_port_stop(struct ata_port *ap)
2326 {
2327 const char *emsg = NULL;
2328 int rc;
2329
2330 /* de-initialize port */
2331 rc = ahci_deinit_port(ap, &emsg);
2332 if (rc)
2333 ata_port_warn(ap, "%s (%d)\n", emsg, rc);
2334 }
2335
2336 void ahci_print_info(struct ata_host *host, const char *scc_s)
2337 {
2338 struct ahci_host_priv *hpriv = host->private_data;
2339 void __iomem *mmio = hpriv->mmio;
2340 u32 vers, cap, cap2, impl, speed;
2341 const char *speed_s;
2342
2343 vers = readl(mmio + HOST_VERSION);
2344 cap = hpriv->cap;
2345 cap2 = hpriv->cap2;
2346 impl = hpriv->port_map;
2347
2348 speed = (cap >> 20) & 0xf;
2349 if (speed == 1)
2350 speed_s = "1.5";
2351 else if (speed == 2)
2352 speed_s = "3";
2353 else if (speed == 3)
2354 speed_s = "6";
2355 else
2356 speed_s = "?";
2357
2358 dev_info(host->dev,
2359 "AHCI %02x%02x.%02x%02x "
2360 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
2361 ,
2362
2363 (vers >> 24) & 0xff,
2364 (vers >> 16) & 0xff,
2365 (vers >> 8) & 0xff,
2366 vers & 0xff,
2367
2368 ((cap >> 8) & 0x1f) + 1,
2369 (cap & 0x1f) + 1,
2370 speed_s,
2371 impl,
2372 scc_s);
2373
2374 dev_info(host->dev,
2375 "flags: "
2376 "%s%s%s%s%s%s%s"
2377 "%s%s%s%s%s%s%s"
2378 "%s%s%s%s%s%s%s"
2379 "%s%s\n"
2380 ,
2381
2382 cap & HOST_CAP_64 ? "64bit " : "",
2383 cap & HOST_CAP_NCQ ? "ncq " : "",
2384 cap & HOST_CAP_SNTF ? "sntf " : "",
2385 cap & HOST_CAP_MPS ? "ilck " : "",
2386 cap & HOST_CAP_SSS ? "stag " : "",
2387 cap & HOST_CAP_ALPM ? "pm " : "",
2388 cap & HOST_CAP_LED ? "led " : "",
2389 cap & HOST_CAP_CLO ? "clo " : "",
2390 cap & HOST_CAP_ONLY ? "only " : "",
2391 cap & HOST_CAP_PMP ? "pmp " : "",
2392 cap & HOST_CAP_FBS ? "fbs " : "",
2393 cap & HOST_CAP_PIO_MULTI ? "pio " : "",
2394 cap & HOST_CAP_SSC ? "slum " : "",
2395 cap & HOST_CAP_PART ? "part " : "",
2396 cap & HOST_CAP_CCC ? "ccc " : "",
2397 cap & HOST_CAP_EMS ? "ems " : "",
2398 cap & HOST_CAP_SXS ? "sxs " : "",
2399 cap2 & HOST_CAP2_DESO ? "deso " : "",
2400 cap2 & HOST_CAP2_SADM ? "sadm " : "",
2401 cap2 & HOST_CAP2_SDS ? "sds " : "",
2402 cap2 & HOST_CAP2_APST ? "apst " : "",
2403 cap2 & HOST_CAP2_NVMHCI ? "nvmp " : "",
2404 cap2 & HOST_CAP2_BOH ? "boh " : ""
2405 );
2406 }
2407 EXPORT_SYMBOL_GPL(ahci_print_info);
2408
2409 void ahci_set_em_messages(struct ahci_host_priv *hpriv,
2410 struct ata_port_info *pi)
2411 {
2412 u8 messages;
2413 void __iomem *mmio = hpriv->mmio;
2414 u32 em_loc = readl(mmio + HOST_EM_LOC);
2415 u32 em_ctl = readl(mmio + HOST_EM_CTL);
2416
2417 if (!ahci_em_messages || !(hpriv->cap & HOST_CAP_EMS))
2418 return;
2419
2420 messages = (em_ctl & EM_CTRL_MSG_TYPE) >> 16;
2421
2422 if (messages) {
2423 /* store em_loc */
2424 hpriv->em_loc = ((em_loc >> 16) * 4);
2425 hpriv->em_buf_sz = ((em_loc & 0xff) * 4);
2426 hpriv->em_msg_type = messages;
2427 pi->flags |= ATA_FLAG_EM;
2428 if (!(em_ctl & EM_CTL_ALHD))
2429 pi->flags |= ATA_FLAG_SW_ACTIVITY;
2430 }
2431 }
2432 EXPORT_SYMBOL_GPL(ahci_set_em_messages);
2433
2434 MODULE_AUTHOR("Jeff Garzik");
2435 MODULE_DESCRIPTION("Common AHCI SATA low-level routines");
2436 MODULE_LICENSE("GPL");
kernel source for telekom puls (alcatel/mediatek)