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ARM: shmobile: force enable of r8a7790 arch timer
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / ata_piix.c
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publicly available from Intel web site. Errata documentation
42 * is also publicly available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independent device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independent timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
97
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
100
101 enum {
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
109
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
112
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
115
116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* constants for mapping table */
122 P0 = 0, /* port 0 */
123 P1 = 1, /* port 1 */
124 P2 = 2, /* port 2 */
125 P3 = 3, /* port 3 */
126 IDE = -1, /* IDE */
127 NA = -2, /* not available */
128 RV = -3, /* reserved */
129
130 PIIX_AHCI_DEVICE = 6,
131
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
134 };
135
136 enum piix_controller_ids {
137 /* controller IDs */
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
144 ich5_sata,
145 ich6_sata,
146 ich6m_sata,
147 ich8_sata,
148 ich8_2port_sata,
149 ich8m_apple_sata, /* locks up on second port enable */
150 tolapai_sata,
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
152 ich8_sata_snb,
153 };
154
155 struct piix_map_db {
156 const u32 mask;
157 const u16 port_enable;
158 const int map[][4];
159 };
160
161 struct piix_host_priv {
162 const int *map;
163 u32 saved_iocfg;
164 void __iomem *sidpr;
165 };
166
167 static unsigned int in_module_init = 1;
168
169 static const struct pci_device_id piix_pci_tbl[] = {
170 /* Intel PIIX3 for the 430HX etc */
171 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
172 /* VMware ICH4 */
173 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
174 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
175 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
176 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
177 /* Intel PIIX4 */
178 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
179 /* Intel PIIX4 */
180 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
181 /* Intel PIIX */
182 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
183 /* Intel ICH (i810, i815, i840) UDMA 66*/
184 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
185 /* Intel ICH0 : UDMA 33*/
186 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
187 /* Intel ICH2M */
188 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
189 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
190 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 /* Intel ICH3M */
192 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH3 (E7500/1) UDMA 100 */
194 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH4-L */
196 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
198 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 /* Intel ICH5 */
201 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 /* C-ICH (i810E2) */
203 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
205 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* ICH6 (and 6) (i915) UDMA 100 */
207 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* ICH7/7-R (i945, i975) UDMA 100*/
209 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
210 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
211 /* ICH8 Mobile PATA Controller */
212 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213
214 /* SATA ports */
215
216 /* 82801EB (ICH5) */
217 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
218 /* 82801EB (ICH5) */
219 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
220 /* 6300ESB (ICH5 variant with broken PCS present bits) */
221 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
222 /* 6300ESB pretending RAID */
223 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
224 /* 82801FB/FW (ICH6/ICH6W) */
225 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
226 /* 82801FR/FRW (ICH6R/ICH6RW) */
227 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
228 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
229 * Attach iff the controller is in IDE mode. */
230 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
231 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
232 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
233 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
234 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
235 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
236 /* Enterprise Southbridge 2 (631xESB/632xESB) */
237 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
238 /* SATA Controller 1 IDE (ICH8) */
239 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
240 /* SATA Controller 2 IDE (ICH8) */
241 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
242 /* Mobile SATA Controller IDE (ICH8M), Apple */
243 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
244 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
245 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
246 /* Mobile SATA Controller IDE (ICH8M) */
247 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
248 /* SATA Controller IDE (ICH9) */
249 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
250 /* SATA Controller IDE (ICH9) */
251 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
252 /* SATA Controller IDE (ICH9) */
253 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
254 /* SATA Controller IDE (ICH9M) */
255 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
256 /* SATA Controller IDE (ICH9M) */
257 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
258 /* SATA Controller IDE (ICH9M) */
259 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
260 /* SATA Controller IDE (Tolapai) */
261 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
262 /* SATA Controller IDE (ICH10) */
263 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
264 /* SATA Controller IDE (ICH10) */
265 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (ICH10) */
267 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
268 /* SATA Controller IDE (ICH10) */
269 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
270 /* SATA Controller IDE (PCH) */
271 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
272 /* SATA Controller IDE (PCH) */
273 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (PCH) */
275 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (PCH) */
277 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
278 /* SATA Controller IDE (PCH) */
279 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (PCH) */
281 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
282 /* SATA Controller IDE (CPT) */
283 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
284 /* SATA Controller IDE (CPT) */
285 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
286 /* SATA Controller IDE (CPT) */
287 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (CPT) */
289 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
290 /* SATA Controller IDE (PBG) */
291 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
292 /* SATA Controller IDE (PBG) */
293 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
294 /* SATA Controller IDE (Panther Point) */
295 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
296 /* SATA Controller IDE (Panther Point) */
297 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
298 /* SATA Controller IDE (Panther Point) */
299 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
300 /* SATA Controller IDE (Panther Point) */
301 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
302 /* SATA Controller IDE (Lynx Point) */
303 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
304 /* SATA Controller IDE (Lynx Point) */
305 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
306 /* SATA Controller IDE (Lynx Point) */
307 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
308 /* SATA Controller IDE (Lynx Point) */
309 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
310 /* SATA Controller IDE (Lynx Point-LP) */
311 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
312 /* SATA Controller IDE (Lynx Point-LP) */
313 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
314 /* SATA Controller IDE (Lynx Point-LP) */
315 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
316 /* SATA Controller IDE (Lynx Point-LP) */
317 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
318 /* SATA Controller IDE (DH89xxCC) */
319 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
320 /* SATA Controller IDE (Avoton) */
321 { 0x8086, 0x1f20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
322 /* SATA Controller IDE (Avoton) */
323 { 0x8086, 0x1f21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
324 /* SATA Controller IDE (Avoton) */
325 { 0x8086, 0x1f30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
326 /* SATA Controller IDE (Avoton) */
327 { 0x8086, 0x1f31, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
328 /* SATA Controller IDE (Wellsburg) */
329 { 0x8086, 0x8d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
330 /* SATA Controller IDE (Wellsburg) */
331 { 0x8086, 0x8d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
332 /* SATA Controller IDE (Wellsburg) */
333 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
334 /* SATA Controller IDE (Wellsburg) */
335 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
336
337 { } /* terminate list */
338 };
339
340 static const struct piix_map_db ich5_map_db = {
341 .mask = 0x7,
342 .port_enable = 0x3,
343 .map = {
344 /* PM PS SM SS MAP */
345 { P0, NA, P1, NA }, /* 000b */
346 { P1, NA, P0, NA }, /* 001b */
347 { RV, RV, RV, RV },
348 { RV, RV, RV, RV },
349 { P0, P1, IDE, IDE }, /* 100b */
350 { P1, P0, IDE, IDE }, /* 101b */
351 { IDE, IDE, P0, P1 }, /* 110b */
352 { IDE, IDE, P1, P0 }, /* 111b */
353 },
354 };
355
356 static const struct piix_map_db ich6_map_db = {
357 .mask = 0x3,
358 .port_enable = 0xf,
359 .map = {
360 /* PM PS SM SS MAP */
361 { P0, P2, P1, P3 }, /* 00b */
362 { IDE, IDE, P1, P3 }, /* 01b */
363 { P0, P2, IDE, IDE }, /* 10b */
364 { RV, RV, RV, RV },
365 },
366 };
367
368 static const struct piix_map_db ich6m_map_db = {
369 .mask = 0x3,
370 .port_enable = 0x5,
371
372 /* Map 01b isn't specified in the doc but some notebooks use
373 * it anyway. MAP 01b have been spotted on both ICH6M and
374 * ICH7M.
375 */
376 .map = {
377 /* PM PS SM SS MAP */
378 { P0, P2, NA, NA }, /* 00b */
379 { IDE, IDE, P1, P3 }, /* 01b */
380 { P0, P2, IDE, IDE }, /* 10b */
381 { RV, RV, RV, RV },
382 },
383 };
384
385 static const struct piix_map_db ich8_map_db = {
386 .mask = 0x3,
387 .port_enable = 0xf,
388 .map = {
389 /* PM PS SM SS MAP */
390 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
391 { RV, RV, RV, RV },
392 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
393 { RV, RV, RV, RV },
394 },
395 };
396
397 static const struct piix_map_db ich8_2port_map_db = {
398 .mask = 0x3,
399 .port_enable = 0x3,
400 .map = {
401 /* PM PS SM SS MAP */
402 { P0, NA, P1, NA }, /* 00b */
403 { RV, RV, RV, RV }, /* 01b */
404 { RV, RV, RV, RV }, /* 10b */
405 { RV, RV, RV, RV },
406 },
407 };
408
409 static const struct piix_map_db ich8m_apple_map_db = {
410 .mask = 0x3,
411 .port_enable = 0x1,
412 .map = {
413 /* PM PS SM SS MAP */
414 { P0, NA, NA, NA }, /* 00b */
415 { RV, RV, RV, RV },
416 { P0, P2, IDE, IDE }, /* 10b */
417 { RV, RV, RV, RV },
418 },
419 };
420
421 static const struct piix_map_db tolapai_map_db = {
422 .mask = 0x3,
423 .port_enable = 0x3,
424 .map = {
425 /* PM PS SM SS MAP */
426 { P0, NA, P1, NA }, /* 00b */
427 { RV, RV, RV, RV }, /* 01b */
428 { RV, RV, RV, RV }, /* 10b */
429 { RV, RV, RV, RV },
430 },
431 };
432
433 static const struct piix_map_db *piix_map_db_table[] = {
434 [ich5_sata] = &ich5_map_db,
435 [ich6_sata] = &ich6_map_db,
436 [ich6m_sata] = &ich6m_map_db,
437 [ich8_sata] = &ich8_map_db,
438 [ich8_2port_sata] = &ich8_2port_map_db,
439 [ich8m_apple_sata] = &ich8m_apple_map_db,
440 [tolapai_sata] = &tolapai_map_db,
441 [ich8_sata_snb] = &ich8_map_db,
442 };
443
444 static struct pci_bits piix_enable_bits[] = {
445 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
446 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
447 };
448
449 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
450 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
451 MODULE_LICENSE("GPL");
452 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
453 MODULE_VERSION(DRV_VERSION);
454
455 struct ich_laptop {
456 u16 device;
457 u16 subvendor;
458 u16 subdevice;
459 };
460
461 /*
462 * List of laptops that use short cables rather than 80 wire
463 */
464
465 static const struct ich_laptop ich_laptop[] = {
466 /* devid, subvendor, subdev */
467 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
468 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
469 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
470 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
471 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
472 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
473 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
474 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
475 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
476 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
477 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
478 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
479 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
480 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
481 /* end marker */
482 { 0, }
483 };
484
485 static int piix_port_start(struct ata_port *ap)
486 {
487 if (!(ap->flags & PIIX_FLAG_PIO16))
488 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
489
490 return ata_bmdma_port_start(ap);
491 }
492
493 /**
494 * ich_pata_cable_detect - Probe host controller cable detect info
495 * @ap: Port for which cable detect info is desired
496 *
497 * Read 80c cable indicator from ATA PCI device's PCI config
498 * register. This register is normally set by firmware (BIOS).
499 *
500 * LOCKING:
501 * None (inherited from caller).
502 */
503
504 static int ich_pata_cable_detect(struct ata_port *ap)
505 {
506 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
507 struct piix_host_priv *hpriv = ap->host->private_data;
508 const struct ich_laptop *lap = &ich_laptop[0];
509 u8 mask;
510
511 /* Check for specials - Acer Aspire 5602WLMi */
512 while (lap->device) {
513 if (lap->device == pdev->device &&
514 lap->subvendor == pdev->subsystem_vendor &&
515 lap->subdevice == pdev->subsystem_device)
516 return ATA_CBL_PATA40_SHORT;
517
518 lap++;
519 }
520
521 /* check BIOS cable detect results */
522 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
523 if ((hpriv->saved_iocfg & mask) == 0)
524 return ATA_CBL_PATA40;
525 return ATA_CBL_PATA80;
526 }
527
528 /**
529 * piix_pata_prereset - prereset for PATA host controller
530 * @link: Target link
531 * @deadline: deadline jiffies for the operation
532 *
533 * LOCKING:
534 * None (inherited from caller).
535 */
536 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
537 {
538 struct ata_port *ap = link->ap;
539 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
540
541 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
542 return -ENOENT;
543 return ata_sff_prereset(link, deadline);
544 }
545
546 static DEFINE_SPINLOCK(piix_lock);
547
548 static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
549 u8 pio)
550 {
551 struct pci_dev *dev = to_pci_dev(ap->host->dev);
552 unsigned long flags;
553 unsigned int is_slave = (adev->devno != 0);
554 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
555 unsigned int slave_port = 0x44;
556 u16 master_data;
557 u8 slave_data;
558 u8 udma_enable;
559 int control = 0;
560
561 /*
562 * See Intel Document 298600-004 for the timing programing rules
563 * for ICH controllers.
564 */
565
566 static const /* ISP RTC */
567 u8 timings[][2] = { { 0, 0 },
568 { 0, 0 },
569 { 1, 0 },
570 { 2, 1 },
571 { 2, 3 }, };
572
573 if (pio >= 2)
574 control |= 1; /* TIME1 enable */
575 if (ata_pio_need_iordy(adev))
576 control |= 2; /* IE enable */
577 /* Intel specifies that the PPE functionality is for disk only */
578 if (adev->class == ATA_DEV_ATA)
579 control |= 4; /* PPE enable */
580 /*
581 * If the drive MWDMA is faster than it can do PIO then
582 * we must force PIO into PIO0
583 */
584 if (adev->pio_mode < XFER_PIO_0 + pio)
585 /* Enable DMA timing only */
586 control |= 8; /* PIO cycles in PIO0 */
587
588 spin_lock_irqsave(&piix_lock, flags);
589
590 /* PIO configuration clears DTE unconditionally. It will be
591 * programmed in set_dmamode which is guaranteed to be called
592 * after set_piomode if any DMA mode is available.
593 */
594 pci_read_config_word(dev, master_port, &master_data);
595 if (is_slave) {
596 /* clear TIME1|IE1|PPE1|DTE1 */
597 master_data &= 0xff0f;
598 /* enable PPE1, IE1 and TIME1 as needed */
599 master_data |= (control << 4);
600 pci_read_config_byte(dev, slave_port, &slave_data);
601 slave_data &= (ap->port_no ? 0x0f : 0xf0);
602 /* Load the timing nibble for this slave */
603 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
604 << (ap->port_no ? 4 : 0);
605 } else {
606 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
607 master_data &= 0xccf0;
608 /* Enable PPE, IE and TIME as appropriate */
609 master_data |= control;
610 /* load ISP and RCT */
611 master_data |=
612 (timings[pio][0] << 12) |
613 (timings[pio][1] << 8);
614 }
615
616 /* Enable SITRE (separate slave timing register) */
617 master_data |= 0x4000;
618 pci_write_config_word(dev, master_port, master_data);
619 if (is_slave)
620 pci_write_config_byte(dev, slave_port, slave_data);
621
622 /* Ensure the UDMA bit is off - it will be turned back on if
623 UDMA is selected */
624
625 if (ap->udma_mask) {
626 pci_read_config_byte(dev, 0x48, &udma_enable);
627 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
628 pci_write_config_byte(dev, 0x48, udma_enable);
629 }
630
631 spin_unlock_irqrestore(&piix_lock, flags);
632 }
633
634 /**
635 * piix_set_piomode - Initialize host controller PATA PIO timings
636 * @ap: Port whose timings we are configuring
637 * @adev: Drive in question
638 *
639 * Set PIO mode for device, in host controller PCI config space.
640 *
641 * LOCKING:
642 * None (inherited from caller).
643 */
644
645 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
646 {
647 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
648 }
649
650 /**
651 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
652 * @ap: Port whose timings we are configuring
653 * @adev: Drive in question
654 * @isich: set if the chip is an ICH device
655 *
656 * Set UDMA mode for device, in host controller PCI config space.
657 *
658 * LOCKING:
659 * None (inherited from caller).
660 */
661
662 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
663 {
664 struct pci_dev *dev = to_pci_dev(ap->host->dev);
665 unsigned long flags;
666 u8 speed = adev->dma_mode;
667 int devid = adev->devno + 2 * ap->port_no;
668 u8 udma_enable = 0;
669
670 if (speed >= XFER_UDMA_0) {
671 unsigned int udma = speed - XFER_UDMA_0;
672 u16 udma_timing;
673 u16 ideconf;
674 int u_clock, u_speed;
675
676 spin_lock_irqsave(&piix_lock, flags);
677
678 pci_read_config_byte(dev, 0x48, &udma_enable);
679
680 /*
681 * UDMA is handled by a combination of clock switching and
682 * selection of dividers
683 *
684 * Handy rule: Odd modes are UDMATIMx 01, even are 02
685 * except UDMA0 which is 00
686 */
687 u_speed = min(2 - (udma & 1), udma);
688 if (udma == 5)
689 u_clock = 0x1000; /* 100Mhz */
690 else if (udma > 2)
691 u_clock = 1; /* 66Mhz */
692 else
693 u_clock = 0; /* 33Mhz */
694
695 udma_enable |= (1 << devid);
696
697 /* Load the CT/RP selection */
698 pci_read_config_word(dev, 0x4A, &udma_timing);
699 udma_timing &= ~(3 << (4 * devid));
700 udma_timing |= u_speed << (4 * devid);
701 pci_write_config_word(dev, 0x4A, udma_timing);
702
703 if (isich) {
704 /* Select a 33/66/100Mhz clock */
705 pci_read_config_word(dev, 0x54, &ideconf);
706 ideconf &= ~(0x1001 << devid);
707 ideconf |= u_clock << devid;
708 /* For ICH or later we should set bit 10 for better
709 performance (WR_PingPong_En) */
710 pci_write_config_word(dev, 0x54, ideconf);
711 }
712
713 pci_write_config_byte(dev, 0x48, udma_enable);
714
715 spin_unlock_irqrestore(&piix_lock, flags);
716 } else {
717 /* MWDMA is driven by the PIO timings. */
718 unsigned int mwdma = speed - XFER_MW_DMA_0;
719 const unsigned int needed_pio[3] = {
720 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
721 };
722 int pio = needed_pio[mwdma] - XFER_PIO_0;
723
724 /* XFER_PIO_0 is never used currently */
725 piix_set_timings(ap, adev, pio);
726 }
727 }
728
729 /**
730 * piix_set_dmamode - Initialize host controller PATA DMA timings
731 * @ap: Port whose timings we are configuring
732 * @adev: um
733 *
734 * Set MW/UDMA mode for device, in host controller PCI config space.
735 *
736 * LOCKING:
737 * None (inherited from caller).
738 */
739
740 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
741 {
742 do_pata_set_dmamode(ap, adev, 0);
743 }
744
745 /**
746 * ich_set_dmamode - Initialize host controller PATA DMA timings
747 * @ap: Port whose timings we are configuring
748 * @adev: um
749 *
750 * Set MW/UDMA mode for device, in host controller PCI config space.
751 *
752 * LOCKING:
753 * None (inherited from caller).
754 */
755
756 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
757 {
758 do_pata_set_dmamode(ap, adev, 1);
759 }
760
761 /*
762 * Serial ATA Index/Data Pair Superset Registers access
763 *
764 * Beginning from ICH8, there's a sane way to access SCRs using index
765 * and data register pair located at BAR5 which means that we have
766 * separate SCRs for master and slave. This is handled using libata
767 * slave_link facility.
768 */
769 static const int piix_sidx_map[] = {
770 [SCR_STATUS] = 0,
771 [SCR_ERROR] = 2,
772 [SCR_CONTROL] = 1,
773 };
774
775 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
776 {
777 struct ata_port *ap = link->ap;
778 struct piix_host_priv *hpriv = ap->host->private_data;
779
780 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
781 hpriv->sidpr + PIIX_SIDPR_IDX);
782 }
783
784 static int piix_sidpr_scr_read(struct ata_link *link,
785 unsigned int reg, u32 *val)
786 {
787 struct piix_host_priv *hpriv = link->ap->host->private_data;
788
789 if (reg >= ARRAY_SIZE(piix_sidx_map))
790 return -EINVAL;
791
792 piix_sidpr_sel(link, reg);
793 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
794 return 0;
795 }
796
797 static int piix_sidpr_scr_write(struct ata_link *link,
798 unsigned int reg, u32 val)
799 {
800 struct piix_host_priv *hpriv = link->ap->host->private_data;
801
802 if (reg >= ARRAY_SIZE(piix_sidx_map))
803 return -EINVAL;
804
805 piix_sidpr_sel(link, reg);
806 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
807 return 0;
808 }
809
810 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
811 unsigned hints)
812 {
813 return sata_link_scr_lpm(link, policy, false);
814 }
815
816 static bool piix_irq_check(struct ata_port *ap)
817 {
818 if (unlikely(!ap->ioaddr.bmdma_addr))
819 return false;
820
821 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
822 }
823
824 #ifdef CONFIG_PM
825 static int piix_broken_suspend(void)
826 {
827 static const struct dmi_system_id sysids[] = {
828 {
829 .ident = "TECRA M3",
830 .matches = {
831 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
832 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
833 },
834 },
835 {
836 .ident = "TECRA M3",
837 .matches = {
838 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
839 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
840 },
841 },
842 {
843 .ident = "TECRA M4",
844 .matches = {
845 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
846 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
847 },
848 },
849 {
850 .ident = "TECRA M4",
851 .matches = {
852 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
853 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
854 },
855 },
856 {
857 .ident = "TECRA M5",
858 .matches = {
859 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
860 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
861 },
862 },
863 {
864 .ident = "TECRA M6",
865 .matches = {
866 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
867 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
868 },
869 },
870 {
871 .ident = "TECRA M7",
872 .matches = {
873 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
874 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
875 },
876 },
877 {
878 .ident = "TECRA A8",
879 .matches = {
880 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
881 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
882 },
883 },
884 {
885 .ident = "Satellite R20",
886 .matches = {
887 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
888 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
889 },
890 },
891 {
892 .ident = "Satellite R25",
893 .matches = {
894 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
895 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
896 },
897 },
898 {
899 .ident = "Satellite U200",
900 .matches = {
901 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
902 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
903 },
904 },
905 {
906 .ident = "Satellite U200",
907 .matches = {
908 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
909 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
910 },
911 },
912 {
913 .ident = "Satellite Pro U200",
914 .matches = {
915 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
916 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
917 },
918 },
919 {
920 .ident = "Satellite U205",
921 .matches = {
922 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
923 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
924 },
925 },
926 {
927 .ident = "SATELLITE U205",
928 .matches = {
929 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
930 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
931 },
932 },
933 {
934 .ident = "Satellite Pro A120",
935 .matches = {
936 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
937 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
938 },
939 },
940 {
941 .ident = "Portege M500",
942 .matches = {
943 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
944 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
945 },
946 },
947 {
948 .ident = "VGN-BX297XP",
949 .matches = {
950 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
951 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
952 },
953 },
954
955 { } /* terminate list */
956 };
957 static const char *oemstrs[] = {
958 "Tecra M3,",
959 };
960 int i;
961
962 if (dmi_check_system(sysids))
963 return 1;
964
965 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
966 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
967 return 1;
968
969 /* TECRA M4 sometimes forgets its identify and reports bogus
970 * DMI information. As the bogus information is a bit
971 * generic, match as many entries as possible. This manual
972 * matching is necessary because dmi_system_id.matches is
973 * limited to four entries.
974 */
975 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
976 dmi_match(DMI_PRODUCT_NAME, "000000") &&
977 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
978 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
979 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
980 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
981 dmi_match(DMI_BOARD_VERSION, "Version A0"))
982 return 1;
983
984 return 0;
985 }
986
987 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
988 {
989 struct ata_host *host = dev_get_drvdata(&pdev->dev);
990 unsigned long flags;
991 int rc = 0;
992
993 rc = ata_host_suspend(host, mesg);
994 if (rc)
995 return rc;
996
997 /* Some braindamaged ACPI suspend implementations expect the
998 * controller to be awake on entry; otherwise, it burns cpu
999 * cycles and power trying to do something to the sleeping
1000 * beauty.
1001 */
1002 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1003 pci_save_state(pdev);
1004
1005 /* mark its power state as "unknown", since we don't
1006 * know if e.g. the BIOS will change its device state
1007 * when we suspend.
1008 */
1009 if (pdev->current_state == PCI_D0)
1010 pdev->current_state = PCI_UNKNOWN;
1011
1012 /* tell resume that it's waking up from broken suspend */
1013 spin_lock_irqsave(&host->lock, flags);
1014 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1015 spin_unlock_irqrestore(&host->lock, flags);
1016 } else
1017 ata_pci_device_do_suspend(pdev, mesg);
1018
1019 return 0;
1020 }
1021
1022 static int piix_pci_device_resume(struct pci_dev *pdev)
1023 {
1024 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1025 unsigned long flags;
1026 int rc;
1027
1028 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1029 spin_lock_irqsave(&host->lock, flags);
1030 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1031 spin_unlock_irqrestore(&host->lock, flags);
1032
1033 pci_set_power_state(pdev, PCI_D0);
1034 pci_restore_state(pdev);
1035
1036 /* PCI device wasn't disabled during suspend. Use
1037 * pci_reenable_device() to avoid affecting the enable
1038 * count.
1039 */
1040 rc = pci_reenable_device(pdev);
1041 if (rc)
1042 dev_err(&pdev->dev,
1043 "failed to enable device after resume (%d)\n",
1044 rc);
1045 } else
1046 rc = ata_pci_device_do_resume(pdev);
1047
1048 if (rc == 0)
1049 ata_host_resume(host);
1050
1051 return rc;
1052 }
1053 #endif
1054
1055 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1056 {
1057 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1058 }
1059
1060 static struct scsi_host_template piix_sht = {
1061 ATA_BMDMA_SHT(DRV_NAME),
1062 };
1063
1064 static struct ata_port_operations piix_sata_ops = {
1065 .inherits = &ata_bmdma32_port_ops,
1066 .sff_irq_check = piix_irq_check,
1067 .port_start = piix_port_start,
1068 };
1069
1070 static struct ata_port_operations piix_pata_ops = {
1071 .inherits = &piix_sata_ops,
1072 .cable_detect = ata_cable_40wire,
1073 .set_piomode = piix_set_piomode,
1074 .set_dmamode = piix_set_dmamode,
1075 .prereset = piix_pata_prereset,
1076 };
1077
1078 static struct ata_port_operations piix_vmw_ops = {
1079 .inherits = &piix_pata_ops,
1080 .bmdma_status = piix_vmw_bmdma_status,
1081 };
1082
1083 static struct ata_port_operations ich_pata_ops = {
1084 .inherits = &piix_pata_ops,
1085 .cable_detect = ich_pata_cable_detect,
1086 .set_dmamode = ich_set_dmamode,
1087 };
1088
1089 static struct device_attribute *piix_sidpr_shost_attrs[] = {
1090 &dev_attr_link_power_management_policy,
1091 NULL
1092 };
1093
1094 static struct scsi_host_template piix_sidpr_sht = {
1095 ATA_BMDMA_SHT(DRV_NAME),
1096 .shost_attrs = piix_sidpr_shost_attrs,
1097 };
1098
1099 static struct ata_port_operations piix_sidpr_sata_ops = {
1100 .inherits = &piix_sata_ops,
1101 .hardreset = sata_std_hardreset,
1102 .scr_read = piix_sidpr_scr_read,
1103 .scr_write = piix_sidpr_scr_write,
1104 .set_lpm = piix_sidpr_set_lpm,
1105 };
1106
1107 static struct ata_port_info piix_port_info[] = {
1108 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
1109 {
1110 .flags = PIIX_PATA_FLAGS,
1111 .pio_mask = ATA_PIO4,
1112 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1113 .port_ops = &piix_pata_ops,
1114 },
1115
1116 [piix_pata_33] = /* PIIX4 at 33MHz */
1117 {
1118 .flags = PIIX_PATA_FLAGS,
1119 .pio_mask = ATA_PIO4,
1120 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1121 .udma_mask = ATA_UDMA2,
1122 .port_ops = &piix_pata_ops,
1123 },
1124
1125 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
1126 {
1127 .flags = PIIX_PATA_FLAGS,
1128 .pio_mask = ATA_PIO4,
1129 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
1130 .udma_mask = ATA_UDMA2,
1131 .port_ops = &ich_pata_ops,
1132 },
1133
1134 [ich_pata_66] = /* ICH controllers up to 66MHz */
1135 {
1136 .flags = PIIX_PATA_FLAGS,
1137 .pio_mask = ATA_PIO4,
1138 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
1139 .udma_mask = ATA_UDMA4,
1140 .port_ops = &ich_pata_ops,
1141 },
1142
1143 [ich_pata_100] =
1144 {
1145 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1146 .pio_mask = ATA_PIO4,
1147 .mwdma_mask = ATA_MWDMA12_ONLY,
1148 .udma_mask = ATA_UDMA5,
1149 .port_ops = &ich_pata_ops,
1150 },
1151
1152 [ich_pata_100_nomwdma1] =
1153 {
1154 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1155 .pio_mask = ATA_PIO4,
1156 .mwdma_mask = ATA_MWDMA2_ONLY,
1157 .udma_mask = ATA_UDMA5,
1158 .port_ops = &ich_pata_ops,
1159 },
1160
1161 [ich5_sata] =
1162 {
1163 .flags = PIIX_SATA_FLAGS,
1164 .pio_mask = ATA_PIO4,
1165 .mwdma_mask = ATA_MWDMA2,
1166 .udma_mask = ATA_UDMA6,
1167 .port_ops = &piix_sata_ops,
1168 },
1169
1170 [ich6_sata] =
1171 {
1172 .flags = PIIX_SATA_FLAGS,
1173 .pio_mask = ATA_PIO4,
1174 .mwdma_mask = ATA_MWDMA2,
1175 .udma_mask = ATA_UDMA6,
1176 .port_ops = &piix_sata_ops,
1177 },
1178
1179 [ich6m_sata] =
1180 {
1181 .flags = PIIX_SATA_FLAGS,
1182 .pio_mask = ATA_PIO4,
1183 .mwdma_mask = ATA_MWDMA2,
1184 .udma_mask = ATA_UDMA6,
1185 .port_ops = &piix_sata_ops,
1186 },
1187
1188 [ich8_sata] =
1189 {
1190 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1191 .pio_mask = ATA_PIO4,
1192 .mwdma_mask = ATA_MWDMA2,
1193 .udma_mask = ATA_UDMA6,
1194 .port_ops = &piix_sata_ops,
1195 },
1196
1197 [ich8_2port_sata] =
1198 {
1199 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1200 .pio_mask = ATA_PIO4,
1201 .mwdma_mask = ATA_MWDMA2,
1202 .udma_mask = ATA_UDMA6,
1203 .port_ops = &piix_sata_ops,
1204 },
1205
1206 [tolapai_sata] =
1207 {
1208 .flags = PIIX_SATA_FLAGS,
1209 .pio_mask = ATA_PIO4,
1210 .mwdma_mask = ATA_MWDMA2,
1211 .udma_mask = ATA_UDMA6,
1212 .port_ops = &piix_sata_ops,
1213 },
1214
1215 [ich8m_apple_sata] =
1216 {
1217 .flags = PIIX_SATA_FLAGS,
1218 .pio_mask = ATA_PIO4,
1219 .mwdma_mask = ATA_MWDMA2,
1220 .udma_mask = ATA_UDMA6,
1221 .port_ops = &piix_sata_ops,
1222 },
1223
1224 [piix_pata_vmw] =
1225 {
1226 .flags = PIIX_PATA_FLAGS,
1227 .pio_mask = ATA_PIO4,
1228 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1229 .udma_mask = ATA_UDMA2,
1230 .port_ops = &piix_vmw_ops,
1231 },
1232
1233 /*
1234 * some Sandybridge chipsets have broken 32 mode up to now,
1235 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
1236 */
1237 [ich8_sata_snb] =
1238 {
1239 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1240 .pio_mask = ATA_PIO4,
1241 .mwdma_mask = ATA_MWDMA2,
1242 .udma_mask = ATA_UDMA6,
1243 .port_ops = &piix_sata_ops,
1244 },
1245 };
1246
1247 #define AHCI_PCI_BAR 5
1248 #define AHCI_GLOBAL_CTL 0x04
1249 #define AHCI_ENABLE (1 << 31)
1250 static int piix_disable_ahci(struct pci_dev *pdev)
1251 {
1252 void __iomem *mmio;
1253 u32 tmp;
1254 int rc = 0;
1255
1256 /* BUG: pci_enable_device has not yet been called. This
1257 * works because this device is usually set up by BIOS.
1258 */
1259
1260 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1261 !pci_resource_len(pdev, AHCI_PCI_BAR))
1262 return 0;
1263
1264 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1265 if (!mmio)
1266 return -ENOMEM;
1267
1268 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1269 if (tmp & AHCI_ENABLE) {
1270 tmp &= ~AHCI_ENABLE;
1271 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1272
1273 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1274 if (tmp & AHCI_ENABLE)
1275 rc = -EIO;
1276 }
1277
1278 pci_iounmap(pdev, mmio);
1279 return rc;
1280 }
1281
1282 /**
1283 * piix_check_450nx_errata - Check for problem 450NX setup
1284 * @ata_dev: the PCI device to check
1285 *
1286 * Check for the present of 450NX errata #19 and errata #25. If
1287 * they are found return an error code so we can turn off DMA
1288 */
1289
1290 static int piix_check_450nx_errata(struct pci_dev *ata_dev)
1291 {
1292 struct pci_dev *pdev = NULL;
1293 u16 cfg;
1294 int no_piix_dma = 0;
1295
1296 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1297 /* Look for 450NX PXB. Check for problem configurations
1298 A PCI quirk checks bit 6 already */
1299 pci_read_config_word(pdev, 0x41, &cfg);
1300 /* Only on the original revision: IDE DMA can hang */
1301 if (pdev->revision == 0x00)
1302 no_piix_dma = 1;
1303 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1304 else if (cfg & (1<<14) && pdev->revision < 5)
1305 no_piix_dma = 2;
1306 }
1307 if (no_piix_dma)
1308 dev_warn(&ata_dev->dev,
1309 "450NX errata present, disabling IDE DMA%s\n",
1310 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1311 : "");
1312
1313 return no_piix_dma;
1314 }
1315
1316 static void piix_init_pcs(struct ata_host *host,
1317 const struct piix_map_db *map_db)
1318 {
1319 struct pci_dev *pdev = to_pci_dev(host->dev);
1320 u16 pcs, new_pcs;
1321
1322 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1323
1324 new_pcs = pcs | map_db->port_enable;
1325
1326 if (new_pcs != pcs) {
1327 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1328 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1329 msleep(150);
1330 }
1331 }
1332
1333 static const int *piix_init_sata_map(struct pci_dev *pdev,
1334 struct ata_port_info *pinfo,
1335 const struct piix_map_db *map_db)
1336 {
1337 const int *map;
1338 int i, invalid_map = 0;
1339 u8 map_value;
1340
1341 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1342
1343 map = map_db->map[map_value & map_db->mask];
1344
1345 dev_info(&pdev->dev, "MAP [");
1346 for (i = 0; i < 4; i++) {
1347 switch (map[i]) {
1348 case RV:
1349 invalid_map = 1;
1350 pr_cont(" XX");
1351 break;
1352
1353 case NA:
1354 pr_cont(" --");
1355 break;
1356
1357 case IDE:
1358 WARN_ON((i & 1) || map[i + 1] != IDE);
1359 pinfo[i / 2] = piix_port_info[ich_pata_100];
1360 i++;
1361 pr_cont(" IDE IDE");
1362 break;
1363
1364 default:
1365 pr_cont(" P%d", map[i]);
1366 if (i & 1)
1367 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1368 break;
1369 }
1370 }
1371 pr_cont(" ]\n");
1372
1373 if (invalid_map)
1374 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1375
1376 return map;
1377 }
1378
1379 static bool piix_no_sidpr(struct ata_host *host)
1380 {
1381 struct pci_dev *pdev = to_pci_dev(host->dev);
1382
1383 /*
1384 * Samsung DB-P70 only has three ATA ports exposed and
1385 * curiously the unconnected first port reports link online
1386 * while not responding to SRST protocol causing excessive
1387 * detection delay.
1388 *
1389 * Unfortunately, the system doesn't carry enough DMI
1390 * information to identify the machine but does have subsystem
1391 * vendor and device set. As it's unclear whether the
1392 * subsystem vendor/device is used only for this specific
1393 * board, the port can't be disabled solely with the
1394 * information; however, turning off SIDPR access works around
1395 * the problem. Turn it off.
1396 *
1397 * This problem is reported in bnc#441240.
1398 *
1399 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1400 */
1401 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1402 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1403 pdev->subsystem_device == 0xb049) {
1404 dev_warn(host->dev,
1405 "Samsung DB-P70 detected, disabling SIDPR\n");
1406 return true;
1407 }
1408
1409 return false;
1410 }
1411
1412 static int piix_init_sidpr(struct ata_host *host)
1413 {
1414 struct pci_dev *pdev = to_pci_dev(host->dev);
1415 struct piix_host_priv *hpriv = host->private_data;
1416 struct ata_link *link0 = &host->ports[0]->link;
1417 u32 scontrol;
1418 int i, rc;
1419
1420 /* check for availability */
1421 for (i = 0; i < 4; i++)
1422 if (hpriv->map[i] == IDE)
1423 return 0;
1424
1425 /* is it blacklisted? */
1426 if (piix_no_sidpr(host))
1427 return 0;
1428
1429 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1430 return 0;
1431
1432 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1433 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1434 return 0;
1435
1436 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1437 return 0;
1438
1439 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1440
1441 /* SCR access via SIDPR doesn't work on some configurations.
1442 * Give it a test drive by inhibiting power save modes which
1443 * we'll do anyway.
1444 */
1445 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1446
1447 /* if IPM is already 3, SCR access is probably working. Don't
1448 * un-inhibit power save modes as BIOS might have inhibited
1449 * them for a reason.
1450 */
1451 if ((scontrol & 0xf00) != 0x300) {
1452 scontrol |= 0x300;
1453 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1454 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1455
1456 if ((scontrol & 0xf00) != 0x300) {
1457 dev_info(host->dev,
1458 "SCR access via SIDPR is available but doesn't work\n");
1459 return 0;
1460 }
1461 }
1462
1463 /* okay, SCRs available, set ops and ask libata for slave_link */
1464 for (i = 0; i < 2; i++) {
1465 struct ata_port *ap = host->ports[i];
1466
1467 ap->ops = &piix_sidpr_sata_ops;
1468
1469 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1470 rc = ata_slave_link_init(ap);
1471 if (rc)
1472 return rc;
1473 }
1474 }
1475
1476 return 0;
1477 }
1478
1479 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1480 {
1481 static const struct dmi_system_id sysids[] = {
1482 {
1483 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1484 * isn't used to boot the system which
1485 * disables the channel.
1486 */
1487 .ident = "M570U",
1488 .matches = {
1489 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1490 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1491 },
1492 },
1493
1494 { } /* terminate list */
1495 };
1496 struct pci_dev *pdev = to_pci_dev(host->dev);
1497 struct piix_host_priv *hpriv = host->private_data;
1498
1499 if (!dmi_check_system(sysids))
1500 return;
1501
1502 /* The datasheet says that bit 18 is NOOP but certain systems
1503 * seem to use it to disable a channel. Clear the bit on the
1504 * affected systems.
1505 */
1506 if (hpriv->saved_iocfg & (1 << 18)) {
1507 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1508 pci_write_config_dword(pdev, PIIX_IOCFG,
1509 hpriv->saved_iocfg & ~(1 << 18));
1510 }
1511 }
1512
1513 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1514 {
1515 static const struct dmi_system_id broken_systems[] = {
1516 {
1517 .ident = "HP Compaq 2510p",
1518 .matches = {
1519 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1520 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1521 },
1522 /* PCI slot number of the controller */
1523 .driver_data = (void *)0x1FUL,
1524 },
1525 {
1526 .ident = "HP Compaq nc6000",
1527 .matches = {
1528 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1529 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1530 },
1531 /* PCI slot number of the controller */
1532 .driver_data = (void *)0x1FUL,
1533 },
1534
1535 { } /* terminate list */
1536 };
1537 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1538
1539 if (dmi) {
1540 unsigned long slot = (unsigned long)dmi->driver_data;
1541 /* apply the quirk only to on-board controllers */
1542 return slot == PCI_SLOT(pdev->devfn);
1543 }
1544
1545 return false;
1546 }
1547
1548 static int prefer_ms_hyperv = 1;
1549 module_param(prefer_ms_hyperv, int, 0);
1550
1551 static void piix_ignore_devices_quirk(struct ata_host *host)
1552 {
1553 #if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1554 static const struct dmi_system_id ignore_hyperv[] = {
1555 {
1556 /* On Hyper-V hypervisors the disks are exposed on
1557 * both the emulated SATA controller and on the
1558 * paravirtualised drivers. The CD/DVD devices
1559 * are only exposed on the emulated controller.
1560 * Request we ignore ATA devices on this host.
1561 */
1562 .ident = "Hyper-V Virtual Machine",
1563 .matches = {
1564 DMI_MATCH(DMI_SYS_VENDOR,
1565 "Microsoft Corporation"),
1566 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1567 },
1568 },
1569 { } /* terminate list */
1570 };
1571 static const struct dmi_system_id allow_virtual_pc[] = {
1572 {
1573 /* In MS Virtual PC guests the DMI ident is nearly
1574 * identical to a Hyper-V guest. One difference is the
1575 * product version which is used here to identify
1576 * a Virtual PC guest. This entry allows ata_piix to
1577 * drive the emulated hardware.
1578 */
1579 .ident = "MS Virtual PC 2007",
1580 .matches = {
1581 DMI_MATCH(DMI_SYS_VENDOR,
1582 "Microsoft Corporation"),
1583 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1584 DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
1585 },
1586 },
1587 { } /* terminate list */
1588 };
1589 const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
1590 const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
1591
1592 if (ignore && !allow && prefer_ms_hyperv) {
1593 host->flags |= ATA_HOST_IGNORE_ATA;
1594 dev_info(host->dev, "%s detected, ATA device ignore set\n",
1595 ignore->ident);
1596 }
1597 #endif
1598 }
1599
1600 /**
1601 * piix_init_one - Register PIIX ATA PCI device with kernel services
1602 * @pdev: PCI device to register
1603 * @ent: Entry in piix_pci_tbl matching with @pdev
1604 *
1605 * Called from kernel PCI layer. We probe for combined mode (sigh),
1606 * and then hand over control to libata, for it to do the rest.
1607 *
1608 * LOCKING:
1609 * Inherited from PCI layer (may sleep).
1610 *
1611 * RETURNS:
1612 * Zero on success, or -ERRNO value.
1613 */
1614
1615 static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1616 {
1617 struct device *dev = &pdev->dev;
1618 struct ata_port_info port_info[2];
1619 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1620 struct scsi_host_template *sht = &piix_sht;
1621 unsigned long port_flags;
1622 struct ata_host *host;
1623 struct piix_host_priv *hpriv;
1624 int rc;
1625
1626 ata_print_version_once(&pdev->dev, DRV_VERSION);
1627
1628 /* no hotplugging support for later devices (FIXME) */
1629 if (!in_module_init && ent->driver_data >= ich5_sata)
1630 return -ENODEV;
1631
1632 if (piix_broken_system_poweroff(pdev)) {
1633 piix_port_info[ent->driver_data].flags |=
1634 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1635 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1636 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1637 "on poweroff and hibernation\n");
1638 }
1639
1640 port_info[0] = piix_port_info[ent->driver_data];
1641 port_info[1] = piix_port_info[ent->driver_data];
1642
1643 port_flags = port_info[0].flags;
1644
1645 /* enable device and prepare host */
1646 rc = pcim_enable_device(pdev);
1647 if (rc)
1648 return rc;
1649
1650 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1651 if (!hpriv)
1652 return -ENOMEM;
1653
1654 /* Save IOCFG, this will be used for cable detection, quirk
1655 * detection and restoration on detach. This is necessary
1656 * because some ACPI implementations mess up cable related
1657 * bits on _STM. Reported on kernel bz#11879.
1658 */
1659 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1660
1661 /* ICH6R may be driven by either ata_piix or ahci driver
1662 * regardless of BIOS configuration. Make sure AHCI mode is
1663 * off.
1664 */
1665 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1666 rc = piix_disable_ahci(pdev);
1667 if (rc)
1668 return rc;
1669 }
1670
1671 /* SATA map init can change port_info, do it before prepping host */
1672 if (port_flags & ATA_FLAG_SATA)
1673 hpriv->map = piix_init_sata_map(pdev, port_info,
1674 piix_map_db_table[ent->driver_data]);
1675
1676 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1677 if (rc)
1678 return rc;
1679 host->private_data = hpriv;
1680
1681 /* initialize controller */
1682 if (port_flags & ATA_FLAG_SATA) {
1683 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1684 rc = piix_init_sidpr(host);
1685 if (rc)
1686 return rc;
1687 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1688 sht = &piix_sidpr_sht;
1689 }
1690
1691 /* apply IOCFG bit18 quirk */
1692 piix_iocfg_bit18_quirk(host);
1693
1694 /* On ICH5, some BIOSen disable the interrupt using the
1695 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1696 * On ICH6, this bit has the same effect, but only when
1697 * MSI is disabled (and it is disabled, as we don't use
1698 * message-signalled interrupts currently).
1699 */
1700 if (port_flags & PIIX_FLAG_CHECKINTR)
1701 pci_intx(pdev, 1);
1702
1703 if (piix_check_450nx_errata(pdev)) {
1704 /* This writes into the master table but it does not
1705 really matter for this errata as we will apply it to
1706 all the PIIX devices on the board */
1707 host->ports[0]->mwdma_mask = 0;
1708 host->ports[0]->udma_mask = 0;
1709 host->ports[1]->mwdma_mask = 0;
1710 host->ports[1]->udma_mask = 0;
1711 }
1712 host->flags |= ATA_HOST_PARALLEL_SCAN;
1713
1714 /* Allow hosts to specify device types to ignore when scanning. */
1715 piix_ignore_devices_quirk(host);
1716
1717 pci_set_master(pdev);
1718 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1719 }
1720
1721 static void piix_remove_one(struct pci_dev *pdev)
1722 {
1723 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1724 struct piix_host_priv *hpriv = host->private_data;
1725
1726 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1727
1728 ata_pci_remove_one(pdev);
1729 }
1730
1731 static struct pci_driver piix_pci_driver = {
1732 .name = DRV_NAME,
1733 .id_table = piix_pci_tbl,
1734 .probe = piix_init_one,
1735 .remove = piix_remove_one,
1736 #ifdef CONFIG_PM
1737 .suspend = piix_pci_device_suspend,
1738 .resume = piix_pci_device_resume,
1739 #endif
1740 };
1741
1742 static int __init piix_init(void)
1743 {
1744 int rc;
1745
1746 DPRINTK("pci_register_driver\n");
1747 rc = pci_register_driver(&piix_pci_driver);
1748 if (rc)
1749 return rc;
1750
1751 in_module_init = 0;
1752
1753 DPRINTK("done\n");
1754 return 0;
1755 }
1756
1757 static void __exit piix_exit(void)
1758 {
1759 pci_unregister_driver(&piix_pci_driver);
1760 }
1761
1762 module_init(piix_init);
1763 module_exit(piix_exit);
kernel source for telekom puls (alcatel/mediatek)