projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
AHCI: Add DeviceIDs for Sunrise Point-LP SATA controller
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
58 };
59
60 enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nomsi,
65 board_ahci_noncq,
66 board_ahci_nosntf,
67 board_ahci_yes_fbs,
68
69 /* board IDs for specific chipsets in alphabetical order */
70 board_ahci_mcp65,
71 board_ahci_mcp77,
72 board_ahci_mcp89,
73 board_ahci_mv,
74 board_ahci_sb600,
75 board_ahci_sb700, /* for SB700 and SB800 */
76 board_ahci_vt8251,
77
78 /* aliases */
79 board_ahci_mcp_linux = board_ahci_mcp65,
80 board_ahci_mcp67 = board_ahci_mcp65,
81 board_ahci_mcp73 = board_ahci_mcp65,
82 board_ahci_mcp79 = board_ahci_mcp77,
83 };
84
85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 #ifdef CONFIG_PM
91 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 #endif
94
95 static struct scsi_host_template ahci_sht = {
96 AHCI_SHT("ahci"),
97 };
98
99 static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
101 .hardreset = ahci_vt8251_hardreset,
102 };
103
104 static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
106 .hardreset = ahci_p5wdh_hardreset,
107 };
108
109 static const struct ata_port_info ahci_port_info[] = {
110 /* by features */
111 [board_ahci] = {
112 .flags = AHCI_FLAG_COMMON,
113 .pio_mask = ATA_PIO4,
114 .udma_mask = ATA_UDMA6,
115 .port_ops = &ahci_ops,
116 },
117 [board_ahci_ign_iferr] = {
118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_nomsi] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
131 [board_ahci_noncq] = {
132 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
137 },
138 [board_ahci_nosntf] = {
139 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
145 [board_ahci_yes_fbs] = {
146 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
152 /* by chipsets */
153 [board_ahci_mcp65] = {
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
155 AHCI_HFLAG_YES_NCQ),
156 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
161 [board_ahci_mcp77] = {
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
167 },
168 [board_ahci_mcp89] = {
169 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
170 .flags = AHCI_FLAG_COMMON,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
174 },
175 [board_ahci_mv] = {
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
183 [board_ahci_sb600] = {
184 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
185 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
186 AHCI_HFLAG_32BIT_ONLY),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_pmp_retry_srst_ops,
191 },
192 [board_ahci_sb700] = { /* for SB700 and SB800 */
193 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
197 .port_ops = &ahci_pmp_retry_srst_ops,
198 },
199 [board_ahci_vt8251] = {
200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
201 .flags = AHCI_FLAG_COMMON,
202 .pio_mask = ATA_PIO4,
203 .udma_mask = ATA_UDMA6,
204 .port_ops = &ahci_vt8251_ops,
205 },
206 };
207
208 static const struct pci_device_id ahci_pci_tbl[] = {
209 /* Intel */
210 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
211 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
212 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
213 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
214 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
215 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
216 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
217 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
220 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
221 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
222 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
223 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
224 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
236 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
238 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
239 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
240 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
241 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
242 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
243 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
245 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
248 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
250 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
251 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
252 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
253 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
254 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
255 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
256 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
257 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
258 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
259 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
260 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
261 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
262 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
263 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
264 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
266 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
267 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
269 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
270 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
271 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
273 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
274 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
275 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
276 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
277 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
278 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
279 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
280 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
281 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
282 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
283 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
284 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
285 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
286 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
287 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
288 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
289 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
290 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
291 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
292 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
293 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
294 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
295 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
296 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
297 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
298 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
299 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
300 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
301 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
302 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
303 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
304 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
305 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
306 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
307 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
308 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
309 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
310 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
311 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
312 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
313 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
314 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
315 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
316 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
317 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
318 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
319 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
320 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
321 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
322 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
323 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
324 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
325 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
327 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H RAID */
328 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
329 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
330 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
331
332 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
333 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
334 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
335 /* JMicron 362B and 362C have an AHCI function with IDE class code */
336 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
337 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
338
339 /* ATI */
340 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
341 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
342 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
343 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
344 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
345 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
346 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
347
348 /* AMD */
349 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
350 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
351 /* AMD is using RAID class only for ahci controllers */
352 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
353 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
354
355 /* VIA */
356 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
357 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
358
359 /* NVIDIA */
360 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
361 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
362 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
363 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
364 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
365 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
366 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
367 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
368 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
369 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
370 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
371 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
372 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
373 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
374 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
375 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
376 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
377 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
378 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
379 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
380 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
381 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
382 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
383 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
384 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
385 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
386 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
387 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
388 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
389 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
390 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
391 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
392 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
393 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
394 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
395 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
396 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
397 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
398 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
399 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
400 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
401 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
402 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
403 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
404 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
405 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
406 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
407 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
408 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
409 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
410 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
411 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
412 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
413 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
414 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
415 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
416 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
417 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
418 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
419 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
420 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
421 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
422 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
423 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
424 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
425 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
426 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
427 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
428 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
429 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
430 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
431 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
432 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
433 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
434 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
435 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
436 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
437 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
438 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
439 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
440 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
441 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
442 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
443 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
444
445 /* SiS */
446 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
447 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
448 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
449
450 /* ST Microelectronics */
451 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
452
453 /* Marvell */
454 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
455 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
456 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
457 .class = PCI_CLASS_STORAGE_SATA_AHCI,
458 .class_mask = 0xffffff,
459 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
460 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
461 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
462 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
463 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
464 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
465 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
466 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
467 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
468 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
469 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
470 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
471 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
472 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
473 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
474 .driver_data = board_ahci_yes_fbs },
475 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
476 .driver_data = board_ahci_yes_fbs },
477 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
478 .driver_data = board_ahci_yes_fbs },
479 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
480 .driver_data = board_ahci_yes_fbs },
481
482 /* Promise */
483 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
484 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
485
486 /* Asmedia */
487 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
488 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
489 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
490 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
491
492 /*
493 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
494 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
495 */
496 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
497
498 /* Enmotus */
499 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
500
501 /* Generic, PCI class code for AHCI */
502 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
503 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
504
505 { } /* terminate list */
506 };
507
508
509 static struct pci_driver ahci_pci_driver = {
510 .name = DRV_NAME,
511 .id_table = ahci_pci_tbl,
512 .probe = ahci_init_one,
513 .remove = ata_pci_remove_one,
514 #ifdef CONFIG_PM
515 .suspend = ahci_pci_device_suspend,
516 .resume = ahci_pci_device_resume,
517 #endif
518 };
519
520 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
521 static int marvell_enable;
522 #else
523 static int marvell_enable = 1;
524 #endif
525 module_param(marvell_enable, int, 0644);
526 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
527
528
529 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
530 struct ahci_host_priv *hpriv)
531 {
532 unsigned int force_port_map = 0;
533 unsigned int mask_port_map = 0;
534
535 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
536 dev_info(&pdev->dev, "JMB361 has only one port\n");
537 force_port_map = 1;
538 }
539
540 /*
541 * Temporary Marvell 6145 hack: PATA port presence
542 * is asserted through the standard AHCI port
543 * presence register, as bit 4 (counting from 0)
544 */
545 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
546 if (pdev->device == 0x6121)
547 mask_port_map = 0x3;
548 else
549 mask_port_map = 0xf;
550 dev_info(&pdev->dev,
551 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
552 }
553
554 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
555 mask_port_map);
556 }
557
558 static int ahci_pci_reset_controller(struct ata_host *host)
559 {
560 struct pci_dev *pdev = to_pci_dev(host->dev);
561
562 ahci_reset_controller(host);
563
564 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
565 struct ahci_host_priv *hpriv = host->private_data;
566 u16 tmp16;
567
568 /* configure PCS */
569 pci_read_config_word(pdev, 0x92, &tmp16);
570 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
571 tmp16 |= hpriv->port_map;
572 pci_write_config_word(pdev, 0x92, tmp16);
573 }
574 }
575
576 return 0;
577 }
578
579 static void ahci_pci_init_controller(struct ata_host *host)
580 {
581 struct ahci_host_priv *hpriv = host->private_data;
582 struct pci_dev *pdev = to_pci_dev(host->dev);
583 void __iomem *port_mmio;
584 u32 tmp;
585 int mv;
586
587 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
588 if (pdev->device == 0x6121)
589 mv = 2;
590 else
591 mv = 4;
592 port_mmio = __ahci_port_base(host, mv);
593
594 writel(0, port_mmio + PORT_IRQ_MASK);
595
596 /* clear port IRQ */
597 tmp = readl(port_mmio + PORT_IRQ_STAT);
598 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
599 if (tmp)
600 writel(tmp, port_mmio + PORT_IRQ_STAT);
601 }
602
603 ahci_init_controller(host);
604 }
605
606 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
607 unsigned long deadline)
608 {
609 struct ata_port *ap = link->ap;
610 bool online;
611 int rc;
612
613 DPRINTK("ENTER\n");
614
615 ahci_stop_engine(ap);
616
617 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
618 deadline, &online, NULL);
619
620 ahci_start_engine(ap);
621
622 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
623
624 /* vt8251 doesn't clear BSY on signature FIS reception,
625 * request follow-up softreset.
626 */
627 return online ? -EAGAIN : rc;
628 }
629
630 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
631 unsigned long deadline)
632 {
633 struct ata_port *ap = link->ap;
634 struct ahci_port_priv *pp = ap->private_data;
635 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
636 struct ata_taskfile tf;
637 bool online;
638 int rc;
639
640 ahci_stop_engine(ap);
641
642 /* clear D2H reception area to properly wait for D2H FIS */
643 ata_tf_init(link->device, &tf);
644 tf.command = 0x80;
645 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
646
647 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
648 deadline, &online, NULL);
649
650 ahci_start_engine(ap);
651
652 /* The pseudo configuration device on SIMG4726 attached to
653 * ASUS P5W-DH Deluxe doesn't send signature FIS after
654 * hardreset if no device is attached to the first downstream
655 * port && the pseudo device locks up on SRST w/ PMP==0. To
656 * work around this, wait for !BSY only briefly. If BSY isn't
657 * cleared, perform CLO and proceed to IDENTIFY (achieved by
658 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
659 *
660 * Wait for two seconds. Devices attached to downstream port
661 * which can't process the following IDENTIFY after this will
662 * have to be reset again. For most cases, this should
663 * suffice while making probing snappish enough.
664 */
665 if (online) {
666 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
667 ahci_check_ready);
668 if (rc)
669 ahci_kick_engine(ap);
670 }
671 return rc;
672 }
673
674 #ifdef CONFIG_PM
675 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
676 {
677 struct ata_host *host = dev_get_drvdata(&pdev->dev);
678 struct ahci_host_priv *hpriv = host->private_data;
679 void __iomem *mmio = hpriv->mmio;
680 u32 ctl;
681
682 if (mesg.event & PM_EVENT_SUSPEND &&
683 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
684 dev_err(&pdev->dev,
685 "BIOS update required for suspend/resume\n");
686 return -EIO;
687 }
688
689 if (mesg.event & PM_EVENT_SLEEP) {
690 /* AHCI spec rev1.1 section 8.3.3:
691 * Software must disable interrupts prior to requesting a
692 * transition of the HBA to D3 state.
693 */
694 ctl = readl(mmio + HOST_CTL);
695 ctl &= ~HOST_IRQ_EN;
696 writel(ctl, mmio + HOST_CTL);
697 readl(mmio + HOST_CTL); /* flush */
698 }
699
700 return ata_pci_device_suspend(pdev, mesg);
701 }
702
703 static int ahci_pci_device_resume(struct pci_dev *pdev)
704 {
705 struct ata_host *host = dev_get_drvdata(&pdev->dev);
706 int rc;
707
708 rc = ata_pci_device_do_resume(pdev);
709 if (rc)
710 return rc;
711
712 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
713 rc = ahci_pci_reset_controller(host);
714 if (rc)
715 return rc;
716
717 ahci_pci_init_controller(host);
718 }
719
720 ata_host_resume(host);
721
722 return 0;
723 }
724 #endif
725
726 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
727 {
728 int rc;
729
730 /*
731 * If the device fixup already set the dma_mask to some non-standard
732 * value, don't extend it here. This happens on STA2X11, for example.
733 */
734 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
735 return 0;
736
737 if (using_dac &&
738 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
739 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
740 if (rc) {
741 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
742 if (rc) {
743 dev_err(&pdev->dev,
744 "64-bit DMA enable failed\n");
745 return rc;
746 }
747 }
748 } else {
749 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
750 if (rc) {
751 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
752 return rc;
753 }
754 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
755 if (rc) {
756 dev_err(&pdev->dev,
757 "32-bit consistent DMA enable failed\n");
758 return rc;
759 }
760 }
761 return 0;
762 }
763
764 static void ahci_pci_print_info(struct ata_host *host)
765 {
766 struct pci_dev *pdev = to_pci_dev(host->dev);
767 u16 cc;
768 const char *scc_s;
769
770 pci_read_config_word(pdev, 0x0a, &cc);
771 if (cc == PCI_CLASS_STORAGE_IDE)
772 scc_s = "IDE";
773 else if (cc == PCI_CLASS_STORAGE_SATA)
774 scc_s = "SATA";
775 else if (cc == PCI_CLASS_STORAGE_RAID)
776 scc_s = "RAID";
777 else
778 scc_s = "unknown";
779
780 ahci_print_info(host, scc_s);
781 }
782
783 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
784 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
785 * support PMP and the 4726 either directly exports the device
786 * attached to the first downstream port or acts as a hardware storage
787 * controller and emulate a single ATA device (can be RAID 0/1 or some
788 * other configuration).
789 *
790 * When there's no device attached to the first downstream port of the
791 * 4726, "Config Disk" appears, which is a pseudo ATA device to
792 * configure the 4726. However, ATA emulation of the device is very
793 * lame. It doesn't send signature D2H Reg FIS after the initial
794 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
795 *
796 * The following function works around the problem by always using
797 * hardreset on the port and not depending on receiving signature FIS
798 * afterward. If signature FIS isn't received soon, ATA class is
799 * assumed without follow-up softreset.
800 */
801 static void ahci_p5wdh_workaround(struct ata_host *host)
802 {
803 static struct dmi_system_id sysids[] = {
804 {
805 .ident = "P5W DH Deluxe",
806 .matches = {
807 DMI_MATCH(DMI_SYS_VENDOR,
808 "ASUSTEK COMPUTER INC"),
809 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
810 },
811 },
812 { }
813 };
814 struct pci_dev *pdev = to_pci_dev(host->dev);
815
816 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
817 dmi_check_system(sysids)) {
818 struct ata_port *ap = host->ports[1];
819
820 dev_info(&pdev->dev,
821 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
822
823 ap->ops = &ahci_p5wdh_ops;
824 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
825 }
826 }
827
828 /* only some SB600 ahci controllers can do 64bit DMA */
829 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
830 {
831 static const struct dmi_system_id sysids[] = {
832 /*
833 * The oldest version known to be broken is 0901 and
834 * working is 1501 which was released on 2007-10-26.
835 * Enable 64bit DMA on 1501 and anything newer.
836 *
837 * Please read bko#9412 for more info.
838 */
839 {
840 .ident = "ASUS M2A-VM",
841 .matches = {
842 DMI_MATCH(DMI_BOARD_VENDOR,
843 "ASUSTeK Computer INC."),
844 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
845 },
846 .driver_data = "20071026", /* yyyymmdd */
847 },
848 /*
849 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
850 * support 64bit DMA.
851 *
852 * BIOS versions earlier than 1.5 had the Manufacturer DMI
853 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
854 * This spelling mistake was fixed in BIOS version 1.5, so
855 * 1.5 and later have the Manufacturer as
856 * "MICRO-STAR INTERNATIONAL CO.,LTD".
857 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
858 *
859 * BIOS versions earlier than 1.9 had a Board Product Name
860 * DMI field of "MS-7376". This was changed to be
861 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
862 * match on DMI_BOARD_NAME of "MS-7376".
863 */
864 {
865 .ident = "MSI K9A2 Platinum",
866 .matches = {
867 DMI_MATCH(DMI_BOARD_VENDOR,
868 "MICRO-STAR INTER"),
869 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
870 },
871 },
872 /*
873 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
874 * 64bit DMA.
875 *
876 * This board also had the typo mentioned above in the
877 * Manufacturer DMI field (fixed in BIOS version 1.5), so
878 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
879 */
880 {
881 .ident = "MSI K9AGM2",
882 .matches = {
883 DMI_MATCH(DMI_BOARD_VENDOR,
884 "MICRO-STAR INTER"),
885 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
886 },
887 },
888 /*
889 * All BIOS versions for the Asus M3A support 64bit DMA.
890 * (all release versions from 0301 to 1206 were tested)
891 */
892 {
893 .ident = "ASUS M3A",
894 .matches = {
895 DMI_MATCH(DMI_BOARD_VENDOR,
896 "ASUSTeK Computer INC."),
897 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
898 },
899 },
900 { }
901 };
902 const struct dmi_system_id *match;
903 int year, month, date;
904 char buf[9];
905
906 match = dmi_first_match(sysids);
907 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
908 !match)
909 return false;
910
911 if (!match->driver_data)
912 goto enable_64bit;
913
914 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
915 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
916
917 if (strcmp(buf, match->driver_data) >= 0)
918 goto enable_64bit;
919 else {
920 dev_warn(&pdev->dev,
921 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
922 match->ident);
923 return false;
924 }
925
926 enable_64bit:
927 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
928 return true;
929 }
930
931 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
932 {
933 static const struct dmi_system_id broken_systems[] = {
934 {
935 .ident = "HP Compaq nx6310",
936 .matches = {
937 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
938 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
939 },
940 /* PCI slot number of the controller */
941 .driver_data = (void *)0x1FUL,
942 },
943 {
944 .ident = "HP Compaq 6720s",
945 .matches = {
946 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
947 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
948 },
949 /* PCI slot number of the controller */
950 .driver_data = (void *)0x1FUL,
951 },
952
953 { } /* terminate list */
954 };
955 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
956
957 if (dmi) {
958 unsigned long slot = (unsigned long)dmi->driver_data;
959 /* apply the quirk only to on-board controllers */
960 return slot == PCI_SLOT(pdev->devfn);
961 }
962
963 return false;
964 }
965
966 static bool ahci_broken_suspend(struct pci_dev *pdev)
967 {
968 static const struct dmi_system_id sysids[] = {
969 /*
970 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
971 * to the harddisk doesn't become online after
972 * resuming from STR. Warn and fail suspend.
973 *
974 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
975 *
976 * Use dates instead of versions to match as HP is
977 * apparently recycling both product and version
978 * strings.
979 *
980 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
981 */
982 {
983 .ident = "dv4",
984 .matches = {
985 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
986 DMI_MATCH(DMI_PRODUCT_NAME,
987 "HP Pavilion dv4 Notebook PC"),
988 },
989 .driver_data = "20090105", /* F.30 */
990 },
991 {
992 .ident = "dv5",
993 .matches = {
994 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
995 DMI_MATCH(DMI_PRODUCT_NAME,
996 "HP Pavilion dv5 Notebook PC"),
997 },
998 .driver_data = "20090506", /* F.16 */
999 },
1000 {
1001 .ident = "dv6",
1002 .matches = {
1003 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1004 DMI_MATCH(DMI_PRODUCT_NAME,
1005 "HP Pavilion dv6 Notebook PC"),
1006 },
1007 .driver_data = "20090423", /* F.21 */
1008 },
1009 {
1010 .ident = "HDX18",
1011 .matches = {
1012 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1013 DMI_MATCH(DMI_PRODUCT_NAME,
1014 "HP HDX18 Notebook PC"),
1015 },
1016 .driver_data = "20090430", /* F.23 */
1017 },
1018 /*
1019 * Acer eMachines G725 has the same problem. BIOS
1020 * V1.03 is known to be broken. V3.04 is known to
1021 * work. Between, there are V1.06, V2.06 and V3.03
1022 * that we don't have much idea about. For now,
1023 * blacklist anything older than V3.04.
1024 *
1025 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1026 */
1027 {
1028 .ident = "G725",
1029 .matches = {
1030 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1031 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1032 },
1033 .driver_data = "20091216", /* V3.04 */
1034 },
1035 { } /* terminate list */
1036 };
1037 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1038 int year, month, date;
1039 char buf[9];
1040
1041 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1042 return false;
1043
1044 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1045 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1046
1047 return strcmp(buf, dmi->driver_data) < 0;
1048 }
1049
1050 static bool ahci_broken_online(struct pci_dev *pdev)
1051 {
1052 #define ENCODE_BUSDEVFN(bus, slot, func) \
1053 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1054 static const struct dmi_system_id sysids[] = {
1055 /*
1056 * There are several gigabyte boards which use
1057 * SIMG5723s configured as hardware RAID. Certain
1058 * 5723 firmware revisions shipped there keep the link
1059 * online but fail to answer properly to SRST or
1060 * IDENTIFY when no device is attached downstream
1061 * causing libata to retry quite a few times leading
1062 * to excessive detection delay.
1063 *
1064 * As these firmwares respond to the second reset try
1065 * with invalid device signature, considering unknown
1066 * sig as offline works around the problem acceptably.
1067 */
1068 {
1069 .ident = "EP45-DQ6",
1070 .matches = {
1071 DMI_MATCH(DMI_BOARD_VENDOR,
1072 "Gigabyte Technology Co., Ltd."),
1073 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1074 },
1075 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1076 },
1077 {
1078 .ident = "EP45-DS5",
1079 .matches = {
1080 DMI_MATCH(DMI_BOARD_VENDOR,
1081 "Gigabyte Technology Co., Ltd."),
1082 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1083 },
1084 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1085 },
1086 { } /* terminate list */
1087 };
1088 #undef ENCODE_BUSDEVFN
1089 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1090 unsigned int val;
1091
1092 if (!dmi)
1093 return false;
1094
1095 val = (unsigned long)dmi->driver_data;
1096
1097 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1098 }
1099
1100 #ifdef CONFIG_ATA_ACPI
1101 static void ahci_gtf_filter_workaround(struct ata_host *host)
1102 {
1103 static const struct dmi_system_id sysids[] = {
1104 /*
1105 * Aspire 3810T issues a bunch of SATA enable commands
1106 * via _GTF including an invalid one and one which is
1107 * rejected by the device. Among the successful ones
1108 * is FPDMA non-zero offset enable which when enabled
1109 * only on the drive side leads to NCQ command
1110 * failures. Filter it out.
1111 */
1112 {
1113 .ident = "Aspire 3810T",
1114 .matches = {
1115 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1116 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1117 },
1118 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1119 },
1120 { }
1121 };
1122 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1123 unsigned int filter;
1124 int i;
1125
1126 if (!dmi)
1127 return;
1128
1129 filter = (unsigned long)dmi->driver_data;
1130 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1131 filter, dmi->ident);
1132
1133 for (i = 0; i < host->n_ports; i++) {
1134 struct ata_port *ap = host->ports[i];
1135 struct ata_link *link;
1136 struct ata_device *dev;
1137
1138 ata_for_each_link(link, ap, EDGE)
1139 ata_for_each_dev(dev, link, ALL)
1140 dev->gtf_filter |= filter;
1141 }
1142 }
1143 #else
1144 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1145 {}
1146 #endif
1147
1148 int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1149 {
1150 int rc;
1151 unsigned int maxvec;
1152
1153 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1154 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1155 if (rc > 0) {
1156 if ((rc == maxvec) || (rc == 1))
1157 return rc;
1158 /*
1159 * Assume that advantage of multipe MSIs is negated,
1160 * so fallback to single MSI mode to save resources
1161 */
1162 pci_disable_msi(pdev);
1163 if (!pci_enable_msi(pdev))
1164 return 1;
1165 }
1166 }
1167
1168 pci_intx(pdev, 1);
1169 return 0;
1170 }
1171
1172 /**
1173 * ahci_host_activate - start AHCI host, request IRQs and register it
1174 * @host: target ATA host
1175 * @irq: base IRQ number to request
1176 * @n_msis: number of MSIs allocated for this host
1177 * @irq_handler: irq_handler used when requesting IRQs
1178 * @irq_flags: irq_flags used when requesting IRQs
1179 *
1180 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1181 * when multiple MSIs were allocated. That is one MSI per port, starting
1182 * from @irq.
1183 *
1184 * LOCKING:
1185 * Inherited from calling layer (may sleep).
1186 *
1187 * RETURNS:
1188 * 0 on success, -errno otherwise.
1189 */
1190 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1191 {
1192 int i, rc;
1193
1194 /* Sharing Last Message among several ports is not supported */
1195 if (n_msis < host->n_ports)
1196 return -EINVAL;
1197
1198 rc = ata_host_start(host);
1199 if (rc)
1200 return rc;
1201
1202 for (i = 0; i < host->n_ports; i++) {
1203 rc = devm_request_threaded_irq(host->dev,
1204 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1205 dev_driver_string(host->dev), host->ports[i]);
1206 if (rc)
1207 goto out_free_irqs;
1208 }
1209
1210 for (i = 0; i < host->n_ports; i++)
1211 ata_port_desc(host->ports[i], "irq %d", irq + i);
1212
1213 rc = ata_host_register(host, &ahci_sht);
1214 if (rc)
1215 goto out_free_all_irqs;
1216
1217 return 0;
1218
1219 out_free_all_irqs:
1220 i = host->n_ports;
1221 out_free_irqs:
1222 for (i--; i >= 0; i--)
1223 devm_free_irq(host->dev, irq + i, host->ports[i]);
1224
1225 return rc;
1226 }
1227
1228 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1229 {
1230 unsigned int board_id = ent->driver_data;
1231 struct ata_port_info pi = ahci_port_info[board_id];
1232 const struct ata_port_info *ppi[] = { &pi, NULL };
1233 struct device *dev = &pdev->dev;
1234 struct ahci_host_priv *hpriv;
1235 struct ata_host *host;
1236 int n_ports, n_msis, i, rc;
1237 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1238
1239 VPRINTK("ENTER\n");
1240
1241 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1242
1243 ata_print_version_once(&pdev->dev, DRV_VERSION);
1244
1245 /* The AHCI driver can only drive the SATA ports, the PATA driver
1246 can drive them all so if both drivers are selected make sure
1247 AHCI stays out of the way */
1248 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1249 return -ENODEV;
1250
1251 /*
1252 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1253 * ahci, use ata_generic instead.
1254 */
1255 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1256 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1257 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1258 pdev->subsystem_device == 0xcb89)
1259 return -ENODEV;
1260
1261 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1262 * At the moment, we can only use the AHCI mode. Let the users know
1263 * that for SAS drives they're out of luck.
1264 */
1265 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1266 dev_info(&pdev->dev,
1267 "PDC42819 can only drive SATA devices with this driver\n");
1268
1269 /* Both Connext and Enmotus devices use non-standard BARs */
1270 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1271 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1272 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1273 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1274
1275 /* acquire resources */
1276 rc = pcim_enable_device(pdev);
1277 if (rc)
1278 return rc;
1279
1280 /* AHCI controllers often implement SFF compatible interface.
1281 * Grab all PCI BARs just in case.
1282 */
1283 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1284 if (rc == -EBUSY)
1285 pcim_pin_device(pdev);
1286 if (rc)
1287 return rc;
1288
1289 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1290 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1291 u8 map;
1292
1293 /* ICH6s share the same PCI ID for both piix and ahci
1294 * modes. Enabling ahci mode while MAP indicates
1295 * combined mode is a bad idea. Yield to ata_piix.
1296 */
1297 pci_read_config_byte(pdev, ICH_MAP, &map);
1298 if (map & 0x3) {
1299 dev_info(&pdev->dev,
1300 "controller is in combined mode, can't enable AHCI mode\n");
1301 return -ENODEV;
1302 }
1303 }
1304
1305 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1306 if (!hpriv)
1307 return -ENOMEM;
1308 hpriv->flags |= (unsigned long)pi.private_data;
1309
1310 /* MCP65 revision A1 and A2 can't do MSI */
1311 if (board_id == board_ahci_mcp65 &&
1312 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1313 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1314
1315 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1316 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1317 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1318
1319 /* only some SB600s can do 64bit DMA */
1320 if (ahci_sb600_enable_64bit(pdev))
1321 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1322
1323 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1324
1325 n_msis = ahci_init_interrupts(pdev, hpriv);
1326 if (n_msis > 1)
1327 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1328
1329 /* save initial config */
1330 ahci_pci_save_initial_config(pdev, hpriv);
1331
1332 /* prepare host */
1333 if (hpriv->cap & HOST_CAP_NCQ) {
1334 pi.flags |= ATA_FLAG_NCQ;
1335 /*
1336 * Auto-activate optimization is supposed to be
1337 * supported on all AHCI controllers indicating NCQ
1338 * capability, but it seems to be broken on some
1339 * chipsets including NVIDIAs.
1340 */
1341 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1342 pi.flags |= ATA_FLAG_FPDMA_AA;
1343 }
1344
1345 if (hpriv->cap & HOST_CAP_PMP)
1346 pi.flags |= ATA_FLAG_PMP;
1347
1348 ahci_set_em_messages(hpriv, &pi);
1349
1350 if (ahci_broken_system_poweroff(pdev)) {
1351 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1352 dev_info(&pdev->dev,
1353 "quirky BIOS, skipping spindown on poweroff\n");
1354 }
1355
1356 if (ahci_broken_suspend(pdev)) {
1357 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1358 dev_warn(&pdev->dev,
1359 "BIOS update required for suspend/resume\n");
1360 }
1361
1362 if (ahci_broken_online(pdev)) {
1363 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1364 dev_info(&pdev->dev,
1365 "online status unreliable, applying workaround\n");
1366 }
1367
1368 /* CAP.NP sometimes indicate the index of the last enabled
1369 * port, at other times, that of the last possible port, so
1370 * determining the maximum port number requires looking at
1371 * both CAP.NP and port_map.
1372 */
1373 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1374
1375 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1376 if (!host)
1377 return -ENOMEM;
1378 host->private_data = hpriv;
1379
1380 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1381 host->flags |= ATA_HOST_PARALLEL_SCAN;
1382 else
1383 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1384
1385 if (pi.flags & ATA_FLAG_EM)
1386 ahci_reset_em(host);
1387
1388 for (i = 0; i < host->n_ports; i++) {
1389 struct ata_port *ap = host->ports[i];
1390
1391 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1392 ata_port_pbar_desc(ap, ahci_pci_bar,
1393 0x100 + ap->port_no * 0x80, "port");
1394
1395 /* set enclosure management message type */
1396 if (ap->flags & ATA_FLAG_EM)
1397 ap->em_message_type = hpriv->em_msg_type;
1398
1399
1400 /* disabled/not-implemented port */
1401 if (!(hpriv->port_map & (1 << i)))
1402 ap->ops = &ata_dummy_port_ops;
1403 }
1404
1405 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1406 ahci_p5wdh_workaround(host);
1407
1408 /* apply gtf filter quirk */
1409 ahci_gtf_filter_workaround(host);
1410
1411 /* initialize adapter */
1412 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1413 if (rc)
1414 return rc;
1415
1416 rc = ahci_pci_reset_controller(host);
1417 if (rc)
1418 return rc;
1419
1420 ahci_pci_init_controller(host);
1421 ahci_pci_print_info(host);
1422
1423 pci_set_master(pdev);
1424
1425 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1426 return ahci_host_activate(host, pdev->irq, n_msis);
1427
1428 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1429 &ahci_sht);
1430 }
1431
1432 module_pci_driver(ahci_pci_driver);
1433
1434 MODULE_AUTHOR("Jeff Garzik");
1435 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1436 MODULE_LICENSE("GPL");
1437 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1438 MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)