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libata: fix sff host state machine locking while polling
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / ata / ahci.c
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
58 };
59
60 enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nomsi,
65 board_ahci_noncq,
66 board_ahci_nosntf,
67 board_ahci_yes_fbs,
68
69 /* board IDs for specific chipsets in alphabetical order */
70 board_ahci_mcp65,
71 board_ahci_mcp77,
72 board_ahci_mcp89,
73 board_ahci_mv,
74 board_ahci_sb600,
75 board_ahci_sb700, /* for SB700 and SB800 */
76 board_ahci_vt8251,
77
78 /* aliases */
79 board_ahci_mcp_linux = board_ahci_mcp65,
80 board_ahci_mcp67 = board_ahci_mcp65,
81 board_ahci_mcp73 = board_ahci_mcp65,
82 board_ahci_mcp79 = board_ahci_mcp77,
83 };
84
85 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
86 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
89 unsigned long deadline);
90 #ifdef CONFIG_PM
91 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
92 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 #endif
94
95 static struct scsi_host_template ahci_sht = {
96 AHCI_SHT("ahci"),
97 };
98
99 static struct ata_port_operations ahci_vt8251_ops = {
100 .inherits = &ahci_ops,
101 .hardreset = ahci_vt8251_hardreset,
102 };
103
104 static struct ata_port_operations ahci_p5wdh_ops = {
105 .inherits = &ahci_ops,
106 .hardreset = ahci_p5wdh_hardreset,
107 };
108
109 static const struct ata_port_info ahci_port_info[] = {
110 /* by features */
111 [board_ahci] = {
112 .flags = AHCI_FLAG_COMMON,
113 .pio_mask = ATA_PIO4,
114 .udma_mask = ATA_UDMA6,
115 .port_ops = &ahci_ops,
116 },
117 [board_ahci_ign_iferr] = {
118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_nomsi] = {
125 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
126 .flags = AHCI_FLAG_COMMON,
127 .pio_mask = ATA_PIO4,
128 .udma_mask = ATA_UDMA6,
129 .port_ops = &ahci_ops,
130 },
131 [board_ahci_noncq] = {
132 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
133 .flags = AHCI_FLAG_COMMON,
134 .pio_mask = ATA_PIO4,
135 .udma_mask = ATA_UDMA6,
136 .port_ops = &ahci_ops,
137 },
138 [board_ahci_nosntf] = {
139 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
140 .flags = AHCI_FLAG_COMMON,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
145 [board_ahci_yes_fbs] = {
146 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
152 /* by chipsets */
153 [board_ahci_mcp65] = {
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
155 AHCI_HFLAG_YES_NCQ),
156 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
157 .pio_mask = ATA_PIO4,
158 .udma_mask = ATA_UDMA6,
159 .port_ops = &ahci_ops,
160 },
161 [board_ahci_mcp77] = {
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
167 },
168 [board_ahci_mcp89] = {
169 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
170 .flags = AHCI_FLAG_COMMON,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
174 },
175 [board_ahci_mv] = {
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_ops,
182 },
183 [board_ahci_sb600] = {
184 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
185 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
186 AHCI_HFLAG_32BIT_ONLY),
187 .flags = AHCI_FLAG_COMMON,
188 .pio_mask = ATA_PIO4,
189 .udma_mask = ATA_UDMA6,
190 .port_ops = &ahci_pmp_retry_srst_ops,
191 },
192 [board_ahci_sb700] = { /* for SB700 and SB800 */
193 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
194 .flags = AHCI_FLAG_COMMON,
195 .pio_mask = ATA_PIO4,
196 .udma_mask = ATA_UDMA6,
197 .port_ops = &ahci_pmp_retry_srst_ops,
198 },
199 [board_ahci_vt8251] = {
200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
201 .flags = AHCI_FLAG_COMMON,
202 .pio_mask = ATA_PIO4,
203 .udma_mask = ATA_UDMA6,
204 .port_ops = &ahci_vt8251_ops,
205 },
206 };
207
208 static const struct pci_device_id ahci_pci_tbl[] = {
209 /* Intel */
210 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
211 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
212 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
213 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
214 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
215 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
216 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
217 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
218 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
219 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
220 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
221 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
222 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
223 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
224 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
225 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
228 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
229 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
233 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
236 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
238 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
239 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
240 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
241 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
242 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
243 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
245 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
248 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
250 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
251 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
252 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
253 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
254 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
255 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
256 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
257 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
258 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
259 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
260 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
261 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
262 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
263 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
264 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
265 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
266 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
267 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
268 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
269 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
270 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
271 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
272 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
273 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
274 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
275 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
276 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
277 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
278 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
279 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
280 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
281 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
282 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
283 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
284 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
285 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
286 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
287 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
288 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
289 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
290 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
291 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
292 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
293 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
294 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
295 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
296 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
297 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
298 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
299 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
300 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
301 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
302 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
303 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
304 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
305 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
306 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
307 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
308 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
309 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
310 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
311 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
312 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
313 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
314 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
315 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
316 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
317 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
318 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
319 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
320 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
321 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
322 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
323 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
324 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
325 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
326 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
327 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
328 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
329 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
330 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
331 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
332 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
333 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
334 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
335 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
336 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
337 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
338 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
339 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
340 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
341 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
342 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
343 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
344 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
345 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
346 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
347 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H RAID */
348 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
349 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
350 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
351
352 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
353 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
354 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
355 /* JMicron 362B and 362C have an AHCI function with IDE class code */
356 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
357 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
358
359 /* ATI */
360 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
361 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
362 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
363 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
364 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
365 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
366 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
367
368 /* AMD */
369 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
370 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
371 /* AMD is using RAID class only for ahci controllers */
372 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
373 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
374
375 /* VIA */
376 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
377 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
378
379 /* NVIDIA */
380 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
381 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
382 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
383 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
384 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
385 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
386 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
387 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
388 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
389 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
390 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
391 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
392 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
393 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
394 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
395 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
396 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
397 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
398 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
399 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
400 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
401 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
402 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
403 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
404 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
405 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
406 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
407 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
408 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
409 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
410 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
411 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
412 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
413 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
414 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
415 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
416 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
417 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
418 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
419 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
420 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
421 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
422 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
423 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
424 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
425 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
426 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
427 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
428 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
429 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
430 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
431 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
432 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
433 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
434 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
435 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
436 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
437 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
438 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
439 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
440 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
441 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
442 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
443 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
444 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
445 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
446 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
447 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
448 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
449 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
450 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
451 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
452 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
453 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
454 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
455 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
456 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
457 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
458 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
459 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
460 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
461 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
462 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
463 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
464
465 /* SiS */
466 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
467 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
468 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
469
470 /* ST Microelectronics */
471 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
472
473 /* Marvell */
474 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
475 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
476 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
477 .class = PCI_CLASS_STORAGE_SATA_AHCI,
478 .class_mask = 0xffffff,
479 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
480 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
481 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
482 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
483 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
484 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
485 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
486 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
487 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
488 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
489 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
490 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
491 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
492 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
493 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
494 .driver_data = board_ahci_yes_fbs },
495 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
496 .driver_data = board_ahci_yes_fbs },
497 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
498 .driver_data = board_ahci_yes_fbs },
499 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
500 .driver_data = board_ahci_yes_fbs },
501
502 /* Promise */
503 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
504 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
505
506 /* Asmedia */
507 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
508 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
509 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
510 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
511
512 /*
513 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
514 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
515 */
516 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
517 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
518
519 /* Enmotus */
520 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
521
522 /* Generic, PCI class code for AHCI */
523 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
524 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
525
526 { } /* terminate list */
527 };
528
529
530 static struct pci_driver ahci_pci_driver = {
531 .name = DRV_NAME,
532 .id_table = ahci_pci_tbl,
533 .probe = ahci_init_one,
534 .remove = ata_pci_remove_one,
535 #ifdef CONFIG_PM
536 .suspend = ahci_pci_device_suspend,
537 .resume = ahci_pci_device_resume,
538 #endif
539 };
540
541 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
542 static int marvell_enable;
543 #else
544 static int marvell_enable = 1;
545 #endif
546 module_param(marvell_enable, int, 0644);
547 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
548
549
550 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
551 struct ahci_host_priv *hpriv)
552 {
553 unsigned int force_port_map = 0;
554 unsigned int mask_port_map = 0;
555
556 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
557 dev_info(&pdev->dev, "JMB361 has only one port\n");
558 force_port_map = 1;
559 }
560
561 /*
562 * Temporary Marvell 6145 hack: PATA port presence
563 * is asserted through the standard AHCI port
564 * presence register, as bit 4 (counting from 0)
565 */
566 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
567 if (pdev->device == 0x6121)
568 mask_port_map = 0x3;
569 else
570 mask_port_map = 0xf;
571 dev_info(&pdev->dev,
572 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
573 }
574
575 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
576 mask_port_map);
577 }
578
579 static int ahci_pci_reset_controller(struct ata_host *host)
580 {
581 struct pci_dev *pdev = to_pci_dev(host->dev);
582
583 ahci_reset_controller(host);
584
585 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
586 struct ahci_host_priv *hpriv = host->private_data;
587 u16 tmp16;
588
589 /* configure PCS */
590 pci_read_config_word(pdev, 0x92, &tmp16);
591 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
592 tmp16 |= hpriv->port_map;
593 pci_write_config_word(pdev, 0x92, tmp16);
594 }
595 }
596
597 return 0;
598 }
599
600 static void ahci_pci_init_controller(struct ata_host *host)
601 {
602 struct ahci_host_priv *hpriv = host->private_data;
603 struct pci_dev *pdev = to_pci_dev(host->dev);
604 void __iomem *port_mmio;
605 u32 tmp;
606 int mv;
607
608 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
609 if (pdev->device == 0x6121)
610 mv = 2;
611 else
612 mv = 4;
613 port_mmio = __ahci_port_base(host, mv);
614
615 writel(0, port_mmio + PORT_IRQ_MASK);
616
617 /* clear port IRQ */
618 tmp = readl(port_mmio + PORT_IRQ_STAT);
619 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
620 if (tmp)
621 writel(tmp, port_mmio + PORT_IRQ_STAT);
622 }
623
624 ahci_init_controller(host);
625 }
626
627 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
628 unsigned long deadline)
629 {
630 struct ata_port *ap = link->ap;
631 bool online;
632 int rc;
633
634 DPRINTK("ENTER\n");
635
636 ahci_stop_engine(ap);
637
638 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
639 deadline, &online, NULL);
640
641 ahci_start_engine(ap);
642
643 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
644
645 /* vt8251 doesn't clear BSY on signature FIS reception,
646 * request follow-up softreset.
647 */
648 return online ? -EAGAIN : rc;
649 }
650
651 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
652 unsigned long deadline)
653 {
654 struct ata_port *ap = link->ap;
655 struct ahci_port_priv *pp = ap->private_data;
656 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
657 struct ata_taskfile tf;
658 bool online;
659 int rc;
660
661 ahci_stop_engine(ap);
662
663 /* clear D2H reception area to properly wait for D2H FIS */
664 ata_tf_init(link->device, &tf);
665 tf.command = 0x80;
666 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
667
668 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
669 deadline, &online, NULL);
670
671 ahci_start_engine(ap);
672
673 /* The pseudo configuration device on SIMG4726 attached to
674 * ASUS P5W-DH Deluxe doesn't send signature FIS after
675 * hardreset if no device is attached to the first downstream
676 * port && the pseudo device locks up on SRST w/ PMP==0. To
677 * work around this, wait for !BSY only briefly. If BSY isn't
678 * cleared, perform CLO and proceed to IDENTIFY (achieved by
679 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
680 *
681 * Wait for two seconds. Devices attached to downstream port
682 * which can't process the following IDENTIFY after this will
683 * have to be reset again. For most cases, this should
684 * suffice while making probing snappish enough.
685 */
686 if (online) {
687 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
688 ahci_check_ready);
689 if (rc)
690 ahci_kick_engine(ap);
691 }
692 return rc;
693 }
694
695 #ifdef CONFIG_PM
696 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
697 {
698 struct ata_host *host = dev_get_drvdata(&pdev->dev);
699 struct ahci_host_priv *hpriv = host->private_data;
700 void __iomem *mmio = hpriv->mmio;
701 u32 ctl;
702
703 if (mesg.event & PM_EVENT_SUSPEND &&
704 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
705 dev_err(&pdev->dev,
706 "BIOS update required for suspend/resume\n");
707 return -EIO;
708 }
709
710 if (mesg.event & PM_EVENT_SLEEP) {
711 /* AHCI spec rev1.1 section 8.3.3:
712 * Software must disable interrupts prior to requesting a
713 * transition of the HBA to D3 state.
714 */
715 ctl = readl(mmio + HOST_CTL);
716 ctl &= ~HOST_IRQ_EN;
717 writel(ctl, mmio + HOST_CTL);
718 readl(mmio + HOST_CTL); /* flush */
719 }
720
721 return ata_pci_device_suspend(pdev, mesg);
722 }
723
724 static int ahci_pci_device_resume(struct pci_dev *pdev)
725 {
726 struct ata_host *host = dev_get_drvdata(&pdev->dev);
727 int rc;
728
729 rc = ata_pci_device_do_resume(pdev);
730 if (rc)
731 return rc;
732
733 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
734 rc = ahci_pci_reset_controller(host);
735 if (rc)
736 return rc;
737
738 ahci_pci_init_controller(host);
739 }
740
741 ata_host_resume(host);
742
743 return 0;
744 }
745 #endif
746
747 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
748 {
749 int rc;
750
751 /*
752 * If the device fixup already set the dma_mask to some non-standard
753 * value, don't extend it here. This happens on STA2X11, for example.
754 */
755 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
756 return 0;
757
758 if (using_dac &&
759 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
760 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
761 if (rc) {
762 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
763 if (rc) {
764 dev_err(&pdev->dev,
765 "64-bit DMA enable failed\n");
766 return rc;
767 }
768 }
769 } else {
770 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
771 if (rc) {
772 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
773 return rc;
774 }
775 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
776 if (rc) {
777 dev_err(&pdev->dev,
778 "32-bit consistent DMA enable failed\n");
779 return rc;
780 }
781 }
782 return 0;
783 }
784
785 static void ahci_pci_print_info(struct ata_host *host)
786 {
787 struct pci_dev *pdev = to_pci_dev(host->dev);
788 u16 cc;
789 const char *scc_s;
790
791 pci_read_config_word(pdev, 0x0a, &cc);
792 if (cc == PCI_CLASS_STORAGE_IDE)
793 scc_s = "IDE";
794 else if (cc == PCI_CLASS_STORAGE_SATA)
795 scc_s = "SATA";
796 else if (cc == PCI_CLASS_STORAGE_RAID)
797 scc_s = "RAID";
798 else
799 scc_s = "unknown";
800
801 ahci_print_info(host, scc_s);
802 }
803
804 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
805 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
806 * support PMP and the 4726 either directly exports the device
807 * attached to the first downstream port or acts as a hardware storage
808 * controller and emulate a single ATA device (can be RAID 0/1 or some
809 * other configuration).
810 *
811 * When there's no device attached to the first downstream port of the
812 * 4726, "Config Disk" appears, which is a pseudo ATA device to
813 * configure the 4726. However, ATA emulation of the device is very
814 * lame. It doesn't send signature D2H Reg FIS after the initial
815 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
816 *
817 * The following function works around the problem by always using
818 * hardreset on the port and not depending on receiving signature FIS
819 * afterward. If signature FIS isn't received soon, ATA class is
820 * assumed without follow-up softreset.
821 */
822 static void ahci_p5wdh_workaround(struct ata_host *host)
823 {
824 static struct dmi_system_id sysids[] = {
825 {
826 .ident = "P5W DH Deluxe",
827 .matches = {
828 DMI_MATCH(DMI_SYS_VENDOR,
829 "ASUSTEK COMPUTER INC"),
830 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
831 },
832 },
833 { }
834 };
835 struct pci_dev *pdev = to_pci_dev(host->dev);
836
837 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
838 dmi_check_system(sysids)) {
839 struct ata_port *ap = host->ports[1];
840
841 dev_info(&pdev->dev,
842 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
843
844 ap->ops = &ahci_p5wdh_ops;
845 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
846 }
847 }
848
849 /* only some SB600 ahci controllers can do 64bit DMA */
850 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
851 {
852 static const struct dmi_system_id sysids[] = {
853 /*
854 * The oldest version known to be broken is 0901 and
855 * working is 1501 which was released on 2007-10-26.
856 * Enable 64bit DMA on 1501 and anything newer.
857 *
858 * Please read bko#9412 for more info.
859 */
860 {
861 .ident = "ASUS M2A-VM",
862 .matches = {
863 DMI_MATCH(DMI_BOARD_VENDOR,
864 "ASUSTeK Computer INC."),
865 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
866 },
867 .driver_data = "20071026", /* yyyymmdd */
868 },
869 /*
870 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
871 * support 64bit DMA.
872 *
873 * BIOS versions earlier than 1.5 had the Manufacturer DMI
874 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
875 * This spelling mistake was fixed in BIOS version 1.5, so
876 * 1.5 and later have the Manufacturer as
877 * "MICRO-STAR INTERNATIONAL CO.,LTD".
878 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
879 *
880 * BIOS versions earlier than 1.9 had a Board Product Name
881 * DMI field of "MS-7376". This was changed to be
882 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
883 * match on DMI_BOARD_NAME of "MS-7376".
884 */
885 {
886 .ident = "MSI K9A2 Platinum",
887 .matches = {
888 DMI_MATCH(DMI_BOARD_VENDOR,
889 "MICRO-STAR INTER"),
890 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
891 },
892 },
893 /*
894 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
895 * 64bit DMA.
896 *
897 * This board also had the typo mentioned above in the
898 * Manufacturer DMI field (fixed in BIOS version 1.5), so
899 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
900 */
901 {
902 .ident = "MSI K9AGM2",
903 .matches = {
904 DMI_MATCH(DMI_BOARD_VENDOR,
905 "MICRO-STAR INTER"),
906 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
907 },
908 },
909 /*
910 * All BIOS versions for the Asus M3A support 64bit DMA.
911 * (all release versions from 0301 to 1206 were tested)
912 */
913 {
914 .ident = "ASUS M3A",
915 .matches = {
916 DMI_MATCH(DMI_BOARD_VENDOR,
917 "ASUSTeK Computer INC."),
918 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
919 },
920 },
921 { }
922 };
923 const struct dmi_system_id *match;
924 int year, month, date;
925 char buf[9];
926
927 match = dmi_first_match(sysids);
928 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
929 !match)
930 return false;
931
932 if (!match->driver_data)
933 goto enable_64bit;
934
935 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
936 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
937
938 if (strcmp(buf, match->driver_data) >= 0)
939 goto enable_64bit;
940 else {
941 dev_warn(&pdev->dev,
942 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
943 match->ident);
944 return false;
945 }
946
947 enable_64bit:
948 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
949 return true;
950 }
951
952 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
953 {
954 static const struct dmi_system_id broken_systems[] = {
955 {
956 .ident = "HP Compaq nx6310",
957 .matches = {
958 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
959 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
960 },
961 /* PCI slot number of the controller */
962 .driver_data = (void *)0x1FUL,
963 },
964 {
965 .ident = "HP Compaq 6720s",
966 .matches = {
967 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
968 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
969 },
970 /* PCI slot number of the controller */
971 .driver_data = (void *)0x1FUL,
972 },
973
974 { } /* terminate list */
975 };
976 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
977
978 if (dmi) {
979 unsigned long slot = (unsigned long)dmi->driver_data;
980 /* apply the quirk only to on-board controllers */
981 return slot == PCI_SLOT(pdev->devfn);
982 }
983
984 return false;
985 }
986
987 static bool ahci_broken_suspend(struct pci_dev *pdev)
988 {
989 static const struct dmi_system_id sysids[] = {
990 /*
991 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
992 * to the harddisk doesn't become online after
993 * resuming from STR. Warn and fail suspend.
994 *
995 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
996 *
997 * Use dates instead of versions to match as HP is
998 * apparently recycling both product and version
999 * strings.
1000 *
1001 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1002 */
1003 {
1004 .ident = "dv4",
1005 .matches = {
1006 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1007 DMI_MATCH(DMI_PRODUCT_NAME,
1008 "HP Pavilion dv4 Notebook PC"),
1009 },
1010 .driver_data = "20090105", /* F.30 */
1011 },
1012 {
1013 .ident = "dv5",
1014 .matches = {
1015 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1016 DMI_MATCH(DMI_PRODUCT_NAME,
1017 "HP Pavilion dv5 Notebook PC"),
1018 },
1019 .driver_data = "20090506", /* F.16 */
1020 },
1021 {
1022 .ident = "dv6",
1023 .matches = {
1024 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1025 DMI_MATCH(DMI_PRODUCT_NAME,
1026 "HP Pavilion dv6 Notebook PC"),
1027 },
1028 .driver_data = "20090423", /* F.21 */
1029 },
1030 {
1031 .ident = "HDX18",
1032 .matches = {
1033 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1034 DMI_MATCH(DMI_PRODUCT_NAME,
1035 "HP HDX18 Notebook PC"),
1036 },
1037 .driver_data = "20090430", /* F.23 */
1038 },
1039 /*
1040 * Acer eMachines G725 has the same problem. BIOS
1041 * V1.03 is known to be broken. V3.04 is known to
1042 * work. Between, there are V1.06, V2.06 and V3.03
1043 * that we don't have much idea about. For now,
1044 * blacklist anything older than V3.04.
1045 *
1046 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1047 */
1048 {
1049 .ident = "G725",
1050 .matches = {
1051 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1052 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1053 },
1054 .driver_data = "20091216", /* V3.04 */
1055 },
1056 { } /* terminate list */
1057 };
1058 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1059 int year, month, date;
1060 char buf[9];
1061
1062 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1063 return false;
1064
1065 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1066 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1067
1068 return strcmp(buf, dmi->driver_data) < 0;
1069 }
1070
1071 static bool ahci_broken_online(struct pci_dev *pdev)
1072 {
1073 #define ENCODE_BUSDEVFN(bus, slot, func) \
1074 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1075 static const struct dmi_system_id sysids[] = {
1076 /*
1077 * There are several gigabyte boards which use
1078 * SIMG5723s configured as hardware RAID. Certain
1079 * 5723 firmware revisions shipped there keep the link
1080 * online but fail to answer properly to SRST or
1081 * IDENTIFY when no device is attached downstream
1082 * causing libata to retry quite a few times leading
1083 * to excessive detection delay.
1084 *
1085 * As these firmwares respond to the second reset try
1086 * with invalid device signature, considering unknown
1087 * sig as offline works around the problem acceptably.
1088 */
1089 {
1090 .ident = "EP45-DQ6",
1091 .matches = {
1092 DMI_MATCH(DMI_BOARD_VENDOR,
1093 "Gigabyte Technology Co., Ltd."),
1094 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1095 },
1096 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1097 },
1098 {
1099 .ident = "EP45-DS5",
1100 .matches = {
1101 DMI_MATCH(DMI_BOARD_VENDOR,
1102 "Gigabyte Technology Co., Ltd."),
1103 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1104 },
1105 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1106 },
1107 { } /* terminate list */
1108 };
1109 #undef ENCODE_BUSDEVFN
1110 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1111 unsigned int val;
1112
1113 if (!dmi)
1114 return false;
1115
1116 val = (unsigned long)dmi->driver_data;
1117
1118 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1119 }
1120
1121 #ifdef CONFIG_ATA_ACPI
1122 static void ahci_gtf_filter_workaround(struct ata_host *host)
1123 {
1124 static const struct dmi_system_id sysids[] = {
1125 /*
1126 * Aspire 3810T issues a bunch of SATA enable commands
1127 * via _GTF including an invalid one and one which is
1128 * rejected by the device. Among the successful ones
1129 * is FPDMA non-zero offset enable which when enabled
1130 * only on the drive side leads to NCQ command
1131 * failures. Filter it out.
1132 */
1133 {
1134 .ident = "Aspire 3810T",
1135 .matches = {
1136 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1137 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1138 },
1139 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1140 },
1141 { }
1142 };
1143 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1144 unsigned int filter;
1145 int i;
1146
1147 if (!dmi)
1148 return;
1149
1150 filter = (unsigned long)dmi->driver_data;
1151 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1152 filter, dmi->ident);
1153
1154 for (i = 0; i < host->n_ports; i++) {
1155 struct ata_port *ap = host->ports[i];
1156 struct ata_link *link;
1157 struct ata_device *dev;
1158
1159 ata_for_each_link(link, ap, EDGE)
1160 ata_for_each_dev(dev, link, ALL)
1161 dev->gtf_filter |= filter;
1162 }
1163 }
1164 #else
1165 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1166 {}
1167 #endif
1168
1169 int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1170 {
1171 int rc;
1172 unsigned int maxvec;
1173
1174 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1175 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1176 if (rc > 0) {
1177 if ((rc == maxvec) || (rc == 1))
1178 return rc;
1179 /*
1180 * Assume that advantage of multipe MSIs is negated,
1181 * so fallback to single MSI mode to save resources
1182 */
1183 pci_disable_msi(pdev);
1184 if (!pci_enable_msi(pdev))
1185 return 1;
1186 }
1187 }
1188
1189 pci_intx(pdev, 1);
1190 return 0;
1191 }
1192
1193 /**
1194 * ahci_host_activate - start AHCI host, request IRQs and register it
1195 * @host: target ATA host
1196 * @irq: base IRQ number to request
1197 * @n_msis: number of MSIs allocated for this host
1198 * @irq_handler: irq_handler used when requesting IRQs
1199 * @irq_flags: irq_flags used when requesting IRQs
1200 *
1201 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1202 * when multiple MSIs were allocated. That is one MSI per port, starting
1203 * from @irq.
1204 *
1205 * LOCKING:
1206 * Inherited from calling layer (may sleep).
1207 *
1208 * RETURNS:
1209 * 0 on success, -errno otherwise.
1210 */
1211 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1212 {
1213 int i, rc;
1214
1215 /* Sharing Last Message among several ports is not supported */
1216 if (n_msis < host->n_ports)
1217 return -EINVAL;
1218
1219 rc = ata_host_start(host);
1220 if (rc)
1221 return rc;
1222
1223 for (i = 0; i < host->n_ports; i++) {
1224 rc = devm_request_threaded_irq(host->dev,
1225 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1226 dev_driver_string(host->dev), host->ports[i]);
1227 if (rc)
1228 goto out_free_irqs;
1229 }
1230
1231 for (i = 0; i < host->n_ports; i++)
1232 ata_port_desc(host->ports[i], "irq %d", irq + i);
1233
1234 rc = ata_host_register(host, &ahci_sht);
1235 if (rc)
1236 goto out_free_all_irqs;
1237
1238 return 0;
1239
1240 out_free_all_irqs:
1241 i = host->n_ports;
1242 out_free_irqs:
1243 for (i--; i >= 0; i--)
1244 devm_free_irq(host->dev, irq + i, host->ports[i]);
1245
1246 return rc;
1247 }
1248
1249 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1250 {
1251 unsigned int board_id = ent->driver_data;
1252 struct ata_port_info pi = ahci_port_info[board_id];
1253 const struct ata_port_info *ppi[] = { &pi, NULL };
1254 struct device *dev = &pdev->dev;
1255 struct ahci_host_priv *hpriv;
1256 struct ata_host *host;
1257 int n_ports, n_msis, i, rc;
1258 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1259
1260 VPRINTK("ENTER\n");
1261
1262 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1263
1264 ata_print_version_once(&pdev->dev, DRV_VERSION);
1265
1266 /* The AHCI driver can only drive the SATA ports, the PATA driver
1267 can drive them all so if both drivers are selected make sure
1268 AHCI stays out of the way */
1269 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1270 return -ENODEV;
1271
1272 /*
1273 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1274 * ahci, use ata_generic instead.
1275 */
1276 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1277 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1278 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1279 pdev->subsystem_device == 0xcb89)
1280 return -ENODEV;
1281
1282 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1283 * At the moment, we can only use the AHCI mode. Let the users know
1284 * that for SAS drives they're out of luck.
1285 */
1286 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1287 dev_info(&pdev->dev,
1288 "PDC42819 can only drive SATA devices with this driver\n");
1289
1290 /* Both Connext and Enmotus devices use non-standard BARs */
1291 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1292 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1293 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1294 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1295
1296 /* acquire resources */
1297 rc = pcim_enable_device(pdev);
1298 if (rc)
1299 return rc;
1300
1301 /* AHCI controllers often implement SFF compatible interface.
1302 * Grab all PCI BARs just in case.
1303 */
1304 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1305 if (rc == -EBUSY)
1306 pcim_pin_device(pdev);
1307 if (rc)
1308 return rc;
1309
1310 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1311 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1312 u8 map;
1313
1314 /* ICH6s share the same PCI ID for both piix and ahci
1315 * modes. Enabling ahci mode while MAP indicates
1316 * combined mode is a bad idea. Yield to ata_piix.
1317 */
1318 pci_read_config_byte(pdev, ICH_MAP, &map);
1319 if (map & 0x3) {
1320 dev_info(&pdev->dev,
1321 "controller is in combined mode, can't enable AHCI mode\n");
1322 return -ENODEV;
1323 }
1324 }
1325
1326 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1327 if (!hpriv)
1328 return -ENOMEM;
1329 hpriv->flags |= (unsigned long)pi.private_data;
1330
1331 /* MCP65 revision A1 and A2 can't do MSI */
1332 if (board_id == board_ahci_mcp65 &&
1333 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1334 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1335
1336 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1337 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1338 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1339
1340 /* only some SB600s can do 64bit DMA */
1341 if (ahci_sb600_enable_64bit(pdev))
1342 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1343
1344 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1345
1346 n_msis = ahci_init_interrupts(pdev, hpriv);
1347 if (n_msis > 1)
1348 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1349
1350 /* save initial config */
1351 ahci_pci_save_initial_config(pdev, hpriv);
1352
1353 /* prepare host */
1354 if (hpriv->cap & HOST_CAP_NCQ) {
1355 pi.flags |= ATA_FLAG_NCQ;
1356 /*
1357 * Auto-activate optimization is supposed to be
1358 * supported on all AHCI controllers indicating NCQ
1359 * capability, but it seems to be broken on some
1360 * chipsets including NVIDIAs.
1361 */
1362 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1363 pi.flags |= ATA_FLAG_FPDMA_AA;
1364 }
1365
1366 if (hpriv->cap & HOST_CAP_PMP)
1367 pi.flags |= ATA_FLAG_PMP;
1368
1369 ahci_set_em_messages(hpriv, &pi);
1370
1371 if (ahci_broken_system_poweroff(pdev)) {
1372 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1373 dev_info(&pdev->dev,
1374 "quirky BIOS, skipping spindown on poweroff\n");
1375 }
1376
1377 if (ahci_broken_suspend(pdev)) {
1378 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1379 dev_warn(&pdev->dev,
1380 "BIOS update required for suspend/resume\n");
1381 }
1382
1383 if (ahci_broken_online(pdev)) {
1384 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1385 dev_info(&pdev->dev,
1386 "online status unreliable, applying workaround\n");
1387 }
1388
1389 /* CAP.NP sometimes indicate the index of the last enabled
1390 * port, at other times, that of the last possible port, so
1391 * determining the maximum port number requires looking at
1392 * both CAP.NP and port_map.
1393 */
1394 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1395
1396 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1397 if (!host)
1398 return -ENOMEM;
1399 host->private_data = hpriv;
1400
1401 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1402 host->flags |= ATA_HOST_PARALLEL_SCAN;
1403 else
1404 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1405
1406 if (pi.flags & ATA_FLAG_EM)
1407 ahci_reset_em(host);
1408
1409 for (i = 0; i < host->n_ports; i++) {
1410 struct ata_port *ap = host->ports[i];
1411
1412 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1413 ata_port_pbar_desc(ap, ahci_pci_bar,
1414 0x100 + ap->port_no * 0x80, "port");
1415
1416 /* set enclosure management message type */
1417 if (ap->flags & ATA_FLAG_EM)
1418 ap->em_message_type = hpriv->em_msg_type;
1419
1420
1421 /* disabled/not-implemented port */
1422 if (!(hpriv->port_map & (1 << i)))
1423 ap->ops = &ata_dummy_port_ops;
1424 }
1425
1426 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1427 ahci_p5wdh_workaround(host);
1428
1429 /* apply gtf filter quirk */
1430 ahci_gtf_filter_workaround(host);
1431
1432 /* initialize adapter */
1433 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1434 if (rc)
1435 return rc;
1436
1437 rc = ahci_pci_reset_controller(host);
1438 if (rc)
1439 return rc;
1440
1441 ahci_pci_init_controller(host);
1442 ahci_pci_print_info(host);
1443
1444 pci_set_master(pdev);
1445
1446 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1447 return ahci_host_activate(host, pdev->irq, n_msis);
1448
1449 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1450 &ahci_sht);
1451 }
1452
1453 module_pci_driver(ahci_pci_driver);
1454
1455 MODULE_AUTHOR("Jeff Garzik");
1456 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1457 MODULE_LICENSE("GPL");
1458 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1459 MODULE_VERSION(DRV_VERSION);
kernel source for telekom puls (alcatel/mediatek)