arch/x86/power/cpu.c

   1 /*
   2  * Suspend support specific for i386/x86-64.
   3  *
   4  * Distribute under GPLv2
   5  *
   6  * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
   7  * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
   8  * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
   9  */
  10
  11 #include <linux/suspend.h>
  12 #include <linux/export.h>
  13 #include <linux/smp.h>
  14 #include <linux/perf_event.h>
  15
  16 #include <asm/pgtable.h>
  17 #include <asm/proto.h>
  18 #include <asm/mtrr.h>
  19 #include <asm/page.h>
  20 #include <asm/mce.h>
  21 #include <asm/xcr.h>
  22 #include <asm/suspend.h>
  23 #include <asm/debugreg.h>
  24 #include <asm/fpu-internal.h> /* pcntxt_mask */
  25 #include <asm/cpu.h>
  26
  27 #ifdef CONFIG_X86_32
  28 unsigned long saved_context_ebx;
  29 unsigned long saved_context_esp, saved_context_ebp;
  30 unsigned long saved_context_esi, saved_context_edi;
  31 unsigned long saved_context_eflags;
  32 #endif
  33 struct saved_context saved_context;
  34
  35 /**
  36  *      __save_processor_state - save CPU registers before creating a
  37  *              hibernation image and before restoring the memory state from it
  38  *      @ctxt - structure to store the registers contents in
  39  *
  40  *      NOTE: If there is a CPU register the modification of which by the
  41  *      boot kernel (ie. the kernel used for loading the hibernation image)
  42  *      might affect the operations of the restored target kernel (ie. the one
  43  *      saved in the hibernation image), then its contents must be saved by this
  44  *      function.  In other words, if kernel A is hibernated and different
  45  *      kernel B is used for loading the hibernation image into memory, the
  46  *      kernel A's __save_processor_state() function must save all registers
  47  *      needed by kernel A, so that it can operate correctly after the resume
  48  *      regardless of what kernel B does in the meantime.
  49  */
  50 static void __save_processor_state(struct saved_context *ctxt)
  51 {
  52 #ifdef CONFIG_X86_32
  53         mtrr_save_fixed_ranges(NULL);
  54 #endif
  55         kernel_fpu_begin();
  56
  57         /*
  58          * descriptor tables
  59          */
  60 #ifdef CONFIG_X86_32
  61         store_idt(&ctxt->idt);
  62 #else
  63 /* CONFIG_X86_64 */
  64         store_idt((struct desc_ptr *)&ctxt->idt_limit);
  65 #endif
  66         /*
  67          * We save it here, but restore it only in the hibernate case.
  68          * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
  69          * mode in "secondary_startup_64". In 32-bit mode it is done via
  70          * 'pmode_gdt' in wakeup_start.
  71          */
  72         ctxt->gdt_desc.size = GDT_SIZE - 1;
  73         ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
  74
  75         store_tr(ctxt->tr);
  76
  77         /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
  78         /*
  79          * segment registers
  80          */
  81 #ifdef CONFIG_X86_32
  82         savesegment(es, ctxt->es);
  83         savesegment(fs, ctxt->fs);
  84         savesegment(gs, ctxt->gs);
  85         savesegment(ss, ctxt->ss);
  86 #else
  87 /* CONFIG_X86_64 */
  88         asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
  89         asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
  90         asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
  91         asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
  92         asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
  93
  94         rdmsrl(MSR_FS_BASE, ctxt->fs_base);
  95         rdmsrl(MSR_GS_BASE, ctxt->gs_base);
  96         rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
  97         mtrr_save_fixed_ranges(NULL);
  98
  99         rdmsrl(MSR_EFER, ctxt->efer);
 100 #endif
 101
 102         /*
 103          * control registers
 104          */
 105         ctxt->cr0 = read_cr0();
 106         ctxt->cr2 = read_cr2();
 107         ctxt->cr3 = read_cr3();
 108 #ifdef CONFIG_X86_32
 109         ctxt->cr4 = read_cr4_safe();
 110 #else
 111 /* CONFIG_X86_64 */
 112         ctxt->cr4 = read_cr4();
 113         ctxt->cr8 = read_cr8();
 114 #endif
 115         ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
 116                                                &ctxt->misc_enable);
 117 }
 118
 119 /* Needed by apm.c */
 120 void save_processor_state(void)
 121 {
 122         __save_processor_state(&saved_context);
 123         x86_platform.save_sched_clock_state();
 124 }
 125 #ifdef CONFIG_X86_32
 126 EXPORT_SYMBOL(save_processor_state);
 127 #endif
 128
 129 static void do_fpu_end(void)
 130 {
 131         /*
 132          * Restore FPU regs if necessary.
 133          */
 134         kernel_fpu_end();
 135 }
 136
 137 static void fix_processor_context(void)
 138 {
 139         int cpu = smp_processor_id();
 140         struct tss_struct *t = &per_cpu(init_tss, cpu);
 141 #ifdef CONFIG_X86_64
 142         struct desc_struct *desc = get_cpu_gdt_table(cpu);
 143         tss_desc tss;
 144 #endif
 145         set_tss_desc(cpu, t);   /*
 146                                  * This just modifies memory; should not be
 147                                  * necessary. But... This is necessary, because
 148                                  * 386 hardware has concept of busy TSS or some
 149                                  * similar stupidity.
 150                                  */
 151
 152 #ifdef CONFIG_X86_64
 153         memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
 154         tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
 155         write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
 156
 157         syscall_init();                         /* This sets MSR_*STAR and related */
 158 #endif
 159         load_TR_desc();                         /* This does ltr */
 160         load_LDT(&current->active_mm->context); /* This does lldt */
 161 }
 162
 163 /**
 164  *      __restore_processor_state - restore the contents of CPU registers saved
 165  *              by __save_processor_state()
 166  *      @ctxt - structure to load the registers contents from
 167  */
 168 static void __restore_processor_state(struct saved_context *ctxt)
 169 {
 170         if (ctxt->misc_enable_saved)
 171                 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
 172         /*
 173          * control registers
 174          */
 175         /* cr4 was introduced in the Pentium CPU */
 176 #ifdef CONFIG_X86_32
 177         if (ctxt->cr4)
 178                 write_cr4(ctxt->cr4);
 179 #else
 180 /* CONFIG X86_64 */
 181         wrmsrl(MSR_EFER, ctxt->efer);
 182         write_cr8(ctxt->cr8);
 183         write_cr4(ctxt->cr4);
 184 #endif
 185         write_cr3(ctxt->cr3);
 186         write_cr2(ctxt->cr2);
 187         write_cr0(ctxt->cr0);
 188
 189         /*
 190          * now restore the descriptor tables to their proper values
 191          * ltr is done i fix_processor_context().
 192          */
 193 #ifdef CONFIG_X86_32
 194         load_idt(&ctxt->idt);
 195 #else
 196 /* CONFIG_X86_64 */
 197         load_idt((const struct desc_ptr *)&ctxt->idt_limit);
 198 #endif
 199
 200         /*
 201          * segment registers
 202          */
 203 #ifdef CONFIG_X86_32
 204         loadsegment(es, ctxt->es);
 205         loadsegment(fs, ctxt->fs);
 206         loadsegment(gs, ctxt->gs);
 207         loadsegment(ss, ctxt->ss);
 208
 209         /*
 210          * sysenter MSRs
 211          */
 212         if (boot_cpu_has(X86_FEATURE_SEP))
 213                 enable_sep_cpu();
 214 #else
 215 /* CONFIG_X86_64 */
 216         asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
 217         asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
 218         asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
 219         load_gs_index(ctxt->gs);
 220         asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
 221
 222         wrmsrl(MSR_FS_BASE, ctxt->fs_base);
 223         wrmsrl(MSR_GS_BASE, ctxt->gs_base);
 224         wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
 225 #endif
 226
 227         /*
 228          * restore XCR0 for xsave capable cpu's.
 229          */
 230         if (cpu_has_xsave)
 231                 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
 232
 233         fix_processor_context();
 234
 235         do_fpu_end();
 236         x86_platform.restore_sched_clock_state();
 237         mtrr_bp_restore();
 238         perf_restore_debug_store();
 239 }
 240
 241 /* Needed by apm.c */
 242 void restore_processor_state(void)
 243 {
 244         __restore_processor_state(&saved_context);
 245 }
 246 #ifdef CONFIG_X86_32
 247 EXPORT_SYMBOL(restore_processor_state);
 248 #endif
 249
 250 /*
 251  * When bsp_check() is called in hibernate and suspend, cpu hotplug
 252  * is disabled already. So it's unnessary to handle race condition between
 253  * cpumask query and cpu hotplug.
 254  */
 255 static int bsp_check(void)
 256 {
 257         if (cpumask_first(cpu_online_mask) != 0) {
 258                 pr_warn("CPU0 is offline.\n");
 259                 return -ENODEV;
 260         }
 261
 262         return 0;
 263 }
 264
 265 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
 266                            void *ptr)
 267 {
 268         int ret = 0;
 269
 270         switch (action) {
 271         case PM_SUSPEND_PREPARE:
 272         case PM_HIBERNATION_PREPARE:
 273                 ret = bsp_check();
 274                 break;
 275 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0
 276         case PM_RESTORE_PREPARE:
 277                 /*
 278                  * When system resumes from hibernation, online CPU0 because
 279                  * 1. it's required for resume and
 280                  * 2. the CPU was online before hibernation
 281                  */
 282                 if (!cpu_online(0))
 283                         _debug_hotplug_cpu(0, 1);
 284                 break;
 285         case PM_POST_RESTORE:
 286                 /*
 287                  * When a resume really happens, this code won't be called.
 288                  *
 289                  * This code is called only when user space hibernation software
 290                  * prepares for snapshot device during boot time. So we just
 291                  * call _debug_hotplug_cpu() to restore to CPU0's state prior to
 292                  * preparing the snapshot device.
 293                  *
 294                  * This works for normal boot case in our CPU0 hotplug debug
 295                  * mode, i.e. CPU0 is offline and user mode hibernation
 296                  * software initializes during boot time.
 297                  *
 298                  * If CPU0 is online and user application accesses snapshot
 299                  * device after boot time, this will offline CPU0 and user may
 300                  * see different CPU0 state before and after accessing
 301                  * the snapshot device. But hopefully this is not a case when
 302                  * user debugging CPU0 hotplug. Even if users hit this case,
 303                  * they can easily online CPU0 back.
 304                  *
 305                  * To simplify this debug code, we only consider normal boot
 306                  * case. Otherwise we need to remember CPU0's state and restore
 307                  * to that state and resolve racy conditions etc.
 308                  */
 309                 _debug_hotplug_cpu(0, 0);
 310                 break;
 311 #endif
 312         default:
 313                 break;
 314         }
 315         return notifier_from_errno(ret);
 316 }
 317
 318 static int __init bsp_pm_check_init(void)
 319 {
 320         /*
 321          * Set this bsp_pm_callback as lower priority than
 322          * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
 323          * earlier to disable cpu hotplug before bsp online check.
 324          */
 325         pm_notifier(bsp_pm_callback, -INT_MAX);
 326         return 0;
 327 }
 328
 329 core_initcall(bsp_pm_check_init);