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Merge tag 'v3.10.103' into update
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / x86.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
22 #include <linux/kvm_host.h>
23 #include "irq.h"
24 #include "mmu.h"
25 #include "i8254.h"
26 #include "tss.h"
27 #include "kvm_cache_regs.h"
28 #include "x86.h"
29 #include "cpuid.h"
30
31 #include <linux/clocksource.h>
32 #include <linux/interrupt.h>
33 #include <linux/kvm.h>
34 #include <linux/fs.h>
35 #include <linux/vmalloc.h>
36 #include <linux/module.h>
37 #include <linux/mman.h>
38 #include <linux/highmem.h>
39 #include <linux/iommu.h>
40 #include <linux/intel-iommu.h>
41 #include <linux/cpufreq.h>
42 #include <linux/user-return-notifier.h>
43 #include <linux/srcu.h>
44 #include <linux/slab.h>
45 #include <linux/perf_event.h>
46 #include <linux/uaccess.h>
47 #include <linux/hash.h>
48 #include <linux/pci.h>
49 #include <linux/timekeeper_internal.h>
50 #include <linux/pvclock_gtod.h>
51 #include <trace/events/kvm.h>
52
53 #define CREATE_TRACE_POINTS
54 #include "trace.h"
55
56 #include <asm/debugreg.h>
57 #include <asm/msr.h>
58 #include <asm/desc.h>
59 #include <asm/mtrr.h>
60 #include <asm/mce.h>
61 #include <asm/i387.h>
62 #include <asm/fpu-internal.h> /* Ugh! */
63 #include <asm/xcr.h>
64 #include <asm/pvclock.h>
65 #include <asm/div64.h>
66
67 #define MAX_IO_MSRS 256
68 #define KVM_MAX_MCE_BANKS 32
69 #define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
70
71 #define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
74 /* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78 #ifdef CONFIG_X86_64
79 static
80 u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
81 #else
82 static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
83 #endif
84
85 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
87
88 static void update_cr8_intercept(struct kvm_vcpu *vcpu);
89 static void process_nmi(struct kvm_vcpu *vcpu);
90
91 struct kvm_x86_ops *kvm_x86_ops;
92 EXPORT_SYMBOL_GPL(kvm_x86_ops);
93
94 static bool ignore_msrs = 0;
95 module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
96
97 unsigned int min_timer_period_us = 500;
98 module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
100 bool kvm_has_tsc_control;
101 EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102 u32 kvm_max_guest_tsc_khz;
103 EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
105 /* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106 static u32 tsc_tolerance_ppm = 250;
107 module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
109 #define KVM_NR_SHARED_MSRS 16
110
111 struct kvm_shared_msrs_global {
112 int nr;
113 u32 msrs[KVM_NR_SHARED_MSRS];
114 };
115
116 struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
123 };
124
125 static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
126 static struct kvm_shared_msrs __percpu *shared_msrs;
127
128 struct kvm_stats_debugfs_item debugfs_entries[] = {
129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
141 { "hypercalls", VCPU_STAT(hypercalls) },
142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
149 { "irq_injections", VCPU_STAT(irq_injections) },
150 { "nmi_injections", VCPU_STAT(nmi_injections) },
151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
158 { "mmu_unsync", VM_STAT(mmu_unsync) },
159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
160 { "largepages", VM_STAT(lpages) },
161 { NULL }
162 };
163
164 u64 __read_mostly host_xcr0;
165
166 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
167
168 static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169 {
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173 }
174
175 static void kvm_on_user_return(struct user_return_notifier *urn)
176 {
177 unsigned slot;
178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
180 struct kvm_shared_msr_values *values;
181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191 }
192
193 static void shared_msr_update(unsigned slot, u32 msr)
194 {
195 u64 value;
196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
198
199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208 }
209
210 void kvm_define_shared_msr(unsigned slot, u32 msr)
211 {
212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
217 }
218 EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220 static void kvm_shared_msr_cpu_online(void)
221 {
222 unsigned i;
223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
225 shared_msr_update(i, shared_msrs_global.msrs[i]);
226 }
227
228 int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
229 {
230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
232 int err;
233
234 if (((value ^ smsr->values[slot].curr) & mask) == 0)
235 return 0;
236 smsr->values[slot].curr = value;
237 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
238 if (err)
239 return 1;
240
241 if (!smsr->registered) {
242 smsr->urn.on_user_return = kvm_on_user_return;
243 user_return_notifier_register(&smsr->urn);
244 smsr->registered = true;
245 }
246 return 0;
247 }
248 EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
249
250 static void drop_user_return_notifiers(void *ignore)
251 {
252 unsigned int cpu = smp_processor_id();
253 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
254
255 if (smsr->registered)
256 kvm_on_user_return(&smsr->urn);
257 }
258
259 u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
260 {
261 return vcpu->arch.apic_base;
262 }
263 EXPORT_SYMBOL_GPL(kvm_get_apic_base);
264
265 void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
266 {
267 /* TODO: reserve bits check */
268 kvm_lapic_set_base(vcpu, data);
269 }
270 EXPORT_SYMBOL_GPL(kvm_set_apic_base);
271
272 asmlinkage void kvm_spurious_fault(void)
273 {
274 /* Fault while not rebooting. We want the trace. */
275 BUG();
276 }
277 EXPORT_SYMBOL_GPL(kvm_spurious_fault);
278
279 #define EXCPT_BENIGN 0
280 #define EXCPT_CONTRIBUTORY 1
281 #define EXCPT_PF 2
282
283 static int exception_class(int vector)
284 {
285 switch (vector) {
286 case PF_VECTOR:
287 return EXCPT_PF;
288 case DE_VECTOR:
289 case TS_VECTOR:
290 case NP_VECTOR:
291 case SS_VECTOR:
292 case GP_VECTOR:
293 return EXCPT_CONTRIBUTORY;
294 default:
295 break;
296 }
297 return EXCPT_BENIGN;
298 }
299
300 static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
301 unsigned nr, bool has_error, u32 error_code,
302 bool reinject)
303 {
304 u32 prev_nr;
305 int class1, class2;
306
307 kvm_make_request(KVM_REQ_EVENT, vcpu);
308
309 if (!vcpu->arch.exception.pending) {
310 queue:
311 vcpu->arch.exception.pending = true;
312 vcpu->arch.exception.has_error_code = has_error;
313 vcpu->arch.exception.nr = nr;
314 vcpu->arch.exception.error_code = error_code;
315 vcpu->arch.exception.reinject = reinject;
316 return;
317 }
318
319 /* to check exception */
320 prev_nr = vcpu->arch.exception.nr;
321 if (prev_nr == DF_VECTOR) {
322 /* triple fault -> shutdown */
323 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
324 return;
325 }
326 class1 = exception_class(prev_nr);
327 class2 = exception_class(nr);
328 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
329 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
330 /* generate double fault per SDM Table 5-5 */
331 vcpu->arch.exception.pending = true;
332 vcpu->arch.exception.has_error_code = true;
333 vcpu->arch.exception.nr = DF_VECTOR;
334 vcpu->arch.exception.error_code = 0;
335 } else
336 /* replace previous exception with a new one in a hope
337 that instruction re-execution will regenerate lost
338 exception */
339 goto queue;
340 }
341
342 void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
343 {
344 kvm_multiple_exception(vcpu, nr, false, 0, false);
345 }
346 EXPORT_SYMBOL_GPL(kvm_queue_exception);
347
348 void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
349 {
350 kvm_multiple_exception(vcpu, nr, false, 0, true);
351 }
352 EXPORT_SYMBOL_GPL(kvm_requeue_exception);
353
354 void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
355 {
356 if (err)
357 kvm_inject_gp(vcpu, 0);
358 else
359 kvm_x86_ops->skip_emulated_instruction(vcpu);
360 }
361 EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
362
363 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
364 {
365 ++vcpu->stat.pf_guest;
366 vcpu->arch.cr2 = fault->address;
367 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
368 }
369 EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
370
371 void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
372 {
373 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
374 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
375 else
376 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
377 }
378
379 void kvm_inject_nmi(struct kvm_vcpu *vcpu)
380 {
381 atomic_inc(&vcpu->arch.nmi_queued);
382 kvm_make_request(KVM_REQ_NMI, vcpu);
383 }
384 EXPORT_SYMBOL_GPL(kvm_inject_nmi);
385
386 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
387 {
388 kvm_multiple_exception(vcpu, nr, true, error_code, false);
389 }
390 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
391
392 void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
393 {
394 kvm_multiple_exception(vcpu, nr, true, error_code, true);
395 }
396 EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
397
398 /*
399 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
400 * a #GP and return false.
401 */
402 bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
403 {
404 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
405 return true;
406 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
407 return false;
408 }
409 EXPORT_SYMBOL_GPL(kvm_require_cpl);
410
411 /*
412 * This function will be used to read from the physical memory of the currently
413 * running guest. The difference to kvm_read_guest_page is that this function
414 * can read from guest physical or from the guest's guest physical memory.
415 */
416 int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
417 gfn_t ngfn, void *data, int offset, int len,
418 u32 access)
419 {
420 gfn_t real_gfn;
421 gpa_t ngpa;
422
423 ngpa = gfn_to_gpa(ngfn);
424 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
425 if (real_gfn == UNMAPPED_GVA)
426 return -EFAULT;
427
428 real_gfn = gpa_to_gfn(real_gfn);
429
430 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
431 }
432 EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
433
434 int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
435 void *data, int offset, int len, u32 access)
436 {
437 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
438 data, offset, len, access);
439 }
440
441 /*
442 * Load the pae pdptrs. Return true is they are all valid.
443 */
444 int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
445 {
446 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
447 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
448 int i;
449 int ret;
450 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
451
452 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
453 offset * sizeof(u64), sizeof(pdpte),
454 PFERR_USER_MASK|PFERR_WRITE_MASK);
455 if (ret < 0) {
456 ret = 0;
457 goto out;
458 }
459 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
460 if (is_present_gpte(pdpte[i]) &&
461 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
462 ret = 0;
463 goto out;
464 }
465 }
466 ret = 1;
467
468 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
469 __set_bit(VCPU_EXREG_PDPTR,
470 (unsigned long *)&vcpu->arch.regs_avail);
471 __set_bit(VCPU_EXREG_PDPTR,
472 (unsigned long *)&vcpu->arch.regs_dirty);
473 out:
474
475 return ret;
476 }
477 EXPORT_SYMBOL_GPL(load_pdptrs);
478
479 static bool pdptrs_changed(struct kvm_vcpu *vcpu)
480 {
481 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
482 bool changed = true;
483 int offset;
484 gfn_t gfn;
485 int r;
486
487 if (is_long_mode(vcpu) || !is_pae(vcpu))
488 return false;
489
490 if (!test_bit(VCPU_EXREG_PDPTR,
491 (unsigned long *)&vcpu->arch.regs_avail))
492 return true;
493
494 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
495 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
496 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
497 PFERR_USER_MASK | PFERR_WRITE_MASK);
498 if (r < 0)
499 goto out;
500 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
501 out:
502
503 return changed;
504 }
505
506 int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
507 {
508 unsigned long old_cr0 = kvm_read_cr0(vcpu);
509 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
510 X86_CR0_CD | X86_CR0_NW;
511
512 cr0 |= X86_CR0_ET;
513
514 #ifdef CONFIG_X86_64
515 if (cr0 & 0xffffffff00000000UL)
516 return 1;
517 #endif
518
519 cr0 &= ~CR0_RESERVED_BITS;
520
521 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
522 return 1;
523
524 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
525 return 1;
526
527 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
528 #ifdef CONFIG_X86_64
529 if ((vcpu->arch.efer & EFER_LME)) {
530 int cs_db, cs_l;
531
532 if (!is_pae(vcpu))
533 return 1;
534 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
535 if (cs_l)
536 return 1;
537 } else
538 #endif
539 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
540 kvm_read_cr3(vcpu)))
541 return 1;
542 }
543
544 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
545 return 1;
546
547 kvm_x86_ops->set_cr0(vcpu, cr0);
548
549 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
550 kvm_clear_async_pf_completion_queue(vcpu);
551 kvm_async_pf_hash_reset(vcpu);
552 }
553
554 if ((cr0 ^ old_cr0) & update_bits)
555 kvm_mmu_reset_context(vcpu);
556 return 0;
557 }
558 EXPORT_SYMBOL_GPL(kvm_set_cr0);
559
560 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
561 {
562 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
563 }
564 EXPORT_SYMBOL_GPL(kvm_lmsw);
565
566 static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
567 {
568 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
569 !vcpu->guest_xcr0_loaded) {
570 /* kvm_set_xcr() also depends on this */
571 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
572 vcpu->guest_xcr0_loaded = 1;
573 }
574 }
575
576 static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
577 {
578 if (vcpu->guest_xcr0_loaded) {
579 if (vcpu->arch.xcr0 != host_xcr0)
580 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
581 vcpu->guest_xcr0_loaded = 0;
582 }
583 }
584
585 int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
586 {
587 u64 xcr0;
588
589 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
590 if (index != XCR_XFEATURE_ENABLED_MASK)
591 return 1;
592 xcr0 = xcr;
593 if (!(xcr0 & XSTATE_FP))
594 return 1;
595 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
596 return 1;
597 if (xcr0 & ~host_xcr0)
598 return 1;
599 kvm_put_guest_xcr0(vcpu);
600 vcpu->arch.xcr0 = xcr0;
601 return 0;
602 }
603
604 int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
605 {
606 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
607 __kvm_set_xcr(vcpu, index, xcr)) {
608 kvm_inject_gp(vcpu, 0);
609 return 1;
610 }
611 return 0;
612 }
613 EXPORT_SYMBOL_GPL(kvm_set_xcr);
614
615 int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
616 {
617 unsigned long old_cr4 = kvm_read_cr4(vcpu);
618 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
619 X86_CR4_PAE | X86_CR4_SMEP;
620 if (cr4 & CR4_RESERVED_BITS)
621 return 1;
622
623 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
624 return 1;
625
626 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
627 return 1;
628
629 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
630 return 1;
631
632 if (is_long_mode(vcpu)) {
633 if (!(cr4 & X86_CR4_PAE))
634 return 1;
635 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
636 && ((cr4 ^ old_cr4) & pdptr_bits)
637 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
638 kvm_read_cr3(vcpu)))
639 return 1;
640
641 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
642 if (!guest_cpuid_has_pcid(vcpu))
643 return 1;
644
645 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
646 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
647 return 1;
648 }
649
650 if (kvm_x86_ops->set_cr4(vcpu, cr4))
651 return 1;
652
653 if (((cr4 ^ old_cr4) & pdptr_bits) ||
654 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
655 kvm_mmu_reset_context(vcpu);
656
657 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
658 kvm_update_cpuid(vcpu);
659
660 return 0;
661 }
662 EXPORT_SYMBOL_GPL(kvm_set_cr4);
663
664 int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
665 {
666 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
667 kvm_mmu_sync_roots(vcpu);
668 kvm_mmu_flush_tlb(vcpu);
669 return 0;
670 }
671
672 if (is_long_mode(vcpu)) {
673 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
674 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
675 return 1;
676 } else
677 if (cr3 & CR3_L_MODE_RESERVED_BITS)
678 return 1;
679 } else {
680 if (is_pae(vcpu)) {
681 if (cr3 & CR3_PAE_RESERVED_BITS)
682 return 1;
683 if (is_paging(vcpu) &&
684 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
685 return 1;
686 }
687 /*
688 * We don't check reserved bits in nonpae mode, because
689 * this isn't enforced, and VMware depends on this.
690 */
691 }
692
693 /*
694 * Does the new cr3 value map to physical memory? (Note, we
695 * catch an invalid cr3 even in real-mode, because it would
696 * cause trouble later on when we turn on paging anyway.)
697 *
698 * A real CPU would silently accept an invalid cr3 and would
699 * attempt to use it - with largely undefined (and often hard
700 * to debug) behavior on the guest side.
701 */
702 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
703 return 1;
704 vcpu->arch.cr3 = cr3;
705 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
706 vcpu->arch.mmu.new_cr3(vcpu);
707 return 0;
708 }
709 EXPORT_SYMBOL_GPL(kvm_set_cr3);
710
711 int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
712 {
713 if (cr8 & CR8_RESERVED_BITS)
714 return 1;
715 if (irqchip_in_kernel(vcpu->kvm))
716 kvm_lapic_set_tpr(vcpu, cr8);
717 else
718 vcpu->arch.cr8 = cr8;
719 return 0;
720 }
721 EXPORT_SYMBOL_GPL(kvm_set_cr8);
722
723 unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
724 {
725 if (irqchip_in_kernel(vcpu->kvm))
726 return kvm_lapic_get_cr8(vcpu);
727 else
728 return vcpu->arch.cr8;
729 }
730 EXPORT_SYMBOL_GPL(kvm_get_cr8);
731
732 static void kvm_update_dr7(struct kvm_vcpu *vcpu)
733 {
734 unsigned long dr7;
735
736 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
737 dr7 = vcpu->arch.guest_debug_dr7;
738 else
739 dr7 = vcpu->arch.dr7;
740 kvm_x86_ops->set_dr7(vcpu, dr7);
741 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
742 }
743
744 static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
745 {
746 switch (dr) {
747 case 0 ... 3:
748 vcpu->arch.db[dr] = val;
749 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
750 vcpu->arch.eff_db[dr] = val;
751 break;
752 case 4:
753 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
754 return 1; /* #UD */
755 /* fall through */
756 case 6:
757 if (val & 0xffffffff00000000ULL)
758 return -1; /* #GP */
759 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
760 break;
761 case 5:
762 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
763 return 1; /* #UD */
764 /* fall through */
765 default: /* 7 */
766 if (val & 0xffffffff00000000ULL)
767 return -1; /* #GP */
768 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
769 kvm_update_dr7(vcpu);
770 break;
771 }
772
773 return 0;
774 }
775
776 int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
777 {
778 int res;
779
780 res = __kvm_set_dr(vcpu, dr, val);
781 if (res > 0)
782 kvm_queue_exception(vcpu, UD_VECTOR);
783 else if (res < 0)
784 kvm_inject_gp(vcpu, 0);
785
786 return res;
787 }
788 EXPORT_SYMBOL_GPL(kvm_set_dr);
789
790 static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
791 {
792 switch (dr) {
793 case 0 ... 3:
794 *val = vcpu->arch.db[dr];
795 break;
796 case 4:
797 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
798 return 1;
799 /* fall through */
800 case 6:
801 *val = vcpu->arch.dr6;
802 break;
803 case 5:
804 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
805 return 1;
806 /* fall through */
807 default: /* 7 */
808 *val = vcpu->arch.dr7;
809 break;
810 }
811
812 return 0;
813 }
814
815 int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
816 {
817 if (_kvm_get_dr(vcpu, dr, val)) {
818 kvm_queue_exception(vcpu, UD_VECTOR);
819 return 1;
820 }
821 return 0;
822 }
823 EXPORT_SYMBOL_GPL(kvm_get_dr);
824
825 bool kvm_rdpmc(struct kvm_vcpu *vcpu)
826 {
827 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
828 u64 data;
829 int err;
830
831 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
832 if (err)
833 return err;
834 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
835 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
836 return err;
837 }
838 EXPORT_SYMBOL_GPL(kvm_rdpmc);
839
840 /*
841 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
842 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
843 *
844 * This list is modified at module load time to reflect the
845 * capabilities of the host cpu. This capabilities test skips MSRs that are
846 * kvm-specific. Those are put in the beginning of the list.
847 */
848
849 #define KVM_SAVE_MSRS_BEGIN 10
850 static u32 msrs_to_save[] = {
851 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
852 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
853 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
854 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
855 MSR_KVM_PV_EOI_EN,
856 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
857 MSR_STAR,
858 #ifdef CONFIG_X86_64
859 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
860 #endif
861 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
862 };
863
864 static unsigned num_msrs_to_save;
865
866 static const u32 emulated_msrs[] = {
867 MSR_IA32_TSC_ADJUST,
868 MSR_IA32_TSCDEADLINE,
869 MSR_IA32_MISC_ENABLE,
870 MSR_IA32_MCG_STATUS,
871 MSR_IA32_MCG_CTL,
872 };
873
874 bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
875 {
876 if (efer & efer_reserved_bits)
877 return false;
878
879 if (efer & EFER_FFXSR) {
880 struct kvm_cpuid_entry2 *feat;
881
882 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
883 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
884 return false;
885 }
886
887 if (efer & EFER_SVME) {
888 struct kvm_cpuid_entry2 *feat;
889
890 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
891 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
892 return false;
893 }
894
895 return true;
896 }
897 EXPORT_SYMBOL_GPL(kvm_valid_efer);
898
899 static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
900 {
901 u64 old_efer = vcpu->arch.efer;
902
903 if (!kvm_valid_efer(vcpu, efer))
904 return 1;
905
906 if (is_paging(vcpu)
907 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
908 return 1;
909
910 efer &= ~EFER_LMA;
911 efer |= vcpu->arch.efer & EFER_LMA;
912
913 kvm_x86_ops->set_efer(vcpu, efer);
914
915 /* Update reserved bits */
916 if ((efer ^ old_efer) & EFER_NX)
917 kvm_mmu_reset_context(vcpu);
918
919 return 0;
920 }
921
922 void kvm_enable_efer_bits(u64 mask)
923 {
924 efer_reserved_bits &= ~mask;
925 }
926 EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
927
928 /*
929 * Writes msr value into into the appropriate "register".
930 * Returns 0 on success, non-0 otherwise.
931 * Assumes vcpu_load() was already called.
932 */
933 int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
934 {
935 switch (msr->index) {
936 case MSR_FS_BASE:
937 case MSR_GS_BASE:
938 case MSR_KERNEL_GS_BASE:
939 case MSR_CSTAR:
940 case MSR_LSTAR:
941 if (is_noncanonical_address(msr->data))
942 return 1;
943 break;
944 case MSR_IA32_SYSENTER_EIP:
945 case MSR_IA32_SYSENTER_ESP:
946 /*
947 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
948 * non-canonical address is written on Intel but not on
949 * AMD (which ignores the top 32-bits, because it does
950 * not implement 64-bit SYSENTER).
951 *
952 * 64-bit code should hence be able to write a non-canonical
953 * value on AMD. Making the address canonical ensures that
954 * vmentry does not fail on Intel after writing a non-canonical
955 * value, and that something deterministic happens if the guest
956 * invokes 64-bit SYSENTER.
957 */
958 msr->data = get_canonical(msr->data);
959 }
960 return kvm_x86_ops->set_msr(vcpu, msr);
961 }
962 EXPORT_SYMBOL_GPL(kvm_set_msr);
963
964 /*
965 * Adapt set_msr() to msr_io()'s calling convention
966 */
967 static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
968 {
969 struct msr_data msr;
970
971 msr.data = *data;
972 msr.index = index;
973 msr.host_initiated = true;
974 return kvm_set_msr(vcpu, &msr);
975 }
976
977 #ifdef CONFIG_X86_64
978 struct pvclock_gtod_data {
979 seqcount_t seq;
980
981 struct { /* extract of a clocksource struct */
982 int vclock_mode;
983 cycle_t cycle_last;
984 cycle_t mask;
985 u32 mult;
986 u32 shift;
987 } clock;
988
989 /* open coded 'struct timespec' */
990 u64 monotonic_time_snsec;
991 time_t monotonic_time_sec;
992 };
993
994 static struct pvclock_gtod_data pvclock_gtod_data;
995
996 static void update_pvclock_gtod(struct timekeeper *tk)
997 {
998 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
999
1000 write_seqcount_begin(&vdata->seq);
1001
1002 /* copy pvclock gtod data */
1003 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1004 vdata->clock.cycle_last = tk->clock->cycle_last;
1005 vdata->clock.mask = tk->clock->mask;
1006 vdata->clock.mult = tk->mult;
1007 vdata->clock.shift = tk->shift;
1008
1009 vdata->monotonic_time_sec = tk->xtime_sec
1010 + tk->wall_to_monotonic.tv_sec;
1011 vdata->monotonic_time_snsec = tk->xtime_nsec
1012 + (tk->wall_to_monotonic.tv_nsec
1013 << tk->shift);
1014 while (vdata->monotonic_time_snsec >=
1015 (((u64)NSEC_PER_SEC) << tk->shift)) {
1016 vdata->monotonic_time_snsec -=
1017 ((u64)NSEC_PER_SEC) << tk->shift;
1018 vdata->monotonic_time_sec++;
1019 }
1020
1021 write_seqcount_end(&vdata->seq);
1022 }
1023 #endif
1024
1025
1026 static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1027 {
1028 int version;
1029 int r;
1030 struct pvclock_wall_clock wc;
1031 struct timespec boot;
1032
1033 if (!wall_clock)
1034 return;
1035
1036 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1037 if (r)
1038 return;
1039
1040 if (version & 1)
1041 ++version; /* first time write, random junk */
1042
1043 ++version;
1044
1045 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1046
1047 /*
1048 * The guest calculates current wall clock time by adding
1049 * system time (updated by kvm_guest_time_update below) to the
1050 * wall clock specified here. guest system time equals host
1051 * system time for us, thus we must fill in host boot time here.
1052 */
1053 getboottime(&boot);
1054
1055 if (kvm->arch.kvmclock_offset) {
1056 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1057 boot = timespec_sub(boot, ts);
1058 }
1059 wc.sec = boot.tv_sec;
1060 wc.nsec = boot.tv_nsec;
1061 wc.version = version;
1062
1063 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1064
1065 version++;
1066 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1067 }
1068
1069 static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1070 {
1071 uint32_t quotient, remainder;
1072
1073 /* Don't try to replace with do_div(), this one calculates
1074 * "(dividend << 32) / divisor" */
1075 __asm__ ( "divl %4"
1076 : "=a" (quotient), "=d" (remainder)
1077 : "0" (0), "1" (dividend), "r" (divisor) );
1078 return quotient;
1079 }
1080
1081 static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1082 s8 *pshift, u32 *pmultiplier)
1083 {
1084 uint64_t scaled64;
1085 int32_t shift = 0;
1086 uint64_t tps64;
1087 uint32_t tps32;
1088
1089 tps64 = base_khz * 1000LL;
1090 scaled64 = scaled_khz * 1000LL;
1091 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
1092 tps64 >>= 1;
1093 shift--;
1094 }
1095
1096 tps32 = (uint32_t)tps64;
1097 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1098 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
1099 scaled64 >>= 1;
1100 else
1101 tps32 <<= 1;
1102 shift++;
1103 }
1104
1105 *pshift = shift;
1106 *pmultiplier = div_frac(scaled64, tps32);
1107
1108 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1109 __func__, base_khz, scaled_khz, shift, *pmultiplier);
1110 }
1111
1112 static inline u64 get_kernel_ns(void)
1113 {
1114 struct timespec ts;
1115
1116 WARN_ON(preemptible());
1117 ktime_get_ts(&ts);
1118 monotonic_to_bootbased(&ts);
1119 return timespec_to_ns(&ts);
1120 }
1121
1122 #ifdef CONFIG_X86_64
1123 static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
1124 #endif
1125
1126 static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
1127 unsigned long max_tsc_khz;
1128
1129 static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
1130 {
1131 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1132 vcpu->arch.virtual_tsc_shift);
1133 }
1134
1135 static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1136 {
1137 u64 v = (u64)khz * (1000000 + ppm);
1138 do_div(v, 1000000);
1139 return v;
1140 }
1141
1142 static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
1143 {
1144 u32 thresh_lo, thresh_hi;
1145 int use_scaling = 0;
1146
1147 /* tsc_khz can be zero if TSC calibration fails */
1148 if (this_tsc_khz == 0)
1149 return;
1150
1151 /* Compute a scale to convert nanoseconds in TSC cycles */
1152 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
1153 &vcpu->arch.virtual_tsc_shift,
1154 &vcpu->arch.virtual_tsc_mult);
1155 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1156
1157 /*
1158 * Compute the variation in TSC rate which is acceptable
1159 * within the range of tolerance and decide if the
1160 * rate being applied is within that bounds of the hardware
1161 * rate. If so, no scaling or compensation need be done.
1162 */
1163 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1164 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1165 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1166 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1167 use_scaling = 1;
1168 }
1169 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
1170 }
1171
1172 static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1173 {
1174 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
1175 vcpu->arch.virtual_tsc_mult,
1176 vcpu->arch.virtual_tsc_shift);
1177 tsc += vcpu->arch.this_tsc_write;
1178 return tsc;
1179 }
1180
1181 void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1182 {
1183 #ifdef CONFIG_X86_64
1184 bool vcpus_matched;
1185 struct kvm_arch *ka = &vcpu->kvm->arch;
1186 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1187
1188 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1189 atomic_read(&vcpu->kvm->online_vcpus));
1190
1191 /*
1192 * Once the masterclock is enabled, always perform request in
1193 * order to update it.
1194 *
1195 * In order to enable masterclock, the host clocksource must be TSC
1196 * and the vcpus need to have matched TSCs. When that happens,
1197 * perform request to enable masterclock.
1198 */
1199 if (ka->use_master_clock ||
1200 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
1201 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1202
1203 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1204 atomic_read(&vcpu->kvm->online_vcpus),
1205 ka->use_master_clock, gtod->clock.vclock_mode);
1206 #endif
1207 }
1208
1209 static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1210 {
1211 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1212 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1213 }
1214
1215 void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
1216 {
1217 struct kvm *kvm = vcpu->kvm;
1218 u64 offset, ns, elapsed;
1219 unsigned long flags;
1220 s64 usdiff;
1221 bool matched;
1222 u64 data = msr->data;
1223
1224 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
1225 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1226 ns = get_kernel_ns();
1227 elapsed = ns - kvm->arch.last_tsc_nsec;
1228
1229 if (vcpu->arch.virtual_tsc_khz) {
1230 int faulted = 0;
1231
1232 /* n.b - signed multiplication and division required */
1233 usdiff = data - kvm->arch.last_tsc_write;
1234 #ifdef CONFIG_X86_64
1235 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
1236 #else
1237 /* do_div() only does unsigned */
1238 asm("1: idivl %[divisor]\n"
1239 "2: xor %%edx, %%edx\n"
1240 " movl $0, %[faulted]\n"
1241 "3:\n"
1242 ".section .fixup,\"ax\"\n"
1243 "4: movl $1, %[faulted]\n"
1244 " jmp 3b\n"
1245 ".previous\n"
1246
1247 _ASM_EXTABLE(1b, 4b)
1248
1249 : "=A"(usdiff), [faulted] "=r" (faulted)
1250 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1251
1252 #endif
1253 do_div(elapsed, 1000);
1254 usdiff -= elapsed;
1255 if (usdiff < 0)
1256 usdiff = -usdiff;
1257
1258 /* idivl overflow => difference is larger than USEC_PER_SEC */
1259 if (faulted)
1260 usdiff = USEC_PER_SEC;
1261 } else
1262 usdiff = USEC_PER_SEC; /* disable TSC match window below */
1263
1264 /*
1265 * Special case: TSC write with a small delta (1 second) of virtual
1266 * cycle time against real time is interpreted as an attempt to
1267 * synchronize the CPU.
1268 *
1269 * For a reliable TSC, we can match TSC offsets, and for an unstable
1270 * TSC, we add elapsed time in this computation. We could let the
1271 * compensation code attempt to catch up if we fall behind, but
1272 * it's better to try to match offsets from the beginning.
1273 */
1274 if (usdiff < USEC_PER_SEC &&
1275 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
1276 if (!check_tsc_unstable()) {
1277 offset = kvm->arch.cur_tsc_offset;
1278 pr_debug("kvm: matched tsc offset for %llu\n", data);
1279 } else {
1280 u64 delta = nsec_to_cycles(vcpu, elapsed);
1281 data += delta;
1282 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
1283 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
1284 }
1285 matched = true;
1286 } else {
1287 /*
1288 * We split periods of matched TSC writes into generations.
1289 * For each generation, we track the original measured
1290 * nanosecond time, offset, and write, so if TSCs are in
1291 * sync, we can match exact offset, and if not, we can match
1292 * exact software computation in compute_guest_tsc()
1293 *
1294 * These values are tracked in kvm->arch.cur_xxx variables.
1295 */
1296 kvm->arch.cur_tsc_generation++;
1297 kvm->arch.cur_tsc_nsec = ns;
1298 kvm->arch.cur_tsc_write = data;
1299 kvm->arch.cur_tsc_offset = offset;
1300 matched = false;
1301 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1302 kvm->arch.cur_tsc_generation, data);
1303 }
1304
1305 /*
1306 * We also track th most recent recorded KHZ, write and time to
1307 * allow the matching interval to be extended at each write.
1308 */
1309 kvm->arch.last_tsc_nsec = ns;
1310 kvm->arch.last_tsc_write = data;
1311 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
1312
1313 /* Reset of TSC must disable overshoot protection below */
1314 vcpu->arch.hv_clock.tsc_timestamp = 0;
1315 vcpu->arch.last_guest_tsc = data;
1316
1317 /* Keep track of which generation this VCPU has synchronized to */
1318 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1319 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1320 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1321
1322 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1323 update_ia32_tsc_adjust_msr(vcpu, offset);
1324 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1325 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
1326
1327 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1328 if (matched)
1329 kvm->arch.nr_vcpus_matched_tsc++;
1330 else
1331 kvm->arch.nr_vcpus_matched_tsc = 0;
1332
1333 kvm_track_tsc_matching(vcpu);
1334 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
1335 }
1336
1337 EXPORT_SYMBOL_GPL(kvm_write_tsc);
1338
1339 #ifdef CONFIG_X86_64
1340
1341 static cycle_t read_tsc(void)
1342 {
1343 cycle_t ret;
1344 u64 last;
1345
1346 /*
1347 * Empirically, a fence (of type that depends on the CPU)
1348 * before rdtsc is enough to ensure that rdtsc is ordered
1349 * with respect to loads. The various CPU manuals are unclear
1350 * as to whether rdtsc can be reordered with later loads,
1351 * but no one has ever seen it happen.
1352 */
1353 rdtsc_barrier();
1354 ret = (cycle_t)vget_cycles();
1355
1356 last = pvclock_gtod_data.clock.cycle_last;
1357
1358 if (likely(ret >= last))
1359 return ret;
1360
1361 /*
1362 * GCC likes to generate cmov here, but this branch is extremely
1363 * predictable (it's just a funciton of time and the likely is
1364 * very likely) and there's a data dependence, so force GCC
1365 * to generate a branch instead. I don't barrier() because
1366 * we don't actually need a barrier, and if this function
1367 * ever gets inlined it will generate worse code.
1368 */
1369 asm volatile ("");
1370 return last;
1371 }
1372
1373 static inline u64 vgettsc(cycle_t *cycle_now)
1374 {
1375 long v;
1376 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1377
1378 *cycle_now = read_tsc();
1379
1380 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1381 return v * gtod->clock.mult;
1382 }
1383
1384 static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1385 {
1386 unsigned long seq;
1387 u64 ns;
1388 int mode;
1389 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1390
1391 ts->tv_nsec = 0;
1392 do {
1393 seq = read_seqcount_begin(&gtod->seq);
1394 mode = gtod->clock.vclock_mode;
1395 ts->tv_sec = gtod->monotonic_time_sec;
1396 ns = gtod->monotonic_time_snsec;
1397 ns += vgettsc(cycle_now);
1398 ns >>= gtod->clock.shift;
1399 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1400 timespec_add_ns(ts, ns);
1401
1402 return mode;
1403 }
1404
1405 /* returns true if host is using tsc clocksource */
1406 static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1407 {
1408 struct timespec ts;
1409
1410 /* checked again under seqlock below */
1411 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1412 return false;
1413
1414 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1415 return false;
1416
1417 monotonic_to_bootbased(&ts);
1418 *kernel_ns = timespec_to_ns(&ts);
1419
1420 return true;
1421 }
1422 #endif
1423
1424 /*
1425 *
1426 * Assuming a stable TSC across physical CPUS, and a stable TSC
1427 * across virtual CPUs, the following condition is possible.
1428 * Each numbered line represents an event visible to both
1429 * CPUs at the next numbered event.
1430 *
1431 * "timespecX" represents host monotonic time. "tscX" represents
1432 * RDTSC value.
1433 *
1434 * VCPU0 on CPU0 | VCPU1 on CPU1
1435 *
1436 * 1. read timespec0,tsc0
1437 * 2. | timespec1 = timespec0 + N
1438 * | tsc1 = tsc0 + M
1439 * 3. transition to guest | transition to guest
1440 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1441 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1442 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1443 *
1444 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1445 *
1446 * - ret0 < ret1
1447 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1448 * ...
1449 * - 0 < N - M => M < N
1450 *
1451 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1452 * always the case (the difference between two distinct xtime instances
1453 * might be smaller then the difference between corresponding TSC reads,
1454 * when updating guest vcpus pvclock areas).
1455 *
1456 * To avoid that problem, do not allow visibility of distinct
1457 * system_timestamp/tsc_timestamp values simultaneously: use a master
1458 * copy of host monotonic time values. Update that master copy
1459 * in lockstep.
1460 *
1461 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
1462 *
1463 */
1464
1465 static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1466 {
1467 #ifdef CONFIG_X86_64
1468 struct kvm_arch *ka = &kvm->arch;
1469 int vclock_mode;
1470 bool host_tsc_clocksource, vcpus_matched;
1471
1472 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1473 atomic_read(&kvm->online_vcpus));
1474
1475 /*
1476 * If the host uses TSC clock, then passthrough TSC as stable
1477 * to the guest.
1478 */
1479 host_tsc_clocksource = kvm_get_time_and_clockread(
1480 &ka->master_kernel_ns,
1481 &ka->master_cycle_now);
1482
1483 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1484
1485 if (ka->use_master_clock)
1486 atomic_set(&kvm_guest_has_master_clock, 1);
1487
1488 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
1489 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1490 vcpus_matched);
1491 #endif
1492 }
1493
1494 static int kvm_guest_time_update(struct kvm_vcpu *v)
1495 {
1496 unsigned long flags, this_tsc_khz;
1497 struct kvm_vcpu_arch *vcpu = &v->arch;
1498 struct kvm_arch *ka = &v->kvm->arch;
1499 s64 kernel_ns, max_kernel_ns;
1500 u64 tsc_timestamp, host_tsc;
1501 struct pvclock_vcpu_time_info guest_hv_clock;
1502 u8 pvclock_flags;
1503 bool use_master_clock;
1504
1505 kernel_ns = 0;
1506 host_tsc = 0;
1507
1508 /*
1509 * If the host uses TSC clock, then passthrough TSC as stable
1510 * to the guest.
1511 */
1512 spin_lock(&ka->pvclock_gtod_sync_lock);
1513 use_master_clock = ka->use_master_clock;
1514 if (use_master_clock) {
1515 host_tsc = ka->master_cycle_now;
1516 kernel_ns = ka->master_kernel_ns;
1517 }
1518 spin_unlock(&ka->pvclock_gtod_sync_lock);
1519
1520 /* Keep irq disabled to prevent changes to the clock */
1521 local_irq_save(flags);
1522 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1523 if (unlikely(this_tsc_khz == 0)) {
1524 local_irq_restore(flags);
1525 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1526 return 1;
1527 }
1528 if (!use_master_clock) {
1529 host_tsc = native_read_tsc();
1530 kernel_ns = get_kernel_ns();
1531 }
1532
1533 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1534
1535 /*
1536 * We may have to catch up the TSC to match elapsed wall clock
1537 * time for two reasons, even if kvmclock is used.
1538 * 1) CPU could have been running below the maximum TSC rate
1539 * 2) Broken TSC compensation resets the base at each VCPU
1540 * entry to avoid unknown leaps of TSC even when running
1541 * again on the same CPU. This may cause apparent elapsed
1542 * time to disappear, and the guest to stand still or run
1543 * very slowly.
1544 */
1545 if (vcpu->tsc_catchup) {
1546 u64 tsc = compute_guest_tsc(v, kernel_ns);
1547 if (tsc > tsc_timestamp) {
1548 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
1549 tsc_timestamp = tsc;
1550 }
1551 }
1552
1553 local_irq_restore(flags);
1554
1555 if (!vcpu->pv_time_enabled)
1556 return 0;
1557
1558 /*
1559 * Time as measured by the TSC may go backwards when resetting the base
1560 * tsc_timestamp. The reason for this is that the TSC resolution is
1561 * higher than the resolution of the other clock scales. Thus, many
1562 * possible measurments of the TSC correspond to one measurement of any
1563 * other clock, and so a spread of values is possible. This is not a
1564 * problem for the computation of the nanosecond clock; with TSC rates
1565 * around 1GHZ, there can only be a few cycles which correspond to one
1566 * nanosecond value, and any path through this code will inevitably
1567 * take longer than that. However, with the kernel_ns value itself,
1568 * the precision may be much lower, down to HZ granularity. If the
1569 * first sampling of TSC against kernel_ns ends in the low part of the
1570 * range, and the second in the high end of the range, we can get:
1571 *
1572 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1573 *
1574 * As the sampling errors potentially range in the thousands of cycles,
1575 * it is possible such a time value has already been observed by the
1576 * guest. To protect against this, we must compute the system time as
1577 * observed by the guest and ensure the new system time is greater.
1578 */
1579 max_kernel_ns = 0;
1580 if (vcpu->hv_clock.tsc_timestamp) {
1581 max_kernel_ns = vcpu->last_guest_tsc -
1582 vcpu->hv_clock.tsc_timestamp;
1583 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1584 vcpu->hv_clock.tsc_to_system_mul,
1585 vcpu->hv_clock.tsc_shift);
1586 max_kernel_ns += vcpu->last_kernel_ns;
1587 }
1588
1589 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
1590 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1591 &vcpu->hv_clock.tsc_shift,
1592 &vcpu->hv_clock.tsc_to_system_mul);
1593 vcpu->hw_tsc_khz = this_tsc_khz;
1594 }
1595
1596 /* with a master <monotonic time, tsc value> tuple,
1597 * pvclock clock reads always increase at the (scaled) rate
1598 * of guest TSC - no need to deal with sampling errors.
1599 */
1600 if (!use_master_clock) {
1601 if (max_kernel_ns > kernel_ns)
1602 kernel_ns = max_kernel_ns;
1603 }
1604 /* With all the info we got, fill in the values */
1605 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
1606 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1607 vcpu->last_kernel_ns = kernel_ns;
1608 vcpu->last_guest_tsc = tsc_timestamp;
1609
1610 /*
1611 * The interface expects us to write an even number signaling that the
1612 * update is finished. Since the guest won't see the intermediate
1613 * state, we just increase by 2 at the end.
1614 */
1615 vcpu->hv_clock.version += 2;
1616
1617 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1618 &guest_hv_clock, sizeof(guest_hv_clock))))
1619 return 0;
1620
1621 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1622 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1623
1624 if (vcpu->pvclock_set_guest_stopped_request) {
1625 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1626 vcpu->pvclock_set_guest_stopped_request = false;
1627 }
1628
1629 /* If the host uses TSC clocksource, then it is stable */
1630 if (use_master_clock)
1631 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1632
1633 vcpu->hv_clock.flags = pvclock_flags;
1634
1635 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1636 &vcpu->hv_clock,
1637 sizeof(vcpu->hv_clock));
1638 return 0;
1639 }
1640
1641 static bool msr_mtrr_valid(unsigned msr)
1642 {
1643 switch (msr) {
1644 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1645 case MSR_MTRRfix64K_00000:
1646 case MSR_MTRRfix16K_80000:
1647 case MSR_MTRRfix16K_A0000:
1648 case MSR_MTRRfix4K_C0000:
1649 case MSR_MTRRfix4K_C8000:
1650 case MSR_MTRRfix4K_D0000:
1651 case MSR_MTRRfix4K_D8000:
1652 case MSR_MTRRfix4K_E0000:
1653 case MSR_MTRRfix4K_E8000:
1654 case MSR_MTRRfix4K_F0000:
1655 case MSR_MTRRfix4K_F8000:
1656 case MSR_MTRRdefType:
1657 case MSR_IA32_CR_PAT:
1658 return true;
1659 case 0x2f8:
1660 return true;
1661 }
1662 return false;
1663 }
1664
1665 static bool valid_pat_type(unsigned t)
1666 {
1667 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1668 }
1669
1670 static bool valid_mtrr_type(unsigned t)
1671 {
1672 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1673 }
1674
1675 static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1676 {
1677 int i;
1678
1679 if (!msr_mtrr_valid(msr))
1680 return false;
1681
1682 if (msr == MSR_IA32_CR_PAT) {
1683 for (i = 0; i < 8; i++)
1684 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1685 return false;
1686 return true;
1687 } else if (msr == MSR_MTRRdefType) {
1688 if (data & ~0xcff)
1689 return false;
1690 return valid_mtrr_type(data & 0xff);
1691 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1692 for (i = 0; i < 8 ; i++)
1693 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1694 return false;
1695 return true;
1696 }
1697
1698 /* variable MTRRs */
1699 return valid_mtrr_type(data & 0xff);
1700 }
1701
1702 static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1703 {
1704 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1705
1706 if (!mtrr_valid(vcpu, msr, data))
1707 return 1;
1708
1709 if (msr == MSR_MTRRdefType) {
1710 vcpu->arch.mtrr_state.def_type = data;
1711 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1712 } else if (msr == MSR_MTRRfix64K_00000)
1713 p[0] = data;
1714 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1715 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1716 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1717 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1718 else if (msr == MSR_IA32_CR_PAT)
1719 vcpu->arch.pat = data;
1720 else { /* Variable MTRRs */
1721 int idx, is_mtrr_mask;
1722 u64 *pt;
1723
1724 idx = (msr - 0x200) / 2;
1725 is_mtrr_mask = msr - 0x200 - 2 * idx;
1726 if (!is_mtrr_mask)
1727 pt =
1728 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1729 else
1730 pt =
1731 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1732 *pt = data;
1733 }
1734
1735 kvm_mmu_reset_context(vcpu);
1736 return 0;
1737 }
1738
1739 static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1740 {
1741 u64 mcg_cap = vcpu->arch.mcg_cap;
1742 unsigned bank_num = mcg_cap & 0xff;
1743
1744 switch (msr) {
1745 case MSR_IA32_MCG_STATUS:
1746 vcpu->arch.mcg_status = data;
1747 break;
1748 case MSR_IA32_MCG_CTL:
1749 if (!(mcg_cap & MCG_CTL_P))
1750 return 1;
1751 if (data != 0 && data != ~(u64)0)
1752 return -1;
1753 vcpu->arch.mcg_ctl = data;
1754 break;
1755 default:
1756 if (msr >= MSR_IA32_MC0_CTL &&
1757 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1758 u32 offset = msr - MSR_IA32_MC0_CTL;
1759 /* only 0 or all 1s can be written to IA32_MCi_CTL
1760 * some Linux kernels though clear bit 10 in bank 4 to
1761 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1762 * this to avoid an uncatched #GP in the guest
1763 */
1764 if ((offset & 0x3) == 0 &&
1765 data != 0 && (data | (1 << 10)) != ~(u64)0)
1766 return -1;
1767 vcpu->arch.mce_banks[offset] = data;
1768 break;
1769 }
1770 return 1;
1771 }
1772 return 0;
1773 }
1774
1775 static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1776 {
1777 struct kvm *kvm = vcpu->kvm;
1778 int lm = is_long_mode(vcpu);
1779 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1780 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1781 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1782 : kvm->arch.xen_hvm_config.blob_size_32;
1783 u32 page_num = data & ~PAGE_MASK;
1784 u64 page_addr = data & PAGE_MASK;
1785 u8 *page;
1786 int r;
1787
1788 r = -E2BIG;
1789 if (page_num >= blob_size)
1790 goto out;
1791 r = -ENOMEM;
1792 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1793 if (IS_ERR(page)) {
1794 r = PTR_ERR(page);
1795 goto out;
1796 }
1797 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1798 goto out_free;
1799 r = 0;
1800 out_free:
1801 kfree(page);
1802 out:
1803 return r;
1804 }
1805
1806 static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1807 {
1808 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1809 }
1810
1811 static bool kvm_hv_msr_partition_wide(u32 msr)
1812 {
1813 bool r = false;
1814 switch (msr) {
1815 case HV_X64_MSR_GUEST_OS_ID:
1816 case HV_X64_MSR_HYPERCALL:
1817 r = true;
1818 break;
1819 }
1820
1821 return r;
1822 }
1823
1824 static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1825 {
1826 struct kvm *kvm = vcpu->kvm;
1827
1828 switch (msr) {
1829 case HV_X64_MSR_GUEST_OS_ID:
1830 kvm->arch.hv_guest_os_id = data;
1831 /* setting guest os id to zero disables hypercall page */
1832 if (!kvm->arch.hv_guest_os_id)
1833 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1834 break;
1835 case HV_X64_MSR_HYPERCALL: {
1836 u64 gfn;
1837 unsigned long addr;
1838 u8 instructions[4];
1839
1840 /* if guest os id is not set hypercall should remain disabled */
1841 if (!kvm->arch.hv_guest_os_id)
1842 break;
1843 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1844 kvm->arch.hv_hypercall = data;
1845 break;
1846 }
1847 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1848 addr = gfn_to_hva(kvm, gfn);
1849 if (kvm_is_error_hva(addr))
1850 return 1;
1851 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1852 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
1853 if (__copy_to_user((void __user *)addr, instructions, 4))
1854 return 1;
1855 kvm->arch.hv_hypercall = data;
1856 break;
1857 }
1858 default:
1859 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1860 "data 0x%llx\n", msr, data);
1861 return 1;
1862 }
1863 return 0;
1864 }
1865
1866 static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1867 {
1868 switch (msr) {
1869 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1870 unsigned long addr;
1871
1872 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1873 vcpu->arch.hv_vapic = data;
1874 break;
1875 }
1876 addr = gfn_to_hva(vcpu->kvm, data >>
1877 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1878 if (kvm_is_error_hva(addr))
1879 return 1;
1880 if (__clear_user((void __user *)addr, PAGE_SIZE))
1881 return 1;
1882 vcpu->arch.hv_vapic = data;
1883 break;
1884 }
1885 case HV_X64_MSR_EOI:
1886 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1887 case HV_X64_MSR_ICR:
1888 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1889 case HV_X64_MSR_TPR:
1890 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1891 default:
1892 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1893 "data 0x%llx\n", msr, data);
1894 return 1;
1895 }
1896
1897 return 0;
1898 }
1899
1900 static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1901 {
1902 gpa_t gpa = data & ~0x3f;
1903
1904 /* Bits 2:5 are reserved, Should be zero */
1905 if (data & 0x3c)
1906 return 1;
1907
1908 vcpu->arch.apf.msr_val = data;
1909
1910 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1911 kvm_clear_async_pf_completion_queue(vcpu);
1912 kvm_async_pf_hash_reset(vcpu);
1913 return 0;
1914 }
1915
1916 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1917 sizeof(u32)))
1918 return 1;
1919
1920 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
1921 kvm_async_pf_wakeup_all(vcpu);
1922 return 0;
1923 }
1924
1925 static void kvmclock_reset(struct kvm_vcpu *vcpu)
1926 {
1927 vcpu->arch.pv_time_enabled = false;
1928 }
1929
1930 static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1931 {
1932 u64 delta;
1933
1934 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1935 return;
1936
1937 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1938 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1939 vcpu->arch.st.accum_steal = delta;
1940 }
1941
1942 static void record_steal_time(struct kvm_vcpu *vcpu)
1943 {
1944 accumulate_steal_time(vcpu);
1945
1946 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1947 return;
1948
1949 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1950 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1951 return;
1952
1953 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1954 vcpu->arch.st.steal.version += 2;
1955 vcpu->arch.st.accum_steal = 0;
1956
1957 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1958 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1959 }
1960
1961 int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
1962 {
1963 bool pr = false;
1964 u32 msr = msr_info->index;
1965 u64 data = msr_info->data;
1966
1967 switch (msr) {
1968 case MSR_AMD64_NB_CFG:
1969 case MSR_IA32_UCODE_REV:
1970 case MSR_IA32_UCODE_WRITE:
1971 case MSR_VM_HSAVE_PA:
1972 case MSR_AMD64_PATCH_LOADER:
1973 case MSR_AMD64_BU_CFG2:
1974 break;
1975
1976 case MSR_EFER:
1977 return set_efer(vcpu, data);
1978 case MSR_K7_HWCR:
1979 data &= ~(u64)0x40; /* ignore flush filter disable */
1980 data &= ~(u64)0x100; /* ignore ignne emulation enable */
1981 data &= ~(u64)0x8; /* ignore TLB cache disable */
1982 if (data != 0) {
1983 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1984 data);
1985 return 1;
1986 }
1987 break;
1988 case MSR_FAM10H_MMIO_CONF_BASE:
1989 if (data != 0) {
1990 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1991 "0x%llx\n", data);
1992 return 1;
1993 }
1994 break;
1995 case MSR_IA32_DEBUGCTLMSR:
1996 if (!data) {
1997 /* We support the non-activated case already */
1998 break;
1999 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2000 /* Values other than LBR and BTF are vendor-specific,
2001 thus reserved and should throw a #GP */
2002 return 1;
2003 }
2004 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2005 __func__, data);
2006 break;
2007 case 0x200 ... 0x2ff:
2008 return set_msr_mtrr(vcpu, msr, data);
2009 case MSR_IA32_APICBASE:
2010 kvm_set_apic_base(vcpu, data);
2011 break;
2012 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2013 return kvm_x2apic_msr_write(vcpu, msr, data);
2014 case MSR_IA32_TSCDEADLINE:
2015 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2016 break;
2017 case MSR_IA32_TSC_ADJUST:
2018 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2019 if (!msr_info->host_initiated) {
2020 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2021 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2022 }
2023 vcpu->arch.ia32_tsc_adjust_msr = data;
2024 }
2025 break;
2026 case MSR_IA32_MISC_ENABLE:
2027 vcpu->arch.ia32_misc_enable_msr = data;
2028 break;
2029 case MSR_KVM_WALL_CLOCK_NEW:
2030 case MSR_KVM_WALL_CLOCK:
2031 vcpu->kvm->arch.wall_clock = data;
2032 kvm_write_wall_clock(vcpu->kvm, data);
2033 break;
2034 case MSR_KVM_SYSTEM_TIME_NEW:
2035 case MSR_KVM_SYSTEM_TIME: {
2036 u64 gpa_offset;
2037 kvmclock_reset(vcpu);
2038
2039 vcpu->arch.time = data;
2040 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2041
2042 /* we verify if the enable bit is set... */
2043 if (!(data & 1))
2044 break;
2045
2046 gpa_offset = data & ~(PAGE_MASK | 1);
2047
2048 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2049 &vcpu->arch.pv_time, data & ~1ULL,
2050 sizeof(struct pvclock_vcpu_time_info)))
2051 vcpu->arch.pv_time_enabled = false;
2052 else
2053 vcpu->arch.pv_time_enabled = true;
2054
2055 break;
2056 }
2057 case MSR_KVM_ASYNC_PF_EN:
2058 if (kvm_pv_enable_async_pf(vcpu, data))
2059 return 1;
2060 break;
2061 case MSR_KVM_STEAL_TIME:
2062
2063 if (unlikely(!sched_info_on()))
2064 return 1;
2065
2066 if (data & KVM_STEAL_RESERVED_MASK)
2067 return 1;
2068
2069 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
2070 data & KVM_STEAL_VALID_BITS,
2071 sizeof(struct kvm_steal_time)))
2072 return 1;
2073
2074 vcpu->arch.st.msr_val = data;
2075
2076 if (!(data & KVM_MSR_ENABLED))
2077 break;
2078
2079 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2080
2081 break;
2082 case MSR_KVM_PV_EOI_EN:
2083 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2084 return 1;
2085 break;
2086
2087 case MSR_IA32_MCG_CTL:
2088 case MSR_IA32_MCG_STATUS:
2089 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2090 return set_msr_mce(vcpu, msr, data);
2091
2092 /* Performance counters are not protected by a CPUID bit,
2093 * so we should check all of them in the generic path for the sake of
2094 * cross vendor migration.
2095 * Writing a zero into the event select MSRs disables them,
2096 * which we perfectly emulate ;-). Any other value should be at least
2097 * reported, some guests depend on them.
2098 */
2099 case MSR_K7_EVNTSEL0:
2100 case MSR_K7_EVNTSEL1:
2101 case MSR_K7_EVNTSEL2:
2102 case MSR_K7_EVNTSEL3:
2103 if (data != 0)
2104 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2105 "0x%x data 0x%llx\n", msr, data);
2106 break;
2107 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2108 * so we ignore writes to make it happy.
2109 */
2110 case MSR_K7_PERFCTR0:
2111 case MSR_K7_PERFCTR1:
2112 case MSR_K7_PERFCTR2:
2113 case MSR_K7_PERFCTR3:
2114 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2115 "0x%x data 0x%llx\n", msr, data);
2116 break;
2117 case MSR_P6_PERFCTR0:
2118 case MSR_P6_PERFCTR1:
2119 pr = true;
2120 case MSR_P6_EVNTSEL0:
2121 case MSR_P6_EVNTSEL1:
2122 if (kvm_pmu_msr(vcpu, msr))
2123 return kvm_pmu_set_msr(vcpu, msr_info);
2124
2125 if (pr || data != 0)
2126 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2127 "0x%x data 0x%llx\n", msr, data);
2128 break;
2129 case MSR_K7_CLK_CTL:
2130 /*
2131 * Ignore all writes to this no longer documented MSR.
2132 * Writes are only relevant for old K7 processors,
2133 * all pre-dating SVM, but a recommended workaround from
2134 * AMD for these chips. It is possible to specify the
2135 * affected processor models on the command line, hence
2136 * the need to ignore the workaround.
2137 */
2138 break;
2139 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2140 if (kvm_hv_msr_partition_wide(msr)) {
2141 int r;
2142 mutex_lock(&vcpu->kvm->lock);
2143 r = set_msr_hyperv_pw(vcpu, msr, data);
2144 mutex_unlock(&vcpu->kvm->lock);
2145 return r;
2146 } else
2147 return set_msr_hyperv(vcpu, msr, data);
2148 break;
2149 case MSR_IA32_BBL_CR_CTL3:
2150 /* Drop writes to this legacy MSR -- see rdmsr
2151 * counterpart for further detail.
2152 */
2153 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
2154 break;
2155 case MSR_AMD64_OSVW_ID_LENGTH:
2156 if (!guest_cpuid_has_osvw(vcpu))
2157 return 1;
2158 vcpu->arch.osvw.length = data;
2159 break;
2160 case MSR_AMD64_OSVW_STATUS:
2161 if (!guest_cpuid_has_osvw(vcpu))
2162 return 1;
2163 vcpu->arch.osvw.status = data;
2164 break;
2165 default:
2166 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2167 return xen_hvm_config(vcpu, data);
2168 if (kvm_pmu_msr(vcpu, msr))
2169 return kvm_pmu_set_msr(vcpu, msr_info);
2170 if (!ignore_msrs) {
2171 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2172 msr, data);
2173 return 1;
2174 } else {
2175 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2176 msr, data);
2177 break;
2178 }
2179 }
2180 return 0;
2181 }
2182 EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2183
2184
2185 /*
2186 * Reads an msr value (of 'msr_index') into 'pdata'.
2187 * Returns 0 on success, non-0 otherwise.
2188 * Assumes vcpu_load() was already called.
2189 */
2190 int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2191 {
2192 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2193 }
2194
2195 static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2196 {
2197 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2198
2199 if (!msr_mtrr_valid(msr))
2200 return 1;
2201
2202 if (msr == MSR_MTRRdefType)
2203 *pdata = vcpu->arch.mtrr_state.def_type +
2204 (vcpu->arch.mtrr_state.enabled << 10);
2205 else if (msr == MSR_MTRRfix64K_00000)
2206 *pdata = p[0];
2207 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2208 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2209 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2210 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2211 else if (msr == MSR_IA32_CR_PAT)
2212 *pdata = vcpu->arch.pat;
2213 else { /* Variable MTRRs */
2214 int idx, is_mtrr_mask;
2215 u64 *pt;
2216
2217 idx = (msr - 0x200) / 2;
2218 is_mtrr_mask = msr - 0x200 - 2 * idx;
2219 if (!is_mtrr_mask)
2220 pt =
2221 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2222 else
2223 pt =
2224 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2225 *pdata = *pt;
2226 }
2227
2228 return 0;
2229 }
2230
2231 static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2232 {
2233 u64 data;
2234 u64 mcg_cap = vcpu->arch.mcg_cap;
2235 unsigned bank_num = mcg_cap & 0xff;
2236
2237 switch (msr) {
2238 case MSR_IA32_P5_MC_ADDR:
2239 case MSR_IA32_P5_MC_TYPE:
2240 data = 0;
2241 break;
2242 case MSR_IA32_MCG_CAP:
2243 data = vcpu->arch.mcg_cap;
2244 break;
2245 case MSR_IA32_MCG_CTL:
2246 if (!(mcg_cap & MCG_CTL_P))
2247 return 1;
2248 data = vcpu->arch.mcg_ctl;
2249 break;
2250 case MSR_IA32_MCG_STATUS:
2251 data = vcpu->arch.mcg_status;
2252 break;
2253 default:
2254 if (msr >= MSR_IA32_MC0_CTL &&
2255 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2256 u32 offset = msr - MSR_IA32_MC0_CTL;
2257 data = vcpu->arch.mce_banks[offset];
2258 break;
2259 }
2260 return 1;
2261 }
2262 *pdata = data;
2263 return 0;
2264 }
2265
2266 static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2267 {
2268 u64 data = 0;
2269 struct kvm *kvm = vcpu->kvm;
2270
2271 switch (msr) {
2272 case HV_X64_MSR_GUEST_OS_ID:
2273 data = kvm->arch.hv_guest_os_id;
2274 break;
2275 case HV_X64_MSR_HYPERCALL:
2276 data = kvm->arch.hv_hypercall;
2277 break;
2278 default:
2279 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2280 return 1;
2281 }
2282
2283 *pdata = data;
2284 return 0;
2285 }
2286
2287 static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2288 {
2289 u64 data = 0;
2290
2291 switch (msr) {
2292 case HV_X64_MSR_VP_INDEX: {
2293 int r;
2294 struct kvm_vcpu *v;
2295 kvm_for_each_vcpu(r, v, vcpu->kvm)
2296 if (v == vcpu)
2297 data = r;
2298 break;
2299 }
2300 case HV_X64_MSR_EOI:
2301 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2302 case HV_X64_MSR_ICR:
2303 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2304 case HV_X64_MSR_TPR:
2305 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
2306 case HV_X64_MSR_APIC_ASSIST_PAGE:
2307 data = vcpu->arch.hv_vapic;
2308 break;
2309 default:
2310 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
2311 return 1;
2312 }
2313 *pdata = data;
2314 return 0;
2315 }
2316
2317 int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2318 {
2319 u64 data;
2320
2321 switch (msr) {
2322 case MSR_IA32_PLATFORM_ID:
2323 case MSR_IA32_EBL_CR_POWERON:
2324 case MSR_IA32_DEBUGCTLMSR:
2325 case MSR_IA32_LASTBRANCHFROMIP:
2326 case MSR_IA32_LASTBRANCHTOIP:
2327 case MSR_IA32_LASTINTFROMIP:
2328 case MSR_IA32_LASTINTTOIP:
2329 case MSR_K8_SYSCFG:
2330 case MSR_K7_HWCR:
2331 case MSR_VM_HSAVE_PA:
2332 case MSR_K7_EVNTSEL0:
2333 case MSR_K7_PERFCTR0:
2334 case MSR_K8_INT_PENDING_MSG:
2335 case MSR_AMD64_NB_CFG:
2336 case MSR_FAM10H_MMIO_CONF_BASE:
2337 case MSR_AMD64_BU_CFG2:
2338 data = 0;
2339 break;
2340 case MSR_P6_PERFCTR0:
2341 case MSR_P6_PERFCTR1:
2342 case MSR_P6_EVNTSEL0:
2343 case MSR_P6_EVNTSEL1:
2344 if (kvm_pmu_msr(vcpu, msr))
2345 return kvm_pmu_get_msr(vcpu, msr, pdata);
2346 data = 0;
2347 break;
2348 case MSR_IA32_UCODE_REV:
2349 data = 0x100000000ULL;
2350 break;
2351 case MSR_MTRRcap:
2352 data = 0x500 | KVM_NR_VAR_MTRR;
2353 break;
2354 case 0x200 ... 0x2ff:
2355 return get_msr_mtrr(vcpu, msr, pdata);
2356 case 0xcd: /* fsb frequency */
2357 data = 3;
2358 break;
2359 /*
2360 * MSR_EBC_FREQUENCY_ID
2361 * Conservative value valid for even the basic CPU models.
2362 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2363 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2364 * and 266MHz for model 3, or 4. Set Core Clock
2365 * Frequency to System Bus Frequency Ratio to 1 (bits
2366 * 31:24) even though these are only valid for CPU
2367 * models > 2, however guests may end up dividing or
2368 * multiplying by zero otherwise.
2369 */
2370 case MSR_EBC_FREQUENCY_ID:
2371 data = 1 << 24;
2372 break;
2373 case MSR_IA32_APICBASE:
2374 data = kvm_get_apic_base(vcpu);
2375 break;
2376 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2377 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2378 break;
2379 case MSR_IA32_TSCDEADLINE:
2380 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2381 break;
2382 case MSR_IA32_TSC_ADJUST:
2383 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2384 break;
2385 case MSR_IA32_MISC_ENABLE:
2386 data = vcpu->arch.ia32_misc_enable_msr;
2387 break;
2388 case MSR_IA32_PERF_STATUS:
2389 /* TSC increment by tick */
2390 data = 1000ULL;
2391 /* CPU multiplier */
2392 data |= (((uint64_t)4ULL) << 40);
2393 break;
2394 case MSR_EFER:
2395 data = vcpu->arch.efer;
2396 break;
2397 case MSR_KVM_WALL_CLOCK:
2398 case MSR_KVM_WALL_CLOCK_NEW:
2399 data = vcpu->kvm->arch.wall_clock;
2400 break;
2401 case MSR_KVM_SYSTEM_TIME:
2402 case MSR_KVM_SYSTEM_TIME_NEW:
2403 data = vcpu->arch.time;
2404 break;
2405 case MSR_KVM_ASYNC_PF_EN:
2406 data = vcpu->arch.apf.msr_val;
2407 break;
2408 case MSR_KVM_STEAL_TIME:
2409 data = vcpu->arch.st.msr_val;
2410 break;
2411 case MSR_KVM_PV_EOI_EN:
2412 data = vcpu->arch.pv_eoi.msr_val;
2413 break;
2414 case MSR_IA32_P5_MC_ADDR:
2415 case MSR_IA32_P5_MC_TYPE:
2416 case MSR_IA32_MCG_CAP:
2417 case MSR_IA32_MCG_CTL:
2418 case MSR_IA32_MCG_STATUS:
2419 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2420 return get_msr_mce(vcpu, msr, pdata);
2421 case MSR_K7_CLK_CTL:
2422 /*
2423 * Provide expected ramp-up count for K7. All other
2424 * are set to zero, indicating minimum divisors for
2425 * every field.
2426 *
2427 * This prevents guest kernels on AMD host with CPU
2428 * type 6, model 8 and higher from exploding due to
2429 * the rdmsr failing.
2430 */
2431 data = 0x20000000;
2432 break;
2433 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2434 if (kvm_hv_msr_partition_wide(msr)) {
2435 int r;
2436 mutex_lock(&vcpu->kvm->lock);
2437 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2438 mutex_unlock(&vcpu->kvm->lock);
2439 return r;
2440 } else
2441 return get_msr_hyperv(vcpu, msr, pdata);
2442 break;
2443 case MSR_IA32_BBL_CR_CTL3:
2444 /* This legacy MSR exists but isn't fully documented in current
2445 * silicon. It is however accessed by winxp in very narrow
2446 * scenarios where it sets bit #19, itself documented as
2447 * a "reserved" bit. Best effort attempt to source coherent
2448 * read data here should the balance of the register be
2449 * interpreted by the guest:
2450 *
2451 * L2 cache control register 3: 64GB range, 256KB size,
2452 * enabled, latency 0x1, configured
2453 */
2454 data = 0xbe702111;
2455 break;
2456 case MSR_AMD64_OSVW_ID_LENGTH:
2457 if (!guest_cpuid_has_osvw(vcpu))
2458 return 1;
2459 data = vcpu->arch.osvw.length;
2460 break;
2461 case MSR_AMD64_OSVW_STATUS:
2462 if (!guest_cpuid_has_osvw(vcpu))
2463 return 1;
2464 data = vcpu->arch.osvw.status;
2465 break;
2466 default:
2467 if (kvm_pmu_msr(vcpu, msr))
2468 return kvm_pmu_get_msr(vcpu, msr, pdata);
2469 if (!ignore_msrs) {
2470 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
2471 return 1;
2472 } else {
2473 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
2474 data = 0;
2475 }
2476 break;
2477 }
2478 *pdata = data;
2479 return 0;
2480 }
2481 EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2482
2483 /*
2484 * Read or write a bunch of msrs. All parameters are kernel addresses.
2485 *
2486 * @return number of msrs set successfully.
2487 */
2488 static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2489 struct kvm_msr_entry *entries,
2490 int (*do_msr)(struct kvm_vcpu *vcpu,
2491 unsigned index, u64 *data))
2492 {
2493 int i, idx;
2494
2495 idx = srcu_read_lock(&vcpu->kvm->srcu);
2496 for (i = 0; i < msrs->nmsrs; ++i)
2497 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2498 break;
2499 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2500
2501 return i;
2502 }
2503
2504 /*
2505 * Read or write a bunch of msrs. Parameters are user addresses.
2506 *
2507 * @return number of msrs set successfully.
2508 */
2509 static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2510 int (*do_msr)(struct kvm_vcpu *vcpu,
2511 unsigned index, u64 *data),
2512 int writeback)
2513 {
2514 struct kvm_msrs msrs;
2515 struct kvm_msr_entry *entries;
2516 int r, n;
2517 unsigned size;
2518
2519 r = -EFAULT;
2520 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2521 goto out;
2522
2523 r = -E2BIG;
2524 if (msrs.nmsrs >= MAX_IO_MSRS)
2525 goto out;
2526
2527 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
2528 entries = memdup_user(user_msrs->entries, size);
2529 if (IS_ERR(entries)) {
2530 r = PTR_ERR(entries);
2531 goto out;
2532 }
2533
2534 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2535 if (r < 0)
2536 goto out_free;
2537
2538 r = -EFAULT;
2539 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2540 goto out_free;
2541
2542 r = n;
2543
2544 out_free:
2545 kfree(entries);
2546 out:
2547 return r;
2548 }
2549
2550 int kvm_dev_ioctl_check_extension(long ext)
2551 {
2552 int r;
2553
2554 switch (ext) {
2555 case KVM_CAP_IRQCHIP:
2556 case KVM_CAP_HLT:
2557 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
2558 case KVM_CAP_SET_TSS_ADDR:
2559 case KVM_CAP_EXT_CPUID:
2560 case KVM_CAP_CLOCKSOURCE:
2561 case KVM_CAP_PIT:
2562 case KVM_CAP_NOP_IO_DELAY:
2563 case KVM_CAP_MP_STATE:
2564 case KVM_CAP_SYNC_MMU:
2565 case KVM_CAP_USER_NMI:
2566 case KVM_CAP_REINJECT_CONTROL:
2567 case KVM_CAP_IRQ_INJECT_STATUS:
2568 case KVM_CAP_IRQFD:
2569 case KVM_CAP_IOEVENTFD:
2570 case KVM_CAP_PIT2:
2571 case KVM_CAP_PIT_STATE2:
2572 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
2573 case KVM_CAP_XEN_HVM:
2574 case KVM_CAP_ADJUST_CLOCK:
2575 case KVM_CAP_VCPU_EVENTS:
2576 case KVM_CAP_HYPERV:
2577 case KVM_CAP_HYPERV_VAPIC:
2578 case KVM_CAP_HYPERV_SPIN:
2579 case KVM_CAP_PCI_SEGMENT:
2580 case KVM_CAP_DEBUGREGS:
2581 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2582 case KVM_CAP_XSAVE:
2583 case KVM_CAP_ASYNC_PF:
2584 case KVM_CAP_GET_TSC_KHZ:
2585 case KVM_CAP_KVMCLOCK_CTRL:
2586 case KVM_CAP_READONLY_MEM:
2587 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2588 case KVM_CAP_ASSIGN_DEV_IRQ:
2589 case KVM_CAP_PCI_2_3:
2590 #endif
2591 r = 1;
2592 break;
2593 case KVM_CAP_COALESCED_MMIO:
2594 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2595 break;
2596 case KVM_CAP_VAPIC:
2597 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2598 break;
2599 case KVM_CAP_NR_VCPUS:
2600 r = KVM_SOFT_MAX_VCPUS;
2601 break;
2602 case KVM_CAP_MAX_VCPUS:
2603 r = KVM_MAX_VCPUS;
2604 break;
2605 case KVM_CAP_NR_MEMSLOTS:
2606 r = KVM_USER_MEM_SLOTS;
2607 break;
2608 case KVM_CAP_PV_MMU: /* obsolete */
2609 r = 0;
2610 break;
2611 #ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2612 case KVM_CAP_IOMMU:
2613 r = iommu_present(&pci_bus_type);
2614 break;
2615 #endif
2616 case KVM_CAP_MCE:
2617 r = KVM_MAX_MCE_BANKS;
2618 break;
2619 case KVM_CAP_XCRS:
2620 r = cpu_has_xsave;
2621 break;
2622 case KVM_CAP_TSC_CONTROL:
2623 r = kvm_has_tsc_control;
2624 break;
2625 case KVM_CAP_TSC_DEADLINE_TIMER:
2626 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2627 break;
2628 default:
2629 r = 0;
2630 break;
2631 }
2632 return r;
2633
2634 }
2635
2636 long kvm_arch_dev_ioctl(struct file *filp,
2637 unsigned int ioctl, unsigned long arg)
2638 {
2639 void __user *argp = (void __user *)arg;
2640 long r;
2641
2642 switch (ioctl) {
2643 case KVM_GET_MSR_INDEX_LIST: {
2644 struct kvm_msr_list __user *user_msr_list = argp;
2645 struct kvm_msr_list msr_list;
2646 unsigned n;
2647
2648 r = -EFAULT;
2649 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2650 goto out;
2651 n = msr_list.nmsrs;
2652 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2653 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2654 goto out;
2655 r = -E2BIG;
2656 if (n < msr_list.nmsrs)
2657 goto out;
2658 r = -EFAULT;
2659 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2660 num_msrs_to_save * sizeof(u32)))
2661 goto out;
2662 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
2663 &emulated_msrs,
2664 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2665 goto out;
2666 r = 0;
2667 break;
2668 }
2669 case KVM_GET_SUPPORTED_CPUID: {
2670 struct kvm_cpuid2 __user *cpuid_arg = argp;
2671 struct kvm_cpuid2 cpuid;
2672
2673 r = -EFAULT;
2674 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2675 goto out;
2676 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
2677 cpuid_arg->entries);
2678 if (r)
2679 goto out;
2680
2681 r = -EFAULT;
2682 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2683 goto out;
2684 r = 0;
2685 break;
2686 }
2687 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2688 u64 mce_cap;
2689
2690 mce_cap = KVM_MCE_CAP_SUPPORTED;
2691 r = -EFAULT;
2692 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2693 goto out;
2694 r = 0;
2695 break;
2696 }
2697 default:
2698 r = -EINVAL;
2699 }
2700 out:
2701 return r;
2702 }
2703
2704 static void wbinvd_ipi(void *garbage)
2705 {
2706 wbinvd();
2707 }
2708
2709 static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2710 {
2711 return vcpu->kvm->arch.iommu_domain &&
2712 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2713 }
2714
2715 void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2716 {
2717 /* Address WBINVD may be executed by guest */
2718 if (need_emulate_wbinvd(vcpu)) {
2719 if (kvm_x86_ops->has_wbinvd_exit())
2720 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2721 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2722 smp_call_function_single(vcpu->cpu,
2723 wbinvd_ipi, NULL, 1);
2724 }
2725
2726 kvm_x86_ops->vcpu_load(vcpu, cpu);
2727
2728 /* Apply any externally detected TSC adjustments (due to suspend) */
2729 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2730 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2731 vcpu->arch.tsc_offset_adjustment = 0;
2732 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2733 }
2734
2735 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
2736 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2737 native_read_tsc() - vcpu->arch.last_host_tsc;
2738 if (tsc_delta < 0)
2739 mark_tsc_unstable("KVM discovered backwards TSC");
2740 if (check_tsc_unstable()) {
2741 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2742 vcpu->arch.last_guest_tsc);
2743 kvm_x86_ops->write_tsc_offset(vcpu, offset);
2744 vcpu->arch.tsc_catchup = 1;
2745 }
2746 /*
2747 * On a host with synchronized TSC, there is no need to update
2748 * kvmclock on vcpu->cpu migration
2749 */
2750 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2751 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2752 if (vcpu->cpu != cpu)
2753 kvm_migrate_timers(vcpu);
2754 vcpu->cpu = cpu;
2755 }
2756
2757 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2758 }
2759
2760 void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2761 {
2762 kvm_x86_ops->vcpu_put(vcpu);
2763 kvm_put_guest_fpu(vcpu);
2764 vcpu->arch.last_host_tsc = native_read_tsc();
2765 }
2766
2767 static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2768 struct kvm_lapic_state *s)
2769 {
2770 kvm_x86_ops->sync_pir_to_irr(vcpu);
2771 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
2772
2773 return 0;
2774 }
2775
2776 static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2777 struct kvm_lapic_state *s)
2778 {
2779 kvm_apic_post_state_restore(vcpu, s);
2780 update_cr8_intercept(vcpu);
2781
2782 return 0;
2783 }
2784
2785 static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2786 struct kvm_interrupt *irq)
2787 {
2788 if (irq->irq >= KVM_NR_INTERRUPTS)
2789 return -EINVAL;
2790 if (irqchip_in_kernel(vcpu->kvm))
2791 return -ENXIO;
2792
2793 kvm_queue_interrupt(vcpu, irq->irq, false);
2794 kvm_make_request(KVM_REQ_EVENT, vcpu);
2795
2796 return 0;
2797 }
2798
2799 static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2800 {
2801 kvm_inject_nmi(vcpu);
2802
2803 return 0;
2804 }
2805
2806 static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2807 struct kvm_tpr_access_ctl *tac)
2808 {
2809 if (tac->flags)
2810 return -EINVAL;
2811 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2812 return 0;
2813 }
2814
2815 static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2816 u64 mcg_cap)
2817 {
2818 int r;
2819 unsigned bank_num = mcg_cap & 0xff, bank;
2820
2821 r = -EINVAL;
2822 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
2823 goto out;
2824 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2825 goto out;
2826 r = 0;
2827 vcpu->arch.mcg_cap = mcg_cap;
2828 /* Init IA32_MCG_CTL to all 1s */
2829 if (mcg_cap & MCG_CTL_P)
2830 vcpu->arch.mcg_ctl = ~(u64)0;
2831 /* Init IA32_MCi_CTL to all 1s */
2832 for (bank = 0; bank < bank_num; bank++)
2833 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2834 out:
2835 return r;
2836 }
2837
2838 static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2839 struct kvm_x86_mce *mce)
2840 {
2841 u64 mcg_cap = vcpu->arch.mcg_cap;
2842 unsigned bank_num = mcg_cap & 0xff;
2843 u64 *banks = vcpu->arch.mce_banks;
2844
2845 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2846 return -EINVAL;
2847 /*
2848 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2849 * reporting is disabled
2850 */
2851 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2852 vcpu->arch.mcg_ctl != ~(u64)0)
2853 return 0;
2854 banks += 4 * mce->bank;
2855 /*
2856 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2857 * reporting is disabled for the bank
2858 */
2859 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2860 return 0;
2861 if (mce->status & MCI_STATUS_UC) {
2862 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
2863 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
2864 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2865 return 0;
2866 }
2867 if (banks[1] & MCI_STATUS_VAL)
2868 mce->status |= MCI_STATUS_OVER;
2869 banks[2] = mce->addr;
2870 banks[3] = mce->misc;
2871 vcpu->arch.mcg_status = mce->mcg_status;
2872 banks[1] = mce->status;
2873 kvm_queue_exception(vcpu, MC_VECTOR);
2874 } else if (!(banks[1] & MCI_STATUS_VAL)
2875 || !(banks[1] & MCI_STATUS_UC)) {
2876 if (banks[1] & MCI_STATUS_VAL)
2877 mce->status |= MCI_STATUS_OVER;
2878 banks[2] = mce->addr;
2879 banks[3] = mce->misc;
2880 banks[1] = mce->status;
2881 } else
2882 banks[1] |= MCI_STATUS_OVER;
2883 return 0;
2884 }
2885
2886 static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2887 struct kvm_vcpu_events *events)
2888 {
2889 process_nmi(vcpu);
2890 events->exception.injected =
2891 vcpu->arch.exception.pending &&
2892 !kvm_exception_is_soft(vcpu->arch.exception.nr);
2893 events->exception.nr = vcpu->arch.exception.nr;
2894 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
2895 events->exception.pad = 0;
2896 events->exception.error_code = vcpu->arch.exception.error_code;
2897
2898 events->interrupt.injected =
2899 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
2900 events->interrupt.nr = vcpu->arch.interrupt.nr;
2901 events->interrupt.soft = 0;
2902 events->interrupt.shadow =
2903 kvm_x86_ops->get_interrupt_shadow(vcpu,
2904 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
2905
2906 events->nmi.injected = vcpu->arch.nmi_injected;
2907 events->nmi.pending = vcpu->arch.nmi_pending != 0;
2908 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
2909 events->nmi.pad = 0;
2910
2911 events->sipi_vector = 0; /* never valid when reporting to user space */
2912
2913 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
2914 | KVM_VCPUEVENT_VALID_SHADOW);
2915 memset(&events->reserved, 0, sizeof(events->reserved));
2916 }
2917
2918 static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2919 struct kvm_vcpu_events *events)
2920 {
2921 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
2922 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2923 | KVM_VCPUEVENT_VALID_SHADOW))
2924 return -EINVAL;
2925
2926 process_nmi(vcpu);
2927 vcpu->arch.exception.pending = events->exception.injected;
2928 vcpu->arch.exception.nr = events->exception.nr;
2929 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2930 vcpu->arch.exception.error_code = events->exception.error_code;
2931
2932 vcpu->arch.interrupt.pending = events->interrupt.injected;
2933 vcpu->arch.interrupt.nr = events->interrupt.nr;
2934 vcpu->arch.interrupt.soft = events->interrupt.soft;
2935 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2936 kvm_x86_ops->set_interrupt_shadow(vcpu,
2937 events->interrupt.shadow);
2938
2939 vcpu->arch.nmi_injected = events->nmi.injected;
2940 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2941 vcpu->arch.nmi_pending = events->nmi.pending;
2942 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2943
2944 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2945 kvm_vcpu_has_lapic(vcpu))
2946 vcpu->arch.apic->sipi_vector = events->sipi_vector;
2947
2948 kvm_make_request(KVM_REQ_EVENT, vcpu);
2949
2950 return 0;
2951 }
2952
2953 static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2954 struct kvm_debugregs *dbgregs)
2955 {
2956 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2957 dbgregs->dr6 = vcpu->arch.dr6;
2958 dbgregs->dr7 = vcpu->arch.dr7;
2959 dbgregs->flags = 0;
2960 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
2961 }
2962
2963 static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2964 struct kvm_debugregs *dbgregs)
2965 {
2966 if (dbgregs->flags)
2967 return -EINVAL;
2968
2969 if (dbgregs->dr6 & ~0xffffffffull)
2970 return -EINVAL;
2971 if (dbgregs->dr7 & ~0xffffffffull)
2972 return -EINVAL;
2973
2974 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2975 vcpu->arch.dr6 = dbgregs->dr6;
2976 vcpu->arch.dr7 = dbgregs->dr7;
2977
2978 return 0;
2979 }
2980
2981 static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2982 struct kvm_xsave *guest_xsave)
2983 {
2984 if (cpu_has_xsave)
2985 memcpy(guest_xsave->region,
2986 &vcpu->arch.guest_fpu.state->xsave,
2987 xstate_size);
2988 else {
2989 memcpy(guest_xsave->region,
2990 &vcpu->arch.guest_fpu.state->fxsave,
2991 sizeof(struct i387_fxsave_struct));
2992 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2993 XSTATE_FPSSE;
2994 }
2995 }
2996
2997 static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2998 struct kvm_xsave *guest_xsave)
2999 {
3000 u64 xstate_bv =
3001 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3002
3003 if (cpu_has_xsave)
3004 memcpy(&vcpu->arch.guest_fpu.state->xsave,
3005 guest_xsave->region, xstate_size);
3006 else {
3007 if (xstate_bv & ~XSTATE_FPSSE)
3008 return -EINVAL;
3009 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3010 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3011 }
3012 return 0;
3013 }
3014
3015 static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3016 struct kvm_xcrs *guest_xcrs)
3017 {
3018 if (!cpu_has_xsave) {
3019 guest_xcrs->nr_xcrs = 0;
3020 return;
3021 }
3022
3023 guest_xcrs->nr_xcrs = 1;
3024 guest_xcrs->flags = 0;
3025 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3026 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3027 }
3028
3029 static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3030 struct kvm_xcrs *guest_xcrs)
3031 {
3032 int i, r = 0;
3033
3034 if (!cpu_has_xsave)
3035 return -EINVAL;
3036
3037 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3038 return -EINVAL;
3039
3040 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3041 /* Only support XCR0 currently */
3042 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
3043 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3044 guest_xcrs->xcrs[0].value);
3045 break;
3046 }
3047 if (r)
3048 r = -EINVAL;
3049 return r;
3050 }
3051
3052 /*
3053 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3054 * stopped by the hypervisor. This function will be called from the host only.
3055 * EINVAL is returned when the host attempts to set the flag for a guest that
3056 * does not support pv clocks.
3057 */
3058 static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3059 {
3060 if (!vcpu->arch.pv_time_enabled)
3061 return -EINVAL;
3062 vcpu->arch.pvclock_set_guest_stopped_request = true;
3063 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3064 return 0;
3065 }
3066
3067 long kvm_arch_vcpu_ioctl(struct file *filp,
3068 unsigned int ioctl, unsigned long arg)
3069 {
3070 struct kvm_vcpu *vcpu = filp->private_data;
3071 void __user *argp = (void __user *)arg;
3072 int r;
3073 union {
3074 struct kvm_lapic_state *lapic;
3075 struct kvm_xsave *xsave;
3076 struct kvm_xcrs *xcrs;
3077 void *buffer;
3078 } u;
3079
3080 u.buffer = NULL;
3081 switch (ioctl) {
3082 case KVM_GET_LAPIC: {
3083 r = -EINVAL;
3084 if (!vcpu->arch.apic)
3085 goto out;
3086 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
3087
3088 r = -ENOMEM;
3089 if (!u.lapic)
3090 goto out;
3091 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
3092 if (r)
3093 goto out;
3094 r = -EFAULT;
3095 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
3096 goto out;
3097 r = 0;
3098 break;
3099 }
3100 case KVM_SET_LAPIC: {
3101 r = -EINVAL;
3102 if (!vcpu->arch.apic)
3103 goto out;
3104 u.lapic = memdup_user(argp, sizeof(*u.lapic));
3105 if (IS_ERR(u.lapic))
3106 return PTR_ERR(u.lapic);
3107
3108 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
3109 break;
3110 }
3111 case KVM_INTERRUPT: {
3112 struct kvm_interrupt irq;
3113
3114 r = -EFAULT;
3115 if (copy_from_user(&irq, argp, sizeof irq))
3116 goto out;
3117 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
3118 break;
3119 }
3120 case KVM_NMI: {
3121 r = kvm_vcpu_ioctl_nmi(vcpu);
3122 break;
3123 }
3124 case KVM_SET_CPUID: {
3125 struct kvm_cpuid __user *cpuid_arg = argp;
3126 struct kvm_cpuid cpuid;
3127
3128 r = -EFAULT;
3129 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3130 goto out;
3131 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
3132 break;
3133 }
3134 case KVM_SET_CPUID2: {
3135 struct kvm_cpuid2 __user *cpuid_arg = argp;
3136 struct kvm_cpuid2 cpuid;
3137
3138 r = -EFAULT;
3139 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3140 goto out;
3141 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
3142 cpuid_arg->entries);
3143 break;
3144 }
3145 case KVM_GET_CPUID2: {
3146 struct kvm_cpuid2 __user *cpuid_arg = argp;
3147 struct kvm_cpuid2 cpuid;
3148
3149 r = -EFAULT;
3150 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3151 goto out;
3152 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
3153 cpuid_arg->entries);
3154 if (r)
3155 goto out;
3156 r = -EFAULT;
3157 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3158 goto out;
3159 r = 0;
3160 break;
3161 }
3162 case KVM_GET_MSRS:
3163 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3164 break;
3165 case KVM_SET_MSRS:
3166 r = msr_io(vcpu, argp, do_set_msr, 0);
3167 break;
3168 case KVM_TPR_ACCESS_REPORTING: {
3169 struct kvm_tpr_access_ctl tac;
3170
3171 r = -EFAULT;
3172 if (copy_from_user(&tac, argp, sizeof tac))
3173 goto out;
3174 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3175 if (r)
3176 goto out;
3177 r = -EFAULT;
3178 if (copy_to_user(argp, &tac, sizeof tac))
3179 goto out;
3180 r = 0;
3181 break;
3182 };
3183 case KVM_SET_VAPIC_ADDR: {
3184 struct kvm_vapic_addr va;
3185
3186 r = -EINVAL;
3187 if (!irqchip_in_kernel(vcpu->kvm))
3188 goto out;
3189 r = -EFAULT;
3190 if (copy_from_user(&va, argp, sizeof va))
3191 goto out;
3192 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3193 break;
3194 }
3195 case KVM_X86_SETUP_MCE: {
3196 u64 mcg_cap;
3197
3198 r = -EFAULT;
3199 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3200 goto out;
3201 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3202 break;
3203 }
3204 case KVM_X86_SET_MCE: {
3205 struct kvm_x86_mce mce;
3206
3207 r = -EFAULT;
3208 if (copy_from_user(&mce, argp, sizeof mce))
3209 goto out;
3210 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3211 break;
3212 }
3213 case KVM_GET_VCPU_EVENTS: {
3214 struct kvm_vcpu_events events;
3215
3216 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3217
3218 r = -EFAULT;
3219 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3220 break;
3221 r = 0;
3222 break;
3223 }
3224 case KVM_SET_VCPU_EVENTS: {
3225 struct kvm_vcpu_events events;
3226
3227 r = -EFAULT;
3228 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3229 break;
3230
3231 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3232 break;
3233 }
3234 case KVM_GET_DEBUGREGS: {
3235 struct kvm_debugregs dbgregs;
3236
3237 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3238
3239 r = -EFAULT;
3240 if (copy_to_user(argp, &dbgregs,
3241 sizeof(struct kvm_debugregs)))
3242 break;
3243 r = 0;
3244 break;
3245 }
3246 case KVM_SET_DEBUGREGS: {
3247 struct kvm_debugregs dbgregs;
3248
3249 r = -EFAULT;
3250 if (copy_from_user(&dbgregs, argp,
3251 sizeof(struct kvm_debugregs)))
3252 break;
3253
3254 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3255 break;
3256 }
3257 case KVM_GET_XSAVE: {
3258 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
3259 r = -ENOMEM;
3260 if (!u.xsave)
3261 break;
3262
3263 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
3264
3265 r = -EFAULT;
3266 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
3267 break;
3268 r = 0;
3269 break;
3270 }
3271 case KVM_SET_XSAVE: {
3272 u.xsave = memdup_user(argp, sizeof(*u.xsave));
3273 if (IS_ERR(u.xsave))
3274 return PTR_ERR(u.xsave);
3275
3276 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
3277 break;
3278 }
3279 case KVM_GET_XCRS: {
3280 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
3281 r = -ENOMEM;
3282 if (!u.xcrs)
3283 break;
3284
3285 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
3286
3287 r = -EFAULT;
3288 if (copy_to_user(argp, u.xcrs,
3289 sizeof(struct kvm_xcrs)))
3290 break;
3291 r = 0;
3292 break;
3293 }
3294 case KVM_SET_XCRS: {
3295 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
3296 if (IS_ERR(u.xcrs))
3297 return PTR_ERR(u.xcrs);
3298
3299 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
3300 break;
3301 }
3302 case KVM_SET_TSC_KHZ: {
3303 u32 user_tsc_khz;
3304
3305 r = -EINVAL;
3306 user_tsc_khz = (u32)arg;
3307
3308 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3309 goto out;
3310
3311 if (user_tsc_khz == 0)
3312 user_tsc_khz = tsc_khz;
3313
3314 kvm_set_tsc_khz(vcpu, user_tsc_khz);
3315
3316 r = 0;
3317 goto out;
3318 }
3319 case KVM_GET_TSC_KHZ: {
3320 r = vcpu->arch.virtual_tsc_khz;
3321 goto out;
3322 }
3323 case KVM_KVMCLOCK_CTRL: {
3324 r = kvm_set_guest_paused(vcpu);
3325 goto out;
3326 }
3327 default:
3328 r = -EINVAL;
3329 }
3330 out:
3331 kfree(u.buffer);
3332 return r;
3333 }
3334
3335 int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3336 {
3337 return VM_FAULT_SIGBUS;
3338 }
3339
3340 static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3341 {
3342 int ret;
3343
3344 if (addr > (unsigned int)(-3 * PAGE_SIZE))
3345 return -EINVAL;
3346 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3347 return ret;
3348 }
3349
3350 static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3351 u64 ident_addr)
3352 {
3353 kvm->arch.ept_identity_map_addr = ident_addr;
3354 return 0;
3355 }
3356
3357 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3358 u32 kvm_nr_mmu_pages)
3359 {
3360 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3361 return -EINVAL;
3362
3363 mutex_lock(&kvm->slots_lock);
3364
3365 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
3366 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
3367
3368 mutex_unlock(&kvm->slots_lock);
3369 return 0;
3370 }
3371
3372 static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3373 {
3374 return kvm->arch.n_max_mmu_pages;
3375 }
3376
3377 static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3378 {
3379 int r;
3380
3381 r = 0;
3382 switch (chip->chip_id) {
3383 case KVM_IRQCHIP_PIC_MASTER:
3384 memcpy(&chip->chip.pic,
3385 &pic_irqchip(kvm)->pics[0],
3386 sizeof(struct kvm_pic_state));
3387 break;
3388 case KVM_IRQCHIP_PIC_SLAVE:
3389 memcpy(&chip->chip.pic,
3390 &pic_irqchip(kvm)->pics[1],
3391 sizeof(struct kvm_pic_state));
3392 break;
3393 case KVM_IRQCHIP_IOAPIC:
3394 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
3395 break;
3396 default:
3397 r = -EINVAL;
3398 break;
3399 }
3400 return r;
3401 }
3402
3403 static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3404 {
3405 int r;
3406
3407 r = 0;
3408 switch (chip->chip_id) {
3409 case KVM_IRQCHIP_PIC_MASTER:
3410 spin_lock(&pic_irqchip(kvm)->lock);
3411 memcpy(&pic_irqchip(kvm)->pics[0],
3412 &chip->chip.pic,
3413 sizeof(struct kvm_pic_state));
3414 spin_unlock(&pic_irqchip(kvm)->lock);
3415 break;
3416 case KVM_IRQCHIP_PIC_SLAVE:
3417 spin_lock(&pic_irqchip(kvm)->lock);
3418 memcpy(&pic_irqchip(kvm)->pics[1],
3419 &chip->chip.pic,
3420 sizeof(struct kvm_pic_state));
3421 spin_unlock(&pic_irqchip(kvm)->lock);
3422 break;
3423 case KVM_IRQCHIP_IOAPIC:
3424 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
3425 break;
3426 default:
3427 r = -EINVAL;
3428 break;
3429 }
3430 kvm_pic_update_irq(pic_irqchip(kvm));
3431 return r;
3432 }
3433
3434 static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3435 {
3436 int r = 0;
3437
3438 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3439 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
3440 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3441 return r;
3442 }
3443
3444 static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3445 {
3446 int r = 0;
3447
3448 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3449 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
3450 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3451 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3452 return r;
3453 }
3454
3455 static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3456 {
3457 int r = 0;
3458
3459 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3460 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3461 sizeof(ps->channels));
3462 ps->flags = kvm->arch.vpit->pit_state.flags;
3463 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3464 memset(&ps->reserved, 0, sizeof(ps->reserved));
3465 return r;
3466 }
3467
3468 static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3469 {
3470 int r = 0, start = 0;
3471 u32 prev_legacy, cur_legacy;
3472 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3473 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3474 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3475 if (!prev_legacy && cur_legacy)
3476 start = 1;
3477 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3478 sizeof(kvm->arch.vpit->pit_state.channels));
3479 kvm->arch.vpit->pit_state.flags = ps->flags;
3480 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
3481 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3482 return r;
3483 }
3484
3485 static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3486 struct kvm_reinject_control *control)
3487 {
3488 if (!kvm->arch.vpit)
3489 return -ENXIO;
3490 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3491 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
3492 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3493 return 0;
3494 }
3495
3496 /**
3497 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3498 * @kvm: kvm instance
3499 * @log: slot id and address to which we copy the log
3500 *
3501 * We need to keep it in mind that VCPU threads can write to the bitmap
3502 * concurrently. So, to avoid losing data, we keep the following order for
3503 * each bit:
3504 *
3505 * 1. Take a snapshot of the bit and clear it if needed.
3506 * 2. Write protect the corresponding page.
3507 * 3. Flush TLB's if needed.
3508 * 4. Copy the snapshot to the userspace.
3509 *
3510 * Between 2 and 3, the guest may write to the page using the remaining TLB
3511 * entry. This is not a problem because the page will be reported dirty at
3512 * step 4 using the snapshot taken before and step 3 ensures that successive
3513 * writes will be logged for the next call.
3514 */
3515 int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
3516 {
3517 int r;
3518 struct kvm_memory_slot *memslot;
3519 unsigned long n, i;
3520 unsigned long *dirty_bitmap;
3521 unsigned long *dirty_bitmap_buffer;
3522 bool is_dirty = false;
3523
3524 mutex_lock(&kvm->slots_lock);
3525
3526 r = -EINVAL;
3527 if (log->slot >= KVM_USER_MEM_SLOTS)
3528 goto out;
3529
3530 memslot = id_to_memslot(kvm->memslots, log->slot);
3531
3532 dirty_bitmap = memslot->dirty_bitmap;
3533 r = -ENOENT;
3534 if (!dirty_bitmap)
3535 goto out;
3536
3537 n = kvm_dirty_bitmap_bytes(memslot);
3538
3539 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3540 memset(dirty_bitmap_buffer, 0, n);
3541
3542 spin_lock(&kvm->mmu_lock);
3543
3544 for (i = 0; i < n / sizeof(long); i++) {
3545 unsigned long mask;
3546 gfn_t offset;
3547
3548 if (!dirty_bitmap[i])
3549 continue;
3550
3551 is_dirty = true;
3552
3553 mask = xchg(&dirty_bitmap[i], 0);
3554 dirty_bitmap_buffer[i] = mask;
3555
3556 offset = i * BITS_PER_LONG;
3557 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
3558 }
3559 if (is_dirty)
3560 kvm_flush_remote_tlbs(kvm);
3561
3562 spin_unlock(&kvm->mmu_lock);
3563
3564 r = -EFAULT;
3565 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3566 goto out;
3567
3568 r = 0;
3569 out:
3570 mutex_unlock(&kvm->slots_lock);
3571 return r;
3572 }
3573
3574 int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3575 bool line_status)
3576 {
3577 if (!irqchip_in_kernel(kvm))
3578 return -ENXIO;
3579
3580 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3581 irq_event->irq, irq_event->level,
3582 line_status);
3583 return 0;
3584 }
3585
3586 long kvm_arch_vm_ioctl(struct file *filp,
3587 unsigned int ioctl, unsigned long arg)
3588 {
3589 struct kvm *kvm = filp->private_data;
3590 void __user *argp = (void __user *)arg;
3591 int r = -ENOTTY;
3592 /*
3593 * This union makes it completely explicit to gcc-3.x
3594 * that these two variables' stack usage should be
3595 * combined, not added together.
3596 */
3597 union {
3598 struct kvm_pit_state ps;
3599 struct kvm_pit_state2 ps2;
3600 struct kvm_pit_config pit_config;
3601 } u;
3602
3603 switch (ioctl) {
3604 case KVM_SET_TSS_ADDR:
3605 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
3606 break;
3607 case KVM_SET_IDENTITY_MAP_ADDR: {
3608 u64 ident_addr;
3609
3610 r = -EFAULT;
3611 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3612 goto out;
3613 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
3614 break;
3615 }
3616 case KVM_SET_NR_MMU_PAGES:
3617 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
3618 break;
3619 case KVM_GET_NR_MMU_PAGES:
3620 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3621 break;
3622 case KVM_CREATE_IRQCHIP: {
3623 struct kvm_pic *vpic;
3624
3625 mutex_lock(&kvm->lock);
3626 r = -EEXIST;
3627 if (kvm->arch.vpic)
3628 goto create_irqchip_unlock;
3629 r = -EINVAL;
3630 if (atomic_read(&kvm->online_vcpus))
3631 goto create_irqchip_unlock;
3632 r = -ENOMEM;
3633 vpic = kvm_create_pic(kvm);
3634 if (vpic) {
3635 r = kvm_ioapic_init(kvm);
3636 if (r) {
3637 mutex_lock(&kvm->slots_lock);
3638 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3639 &vpic->dev_master);
3640 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3641 &vpic->dev_slave);
3642 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3643 &vpic->dev_eclr);
3644 mutex_unlock(&kvm->slots_lock);
3645 kfree(vpic);
3646 goto create_irqchip_unlock;
3647 }
3648 } else
3649 goto create_irqchip_unlock;
3650 smp_wmb();
3651 kvm->arch.vpic = vpic;
3652 smp_wmb();
3653 r = kvm_setup_default_irq_routing(kvm);
3654 if (r) {
3655 mutex_lock(&kvm->slots_lock);
3656 mutex_lock(&kvm->irq_lock);
3657 kvm_ioapic_destroy(kvm);
3658 kvm_destroy_pic(kvm);
3659 mutex_unlock(&kvm->irq_lock);
3660 mutex_unlock(&kvm->slots_lock);
3661 }
3662 create_irqchip_unlock:
3663 mutex_unlock(&kvm->lock);
3664 break;
3665 }
3666 case KVM_CREATE_PIT:
3667 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3668 goto create_pit;
3669 case KVM_CREATE_PIT2:
3670 r = -EFAULT;
3671 if (copy_from_user(&u.pit_config, argp,
3672 sizeof(struct kvm_pit_config)))
3673 goto out;
3674 create_pit:
3675 mutex_lock(&kvm->slots_lock);
3676 r = -EEXIST;
3677 if (kvm->arch.vpit)
3678 goto create_pit_unlock;
3679 r = -ENOMEM;
3680 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
3681 if (kvm->arch.vpit)
3682 r = 0;
3683 create_pit_unlock:
3684 mutex_unlock(&kvm->slots_lock);
3685 break;
3686 case KVM_GET_IRQCHIP: {
3687 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3688 struct kvm_irqchip *chip;
3689
3690 chip = memdup_user(argp, sizeof(*chip));
3691 if (IS_ERR(chip)) {
3692 r = PTR_ERR(chip);
3693 goto out;
3694 }
3695
3696 r = -ENXIO;
3697 if (!irqchip_in_kernel(kvm))
3698 goto get_irqchip_out;
3699 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
3700 if (r)
3701 goto get_irqchip_out;
3702 r = -EFAULT;
3703 if (copy_to_user(argp, chip, sizeof *chip))
3704 goto get_irqchip_out;
3705 r = 0;
3706 get_irqchip_out:
3707 kfree(chip);
3708 break;
3709 }
3710 case KVM_SET_IRQCHIP: {
3711 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
3712 struct kvm_irqchip *chip;
3713
3714 chip = memdup_user(argp, sizeof(*chip));
3715 if (IS_ERR(chip)) {
3716 r = PTR_ERR(chip);
3717 goto out;
3718 }
3719
3720 r = -ENXIO;
3721 if (!irqchip_in_kernel(kvm))
3722 goto set_irqchip_out;
3723 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
3724 if (r)
3725 goto set_irqchip_out;
3726 r = 0;
3727 set_irqchip_out:
3728 kfree(chip);
3729 break;
3730 }
3731 case KVM_GET_PIT: {
3732 r = -EFAULT;
3733 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
3734 goto out;
3735 r = -ENXIO;
3736 if (!kvm->arch.vpit)
3737 goto out;
3738 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
3739 if (r)
3740 goto out;
3741 r = -EFAULT;
3742 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
3743 goto out;
3744 r = 0;
3745 break;
3746 }
3747 case KVM_SET_PIT: {
3748 r = -EFAULT;
3749 if (copy_from_user(&u.ps, argp, sizeof u.ps))
3750 goto out;
3751 r = -ENXIO;
3752 if (!kvm->arch.vpit)
3753 goto out;
3754 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
3755 break;
3756 }
3757 case KVM_GET_PIT2: {
3758 r = -ENXIO;
3759 if (!kvm->arch.vpit)
3760 goto out;
3761 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3762 if (r)
3763 goto out;
3764 r = -EFAULT;
3765 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3766 goto out;
3767 r = 0;
3768 break;
3769 }
3770 case KVM_SET_PIT2: {
3771 r = -EFAULT;
3772 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3773 goto out;
3774 r = -ENXIO;
3775 if (!kvm->arch.vpit)
3776 goto out;
3777 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
3778 break;
3779 }
3780 case KVM_REINJECT_CONTROL: {
3781 struct kvm_reinject_control control;
3782 r = -EFAULT;
3783 if (copy_from_user(&control, argp, sizeof(control)))
3784 goto out;
3785 r = kvm_vm_ioctl_reinject(kvm, &control);
3786 break;
3787 }
3788 case KVM_XEN_HVM_CONFIG: {
3789 r = -EFAULT;
3790 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3791 sizeof(struct kvm_xen_hvm_config)))
3792 goto out;
3793 r = -EINVAL;
3794 if (kvm->arch.xen_hvm_config.flags)
3795 goto out;
3796 r = 0;
3797 break;
3798 }
3799 case KVM_SET_CLOCK: {
3800 struct kvm_clock_data user_ns;
3801 u64 now_ns;
3802 s64 delta;
3803
3804 r = -EFAULT;
3805 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3806 goto out;
3807
3808 r = -EINVAL;
3809 if (user_ns.flags)
3810 goto out;
3811
3812 r = 0;
3813 local_irq_disable();
3814 now_ns = get_kernel_ns();
3815 delta = user_ns.clock - now_ns;
3816 local_irq_enable();
3817 kvm->arch.kvmclock_offset = delta;
3818 break;
3819 }
3820 case KVM_GET_CLOCK: {
3821 struct kvm_clock_data user_ns;
3822 u64 now_ns;
3823
3824 local_irq_disable();
3825 now_ns = get_kernel_ns();
3826 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
3827 local_irq_enable();
3828 user_ns.flags = 0;
3829 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
3830
3831 r = -EFAULT;
3832 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3833 goto out;
3834 r = 0;
3835 break;
3836 }
3837
3838 default:
3839 ;
3840 }
3841 out:
3842 return r;
3843 }
3844
3845 static void kvm_init_msr_list(void)
3846 {
3847 u32 dummy[2];
3848 unsigned i, j;
3849
3850 /* skip the first msrs in the list. KVM-specific */
3851 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
3852 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3853 continue;
3854 if (j < i)
3855 msrs_to_save[j] = msrs_to_save[i];
3856 j++;
3857 }
3858 num_msrs_to_save = j;
3859 }
3860
3861 static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3862 const void *v)
3863 {
3864 int handled = 0;
3865 int n;
3866
3867 do {
3868 n = min(len, 8);
3869 if (!(vcpu->arch.apic &&
3870 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3871 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3872 break;
3873 handled += n;
3874 addr += n;
3875 len -= n;
3876 v += n;
3877 } while (len);
3878
3879 return handled;
3880 }
3881
3882 static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
3883 {
3884 int handled = 0;
3885 int n;
3886
3887 do {
3888 n = min(len, 8);
3889 if (!(vcpu->arch.apic &&
3890 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3891 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3892 break;
3893 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3894 handled += n;
3895 addr += n;
3896 len -= n;
3897 v += n;
3898 } while (len);
3899
3900 return handled;
3901 }
3902
3903 static void kvm_set_segment(struct kvm_vcpu *vcpu,
3904 struct kvm_segment *var, int seg)
3905 {
3906 kvm_x86_ops->set_segment(vcpu, var, seg);
3907 }
3908
3909 void kvm_get_segment(struct kvm_vcpu *vcpu,
3910 struct kvm_segment *var, int seg)
3911 {
3912 kvm_x86_ops->get_segment(vcpu, var, seg);
3913 }
3914
3915 gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
3916 {
3917 gpa_t t_gpa;
3918 struct x86_exception exception;
3919
3920 BUG_ON(!mmu_is_nested(vcpu));
3921
3922 /* NPT walks are always user-walks */
3923 access |= PFERR_USER_MASK;
3924 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
3925
3926 return t_gpa;
3927 }
3928
3929 gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3930 struct x86_exception *exception)
3931 {
3932 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3933 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3934 }
3935
3936 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3937 struct x86_exception *exception)
3938 {
3939 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3940 access |= PFERR_FETCH_MASK;
3941 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3942 }
3943
3944 gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3945 struct x86_exception *exception)
3946 {
3947 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3948 access |= PFERR_WRITE_MASK;
3949 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3950 }
3951
3952 /* uses this to access any guest's mapped memory without checking CPL */
3953 gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3954 struct x86_exception *exception)
3955 {
3956 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
3957 }
3958
3959 static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3960 struct kvm_vcpu *vcpu, u32 access,
3961 struct x86_exception *exception)
3962 {
3963 void *data = val;
3964 int r = X86EMUL_CONTINUE;
3965
3966 while (bytes) {
3967 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
3968 exception);
3969 unsigned offset = addr & (PAGE_SIZE-1);
3970 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
3971 int ret;
3972
3973 if (gpa == UNMAPPED_GVA)
3974 return X86EMUL_PROPAGATE_FAULT;
3975 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
3976 if (ret < 0) {
3977 r = X86EMUL_IO_NEEDED;
3978 goto out;
3979 }
3980
3981 bytes -= toread;
3982 data += toread;
3983 addr += toread;
3984 }
3985 out:
3986 return r;
3987 }
3988
3989 /* used for instruction fetching */
3990 static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3991 gva_t addr, void *val, unsigned int bytes,
3992 struct x86_exception *exception)
3993 {
3994 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
3995 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3996
3997 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
3998 access | PFERR_FETCH_MASK,
3999 exception);
4000 }
4001
4002 int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
4003 gva_t addr, void *val, unsigned int bytes,
4004 struct x86_exception *exception)
4005 {
4006 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4007 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4008
4009 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
4010 exception);
4011 }
4012 EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
4013
4014 static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4015 gva_t addr, void *val, unsigned int bytes,
4016 struct x86_exception *exception)
4017 {
4018 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4019 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
4020 }
4021
4022 int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4023 gva_t addr, void *val,
4024 unsigned int bytes,
4025 struct x86_exception *exception)
4026 {
4027 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4028 void *data = val;
4029 int r = X86EMUL_CONTINUE;
4030
4031 while (bytes) {
4032 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4033 PFERR_WRITE_MASK,
4034 exception);
4035 unsigned offset = addr & (PAGE_SIZE-1);
4036 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4037 int ret;
4038
4039 if (gpa == UNMAPPED_GVA)
4040 return X86EMUL_PROPAGATE_FAULT;
4041 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4042 if (ret < 0) {
4043 r = X86EMUL_IO_NEEDED;
4044 goto out;
4045 }
4046
4047 bytes -= towrite;
4048 data += towrite;
4049 addr += towrite;
4050 }
4051 out:
4052 return r;
4053 }
4054 EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
4055
4056 static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4057 gpa_t *gpa, struct x86_exception *exception,
4058 bool write)
4059 {
4060 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4061 | (write ? PFERR_WRITE_MASK : 0);
4062
4063 if (vcpu_match_mmio_gva(vcpu, gva)
4064 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
4065 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4066 (gva & (PAGE_SIZE - 1));
4067 trace_vcpu_match_mmio(gva, *gpa, write, false);
4068 return 1;
4069 }
4070
4071 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4072
4073 if (*gpa == UNMAPPED_GVA)
4074 return -1;
4075
4076 /* For APIC access vmexit */
4077 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4078 return 1;
4079
4080 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4081 trace_vcpu_match_mmio(gva, *gpa, write, true);
4082 return 1;
4083 }
4084
4085 return 0;
4086 }
4087
4088 int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
4089 const void *val, int bytes)
4090 {
4091 int ret;
4092
4093 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
4094 if (ret < 0)
4095 return 0;
4096 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
4097 return 1;
4098 }
4099
4100 struct read_write_emulator_ops {
4101 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4102 int bytes);
4103 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4104 void *val, int bytes);
4105 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4106 int bytes, void *val);
4107 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4108 void *val, int bytes);
4109 bool write;
4110 };
4111
4112 static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4113 {
4114 if (vcpu->mmio_read_completed) {
4115 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
4116 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
4117 vcpu->mmio_read_completed = 0;
4118 return 1;
4119 }
4120
4121 return 0;
4122 }
4123
4124 static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4125 void *val, int bytes)
4126 {
4127 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4128 }
4129
4130 static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4131 void *val, int bytes)
4132 {
4133 return emulator_write_phys(vcpu, gpa, val, bytes);
4134 }
4135
4136 static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4137 {
4138 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4139 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4140 }
4141
4142 static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4143 void *val, int bytes)
4144 {
4145 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4146 return X86EMUL_IO_NEEDED;
4147 }
4148
4149 static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4150 void *val, int bytes)
4151 {
4152 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4153
4154 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
4155 return X86EMUL_CONTINUE;
4156 }
4157
4158 static const struct read_write_emulator_ops read_emultor = {
4159 .read_write_prepare = read_prepare,
4160 .read_write_emulate = read_emulate,
4161 .read_write_mmio = vcpu_mmio_read,
4162 .read_write_exit_mmio = read_exit_mmio,
4163 };
4164
4165 static const struct read_write_emulator_ops write_emultor = {
4166 .read_write_emulate = write_emulate,
4167 .read_write_mmio = write_mmio,
4168 .read_write_exit_mmio = write_exit_mmio,
4169 .write = true,
4170 };
4171
4172 static int emulator_read_write_onepage(unsigned long addr, void *val,
4173 unsigned int bytes,
4174 struct x86_exception *exception,
4175 struct kvm_vcpu *vcpu,
4176 const struct read_write_emulator_ops *ops)
4177 {
4178 gpa_t gpa;
4179 int handled, ret;
4180 bool write = ops->write;
4181 struct kvm_mmio_fragment *frag;
4182
4183 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4184
4185 if (ret < 0)
4186 return X86EMUL_PROPAGATE_FAULT;
4187
4188 /* For APIC access vmexit */
4189 if (ret)
4190 goto mmio;
4191
4192 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
4193 return X86EMUL_CONTINUE;
4194
4195 mmio:
4196 /*
4197 * Is this MMIO handled locally?
4198 */
4199 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
4200 if (handled == bytes)
4201 return X86EMUL_CONTINUE;
4202
4203 gpa += handled;
4204 bytes -= handled;
4205 val += handled;
4206
4207 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4208 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4209 frag->gpa = gpa;
4210 frag->data = val;
4211 frag->len = bytes;
4212 return X86EMUL_CONTINUE;
4213 }
4214
4215 int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4216 void *val, unsigned int bytes,
4217 struct x86_exception *exception,
4218 const struct read_write_emulator_ops *ops)
4219 {
4220 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4221 gpa_t gpa;
4222 int rc;
4223
4224 if (ops->read_write_prepare &&
4225 ops->read_write_prepare(vcpu, val, bytes))
4226 return X86EMUL_CONTINUE;
4227
4228 vcpu->mmio_nr_fragments = 0;
4229
4230 /* Crossing a page boundary? */
4231 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
4232 int now;
4233
4234 now = -addr & ~PAGE_MASK;
4235 rc = emulator_read_write_onepage(addr, val, now, exception,
4236 vcpu, ops);
4237
4238 if (rc != X86EMUL_CONTINUE)
4239 return rc;
4240 addr += now;
4241 val += now;
4242 bytes -= now;
4243 }
4244
4245 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4246 vcpu, ops);
4247 if (rc != X86EMUL_CONTINUE)
4248 return rc;
4249
4250 if (!vcpu->mmio_nr_fragments)
4251 return rc;
4252
4253 gpa = vcpu->mmio_fragments[0].gpa;
4254
4255 vcpu->mmio_needed = 1;
4256 vcpu->mmio_cur_fragment = 0;
4257
4258 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
4259 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4260 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4261 vcpu->run->mmio.phys_addr = gpa;
4262
4263 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
4264 }
4265
4266 static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4267 unsigned long addr,
4268 void *val,
4269 unsigned int bytes,
4270 struct x86_exception *exception)
4271 {
4272 return emulator_read_write(ctxt, addr, val, bytes,
4273 exception, &read_emultor);
4274 }
4275
4276 int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4277 unsigned long addr,
4278 const void *val,
4279 unsigned int bytes,
4280 struct x86_exception *exception)
4281 {
4282 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4283 exception, &write_emultor);
4284 }
4285
4286 #define CMPXCHG_TYPE(t, ptr, old, new) \
4287 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4288
4289 #ifdef CONFIG_X86_64
4290 # define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4291 #else
4292 # define CMPXCHG64(ptr, old, new) \
4293 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
4294 #endif
4295
4296 static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4297 unsigned long addr,
4298 const void *old,
4299 const void *new,
4300 unsigned int bytes,
4301 struct x86_exception *exception)
4302 {
4303 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4304 gpa_t gpa;
4305 struct page *page;
4306 char *kaddr;
4307 bool exchanged;
4308
4309 /* guests cmpxchg8b have to be emulated atomically */
4310 if (bytes > 8 || (bytes & (bytes - 1)))
4311 goto emul_write;
4312
4313 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
4314
4315 if (gpa == UNMAPPED_GVA ||
4316 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4317 goto emul_write;
4318
4319 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4320 goto emul_write;
4321
4322 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
4323 if (is_error_page(page))
4324 goto emul_write;
4325
4326 kaddr = kmap_atomic(page);
4327 kaddr += offset_in_page(gpa);
4328 switch (bytes) {
4329 case 1:
4330 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4331 break;
4332 case 2:
4333 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4334 break;
4335 case 4:
4336 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4337 break;
4338 case 8:
4339 exchanged = CMPXCHG64(kaddr, old, new);
4340 break;
4341 default:
4342 BUG();
4343 }
4344 kunmap_atomic(kaddr);
4345 kvm_release_page_dirty(page);
4346
4347 if (!exchanged)
4348 return X86EMUL_CMPXCHG_FAILED;
4349
4350 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
4351
4352 return X86EMUL_CONTINUE;
4353
4354 emul_write:
4355 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
4356
4357 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
4358 }
4359
4360 static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4361 {
4362 /* TODO: String I/O for in kernel device */
4363 int r;
4364
4365 if (vcpu->arch.pio.in)
4366 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4367 vcpu->arch.pio.size, pd);
4368 else
4369 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4370 vcpu->arch.pio.port, vcpu->arch.pio.size,
4371 pd);
4372 return r;
4373 }
4374
4375 static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4376 unsigned short port, void *val,
4377 unsigned int count, bool in)
4378 {
4379 trace_kvm_pio(!in, port, size, count);
4380
4381 vcpu->arch.pio.port = port;
4382 vcpu->arch.pio.in = in;
4383 vcpu->arch.pio.count = count;
4384 vcpu->arch.pio.size = size;
4385
4386 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
4387 vcpu->arch.pio.count = 0;
4388 return 1;
4389 }
4390
4391 vcpu->run->exit_reason = KVM_EXIT_IO;
4392 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
4393 vcpu->run->io.size = size;
4394 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4395 vcpu->run->io.count = count;
4396 vcpu->run->io.port = port;
4397
4398 return 0;
4399 }
4400
4401 static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4402 int size, unsigned short port, void *val,
4403 unsigned int count)
4404 {
4405 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4406 int ret;
4407
4408 if (vcpu->arch.pio.count)
4409 goto data_avail;
4410
4411 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4412 if (ret) {
4413 data_avail:
4414 memcpy(val, vcpu->arch.pio_data, size * count);
4415 vcpu->arch.pio.count = 0;
4416 return 1;
4417 }
4418
4419 return 0;
4420 }
4421
4422 static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4423 int size, unsigned short port,
4424 const void *val, unsigned int count)
4425 {
4426 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4427
4428 memcpy(vcpu->arch.pio_data, val, size * count);
4429 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4430 }
4431
4432 static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4433 {
4434 return kvm_x86_ops->get_segment_base(vcpu, seg);
4435 }
4436
4437 static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
4438 {
4439 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
4440 }
4441
4442 int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4443 {
4444 if (!need_emulate_wbinvd(vcpu))
4445 return X86EMUL_CONTINUE;
4446
4447 if (kvm_x86_ops->has_wbinvd_exit()) {
4448 int cpu = get_cpu();
4449
4450 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
4451 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4452 wbinvd_ipi, NULL, 1);
4453 put_cpu();
4454 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
4455 } else
4456 wbinvd();
4457 return X86EMUL_CONTINUE;
4458 }
4459 EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4460
4461 static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4462 {
4463 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4464 }
4465
4466 int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
4467 {
4468 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
4469 }
4470
4471 int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
4472 {
4473
4474 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
4475 }
4476
4477 static u64 mk_cr_64(u64 curr_cr, u32 new_val)
4478 {
4479 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
4480 }
4481
4482 static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
4483 {
4484 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4485 unsigned long value;
4486
4487 switch (cr) {
4488 case 0:
4489 value = kvm_read_cr0(vcpu);
4490 break;
4491 case 2:
4492 value = vcpu->arch.cr2;
4493 break;
4494 case 3:
4495 value = kvm_read_cr3(vcpu);
4496 break;
4497 case 4:
4498 value = kvm_read_cr4(vcpu);
4499 break;
4500 case 8:
4501 value = kvm_get_cr8(vcpu);
4502 break;
4503 default:
4504 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4505 return 0;
4506 }
4507
4508 return value;
4509 }
4510
4511 static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
4512 {
4513 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4514 int res = 0;
4515
4516 switch (cr) {
4517 case 0:
4518 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
4519 break;
4520 case 2:
4521 vcpu->arch.cr2 = val;
4522 break;
4523 case 3:
4524 res = kvm_set_cr3(vcpu, val);
4525 break;
4526 case 4:
4527 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
4528 break;
4529 case 8:
4530 res = kvm_set_cr8(vcpu, val);
4531 break;
4532 default:
4533 kvm_err("%s: unexpected cr %u\n", __func__, cr);
4534 res = -1;
4535 }
4536
4537 return res;
4538 }
4539
4540 static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4541 {
4542 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4543 }
4544
4545 static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
4546 {
4547 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
4548 }
4549
4550 static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4551 {
4552 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
4553 }
4554
4555 static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4556 {
4557 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
4558 }
4559
4560 static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4561 {
4562 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4563 }
4564
4565 static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4566 {
4567 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4568 }
4569
4570 static unsigned long emulator_get_cached_segment_base(
4571 struct x86_emulate_ctxt *ctxt, int seg)
4572 {
4573 return get_segment_base(emul_to_vcpu(ctxt), seg);
4574 }
4575
4576 static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4577 struct desc_struct *desc, u32 *base3,
4578 int seg)
4579 {
4580 struct kvm_segment var;
4581
4582 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
4583 *selector = var.selector;
4584
4585 if (var.unusable) {
4586 memset(desc, 0, sizeof(*desc));
4587 return false;
4588 }
4589
4590 if (var.g)
4591 var.limit >>= 12;
4592 set_desc_limit(desc, var.limit);
4593 set_desc_base(desc, (unsigned long)var.base);
4594 #ifdef CONFIG_X86_64
4595 if (base3)
4596 *base3 = var.base >> 32;
4597 #endif
4598 desc->type = var.type;
4599 desc->s = var.s;
4600 desc->dpl = var.dpl;
4601 desc->p = var.present;
4602 desc->avl = var.avl;
4603 desc->l = var.l;
4604 desc->d = var.db;
4605 desc->g = var.g;
4606
4607 return true;
4608 }
4609
4610 static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4611 struct desc_struct *desc, u32 base3,
4612 int seg)
4613 {
4614 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4615 struct kvm_segment var;
4616
4617 var.selector = selector;
4618 var.base = get_desc_base(desc);
4619 #ifdef CONFIG_X86_64
4620 var.base |= ((u64)base3) << 32;
4621 #endif
4622 var.limit = get_desc_limit(desc);
4623 if (desc->g)
4624 var.limit = (var.limit << 12) | 0xfff;
4625 var.type = desc->type;
4626 var.present = desc->p;
4627 var.dpl = desc->dpl;
4628 var.db = desc->d;
4629 var.s = desc->s;
4630 var.l = desc->l;
4631 var.g = desc->g;
4632 var.avl = desc->avl;
4633 var.present = desc->p;
4634 var.unusable = !var.present;
4635 var.padding = 0;
4636
4637 kvm_set_segment(vcpu, &var, seg);
4638 return;
4639 }
4640
4641 static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4642 u32 msr_index, u64 *pdata)
4643 {
4644 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4645 }
4646
4647 static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4648 u32 msr_index, u64 data)
4649 {
4650 struct msr_data msr;
4651
4652 msr.data = data;
4653 msr.index = msr_index;
4654 msr.host_initiated = false;
4655 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
4656 }
4657
4658 static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4659 u32 pmc, u64 *pdata)
4660 {
4661 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4662 }
4663
4664 static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4665 {
4666 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4667 }
4668
4669 static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4670 {
4671 preempt_disable();
4672 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
4673 /*
4674 * CR0.TS may reference the host fpu state, not the guest fpu state,
4675 * so it may be clear at this point.
4676 */
4677 clts();
4678 }
4679
4680 static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4681 {
4682 preempt_enable();
4683 }
4684
4685 static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
4686 struct x86_instruction_info *info,
4687 enum x86_intercept_stage stage)
4688 {
4689 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
4690 }
4691
4692 static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
4693 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4694 {
4695 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
4696 }
4697
4698 static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4699 {
4700 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4701 }
4702
4703 static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4704 {
4705 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4706 }
4707
4708 static const struct x86_emulate_ops emulate_ops = {
4709 .read_gpr = emulator_read_gpr,
4710 .write_gpr = emulator_write_gpr,
4711 .read_std = kvm_read_guest_virt_system,
4712 .write_std = kvm_write_guest_virt_system,
4713 .fetch = kvm_fetch_guest_virt,
4714 .read_emulated = emulator_read_emulated,
4715 .write_emulated = emulator_write_emulated,
4716 .cmpxchg_emulated = emulator_cmpxchg_emulated,
4717 .invlpg = emulator_invlpg,
4718 .pio_in_emulated = emulator_pio_in_emulated,
4719 .pio_out_emulated = emulator_pio_out_emulated,
4720 .get_segment = emulator_get_segment,
4721 .set_segment = emulator_set_segment,
4722 .get_cached_segment_base = emulator_get_cached_segment_base,
4723 .get_gdt = emulator_get_gdt,
4724 .get_idt = emulator_get_idt,
4725 .set_gdt = emulator_set_gdt,
4726 .set_idt = emulator_set_idt,
4727 .get_cr = emulator_get_cr,
4728 .set_cr = emulator_set_cr,
4729 .set_rflags = emulator_set_rflags,
4730 .cpl = emulator_get_cpl,
4731 .get_dr = emulator_get_dr,
4732 .set_dr = emulator_set_dr,
4733 .set_msr = emulator_set_msr,
4734 .get_msr = emulator_get_msr,
4735 .read_pmc = emulator_read_pmc,
4736 .halt = emulator_halt,
4737 .wbinvd = emulator_wbinvd,
4738 .fix_hypercall = emulator_fix_hypercall,
4739 .get_fpu = emulator_get_fpu,
4740 .put_fpu = emulator_put_fpu,
4741 .intercept = emulator_intercept,
4742 .get_cpuid = emulator_get_cpuid,
4743 };
4744
4745 static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4746 {
4747 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4748 /*
4749 * an sti; sti; sequence only disable interrupts for the first
4750 * instruction. So, if the last instruction, be it emulated or
4751 * not, left the system with the INT_STI flag enabled, it
4752 * means that the last instruction is an sti. We should not
4753 * leave the flag on in this case. The same goes for mov ss
4754 */
4755 if (!(int_shadow & mask))
4756 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4757 }
4758
4759 static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4760 {
4761 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4762 if (ctxt->exception.vector == PF_VECTOR)
4763 kvm_propagate_fault(vcpu, &ctxt->exception);
4764 else if (ctxt->exception.error_code_valid)
4765 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4766 ctxt->exception.error_code);
4767 else
4768 kvm_queue_exception(vcpu, ctxt->exception.vector);
4769 }
4770
4771 static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
4772 {
4773 memset(&ctxt->twobyte, 0,
4774 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
4775
4776 ctxt->fetch.start = 0;
4777 ctxt->fetch.end = 0;
4778 ctxt->io_read.pos = 0;
4779 ctxt->io_read.end = 0;
4780 ctxt->mem_read.pos = 0;
4781 ctxt->mem_read.end = 0;
4782 }
4783
4784 static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4785 {
4786 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4787 int cs_db, cs_l;
4788
4789 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4790
4791 ctxt->eflags = kvm_get_rflags(vcpu);
4792 ctxt->eip = kvm_rip_read(vcpu);
4793 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4794 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4795 cs_l ? X86EMUL_MODE_PROT64 :
4796 cs_db ? X86EMUL_MODE_PROT32 :
4797 X86EMUL_MODE_PROT16;
4798 ctxt->guest_mode = is_guest_mode(vcpu);
4799
4800 init_decode_cache(ctxt);
4801 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
4802 }
4803
4804 int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
4805 {
4806 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4807 int ret;
4808
4809 init_emulate_ctxt(vcpu);
4810
4811 ctxt->op_bytes = 2;
4812 ctxt->ad_bytes = 2;
4813 ctxt->_eip = ctxt->eip + inc_eip;
4814 ret = emulate_int_real(ctxt, irq);
4815
4816 if (ret != X86EMUL_CONTINUE)
4817 return EMULATE_FAIL;
4818
4819 ctxt->eip = ctxt->_eip;
4820 kvm_rip_write(vcpu, ctxt->eip);
4821 kvm_set_rflags(vcpu, ctxt->eflags);
4822
4823 if (irq == NMI_VECTOR)
4824 vcpu->arch.nmi_pending = 0;
4825 else
4826 vcpu->arch.interrupt.pending = false;
4827
4828 return EMULATE_DONE;
4829 }
4830 EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4831
4832 static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4833 {
4834 int r = EMULATE_DONE;
4835
4836 ++vcpu->stat.insn_emulation_fail;
4837 trace_kvm_emulate_insn_failed(vcpu);
4838 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
4839 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4840 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4841 vcpu->run->internal.ndata = 0;
4842 r = EMULATE_FAIL;
4843 }
4844 kvm_queue_exception(vcpu, UD_VECTOR);
4845
4846 return r;
4847 }
4848
4849 static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4850 bool write_fault_to_shadow_pgtable,
4851 int emulation_type)
4852 {
4853 gpa_t gpa = cr2;
4854 pfn_t pfn;
4855
4856 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4857 return false;
4858
4859 if (!vcpu->arch.mmu.direct_map) {
4860 /*
4861 * Write permission should be allowed since only
4862 * write access need to be emulated.
4863 */
4864 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4865
4866 /*
4867 * If the mapping is invalid in guest, let cpu retry
4868 * it to generate fault.
4869 */
4870 if (gpa == UNMAPPED_GVA)
4871 return true;
4872 }
4873
4874 /*
4875 * Do not retry the unhandleable instruction if it faults on the
4876 * readonly host memory, otherwise it will goto a infinite loop:
4877 * retry instruction -> write #PF -> emulation fail -> retry
4878 * instruction -> ...
4879 */
4880 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
4881
4882 /*
4883 * If the instruction failed on the error pfn, it can not be fixed,
4884 * report the error to userspace.
4885 */
4886 if (is_error_noslot_pfn(pfn))
4887 return false;
4888
4889 kvm_release_pfn_clean(pfn);
4890
4891 /* The instructions are well-emulated on direct mmu. */
4892 if (vcpu->arch.mmu.direct_map) {
4893 unsigned int indirect_shadow_pages;
4894
4895 spin_lock(&vcpu->kvm->mmu_lock);
4896 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4897 spin_unlock(&vcpu->kvm->mmu_lock);
4898
4899 if (indirect_shadow_pages)
4900 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4901
4902 return true;
4903 }
4904
4905 /*
4906 * if emulation was due to access to shadowed page table
4907 * and it failed try to unshadow page and re-enter the
4908 * guest to let CPU execute the instruction.
4909 */
4910 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4911
4912 /*
4913 * If the access faults on its page table, it can not
4914 * be fixed by unprotecting shadow page and it should
4915 * be reported to userspace.
4916 */
4917 return !write_fault_to_shadow_pgtable;
4918 }
4919
4920 static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4921 unsigned long cr2, int emulation_type)
4922 {
4923 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4924 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4925
4926 last_retry_eip = vcpu->arch.last_retry_eip;
4927 last_retry_addr = vcpu->arch.last_retry_addr;
4928
4929 /*
4930 * If the emulation is caused by #PF and it is non-page_table
4931 * writing instruction, it means the VM-EXIT is caused by shadow
4932 * page protected, we can zap the shadow page and retry this
4933 * instruction directly.
4934 *
4935 * Note: if the guest uses a non-page-table modifying instruction
4936 * on the PDE that points to the instruction, then we will unmap
4937 * the instruction and go to an infinite loop. So, we cache the
4938 * last retried eip and the last fault address, if we meet the eip
4939 * and the address again, we can break out of the potential infinite
4940 * loop.
4941 */
4942 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4943
4944 if (!(emulation_type & EMULTYPE_RETRY))
4945 return false;
4946
4947 if (x86_page_table_writing_insn(ctxt))
4948 return false;
4949
4950 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4951 return false;
4952
4953 vcpu->arch.last_retry_eip = ctxt->eip;
4954 vcpu->arch.last_retry_addr = cr2;
4955
4956 if (!vcpu->arch.mmu.direct_map)
4957 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4958
4959 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4960
4961 return true;
4962 }
4963
4964 static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4965 static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4966
4967 int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4968 unsigned long cr2,
4969 int emulation_type,
4970 void *insn,
4971 int insn_len)
4972 {
4973 int r;
4974 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4975 bool writeback = true;
4976 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
4977
4978 /*
4979 * Clear write_fault_to_shadow_pgtable here to ensure it is
4980 * never reused.
4981 */
4982 vcpu->arch.write_fault_to_shadow_pgtable = false;
4983 kvm_clear_exception_queue(vcpu);
4984
4985 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
4986 init_emulate_ctxt(vcpu);
4987 ctxt->interruptibility = 0;
4988 ctxt->have_exception = false;
4989 ctxt->perm_ok = false;
4990
4991 ctxt->only_vendor_specific_insn
4992 = emulation_type & EMULTYPE_TRAP_UD;
4993
4994 r = x86_decode_insn(ctxt, insn, insn_len);
4995
4996 trace_kvm_emulate_insn_start(vcpu);
4997 ++vcpu->stat.insn_emulation;
4998 if (r != EMULATION_OK) {
4999 if (emulation_type & EMULTYPE_TRAP_UD)
5000 return EMULATE_FAIL;
5001 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5002 emulation_type))
5003 return EMULATE_DONE;
5004 if (emulation_type & EMULTYPE_SKIP)
5005 return EMULATE_FAIL;
5006 return handle_emulation_failure(vcpu);
5007 }
5008 }
5009
5010 if (emulation_type & EMULTYPE_SKIP) {
5011 kvm_rip_write(vcpu, ctxt->_eip);
5012 return EMULATE_DONE;
5013 }
5014
5015 if (retry_instruction(ctxt, cr2, emulation_type))
5016 return EMULATE_DONE;
5017
5018 /* this is needed for vmware backdoor interface to work since it
5019 changes registers values during IO operation */
5020 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5021 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
5022 emulator_invalidate_register_cache(ctxt);
5023 }
5024
5025 restart:
5026 r = x86_emulate_insn(ctxt);
5027
5028 if (r == EMULATION_INTERCEPTED)
5029 return EMULATE_DONE;
5030
5031 if (r == EMULATION_FAILED) {
5032 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5033 emulation_type))
5034 return EMULATE_DONE;
5035
5036 return handle_emulation_failure(vcpu);
5037 }
5038
5039 if (ctxt->have_exception) {
5040 inject_emulated_exception(vcpu);
5041 r = EMULATE_DONE;
5042 } else if (vcpu->arch.pio.count) {
5043 if (!vcpu->arch.pio.in)
5044 vcpu->arch.pio.count = 0;
5045 else {
5046 writeback = false;
5047 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5048 }
5049 r = EMULATE_DO_MMIO;
5050 } else if (vcpu->mmio_needed) {
5051 if (!vcpu->mmio_is_write)
5052 writeback = false;
5053 r = EMULATE_DO_MMIO;
5054 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
5055 } else if (r == EMULATION_RESTART)
5056 goto restart;
5057 else
5058 r = EMULATE_DONE;
5059
5060 if (writeback) {
5061 toggle_interruptibility(vcpu, ctxt->interruptibility);
5062 kvm_set_rflags(vcpu, ctxt->eflags);
5063 kvm_make_request(KVM_REQ_EVENT, vcpu);
5064 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
5065 kvm_rip_write(vcpu, ctxt->eip);
5066 } else
5067 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
5068
5069 return r;
5070 }
5071 EXPORT_SYMBOL_GPL(x86_emulate_instruction);
5072
5073 int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
5074 {
5075 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
5076 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5077 size, port, &val, 1);
5078 /* do not return to emulator after return from userspace */
5079 vcpu->arch.pio.count = 0;
5080 return ret;
5081 }
5082 EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
5083
5084 static void tsc_bad(void *info)
5085 {
5086 __this_cpu_write(cpu_tsc_khz, 0);
5087 }
5088
5089 static void tsc_khz_changed(void *data)
5090 {
5091 struct cpufreq_freqs *freq = data;
5092 unsigned long khz = 0;
5093
5094 if (data)
5095 khz = freq->new;
5096 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5097 khz = cpufreq_quick_get(raw_smp_processor_id());
5098 if (!khz)
5099 khz = tsc_khz;
5100 __this_cpu_write(cpu_tsc_khz, khz);
5101 }
5102
5103 static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5104 void *data)
5105 {
5106 struct cpufreq_freqs *freq = data;
5107 struct kvm *kvm;
5108 struct kvm_vcpu *vcpu;
5109 int i, send_ipi = 0;
5110
5111 /*
5112 * We allow guests to temporarily run on slowing clocks,
5113 * provided we notify them after, or to run on accelerating
5114 * clocks, provided we notify them before. Thus time never
5115 * goes backwards.
5116 *
5117 * However, we have a problem. We can't atomically update
5118 * the frequency of a given CPU from this function; it is
5119 * merely a notifier, which can be called from any CPU.
5120 * Changing the TSC frequency at arbitrary points in time
5121 * requires a recomputation of local variables related to
5122 * the TSC for each VCPU. We must flag these local variables
5123 * to be updated and be sure the update takes place with the
5124 * new frequency before any guests proceed.
5125 *
5126 * Unfortunately, the combination of hotplug CPU and frequency
5127 * change creates an intractable locking scenario; the order
5128 * of when these callouts happen is undefined with respect to
5129 * CPU hotplug, and they can race with each other. As such,
5130 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5131 * undefined; you can actually have a CPU frequency change take
5132 * place in between the computation of X and the setting of the
5133 * variable. To protect against this problem, all updates of
5134 * the per_cpu tsc_khz variable are done in an interrupt
5135 * protected IPI, and all callers wishing to update the value
5136 * must wait for a synchronous IPI to complete (which is trivial
5137 * if the caller is on the CPU already). This establishes the
5138 * necessary total order on variable updates.
5139 *
5140 * Note that because a guest time update may take place
5141 * anytime after the setting of the VCPU's request bit, the
5142 * correct TSC value must be set before the request. However,
5143 * to ensure the update actually makes it to any guest which
5144 * starts running in hardware virtualization between the set
5145 * and the acquisition of the spinlock, we must also ping the
5146 * CPU after setting the request bit.
5147 *
5148 */
5149
5150 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5151 return 0;
5152 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5153 return 0;
5154
5155 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5156
5157 raw_spin_lock(&kvm_lock);
5158 list_for_each_entry(kvm, &vm_list, vm_list) {
5159 kvm_for_each_vcpu(i, vcpu, kvm) {
5160 if (vcpu->cpu != freq->cpu)
5161 continue;
5162 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5163 if (vcpu->cpu != smp_processor_id())
5164 send_ipi = 1;
5165 }
5166 }
5167 raw_spin_unlock(&kvm_lock);
5168
5169 if (freq->old < freq->new && send_ipi) {
5170 /*
5171 * We upscale the frequency. Must make the guest
5172 * doesn't see old kvmclock values while running with
5173 * the new frequency, otherwise we risk the guest sees
5174 * time go backwards.
5175 *
5176 * In case we update the frequency for another cpu
5177 * (which might be in guest context) send an interrupt
5178 * to kick the cpu out of guest context. Next time
5179 * guest context is entered kvmclock will be updated,
5180 * so the guest will not see stale values.
5181 */
5182 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
5183 }
5184 return 0;
5185 }
5186
5187 static struct notifier_block kvmclock_cpufreq_notifier_block = {
5188 .notifier_call = kvmclock_cpufreq_notifier
5189 };
5190
5191 static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5192 unsigned long action, void *hcpu)
5193 {
5194 unsigned int cpu = (unsigned long)hcpu;
5195
5196 switch (action) {
5197 case CPU_ONLINE:
5198 case CPU_DOWN_FAILED:
5199 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5200 break;
5201 case CPU_DOWN_PREPARE:
5202 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5203 break;
5204 }
5205 return NOTIFY_OK;
5206 }
5207
5208 static struct notifier_block kvmclock_cpu_notifier_block = {
5209 .notifier_call = kvmclock_cpu_notifier,
5210 .priority = -INT_MAX
5211 };
5212
5213 static void kvm_timer_init(void)
5214 {
5215 int cpu;
5216
5217 max_tsc_khz = tsc_khz;
5218 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5219 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
5220 #ifdef CONFIG_CPU_FREQ
5221 struct cpufreq_policy policy;
5222 memset(&policy, 0, sizeof(policy));
5223 cpu = get_cpu();
5224 cpufreq_get_policy(&policy, cpu);
5225 if (policy.cpuinfo.max_freq)
5226 max_tsc_khz = policy.cpuinfo.max_freq;
5227 put_cpu();
5228 #endif
5229 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5230 CPUFREQ_TRANSITION_NOTIFIER);
5231 }
5232 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
5233 for_each_online_cpu(cpu)
5234 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5235 }
5236
5237 static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5238
5239 int kvm_is_in_guest(void)
5240 {
5241 return __this_cpu_read(current_vcpu) != NULL;
5242 }
5243
5244 static int kvm_is_user_mode(void)
5245 {
5246 int user_mode = 3;
5247
5248 if (__this_cpu_read(current_vcpu))
5249 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
5250
5251 return user_mode != 0;
5252 }
5253
5254 static unsigned long kvm_get_guest_ip(void)
5255 {
5256 unsigned long ip = 0;
5257
5258 if (__this_cpu_read(current_vcpu))
5259 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
5260
5261 return ip;
5262 }
5263
5264 static struct perf_guest_info_callbacks kvm_guest_cbs = {
5265 .is_in_guest = kvm_is_in_guest,
5266 .is_user_mode = kvm_is_user_mode,
5267 .get_guest_ip = kvm_get_guest_ip,
5268 };
5269
5270 void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5271 {
5272 __this_cpu_write(current_vcpu, vcpu);
5273 }
5274 EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5275
5276 void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5277 {
5278 __this_cpu_write(current_vcpu, NULL);
5279 }
5280 EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5281
5282 static void kvm_set_mmio_spte_mask(void)
5283 {
5284 u64 mask;
5285 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5286
5287 /*
5288 * Set the reserved bits and the present bit of an paging-structure
5289 * entry to generate page fault with PFER.RSV = 1.
5290 */
5291 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5292 mask |= 1ull;
5293
5294 #ifdef CONFIG_X86_64
5295 /*
5296 * If reserved bit is not supported, clear the present bit to disable
5297 * mmio page fault.
5298 */
5299 if (maxphyaddr == 52)
5300 mask &= ~1ull;
5301 #endif
5302
5303 kvm_mmu_set_mmio_spte_mask(mask);
5304 }
5305
5306 #ifdef CONFIG_X86_64
5307 static void pvclock_gtod_update_fn(struct work_struct *work)
5308 {
5309 struct kvm *kvm;
5310
5311 struct kvm_vcpu *vcpu;
5312 int i;
5313
5314 raw_spin_lock(&kvm_lock);
5315 list_for_each_entry(kvm, &vm_list, vm_list)
5316 kvm_for_each_vcpu(i, vcpu, kvm)
5317 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5318 atomic_set(&kvm_guest_has_master_clock, 0);
5319 raw_spin_unlock(&kvm_lock);
5320 }
5321
5322 static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5323
5324 /*
5325 * Notification about pvclock gtod data update.
5326 */
5327 static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5328 void *priv)
5329 {
5330 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5331 struct timekeeper *tk = priv;
5332
5333 update_pvclock_gtod(tk);
5334
5335 /* disable master clock if host does not trust, or does not
5336 * use, TSC clocksource
5337 */
5338 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5339 atomic_read(&kvm_guest_has_master_clock) != 0)
5340 queue_work(system_long_wq, &pvclock_gtod_work);
5341
5342 return 0;
5343 }
5344
5345 static struct notifier_block pvclock_gtod_notifier = {
5346 .notifier_call = pvclock_gtod_notify,
5347 };
5348 #endif
5349
5350 int kvm_arch_init(void *opaque)
5351 {
5352 int r;
5353 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5354
5355 if (kvm_x86_ops) {
5356 printk(KERN_ERR "kvm: already loaded the other module\n");
5357 r = -EEXIST;
5358 goto out;
5359 }
5360
5361 if (!ops->cpu_has_kvm_support()) {
5362 printk(KERN_ERR "kvm: no hardware support\n");
5363 r = -EOPNOTSUPP;
5364 goto out;
5365 }
5366 if (ops->disabled_by_bios()) {
5367 printk(KERN_ERR "kvm: disabled by bios\n");
5368 r = -EOPNOTSUPP;
5369 goto out;
5370 }
5371
5372 r = -ENOMEM;
5373 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5374 if (!shared_msrs) {
5375 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5376 goto out;
5377 }
5378
5379 r = kvm_mmu_module_init();
5380 if (r)
5381 goto out_free_percpu;
5382
5383 kvm_set_mmio_spte_mask();
5384 kvm_init_msr_list();
5385
5386 kvm_x86_ops = ops;
5387 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
5388 PT_DIRTY_MASK, PT64_NX_MASK, 0);
5389
5390 kvm_timer_init();
5391
5392 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5393
5394 if (cpu_has_xsave)
5395 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5396
5397 kvm_lapic_init();
5398 #ifdef CONFIG_X86_64
5399 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5400 #endif
5401
5402 return 0;
5403
5404 out_free_percpu:
5405 free_percpu(shared_msrs);
5406 out:
5407 return r;
5408 }
5409
5410 void kvm_arch_exit(void)
5411 {
5412 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5413
5414 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5415 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5416 CPUFREQ_TRANSITION_NOTIFIER);
5417 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
5418 #ifdef CONFIG_X86_64
5419 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5420 #endif
5421 kvm_x86_ops = NULL;
5422 kvm_mmu_module_exit();
5423 free_percpu(shared_msrs);
5424 }
5425
5426 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5427 {
5428 ++vcpu->stat.halt_exits;
5429 if (irqchip_in_kernel(vcpu->kvm)) {
5430 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
5431 return 1;
5432 } else {
5433 vcpu->run->exit_reason = KVM_EXIT_HLT;
5434 return 0;
5435 }
5436 }
5437 EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5438
5439 int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5440 {
5441 u64 param, ingpa, outgpa, ret;
5442 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5443 bool fast, longmode;
5444 int cs_db, cs_l;
5445
5446 /*
5447 * hypercall generates UD from non zero cpl and real mode
5448 * per HYPER-V spec
5449 */
5450 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
5451 kvm_queue_exception(vcpu, UD_VECTOR);
5452 return 0;
5453 }
5454
5455 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5456 longmode = is_long_mode(vcpu) && cs_l == 1;
5457
5458 if (!longmode) {
5459 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5460 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5461 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5462 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5463 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5464 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
5465 }
5466 #ifdef CONFIG_X86_64
5467 else {
5468 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5469 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5470 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5471 }
5472 #endif
5473
5474 code = param & 0xffff;
5475 fast = (param >> 16) & 0x1;
5476 rep_cnt = (param >> 32) & 0xfff;
5477 rep_idx = (param >> 48) & 0xfff;
5478
5479 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5480
5481 switch (code) {
5482 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5483 kvm_vcpu_on_spin(vcpu);
5484 break;
5485 default:
5486 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5487 break;
5488 }
5489
5490 ret = res | (((u64)rep_done & 0xfff) << 32);
5491 if (longmode) {
5492 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5493 } else {
5494 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5495 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5496 }
5497
5498 return 1;
5499 }
5500
5501 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5502 {
5503 unsigned long nr, a0, a1, a2, a3, ret;
5504 int r = 1;
5505
5506 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5507 return kvm_hv_hypercall(vcpu);
5508
5509 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5510 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5511 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5512 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5513 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
5514
5515 trace_kvm_hypercall(nr, a0, a1, a2, a3);
5516
5517 if (!is_long_mode(vcpu)) {
5518 nr &= 0xFFFFFFFF;
5519 a0 &= 0xFFFFFFFF;
5520 a1 &= 0xFFFFFFFF;
5521 a2 &= 0xFFFFFFFF;
5522 a3 &= 0xFFFFFFFF;
5523 }
5524
5525 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5526 ret = -KVM_EPERM;
5527 goto out;
5528 }
5529
5530 switch (nr) {
5531 case KVM_HC_VAPIC_POLL_IRQ:
5532 ret = 0;
5533 break;
5534 default:
5535 ret = -KVM_ENOSYS;
5536 break;
5537 }
5538 out:
5539 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5540 ++vcpu->stat.hypercalls;
5541 return r;
5542 }
5543 EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5544
5545 static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
5546 {
5547 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5548 char instruction[3];
5549 unsigned long rip = kvm_rip_read(vcpu);
5550
5551 /*
5552 * Blow out the MMU to ensure that no other VCPU has an active mapping
5553 * to ensure that the updated hypercall appears atomically across all
5554 * VCPUs.
5555 */
5556 kvm_mmu_zap_all(vcpu->kvm);
5557
5558 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5559
5560 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
5561 }
5562
5563 /*
5564 * Check if userspace requested an interrupt window, and that the
5565 * interrupt window is open.
5566 *
5567 * No need to exit to userspace if we already have an interrupt queued.
5568 */
5569 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
5570 {
5571 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
5572 vcpu->run->request_interrupt_window &&
5573 kvm_arch_interrupt_allowed(vcpu));
5574 }
5575
5576 static void post_kvm_run_save(struct kvm_vcpu *vcpu)
5577 {
5578 struct kvm_run *kvm_run = vcpu->run;
5579
5580 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
5581 kvm_run->cr8 = kvm_get_cr8(vcpu);
5582 kvm_run->apic_base = kvm_get_apic_base(vcpu);
5583 if (irqchip_in_kernel(vcpu->kvm))
5584 kvm_run->ready_for_interrupt_injection = 1;
5585 else
5586 kvm_run->ready_for_interrupt_injection =
5587 kvm_arch_interrupt_allowed(vcpu) &&
5588 !kvm_cpu_has_interrupt(vcpu) &&
5589 !kvm_event_needs_reinjection(vcpu);
5590 }
5591
5592 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5593 {
5594 int max_irr, tpr;
5595
5596 if (!kvm_x86_ops->update_cr8_intercept)
5597 return;
5598
5599 if (!vcpu->arch.apic)
5600 return;
5601
5602 if (!vcpu->arch.apic->vapic_addr)
5603 max_irr = kvm_lapic_find_highest_irr(vcpu);
5604 else
5605 max_irr = -1;
5606
5607 if (max_irr != -1)
5608 max_irr >>= 4;
5609
5610 tpr = kvm_lapic_get_cr8(vcpu);
5611
5612 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5613 }
5614
5615 static void inject_pending_event(struct kvm_vcpu *vcpu)
5616 {
5617 /* try to reinject previous events if any */
5618 if (vcpu->arch.exception.pending) {
5619 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5620 vcpu->arch.exception.has_error_code,
5621 vcpu->arch.exception.error_code);
5622 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5623 vcpu->arch.exception.has_error_code,
5624 vcpu->arch.exception.error_code,
5625 vcpu->arch.exception.reinject);
5626 return;
5627 }
5628
5629 if (vcpu->arch.nmi_injected) {
5630 kvm_x86_ops->set_nmi(vcpu);
5631 return;
5632 }
5633
5634 if (vcpu->arch.interrupt.pending) {
5635 kvm_x86_ops->set_irq(vcpu);
5636 return;
5637 }
5638
5639 /* try to inject new event if pending */
5640 if (vcpu->arch.nmi_pending) {
5641 if (kvm_x86_ops->nmi_allowed(vcpu)) {
5642 --vcpu->arch.nmi_pending;
5643 vcpu->arch.nmi_injected = true;
5644 kvm_x86_ops->set_nmi(vcpu);
5645 }
5646 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
5647 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
5648 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5649 false);
5650 kvm_x86_ops->set_irq(vcpu);
5651 }
5652 }
5653 }
5654
5655 static void process_nmi(struct kvm_vcpu *vcpu)
5656 {
5657 unsigned limit = 2;
5658
5659 /*
5660 * x86 is limited to one NMI running, and one NMI pending after it.
5661 * If an NMI is already in progress, limit further NMIs to just one.
5662 * Otherwise, allow two (and we'll inject the first one immediately).
5663 */
5664 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5665 limit = 1;
5666
5667 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5668 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5669 kvm_make_request(KVM_REQ_EVENT, vcpu);
5670 }
5671
5672 static void kvm_gen_update_masterclock(struct kvm *kvm)
5673 {
5674 #ifdef CONFIG_X86_64
5675 int i;
5676 struct kvm_vcpu *vcpu;
5677 struct kvm_arch *ka = &kvm->arch;
5678
5679 spin_lock(&ka->pvclock_gtod_sync_lock);
5680 kvm_make_mclock_inprogress_request(kvm);
5681 /* no guest entries from this point */
5682 pvclock_update_vm_gtod_copy(kvm);
5683
5684 kvm_for_each_vcpu(i, vcpu, kvm)
5685 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5686
5687 /* guest entries allowed */
5688 kvm_for_each_vcpu(i, vcpu, kvm)
5689 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5690
5691 spin_unlock(&ka->pvclock_gtod_sync_lock);
5692 #endif
5693 }
5694
5695 static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
5696 {
5697 u64 eoi_exit_bitmap[4];
5698 u32 tmr[8];
5699
5700 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5701 return;
5702
5703 memset(eoi_exit_bitmap, 0, 32);
5704 memset(tmr, 0, 32);
5705
5706 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
5707 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5708 kvm_apic_update_tmr(vcpu, tmr);
5709 }
5710
5711 static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
5712 {
5713 int r;
5714 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
5715 vcpu->run->request_interrupt_window;
5716 bool req_immediate_exit = false;
5717
5718 if (vcpu->requests) {
5719 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
5720 kvm_mmu_unload(vcpu);
5721 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
5722 __kvm_migrate_timers(vcpu);
5723 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5724 kvm_gen_update_masterclock(vcpu->kvm);
5725 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5726 r = kvm_guest_time_update(vcpu);
5727 if (unlikely(r))
5728 goto out;
5729 }
5730 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
5731 kvm_mmu_sync_roots(vcpu);
5732 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
5733 kvm_x86_ops->tlb_flush(vcpu);
5734 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
5735 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
5736 r = 0;
5737 goto out;
5738 }
5739 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
5740 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5741 r = 0;
5742 goto out;
5743 }
5744 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
5745 vcpu->fpu_active = 0;
5746 kvm_x86_ops->fpu_deactivate(vcpu);
5747 }
5748 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5749 /* Page is swapped out. Do synthetic halt */
5750 vcpu->arch.apf.halted = true;
5751 r = 1;
5752 goto out;
5753 }
5754 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5755 record_steal_time(vcpu);
5756 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5757 process_nmi(vcpu);
5758 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5759 kvm_handle_pmu_event(vcpu);
5760 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5761 kvm_deliver_pmi(vcpu);
5762 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5763 vcpu_scan_ioapic(vcpu);
5764 }
5765
5766 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5767 kvm_apic_accept_events(vcpu);
5768 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5769 r = 1;
5770 goto out;
5771 }
5772
5773 inject_pending_event(vcpu);
5774
5775 /* enable NMI/IRQ window open exits if needed */
5776 if (vcpu->arch.nmi_pending)
5777 req_immediate_exit =
5778 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
5779 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
5780 req_immediate_exit =
5781 kvm_x86_ops->enable_irq_window(vcpu) != 0;
5782
5783 if (kvm_lapic_enabled(vcpu)) {
5784 /*
5785 * Update architecture specific hints for APIC
5786 * virtual interrupt delivery.
5787 */
5788 if (kvm_x86_ops->hwapic_irr_update)
5789 kvm_x86_ops->hwapic_irr_update(vcpu,
5790 kvm_lapic_find_highest_irr(vcpu));
5791 update_cr8_intercept(vcpu);
5792 kvm_lapic_sync_to_vapic(vcpu);
5793 }
5794 }
5795
5796 r = kvm_mmu_reload(vcpu);
5797 if (unlikely(r)) {
5798 goto cancel_injection;
5799 }
5800
5801 preempt_disable();
5802
5803 kvm_x86_ops->prepare_guest_switch(vcpu);
5804 if (vcpu->fpu_active)
5805 kvm_load_guest_fpu(vcpu);
5806 kvm_load_guest_xcr0(vcpu);
5807
5808 vcpu->mode = IN_GUEST_MODE;
5809
5810 /* We should set ->mode before check ->requests,
5811 * see the comment in make_all_cpus_request.
5812 */
5813 smp_mb();
5814
5815 local_irq_disable();
5816
5817 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
5818 || need_resched() || signal_pending(current)) {
5819 vcpu->mode = OUTSIDE_GUEST_MODE;
5820 smp_wmb();
5821 local_irq_enable();
5822 preempt_enable();
5823 r = 1;
5824 goto cancel_injection;
5825 }
5826
5827 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5828
5829 if (req_immediate_exit)
5830 smp_send_reschedule(vcpu->cpu);
5831
5832 kvm_guest_enter();
5833
5834 if (unlikely(vcpu->arch.switch_db_regs)) {
5835 set_debugreg(0, 7);
5836 set_debugreg(vcpu->arch.eff_db[0], 0);
5837 set_debugreg(vcpu->arch.eff_db[1], 1);
5838 set_debugreg(vcpu->arch.eff_db[2], 2);
5839 set_debugreg(vcpu->arch.eff_db[3], 3);
5840 }
5841
5842 trace_kvm_entry(vcpu->vcpu_id);
5843 kvm_x86_ops->run(vcpu);
5844
5845 /*
5846 * If the guest has used debug registers, at least dr7
5847 * will be disabled while returning to the host.
5848 * If we don't have active breakpoints in the host, we don't
5849 * care about the messed up debug address registers. But if
5850 * we have some of them active, restore the old state.
5851 */
5852 if (hw_breakpoint_active())
5853 hw_breakpoint_restore();
5854
5855 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5856 native_read_tsc());
5857
5858 vcpu->mode = OUTSIDE_GUEST_MODE;
5859 smp_wmb();
5860
5861 /* Interrupt is enabled by handle_external_intr() */
5862 kvm_x86_ops->handle_external_intr(vcpu);
5863
5864 ++vcpu->stat.exits;
5865
5866 /*
5867 * We must have an instruction between local_irq_enable() and
5868 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5869 * the interrupt shadow. The stat.exits increment will do nicely.
5870 * But we need to prevent reordering, hence this barrier():
5871 */
5872 barrier();
5873
5874 kvm_guest_exit();
5875
5876 preempt_enable();
5877
5878 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5879
5880 /*
5881 * Profile KVM exit RIPs:
5882 */
5883 if (unlikely(prof_on == KVM_PROFILING)) {
5884 unsigned long rip = kvm_rip_read(vcpu);
5885 profile_hit(KVM_PROFILING, (void *)rip);
5886 }
5887
5888 if (unlikely(vcpu->arch.tsc_always_catchup))
5889 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
5890
5891 if (vcpu->arch.apic_attention)
5892 kvm_lapic_sync_from_vapic(vcpu);
5893
5894 r = kvm_x86_ops->handle_exit(vcpu);
5895 return r;
5896
5897 cancel_injection:
5898 kvm_x86_ops->cancel_injection(vcpu);
5899 if (unlikely(vcpu->arch.apic_attention))
5900 kvm_lapic_sync_from_vapic(vcpu);
5901 out:
5902 return r;
5903 }
5904
5905
5906 static int __vcpu_run(struct kvm_vcpu *vcpu)
5907 {
5908 int r;
5909 struct kvm *kvm = vcpu->kvm;
5910
5911 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5912
5913 r = 1;
5914 while (r > 0) {
5915 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5916 !vcpu->arch.apf.halted)
5917 r = vcpu_enter_guest(vcpu);
5918 else {
5919 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5920 kvm_vcpu_block(vcpu);
5921 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5922 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
5923 kvm_apic_accept_events(vcpu);
5924 switch(vcpu->arch.mp_state) {
5925 case KVM_MP_STATE_HALTED:
5926 vcpu->arch.mp_state =
5927 KVM_MP_STATE_RUNNABLE;
5928 case KVM_MP_STATE_RUNNABLE:
5929 vcpu->arch.apf.halted = false;
5930 break;
5931 case KVM_MP_STATE_INIT_RECEIVED:
5932 break;
5933 default:
5934 r = -EINTR;
5935 break;
5936 }
5937 }
5938 }
5939
5940 if (r <= 0)
5941 break;
5942
5943 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5944 if (kvm_cpu_has_pending_timer(vcpu))
5945 kvm_inject_pending_timer_irqs(vcpu);
5946
5947 if (dm_request_for_irq_injection(vcpu)) {
5948 r = -EINTR;
5949 vcpu->run->exit_reason = KVM_EXIT_INTR;
5950 ++vcpu->stat.request_irq_exits;
5951 }
5952
5953 kvm_check_async_pf_completion(vcpu);
5954
5955 if (signal_pending(current)) {
5956 r = -EINTR;
5957 vcpu->run->exit_reason = KVM_EXIT_INTR;
5958 ++vcpu->stat.signal_exits;
5959 }
5960 if (need_resched()) {
5961 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5962 kvm_resched(vcpu);
5963 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
5964 }
5965 }
5966
5967 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5968
5969 return r;
5970 }
5971
5972 static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5973 {
5974 int r;
5975 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5976 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5977 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5978 if (r != EMULATE_DONE)
5979 return 0;
5980 return 1;
5981 }
5982
5983 static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5984 {
5985 BUG_ON(!vcpu->arch.pio.count);
5986
5987 return complete_emulated_io(vcpu);
5988 }
5989
5990 /*
5991 * Implements the following, as a state machine:
5992 *
5993 * read:
5994 * for each fragment
5995 * for each mmio piece in the fragment
5996 * write gpa, len
5997 * exit
5998 * copy data
5999 * execute insn
6000 *
6001 * write:
6002 * for each fragment
6003 * for each mmio piece in the fragment
6004 * write gpa, len
6005 * copy data
6006 * exit
6007 */
6008 static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
6009 {
6010 struct kvm_run *run = vcpu->run;
6011 struct kvm_mmio_fragment *frag;
6012 unsigned len;
6013
6014 BUG_ON(!vcpu->mmio_needed);
6015
6016 /* Complete previous fragment */
6017 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6018 len = min(8u, frag->len);
6019 if (!vcpu->mmio_is_write)
6020 memcpy(frag->data, run->mmio.data, len);
6021
6022 if (frag->len <= 8) {
6023 /* Switch to the next fragment. */
6024 frag++;
6025 vcpu->mmio_cur_fragment++;
6026 } else {
6027 /* Go forward to the next mmio piece. */
6028 frag->data += len;
6029 frag->gpa += len;
6030 frag->len -= len;
6031 }
6032
6033 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
6034 vcpu->mmio_needed = 0;
6035 if (vcpu->mmio_is_write)
6036 return 1;
6037 vcpu->mmio_read_completed = 1;
6038 return complete_emulated_io(vcpu);
6039 }
6040
6041 run->exit_reason = KVM_EXIT_MMIO;
6042 run->mmio.phys_addr = frag->gpa;
6043 if (vcpu->mmio_is_write)
6044 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6045 run->mmio.len = min(8u, frag->len);
6046 run->mmio.is_write = vcpu->mmio_is_write;
6047 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6048 return 0;
6049 }
6050
6051
6052 int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6053 {
6054 int r;
6055 sigset_t sigsaved;
6056
6057 if (!tsk_used_math(current) && init_fpu(current))
6058 return -ENOMEM;
6059
6060 if (vcpu->sigset_active)
6061 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6062
6063 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
6064 kvm_vcpu_block(vcpu);
6065 kvm_apic_accept_events(vcpu);
6066 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
6067 r = -EAGAIN;
6068 goto out;
6069 }
6070
6071 /* re-sync apic's tpr */
6072 if (!irqchip_in_kernel(vcpu->kvm)) {
6073 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6074 r = -EINVAL;
6075 goto out;
6076 }
6077 }
6078
6079 if (unlikely(vcpu->arch.complete_userspace_io)) {
6080 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6081 vcpu->arch.complete_userspace_io = NULL;
6082 r = cui(vcpu);
6083 if (r <= 0)
6084 goto out;
6085 } else
6086 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
6087
6088 r = __vcpu_run(vcpu);
6089
6090 out:
6091 post_kvm_run_save(vcpu);
6092 if (vcpu->sigset_active)
6093 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6094
6095 return r;
6096 }
6097
6098 int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6099 {
6100 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6101 /*
6102 * We are here if userspace calls get_regs() in the middle of
6103 * instruction emulation. Registers state needs to be copied
6104 * back from emulation context to vcpu. Userspace shouldn't do
6105 * that usually, but some bad designed PV devices (vmware
6106 * backdoor interface) need this to work
6107 */
6108 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
6109 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6110 }
6111 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6112 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6113 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6114 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6115 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6116 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6117 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6118 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
6119 #ifdef CONFIG_X86_64
6120 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6121 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6122 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6123 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6124 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6125 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6126 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6127 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
6128 #endif
6129
6130 regs->rip = kvm_rip_read(vcpu);
6131 regs->rflags = kvm_get_rflags(vcpu);
6132
6133 return 0;
6134 }
6135
6136 int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6137 {
6138 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6139 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6140
6141 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6142 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6143 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6144 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6145 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6146 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6147 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6148 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
6149 #ifdef CONFIG_X86_64
6150 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6151 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6152 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6153 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6154 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6155 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6156 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6157 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
6158 #endif
6159
6160 kvm_rip_write(vcpu, regs->rip);
6161 kvm_set_rflags(vcpu, regs->rflags);
6162
6163 vcpu->arch.exception.pending = false;
6164
6165 kvm_make_request(KVM_REQ_EVENT, vcpu);
6166
6167 return 0;
6168 }
6169
6170 void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6171 {
6172 struct kvm_segment cs;
6173
6174 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6175 *db = cs.db;
6176 *l = cs.l;
6177 }
6178 EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6179
6180 int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6181 struct kvm_sregs *sregs)
6182 {
6183 struct desc_ptr dt;
6184
6185 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6186 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6187 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6188 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6189 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6190 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6191
6192 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6193 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6194
6195 kvm_x86_ops->get_idt(vcpu, &dt);
6196 sregs->idt.limit = dt.size;
6197 sregs->idt.base = dt.address;
6198 kvm_x86_ops->get_gdt(vcpu, &dt);
6199 sregs->gdt.limit = dt.size;
6200 sregs->gdt.base = dt.address;
6201
6202 sregs->cr0 = kvm_read_cr0(vcpu);
6203 sregs->cr2 = vcpu->arch.cr2;
6204 sregs->cr3 = kvm_read_cr3(vcpu);
6205 sregs->cr4 = kvm_read_cr4(vcpu);
6206 sregs->cr8 = kvm_get_cr8(vcpu);
6207 sregs->efer = vcpu->arch.efer;
6208 sregs->apic_base = kvm_get_apic_base(vcpu);
6209
6210 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
6211
6212 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
6213 set_bit(vcpu->arch.interrupt.nr,
6214 (unsigned long *)sregs->interrupt_bitmap);
6215
6216 return 0;
6217 }
6218
6219 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6220 struct kvm_mp_state *mp_state)
6221 {
6222 kvm_apic_accept_events(vcpu);
6223 mp_state->mp_state = vcpu->arch.mp_state;
6224 return 0;
6225 }
6226
6227 int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6228 struct kvm_mp_state *mp_state)
6229 {
6230 if (!kvm_vcpu_has_lapic(vcpu) &&
6231 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6232 return -EINVAL;
6233
6234 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6235 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6236 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6237 } else
6238 vcpu->arch.mp_state = mp_state->mp_state;
6239 kvm_make_request(KVM_REQ_EVENT, vcpu);
6240 return 0;
6241 }
6242
6243 int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6244 int reason, bool has_error_code, u32 error_code)
6245 {
6246 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6247 int ret;
6248
6249 init_emulate_ctxt(vcpu);
6250
6251 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
6252 has_error_code, error_code);
6253
6254 if (ret)
6255 return EMULATE_FAIL;
6256
6257 kvm_rip_write(vcpu, ctxt->eip);
6258 kvm_set_rflags(vcpu, ctxt->eflags);
6259 kvm_make_request(KVM_REQ_EVENT, vcpu);
6260 return EMULATE_DONE;
6261 }
6262 EXPORT_SYMBOL_GPL(kvm_task_switch);
6263
6264 int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6265 struct kvm_sregs *sregs)
6266 {
6267 int mmu_reset_needed = 0;
6268 int pending_vec, max_bits, idx;
6269 struct desc_ptr dt;
6270
6271 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6272 return -EINVAL;
6273
6274 dt.size = sregs->idt.limit;
6275 dt.address = sregs->idt.base;
6276 kvm_x86_ops->set_idt(vcpu, &dt);
6277 dt.size = sregs->gdt.limit;
6278 dt.address = sregs->gdt.base;
6279 kvm_x86_ops->set_gdt(vcpu, &dt);
6280
6281 vcpu->arch.cr2 = sregs->cr2;
6282 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
6283 vcpu->arch.cr3 = sregs->cr3;
6284 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
6285
6286 kvm_set_cr8(vcpu, sregs->cr8);
6287
6288 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
6289 kvm_x86_ops->set_efer(vcpu, sregs->efer);
6290 kvm_set_apic_base(vcpu, sregs->apic_base);
6291
6292 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
6293 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
6294 vcpu->arch.cr0 = sregs->cr0;
6295
6296 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
6297 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
6298 if (sregs->cr4 & X86_CR4_OSXSAVE)
6299 kvm_update_cpuid(vcpu);
6300
6301 idx = srcu_read_lock(&vcpu->kvm->srcu);
6302 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
6303 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
6304 mmu_reset_needed = 1;
6305 }
6306 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6307
6308 if (mmu_reset_needed)
6309 kvm_mmu_reset_context(vcpu);
6310
6311 max_bits = KVM_NR_INTERRUPTS;
6312 pending_vec = find_first_bit(
6313 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6314 if (pending_vec < max_bits) {
6315 kvm_queue_interrupt(vcpu, pending_vec, false);
6316 pr_debug("Set back pending irq %d\n", pending_vec);
6317 }
6318
6319 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6320 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6321 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6322 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6323 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6324 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
6325
6326 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6327 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
6328
6329 update_cr8_intercept(vcpu);
6330
6331 /* Older userspace won't unhalt the vcpu on reset. */
6332 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
6333 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
6334 !is_protmode(vcpu))
6335 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6336
6337 kvm_make_request(KVM_REQ_EVENT, vcpu);
6338
6339 return 0;
6340 }
6341
6342 int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6343 struct kvm_guest_debug *dbg)
6344 {
6345 unsigned long rflags;
6346 int i, r;
6347
6348 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6349 r = -EBUSY;
6350 if (vcpu->arch.exception.pending)
6351 goto out;
6352 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6353 kvm_queue_exception(vcpu, DB_VECTOR);
6354 else
6355 kvm_queue_exception(vcpu, BP_VECTOR);
6356 }
6357
6358 /*
6359 * Read rflags as long as potentially injected trace flags are still
6360 * filtered out.
6361 */
6362 rflags = kvm_get_rflags(vcpu);
6363
6364 vcpu->guest_debug = dbg->control;
6365 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6366 vcpu->guest_debug = 0;
6367
6368 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
6369 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6370 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
6371 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
6372 } else {
6373 for (i = 0; i < KVM_NR_DB_REGS; i++)
6374 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
6375 }
6376 kvm_update_dr7(vcpu);
6377
6378 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6379 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6380 get_segment_base(vcpu, VCPU_SREG_CS);
6381
6382 /*
6383 * Trigger an rflags update that will inject or remove the trace
6384 * flags.
6385 */
6386 kvm_set_rflags(vcpu, rflags);
6387
6388 kvm_x86_ops->update_db_bp_intercept(vcpu);
6389
6390 r = 0;
6391
6392 out:
6393
6394 return r;
6395 }
6396
6397 /*
6398 * Translate a guest virtual address to a guest physical address.
6399 */
6400 int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6401 struct kvm_translation *tr)
6402 {
6403 unsigned long vaddr = tr->linear_address;
6404 gpa_t gpa;
6405 int idx;
6406
6407 idx = srcu_read_lock(&vcpu->kvm->srcu);
6408 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
6409 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6410 tr->physical_address = gpa;
6411 tr->valid = gpa != UNMAPPED_GVA;
6412 tr->writeable = 1;
6413 tr->usermode = 0;
6414
6415 return 0;
6416 }
6417
6418 int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6419 {
6420 struct i387_fxsave_struct *fxsave =
6421 &vcpu->arch.guest_fpu.state->fxsave;
6422
6423 memcpy(fpu->fpr, fxsave->st_space, 128);
6424 fpu->fcw = fxsave->cwd;
6425 fpu->fsw = fxsave->swd;
6426 fpu->ftwx = fxsave->twd;
6427 fpu->last_opcode = fxsave->fop;
6428 fpu->last_ip = fxsave->rip;
6429 fpu->last_dp = fxsave->rdp;
6430 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6431
6432 return 0;
6433 }
6434
6435 int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6436 {
6437 struct i387_fxsave_struct *fxsave =
6438 &vcpu->arch.guest_fpu.state->fxsave;
6439
6440 memcpy(fxsave->st_space, fpu->fpr, 128);
6441 fxsave->cwd = fpu->fcw;
6442 fxsave->swd = fpu->fsw;
6443 fxsave->twd = fpu->ftwx;
6444 fxsave->fop = fpu->last_opcode;
6445 fxsave->rip = fpu->last_ip;
6446 fxsave->rdp = fpu->last_dp;
6447 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6448
6449 return 0;
6450 }
6451
6452 int fx_init(struct kvm_vcpu *vcpu)
6453 {
6454 int err;
6455
6456 err = fpu_alloc(&vcpu->arch.guest_fpu);
6457 if (err)
6458 return err;
6459
6460 fpu_finit(&vcpu->arch.guest_fpu);
6461
6462 /*
6463 * Ensure guest xcr0 is valid for loading
6464 */
6465 vcpu->arch.xcr0 = XSTATE_FP;
6466
6467 vcpu->arch.cr0 |= X86_CR0_ET;
6468
6469 return 0;
6470 }
6471 EXPORT_SYMBOL_GPL(fx_init);
6472
6473 static void fx_free(struct kvm_vcpu *vcpu)
6474 {
6475 fpu_free(&vcpu->arch.guest_fpu);
6476 }
6477
6478 void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6479 {
6480 if (vcpu->guest_fpu_loaded)
6481 return;
6482
6483 /*
6484 * Restore all possible states in the guest,
6485 * and assume host would use all available bits.
6486 * Guest xcr0 would be loaded later.
6487 */
6488 kvm_put_guest_xcr0(vcpu);
6489 vcpu->guest_fpu_loaded = 1;
6490 __kernel_fpu_begin();
6491 fpu_restore_checking(&vcpu->arch.guest_fpu);
6492 trace_kvm_fpu(1);
6493 }
6494
6495 void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6496 {
6497 kvm_put_guest_xcr0(vcpu);
6498
6499 if (!vcpu->guest_fpu_loaded)
6500 return;
6501
6502 vcpu->guest_fpu_loaded = 0;
6503 fpu_save_init(&vcpu->arch.guest_fpu);
6504 __kernel_fpu_end();
6505 ++vcpu->stat.fpu_reload;
6506 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
6507 trace_kvm_fpu(0);
6508 }
6509
6510 void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6511 {
6512 kvmclock_reset(vcpu);
6513
6514 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6515 fx_free(vcpu);
6516 kvm_x86_ops->vcpu_free(vcpu);
6517 }
6518
6519 struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6520 unsigned int id)
6521 {
6522 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6523 printk_once(KERN_WARNING
6524 "kvm: SMP vm created on host with unstable TSC; "
6525 "guest TSC will not be reliable\n");
6526 return kvm_x86_ops->vcpu_create(kvm, id);
6527 }
6528
6529 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6530 {
6531 int r;
6532
6533 vcpu->arch.mtrr_state.have_fixed = 1;
6534 r = vcpu_load(vcpu);
6535 if (r)
6536 return r;
6537 kvm_vcpu_reset(vcpu);
6538 r = kvm_mmu_setup(vcpu);
6539 vcpu_put(vcpu);
6540
6541 return r;
6542 }
6543
6544 int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6545 {
6546 int r;
6547 struct msr_data msr;
6548
6549 r = vcpu_load(vcpu);
6550 if (r)
6551 return r;
6552 msr.data = 0x0;
6553 msr.index = MSR_IA32_TSC;
6554 msr.host_initiated = true;
6555 kvm_write_tsc(vcpu, &msr);
6556 vcpu_put(vcpu);
6557
6558 return r;
6559 }
6560
6561 void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
6562 {
6563 int r;
6564 vcpu->arch.apf.msr_val = 0;
6565
6566 r = vcpu_load(vcpu);
6567 BUG_ON(r);
6568 kvm_mmu_unload(vcpu);
6569 vcpu_put(vcpu);
6570
6571 fx_free(vcpu);
6572 kvm_x86_ops->vcpu_free(vcpu);
6573 }
6574
6575 void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
6576 {
6577 atomic_set(&vcpu->arch.nmi_queued, 0);
6578 vcpu->arch.nmi_pending = 0;
6579 vcpu->arch.nmi_injected = false;
6580
6581 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6582 vcpu->arch.dr6 = DR6_FIXED_1;
6583 vcpu->arch.dr7 = DR7_FIXED_1;
6584 kvm_update_dr7(vcpu);
6585
6586 kvm_make_request(KVM_REQ_EVENT, vcpu);
6587 vcpu->arch.apf.msr_val = 0;
6588 vcpu->arch.st.msr_val = 0;
6589
6590 kvmclock_reset(vcpu);
6591
6592 kvm_clear_async_pf_completion_queue(vcpu);
6593 kvm_async_pf_hash_reset(vcpu);
6594 vcpu->arch.apf.halted = false;
6595
6596 kvm_pmu_reset(vcpu);
6597
6598 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6599 vcpu->arch.regs_avail = ~0;
6600 vcpu->arch.regs_dirty = ~0;
6601
6602 kvm_x86_ops->vcpu_reset(vcpu);
6603 }
6604
6605 void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6606 {
6607 struct kvm_segment cs;
6608
6609 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6610 cs.selector = vector << 8;
6611 cs.base = vector << 12;
6612 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6613 kvm_rip_write(vcpu, 0);
6614 }
6615
6616 int kvm_arch_hardware_enable(void *garbage)
6617 {
6618 struct kvm *kvm;
6619 struct kvm_vcpu *vcpu;
6620 int i;
6621 int ret;
6622 u64 local_tsc;
6623 u64 max_tsc = 0;
6624 bool stable, backwards_tsc = false;
6625
6626 kvm_shared_msr_cpu_online();
6627 ret = kvm_x86_ops->hardware_enable(garbage);
6628 if (ret != 0)
6629 return ret;
6630
6631 local_tsc = native_read_tsc();
6632 stable = !check_tsc_unstable();
6633 list_for_each_entry(kvm, &vm_list, vm_list) {
6634 kvm_for_each_vcpu(i, vcpu, kvm) {
6635 if (!stable && vcpu->cpu == smp_processor_id())
6636 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6637 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6638 backwards_tsc = true;
6639 if (vcpu->arch.last_host_tsc > max_tsc)
6640 max_tsc = vcpu->arch.last_host_tsc;
6641 }
6642 }
6643 }
6644
6645 /*
6646 * Sometimes, even reliable TSCs go backwards. This happens on
6647 * platforms that reset TSC during suspend or hibernate actions, but
6648 * maintain synchronization. We must compensate. Fortunately, we can
6649 * detect that condition here, which happens early in CPU bringup,
6650 * before any KVM threads can be running. Unfortunately, we can't
6651 * bring the TSCs fully up to date with real time, as we aren't yet far
6652 * enough into CPU bringup that we know how much real time has actually
6653 * elapsed; our helper function, get_kernel_ns() will be using boot
6654 * variables that haven't been updated yet.
6655 *
6656 * So we simply find the maximum observed TSC above, then record the
6657 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6658 * the adjustment will be applied. Note that we accumulate
6659 * adjustments, in case multiple suspend cycles happen before some VCPU
6660 * gets a chance to run again. In the event that no KVM threads get a
6661 * chance to run, we will miss the entire elapsed period, as we'll have
6662 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6663 * loose cycle time. This isn't too big a deal, since the loss will be
6664 * uniform across all VCPUs (not to mention the scenario is extremely
6665 * unlikely). It is possible that a second hibernate recovery happens
6666 * much faster than a first, causing the observed TSC here to be
6667 * smaller; this would require additional padding adjustment, which is
6668 * why we set last_host_tsc to the local tsc observed here.
6669 *
6670 * N.B. - this code below runs only on platforms with reliable TSC,
6671 * as that is the only way backwards_tsc is set above. Also note
6672 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6673 * have the same delta_cyc adjustment applied if backwards_tsc
6674 * is detected. Note further, this adjustment is only done once,
6675 * as we reset last_host_tsc on all VCPUs to stop this from being
6676 * called multiple times (one for each physical CPU bringup).
6677 *
6678 * Platforms with unreliable TSCs don't have to deal with this, they
6679 * will be compensated by the logic in vcpu_load, which sets the TSC to
6680 * catchup mode. This will catchup all VCPUs to real time, but cannot
6681 * guarantee that they stay in perfect synchronization.
6682 */
6683 if (backwards_tsc) {
6684 u64 delta_cyc = max_tsc - local_tsc;
6685 list_for_each_entry(kvm, &vm_list, vm_list) {
6686 kvm_for_each_vcpu(i, vcpu, kvm) {
6687 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6688 vcpu->arch.last_host_tsc = local_tsc;
6689 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6690 &vcpu->requests);
6691 }
6692
6693 /*
6694 * We have to disable TSC offset matching.. if you were
6695 * booting a VM while issuing an S4 host suspend....
6696 * you may have some problem. Solving this issue is
6697 * left as an exercise to the reader.
6698 */
6699 kvm->arch.last_tsc_nsec = 0;
6700 kvm->arch.last_tsc_write = 0;
6701 }
6702
6703 }
6704 return 0;
6705 }
6706
6707 void kvm_arch_hardware_disable(void *garbage)
6708 {
6709 kvm_x86_ops->hardware_disable(garbage);
6710 drop_user_return_notifiers(garbage);
6711 }
6712
6713 int kvm_arch_hardware_setup(void)
6714 {
6715 return kvm_x86_ops->hardware_setup();
6716 }
6717
6718 void kvm_arch_hardware_unsetup(void)
6719 {
6720 kvm_x86_ops->hardware_unsetup();
6721 }
6722
6723 void kvm_arch_check_processor_compat(void *rtn)
6724 {
6725 kvm_x86_ops->check_processor_compatibility(rtn);
6726 }
6727
6728 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6729 {
6730 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6731 }
6732
6733 struct static_key kvm_no_apic_vcpu __read_mostly;
6734
6735 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6736 {
6737 struct page *page;
6738 struct kvm *kvm;
6739 int r;
6740
6741 BUG_ON(vcpu->kvm == NULL);
6742 kvm = vcpu->kvm;
6743
6744 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
6745 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
6746 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6747 else
6748 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
6749
6750 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6751 if (!page) {
6752 r = -ENOMEM;
6753 goto fail;
6754 }
6755 vcpu->arch.pio_data = page_address(page);
6756
6757 kvm_set_tsc_khz(vcpu, max_tsc_khz);
6758
6759 r = kvm_mmu_create(vcpu);
6760 if (r < 0)
6761 goto fail_free_pio_data;
6762
6763 if (irqchip_in_kernel(kvm)) {
6764 r = kvm_create_lapic(vcpu);
6765 if (r < 0)
6766 goto fail_mmu_destroy;
6767 } else
6768 static_key_slow_inc(&kvm_no_apic_vcpu);
6769
6770 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6771 GFP_KERNEL);
6772 if (!vcpu->arch.mce_banks) {
6773 r = -ENOMEM;
6774 goto fail_free_lapic;
6775 }
6776 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6777
6778 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6779 r = -ENOMEM;
6780 goto fail_free_mce_banks;
6781 }
6782
6783 r = fx_init(vcpu);
6784 if (r)
6785 goto fail_free_wbinvd_dirty_mask;
6786
6787 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
6788 vcpu->arch.pv_time_enabled = false;
6789 kvm_async_pf_hash_reset(vcpu);
6790 kvm_pmu_init(vcpu);
6791
6792 return 0;
6793 fail_free_wbinvd_dirty_mask:
6794 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
6795 fail_free_mce_banks:
6796 kfree(vcpu->arch.mce_banks);
6797 fail_free_lapic:
6798 kvm_free_lapic(vcpu);
6799 fail_mmu_destroy:
6800 kvm_mmu_destroy(vcpu);
6801 fail_free_pio_data:
6802 free_page((unsigned long)vcpu->arch.pio_data);
6803 fail:
6804 return r;
6805 }
6806
6807 void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6808 {
6809 int idx;
6810
6811 kvm_pmu_destroy(vcpu);
6812 kfree(vcpu->arch.mce_banks);
6813 kvm_free_lapic(vcpu);
6814 idx = srcu_read_lock(&vcpu->kvm->srcu);
6815 kvm_mmu_destroy(vcpu);
6816 srcu_read_unlock(&vcpu->kvm->srcu, idx);
6817 free_page((unsigned long)vcpu->arch.pio_data);
6818 if (!irqchip_in_kernel(vcpu->kvm))
6819 static_key_slow_dec(&kvm_no_apic_vcpu);
6820 }
6821
6822 int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
6823 {
6824 if (type)
6825 return -EINVAL;
6826
6827 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6828 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
6829
6830 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6831 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
6832 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6833 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6834 &kvm->arch.irq_sources_bitmap);
6835
6836 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
6837 mutex_init(&kvm->arch.apic_map_lock);
6838 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6839
6840 pvclock_update_vm_gtod_copy(kvm);
6841
6842 return 0;
6843 }
6844
6845 static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6846 {
6847 int r;
6848 r = vcpu_load(vcpu);
6849 BUG_ON(r);
6850 kvm_mmu_unload(vcpu);
6851 vcpu_put(vcpu);
6852 }
6853
6854 static void kvm_free_vcpus(struct kvm *kvm)
6855 {
6856 unsigned int i;
6857 struct kvm_vcpu *vcpu;
6858
6859 /*
6860 * Unpin any mmu pages first.
6861 */
6862 kvm_for_each_vcpu(i, vcpu, kvm) {
6863 kvm_clear_async_pf_completion_queue(vcpu);
6864 kvm_unload_vcpu_mmu(vcpu);
6865 }
6866 kvm_for_each_vcpu(i, vcpu, kvm)
6867 kvm_arch_vcpu_free(vcpu);
6868
6869 mutex_lock(&kvm->lock);
6870 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6871 kvm->vcpus[i] = NULL;
6872
6873 atomic_set(&kvm->online_vcpus, 0);
6874 mutex_unlock(&kvm->lock);
6875 }
6876
6877 void kvm_arch_sync_events(struct kvm *kvm)
6878 {
6879 kvm_free_all_assigned_devices(kvm);
6880 kvm_free_pit(kvm);
6881 }
6882
6883 void kvm_arch_destroy_vm(struct kvm *kvm)
6884 {
6885 if (current->mm == kvm->mm) {
6886 /*
6887 * Free memory regions allocated on behalf of userspace,
6888 * unless the the memory map has changed due to process exit
6889 * or fd copying.
6890 */
6891 struct kvm_userspace_memory_region mem;
6892 memset(&mem, 0, sizeof(mem));
6893 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
6894 kvm_set_memory_region(kvm, &mem);
6895
6896 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
6897 kvm_set_memory_region(kvm, &mem);
6898
6899 mem.slot = TSS_PRIVATE_MEMSLOT;
6900 kvm_set_memory_region(kvm, &mem);
6901 }
6902 kvm_iommu_unmap_guest(kvm);
6903 kfree(kvm->arch.vpic);
6904 kfree(kvm->arch.vioapic);
6905 kvm_free_vcpus(kvm);
6906 if (kvm->arch.apic_access_page)
6907 put_page(kvm->arch.apic_access_page);
6908 if (kvm->arch.ept_identity_pagetable)
6909 put_page(kvm->arch.ept_identity_pagetable);
6910 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
6911 }
6912
6913 void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6914 struct kvm_memory_slot *dont)
6915 {
6916 int i;
6917
6918 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6919 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6920 kvm_kvfree(free->arch.rmap[i]);
6921 free->arch.rmap[i] = NULL;
6922 }
6923 if (i == 0)
6924 continue;
6925
6926 if (!dont || free->arch.lpage_info[i - 1] !=
6927 dont->arch.lpage_info[i - 1]) {
6928 kvm_kvfree(free->arch.lpage_info[i - 1]);
6929 free->arch.lpage_info[i - 1] = NULL;
6930 }
6931 }
6932 }
6933
6934 int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6935 {
6936 int i;
6937
6938 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6939 unsigned long ugfn;
6940 int lpages;
6941 int level = i + 1;
6942
6943 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6944 slot->base_gfn, level) + 1;
6945
6946 slot->arch.rmap[i] =
6947 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6948 if (!slot->arch.rmap[i])
6949 goto out_free;
6950 if (i == 0)
6951 continue;
6952
6953 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6954 sizeof(*slot->arch.lpage_info[i - 1]));
6955 if (!slot->arch.lpage_info[i - 1])
6956 goto out_free;
6957
6958 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
6959 slot->arch.lpage_info[i - 1][0].write_count = 1;
6960 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
6961 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
6962 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6963 /*
6964 * If the gfn and userspace address are not aligned wrt each
6965 * other, or if explicitly asked to, disable large page
6966 * support for this slot
6967 */
6968 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6969 !kvm_largepages_enabled()) {
6970 unsigned long j;
6971
6972 for (j = 0; j < lpages; ++j)
6973 slot->arch.lpage_info[i - 1][j].write_count = 1;
6974 }
6975 }
6976
6977 return 0;
6978
6979 out_free:
6980 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6981 kvm_kvfree(slot->arch.rmap[i]);
6982 slot->arch.rmap[i] = NULL;
6983 if (i == 0)
6984 continue;
6985
6986 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6987 slot->arch.lpage_info[i - 1] = NULL;
6988 }
6989 return -ENOMEM;
6990 }
6991
6992 int kvm_arch_prepare_memory_region(struct kvm *kvm,
6993 struct kvm_memory_slot *memslot,
6994 struct kvm_userspace_memory_region *mem,
6995 enum kvm_mr_change change)
6996 {
6997 /*
6998 * Only private memory slots need to be mapped here since
6999 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
7000 */
7001 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7002 unsigned long userspace_addr;
7003
7004 /*
7005 * MAP_SHARED to prevent internal slot pages from being moved
7006 * by fork()/COW.
7007 */
7008 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7009 PROT_READ | PROT_WRITE,
7010 MAP_SHARED | MAP_ANONYMOUS, 0);
7011
7012 if (IS_ERR((void *)userspace_addr))
7013 return PTR_ERR((void *)userspace_addr);
7014
7015 memslot->userspace_addr = userspace_addr;
7016 }
7017
7018 return 0;
7019 }
7020
7021 void kvm_arch_commit_memory_region(struct kvm *kvm,
7022 struct kvm_userspace_memory_region *mem,
7023 const struct kvm_memory_slot *old,
7024 enum kvm_mr_change change)
7025 {
7026
7027 int nr_mmu_pages = 0;
7028
7029 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
7030 int ret;
7031
7032 ret = vm_munmap(old->userspace_addr,
7033 old->npages * PAGE_SIZE);
7034 if (ret < 0)
7035 printk(KERN_WARNING
7036 "kvm_vm_ioctl_set_memory_region: "
7037 "failed to munmap memory\n");
7038 }
7039
7040 if (!kvm->arch.n_requested_mmu_pages)
7041 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7042
7043 if (nr_mmu_pages)
7044 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
7045 /*
7046 * Write protect all pages for dirty logging.
7047 * Existing largepage mappings are destroyed here and new ones will
7048 * not be created until the end of the logging.
7049 */
7050 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
7051 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7052 /*
7053 * If memory slot is created, or moved, we need to clear all
7054 * mmio sptes.
7055 */
7056 if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
7057 kvm_mmu_zap_mmio_sptes(kvm);
7058 kvm_reload_remote_mmus(kvm);
7059 }
7060 }
7061
7062 void kvm_arch_flush_shadow_all(struct kvm *kvm)
7063 {
7064 kvm_mmu_zap_all(kvm);
7065 kvm_reload_remote_mmus(kvm);
7066 }
7067
7068 void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7069 struct kvm_memory_slot *slot)
7070 {
7071 kvm_arch_flush_shadow_all(kvm);
7072 }
7073
7074 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7075 {
7076 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7077 !vcpu->arch.apf.halted)
7078 || !list_empty_careful(&vcpu->async_pf.done)
7079 || kvm_apic_has_events(vcpu)
7080 || atomic_read(&vcpu->arch.nmi_queued) ||
7081 (kvm_arch_interrupt_allowed(vcpu) &&
7082 kvm_cpu_has_interrupt(vcpu));
7083 }
7084
7085 int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
7086 {
7087 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
7088 }
7089
7090 int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7091 {
7092 return kvm_x86_ops->interrupt_allowed(vcpu);
7093 }
7094
7095 bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7096 {
7097 unsigned long current_rip = kvm_rip_read(vcpu) +
7098 get_segment_base(vcpu, VCPU_SREG_CS);
7099
7100 return current_rip == linear_rip;
7101 }
7102 EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7103
7104 unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7105 {
7106 unsigned long rflags;
7107
7108 rflags = kvm_x86_ops->get_rflags(vcpu);
7109 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7110 rflags &= ~X86_EFLAGS_TF;
7111 return rflags;
7112 }
7113 EXPORT_SYMBOL_GPL(kvm_get_rflags);
7114
7115 void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7116 {
7117 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
7118 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
7119 rflags |= X86_EFLAGS_TF;
7120 kvm_x86_ops->set_rflags(vcpu, rflags);
7121 kvm_make_request(KVM_REQ_EVENT, vcpu);
7122 }
7123 EXPORT_SYMBOL_GPL(kvm_set_rflags);
7124
7125 void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7126 {
7127 int r;
7128
7129 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
7130 is_error_page(work->page))
7131 return;
7132
7133 r = kvm_mmu_reload(vcpu);
7134 if (unlikely(r))
7135 return;
7136
7137 if (!vcpu->arch.mmu.direct_map &&
7138 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7139 return;
7140
7141 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7142 }
7143
7144 static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7145 {
7146 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7147 }
7148
7149 static inline u32 kvm_async_pf_next_probe(u32 key)
7150 {
7151 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7152 }
7153
7154 static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7155 {
7156 u32 key = kvm_async_pf_hash_fn(gfn);
7157
7158 while (vcpu->arch.apf.gfns[key] != ~0)
7159 key = kvm_async_pf_next_probe(key);
7160
7161 vcpu->arch.apf.gfns[key] = gfn;
7162 }
7163
7164 static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7165 {
7166 int i;
7167 u32 key = kvm_async_pf_hash_fn(gfn);
7168
7169 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
7170 (vcpu->arch.apf.gfns[key] != gfn &&
7171 vcpu->arch.apf.gfns[key] != ~0); i++)
7172 key = kvm_async_pf_next_probe(key);
7173
7174 return key;
7175 }
7176
7177 bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7178 {
7179 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7180 }
7181
7182 static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7183 {
7184 u32 i, j, k;
7185
7186 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7187 while (true) {
7188 vcpu->arch.apf.gfns[i] = ~0;
7189 do {
7190 j = kvm_async_pf_next_probe(j);
7191 if (vcpu->arch.apf.gfns[j] == ~0)
7192 return;
7193 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7194 /*
7195 * k lies cyclically in ]i,j]
7196 * | i.k.j |
7197 * |....j i.k.| or |.k..j i...|
7198 */
7199 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7200 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7201 i = j;
7202 }
7203 }
7204
7205 static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7206 {
7207
7208 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7209 sizeof(val));
7210 }
7211
7212 void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7213 struct kvm_async_pf *work)
7214 {
7215 struct x86_exception fault;
7216
7217 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
7218 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7219
7220 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
7221 (vcpu->arch.apf.send_user_only &&
7222 kvm_x86_ops->get_cpl(vcpu) == 0))
7223 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7224 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
7225 fault.vector = PF_VECTOR;
7226 fault.error_code_valid = true;
7227 fault.error_code = 0;
7228 fault.nested_page_fault = false;
7229 fault.address = work->arch.token;
7230 kvm_inject_page_fault(vcpu, &fault);
7231 }
7232 }
7233
7234 void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7235 struct kvm_async_pf *work)
7236 {
7237 struct x86_exception fault;
7238
7239 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7240 if (is_error_page(work->page))
7241 work->arch.token = ~0; /* broadcast wakeup */
7242 else
7243 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7244
7245 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7246 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
7247 fault.vector = PF_VECTOR;
7248 fault.error_code_valid = true;
7249 fault.error_code = 0;
7250 fault.nested_page_fault = false;
7251 fault.address = work->arch.token;
7252 kvm_inject_page_fault(vcpu, &fault);
7253 }
7254 vcpu->arch.apf.halted = false;
7255 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7256 }
7257
7258 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7259 {
7260 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7261 return true;
7262 else
7263 return !kvm_event_needs_reinjection(vcpu) &&
7264 kvm_x86_ops->interrupt_allowed(vcpu);
7265 }
7266
7267 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7268 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7269 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7270 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7271 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
7272 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
7273 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
7274 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
7275 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
7276 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
7277 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
7278 EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
kernel source for telekom puls (alcatel/mediatek)