2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id vmx_cpu_id
[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
60 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
62 static bool __read_mostly enable_vpid
= 1;
63 module_param_named(vpid
, enable_vpid
, bool, 0444);
65 static bool __read_mostly flexpriority_enabled
= 1;
66 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
68 static bool __read_mostly enable_ept
= 1;
69 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
71 static bool __read_mostly enable_unrestricted_guest
= 1;
72 module_param_named(unrestricted_guest
,
73 enable_unrestricted_guest
, bool, S_IRUGO
);
75 static bool __read_mostly enable_ept_ad_bits
= 1;
76 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
78 static bool __read_mostly emulate_invalid_guest_state
= true;
79 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
81 static bool __read_mostly vmm_exclusive
= 1;
82 module_param(vmm_exclusive
, bool, S_IRUGO
);
84 static bool __read_mostly fasteoi
= 1;
85 module_param(fasteoi
, bool, S_IRUGO
);
87 static bool __read_mostly enable_apicv
= 1;
88 module_param(enable_apicv
, bool, S_IRUGO
);
90 static bool __read_mostly enable_shadow_vmcs
= 1;
91 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
97 static bool __read_mostly nested
= 0;
98 module_param(nested
, bool, S_IRUGO
);
100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
102 #define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
104 #define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
117 * According to test, this time is usually smaller than 128 cycles.
118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
124 #define KVM_VMX_DEFAULT_PLE_GAP 128
125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
127 module_param(ple_gap
, int, S_IRUGO
);
129 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
130 module_param(ple_window
, int, S_IRUGO
);
132 extern const ulong vmx_return
;
134 #define NR_AUTOLOAD_MSRS 8
135 #define VMCS02_POOL_SIZE 1
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
152 struct list_head loaded_vmcss_on_cpu_link
;
155 struct shared_msr_entry
{
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
174 typedef u64 natural_width
;
175 struct __packed vmcs12
{
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
182 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding
[7]; /* room for future expansion */
188 u64 vm_exit_msr_store_addr
;
189 u64 vm_exit_msr_load_addr
;
190 u64 vm_entry_msr_load_addr
;
192 u64 virtual_apic_page_addr
;
193 u64 apic_access_addr
;
195 u64 guest_physical_address
;
196 u64 vmcs_link_pointer
;
197 u64 guest_ia32_debugctl
;
200 u64 guest_ia32_perf_global_ctrl
;
207 u64 host_ia32_perf_global_ctrl
;
208 u64 padding64
[8]; /* room for future expansion */
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
215 natural_width cr0_guest_host_mask
;
216 natural_width cr4_guest_host_mask
;
217 natural_width cr0_read_shadow
;
218 natural_width cr4_read_shadow
;
219 natural_width cr3_target_value0
;
220 natural_width cr3_target_value1
;
221 natural_width cr3_target_value2
;
222 natural_width cr3_target_value3
;
223 natural_width exit_qualification
;
224 natural_width guest_linear_address
;
225 natural_width guest_cr0
;
226 natural_width guest_cr3
;
227 natural_width guest_cr4
;
228 natural_width guest_es_base
;
229 natural_width guest_cs_base
;
230 natural_width guest_ss_base
;
231 natural_width guest_ds_base
;
232 natural_width guest_fs_base
;
233 natural_width guest_gs_base
;
234 natural_width guest_ldtr_base
;
235 natural_width guest_tr_base
;
236 natural_width guest_gdtr_base
;
237 natural_width guest_idtr_base
;
238 natural_width guest_dr7
;
239 natural_width guest_rsp
;
240 natural_width guest_rip
;
241 natural_width guest_rflags
;
242 natural_width guest_pending_dbg_exceptions
;
243 natural_width guest_sysenter_esp
;
244 natural_width guest_sysenter_eip
;
245 natural_width host_cr0
;
246 natural_width host_cr3
;
247 natural_width host_cr4
;
248 natural_width host_fs_base
;
249 natural_width host_gs_base
;
250 natural_width host_tr_base
;
251 natural_width host_gdtr_base
;
252 natural_width host_idtr_base
;
253 natural_width host_ia32_sysenter_esp
;
254 natural_width host_ia32_sysenter_eip
;
255 natural_width host_rsp
;
256 natural_width host_rip
;
257 natural_width paddingl
[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control
;
259 u32 cpu_based_vm_exec_control
;
260 u32 exception_bitmap
;
261 u32 page_fault_error_code_mask
;
262 u32 page_fault_error_code_match
;
263 u32 cr3_target_count
;
264 u32 vm_exit_controls
;
265 u32 vm_exit_msr_store_count
;
266 u32 vm_exit_msr_load_count
;
267 u32 vm_entry_controls
;
268 u32 vm_entry_msr_load_count
;
269 u32 vm_entry_intr_info_field
;
270 u32 vm_entry_exception_error_code
;
271 u32 vm_entry_instruction_len
;
273 u32 secondary_vm_exec_control
;
274 u32 vm_instruction_error
;
276 u32 vm_exit_intr_info
;
277 u32 vm_exit_intr_error_code
;
278 u32 idt_vectoring_info_field
;
279 u32 idt_vectoring_error_code
;
280 u32 vm_exit_instruction_len
;
281 u32 vmx_instruction_info
;
288 u32 guest_ldtr_limit
;
290 u32 guest_gdtr_limit
;
291 u32 guest_idtr_limit
;
292 u32 guest_es_ar_bytes
;
293 u32 guest_cs_ar_bytes
;
294 u32 guest_ss_ar_bytes
;
295 u32 guest_ds_ar_bytes
;
296 u32 guest_fs_ar_bytes
;
297 u32 guest_gs_ar_bytes
;
298 u32 guest_ldtr_ar_bytes
;
299 u32 guest_tr_ar_bytes
;
300 u32 guest_interruptibility_info
;
301 u32 guest_activity_state
;
302 u32 guest_sysenter_cs
;
303 u32 host_ia32_sysenter_cs
;
304 u32 vmx_preemption_timer_value
;
305 u32 padding32
[7]; /* room for future expansion */
306 u16 virtual_processor_id
;
307 u16 guest_es_selector
;
308 u16 guest_cs_selector
;
309 u16 guest_ss_selector
;
310 u16 guest_ds_selector
;
311 u16 guest_fs_selector
;
312 u16 guest_gs_selector
;
313 u16 guest_ldtr_selector
;
314 u16 guest_tr_selector
;
315 u16 host_es_selector
;
316 u16 host_cs_selector
;
317 u16 host_ss_selector
;
318 u16 host_ds_selector
;
319 u16 host_fs_selector
;
320 u16 host_gs_selector
;
321 u16 host_tr_selector
;
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
329 #define VMCS12_REVISION 0x11e57ed0
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
336 #define VMCS12_SIZE 0x1000
338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
340 struct list_head list
;
342 struct loaded_vmcs vmcs02
;
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
350 /* Has the level1 guest done vmxon? */
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
355 /* The host-usable pointer to the above */
356 struct page
*current_vmcs12_page
;
357 struct vmcs12
*current_vmcs12
;
358 struct vmcs
*current_shadow_vmcs
;
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
363 bool sync_shadow_vmcs
;
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool
;
368 u64 vmcs01_tsc_offset
;
369 bool change_vmcs01_virtual_x2apic_mode
;
370 /* L2 must run next, and mustn't decide to exit to L1. */
371 bool nested_run_pending
;
373 * Guest pages referred to in vmcs02 with host-physical pointers, so
374 * we must keep them pinned while L2 runs.
376 struct page
*apic_access_page
;
379 #define POSTED_INTR_ON 0
380 /* Posted-Interrupt Descriptor */
382 u32 pir
[8]; /* Posted interrupt requested */
383 u32 control
; /* bit 0 of control is outstanding notification bit */
387 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
389 return test_and_set_bit(POSTED_INTR_ON
,
390 (unsigned long *)&pi_desc
->control
);
393 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
395 return test_and_clear_bit(POSTED_INTR_ON
,
396 (unsigned long *)&pi_desc
->control
);
399 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
401 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
405 struct kvm_vcpu vcpu
;
406 unsigned long host_rsp
;
409 bool nmi_known_unmasked
;
411 u32 idt_vectoring_info
;
413 struct shared_msr_entry
*guest_msrs
;
416 unsigned long host_idt_base
;
418 u64 msr_host_kernel_gs_base
;
419 u64 msr_guest_kernel_gs_base
;
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
426 struct loaded_vmcs vmcs01
;
427 struct loaded_vmcs
*loaded_vmcs
;
428 bool __launched
; /* temporary, used in vmx_vcpu_run */
429 struct msr_autoload
{
431 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
432 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
436 u16 fs_sel
, gs_sel
, ldt_sel
;
440 int gs_ldt_reload_needed
;
441 int fs_reload_needed
;
442 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
447 struct kvm_segment segs
[8];
450 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
451 struct kvm_save_segment
{
459 bool emulation_required
;
461 /* Support for vnmi-less CPUs */
462 int soft_vnmi_blocked
;
464 s64 vnmi_blocked_time
;
469 /* Posted interrupt descriptor */
470 struct pi_desc pi_desc
;
472 /* Support for a guest hypervisor (nested VMX) */
473 struct nested_vmx nested
;
476 enum segment_cache_field
{
485 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
487 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
490 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
491 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
492 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
493 [number##_HIGH] = VMCS12_OFFSET(name)+4
496 static const unsigned long shadow_read_only_fields
[] = {
498 * We do NOT shadow fields that are modified when L0
499 * traps and emulates any vmx instruction (e.g. VMPTRLD,
500 * VMXON...) executed by L1.
501 * For example, VM_INSTRUCTION_ERROR is read
502 * by L1 if a vmx instruction fails (part of the error path).
503 * Note the code assumes this logic. If for some reason
504 * we start shadowing these fields then we need to
505 * force a shadow sync when L0 emulates vmx instructions
506 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
507 * by nested_vmx_failValid)
511 VM_EXIT_INSTRUCTION_LEN
,
512 IDT_VECTORING_INFO_FIELD
,
513 IDT_VECTORING_ERROR_CODE
,
514 VM_EXIT_INTR_ERROR_CODE
,
516 GUEST_LINEAR_ADDRESS
,
517 GUEST_PHYSICAL_ADDRESS
519 static const int max_shadow_read_only_fields
=
520 ARRAY_SIZE(shadow_read_only_fields
);
522 static const unsigned long shadow_read_write_fields
[] = {
528 GUEST_INTERRUPTIBILITY_INFO
,
540 CPU_BASED_VM_EXEC_CONTROL
,
541 VM_ENTRY_EXCEPTION_ERROR_CODE
,
542 VM_ENTRY_INTR_INFO_FIELD
,
543 VM_ENTRY_INSTRUCTION_LEN
,
544 VM_ENTRY_EXCEPTION_ERROR_CODE
,
550 static const int max_shadow_read_write_fields
=
551 ARRAY_SIZE(shadow_read_write_fields
);
553 static const unsigned short vmcs_field_to_offset_table
[] = {
554 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
555 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
556 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
557 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
558 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
559 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
560 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
561 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
562 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
563 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
564 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
565 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
566 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
567 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
568 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
569 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
570 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
571 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
572 FIELD64(MSR_BITMAP
, msr_bitmap
),
573 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
574 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
575 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
576 FIELD64(TSC_OFFSET
, tsc_offset
),
577 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
578 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
579 FIELD64(EPT_POINTER
, ept_pointer
),
580 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
581 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
582 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
583 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
584 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
585 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
586 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
587 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
588 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
589 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
590 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
591 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
592 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
593 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
594 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
595 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
596 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
597 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
598 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
599 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
600 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
601 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
602 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
603 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
604 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
605 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
606 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
607 FIELD(TPR_THRESHOLD
, tpr_threshold
),
608 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
609 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
610 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
611 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
612 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
613 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
614 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
615 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
616 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
617 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
618 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
619 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
620 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
621 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
622 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
623 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
624 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
625 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
626 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
627 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
628 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
629 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
630 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
631 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
632 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
633 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
634 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
635 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
636 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
637 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
638 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
639 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
640 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
641 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
642 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
643 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
644 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
645 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
646 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
647 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
648 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
649 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
650 FIELD(GUEST_CR0
, guest_cr0
),
651 FIELD(GUEST_CR3
, guest_cr3
),
652 FIELD(GUEST_CR4
, guest_cr4
),
653 FIELD(GUEST_ES_BASE
, guest_es_base
),
654 FIELD(GUEST_CS_BASE
, guest_cs_base
),
655 FIELD(GUEST_SS_BASE
, guest_ss_base
),
656 FIELD(GUEST_DS_BASE
, guest_ds_base
),
657 FIELD(GUEST_FS_BASE
, guest_fs_base
),
658 FIELD(GUEST_GS_BASE
, guest_gs_base
),
659 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
660 FIELD(GUEST_TR_BASE
, guest_tr_base
),
661 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
662 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
663 FIELD(GUEST_DR7
, guest_dr7
),
664 FIELD(GUEST_RSP
, guest_rsp
),
665 FIELD(GUEST_RIP
, guest_rip
),
666 FIELD(GUEST_RFLAGS
, guest_rflags
),
667 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
668 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
669 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
670 FIELD(HOST_CR0
, host_cr0
),
671 FIELD(HOST_CR3
, host_cr3
),
672 FIELD(HOST_CR4
, host_cr4
),
673 FIELD(HOST_FS_BASE
, host_fs_base
),
674 FIELD(HOST_GS_BASE
, host_gs_base
),
675 FIELD(HOST_TR_BASE
, host_tr_base
),
676 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
677 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
678 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
679 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
680 FIELD(HOST_RSP
, host_rsp
),
681 FIELD(HOST_RIP
, host_rip
),
683 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
685 static inline short vmcs_field_to_offset(unsigned long field
)
687 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
689 return vmcs_field_to_offset_table
[field
];
692 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
694 return to_vmx(vcpu
)->nested
.current_vmcs12
;
697 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
699 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
700 if (is_error_page(page
))
706 static void nested_release_page(struct page
*page
)
708 kvm_release_page_dirty(page
);
711 static void nested_release_page_clean(struct page
*page
)
713 kvm_release_page_clean(page
);
716 static u64
construct_eptp(unsigned long root_hpa
);
717 static void kvm_cpu_vmxon(u64 addr
);
718 static void kvm_cpu_vmxoff(void);
719 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
);
720 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
721 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
722 struct kvm_segment
*var
, int seg
);
723 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
724 struct kvm_segment
*var
, int seg
);
725 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
726 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
727 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
728 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
729 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
731 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
732 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
734 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
735 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
737 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
738 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
740 static unsigned long *vmx_io_bitmap_a
;
741 static unsigned long *vmx_io_bitmap_b
;
742 static unsigned long *vmx_msr_bitmap_legacy
;
743 static unsigned long *vmx_msr_bitmap_longmode
;
744 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
745 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
746 static unsigned long *vmx_vmread_bitmap
;
747 static unsigned long *vmx_vmwrite_bitmap
;
749 static bool cpu_has_load_ia32_efer
;
750 static bool cpu_has_load_perf_global_ctrl
;
752 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
753 static DEFINE_SPINLOCK(vmx_vpid_lock
);
755 static struct vmcs_config
{
759 u32 pin_based_exec_ctrl
;
760 u32 cpu_based_exec_ctrl
;
761 u32 cpu_based_2nd_exec_ctrl
;
766 static struct vmx_capability
{
771 #define VMX_SEGMENT_FIELD(seg) \
772 [VCPU_SREG_##seg] = { \
773 .selector = GUEST_##seg##_SELECTOR, \
774 .base = GUEST_##seg##_BASE, \
775 .limit = GUEST_##seg##_LIMIT, \
776 .ar_bytes = GUEST_##seg##_AR_BYTES, \
779 static const struct kvm_vmx_segment_field
{
784 } kvm_vmx_segment_fields
[] = {
785 VMX_SEGMENT_FIELD(CS
),
786 VMX_SEGMENT_FIELD(DS
),
787 VMX_SEGMENT_FIELD(ES
),
788 VMX_SEGMENT_FIELD(FS
),
789 VMX_SEGMENT_FIELD(GS
),
790 VMX_SEGMENT_FIELD(SS
),
791 VMX_SEGMENT_FIELD(TR
),
792 VMX_SEGMENT_FIELD(LDTR
),
795 static u64 host_efer
;
797 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
800 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
801 * away by decrementing the array size.
803 static const u32 vmx_msr_index
[] = {
805 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
807 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
809 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
811 static inline bool is_page_fault(u32 intr_info
)
813 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
814 INTR_INFO_VALID_MASK
)) ==
815 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
818 static inline bool is_no_device(u32 intr_info
)
820 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
821 INTR_INFO_VALID_MASK
)) ==
822 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
825 static inline bool is_invalid_opcode(u32 intr_info
)
827 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
828 INTR_INFO_VALID_MASK
)) ==
829 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
832 static inline bool is_external_interrupt(u32 intr_info
)
834 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
835 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
838 static inline bool is_machine_check(u32 intr_info
)
840 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
841 INTR_INFO_VALID_MASK
)) ==
842 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
845 static inline bool cpu_has_vmx_msr_bitmap(void)
847 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
850 static inline bool cpu_has_vmx_tpr_shadow(void)
852 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
855 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
857 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
860 static inline bool cpu_has_secondary_exec_ctrls(void)
862 return vmcs_config
.cpu_based_exec_ctrl
&
863 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
866 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
868 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
869 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
872 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
874 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
875 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
878 static inline bool cpu_has_vmx_apic_register_virt(void)
880 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
881 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
884 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
886 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
887 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
890 static inline bool cpu_has_vmx_posted_intr(void)
892 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
895 static inline bool cpu_has_vmx_apicv(void)
897 return cpu_has_vmx_apic_register_virt() &&
898 cpu_has_vmx_virtual_intr_delivery() &&
899 cpu_has_vmx_posted_intr();
902 static inline bool cpu_has_vmx_flexpriority(void)
904 return cpu_has_vmx_tpr_shadow() &&
905 cpu_has_vmx_virtualize_apic_accesses();
908 static inline bool cpu_has_vmx_ept_execute_only(void)
910 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
913 static inline bool cpu_has_vmx_eptp_uncacheable(void)
915 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
918 static inline bool cpu_has_vmx_eptp_writeback(void)
920 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
923 static inline bool cpu_has_vmx_ept_2m_page(void)
925 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
928 static inline bool cpu_has_vmx_ept_1g_page(void)
930 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
933 static inline bool cpu_has_vmx_ept_4levels(void)
935 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
938 static inline bool cpu_has_vmx_ept_ad_bits(void)
940 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
943 static inline bool cpu_has_vmx_invept_context(void)
945 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
948 static inline bool cpu_has_vmx_invept_global(void)
950 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
953 static inline bool cpu_has_vmx_invvpid_single(void)
955 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
958 static inline bool cpu_has_vmx_invvpid_global(void)
960 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
963 static inline bool cpu_has_vmx_ept(void)
965 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
966 SECONDARY_EXEC_ENABLE_EPT
;
969 static inline bool cpu_has_vmx_unrestricted_guest(void)
971 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
972 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
975 static inline bool cpu_has_vmx_ple(void)
977 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
978 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
981 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
983 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
986 static inline bool cpu_has_vmx_vpid(void)
988 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
989 SECONDARY_EXEC_ENABLE_VPID
;
992 static inline bool cpu_has_vmx_rdtscp(void)
994 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
995 SECONDARY_EXEC_RDTSCP
;
998 static inline bool cpu_has_vmx_invpcid(void)
1000 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1001 SECONDARY_EXEC_ENABLE_INVPCID
;
1004 static inline bool cpu_has_virtual_nmis(void)
1006 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1009 static inline bool cpu_has_vmx_wbinvd_exit(void)
1011 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1012 SECONDARY_EXEC_WBINVD_EXITING
;
1015 static inline bool cpu_has_vmx_shadow_vmcs(void)
1018 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1019 /* check if the cpu supports writing r/o exit information fields */
1020 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1023 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1024 SECONDARY_EXEC_SHADOW_VMCS
;
1027 static inline bool report_flexpriority(void)
1029 return flexpriority_enabled
;
1032 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1034 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1037 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1039 return (vmcs12
->cpu_based_vm_exec_control
&
1040 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1041 (vmcs12
->secondary_vm_exec_control
& bit
);
1044 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
,
1045 struct kvm_vcpu
*vcpu
)
1047 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1050 static inline bool is_nmi(u32 intr_info
)
1052 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1053 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1056 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
);
1057 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1058 struct vmcs12
*vmcs12
,
1059 u32 reason
, unsigned long qualification
);
1061 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1065 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1066 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1071 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1077 } operand
= { vpid
, 0, gva
};
1079 asm volatile (__ex(ASM_VMX_INVVPID
)
1080 /* CF==1 or ZF==1 --> rc = -1 */
1081 "; ja 1f ; ud2 ; 1:"
1082 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1085 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1089 } operand
= {eptp
, gpa
};
1091 asm volatile (__ex(ASM_VMX_INVEPT
)
1092 /* CF==1 or ZF==1 --> rc = -1 */
1093 "; ja 1f ; ud2 ; 1:\n"
1094 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1097 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1101 i
= __find_msr_index(vmx
, msr
);
1103 return &vmx
->guest_msrs
[i
];
1107 static void vmcs_clear(struct vmcs
*vmcs
)
1109 u64 phys_addr
= __pa(vmcs
);
1112 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1113 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1116 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1120 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1122 vmcs_clear(loaded_vmcs
->vmcs
);
1123 loaded_vmcs
->cpu
= -1;
1124 loaded_vmcs
->launched
= 0;
1127 static void vmcs_load(struct vmcs
*vmcs
)
1129 u64 phys_addr
= __pa(vmcs
);
1132 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1133 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1136 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1142 * This bitmap is used to indicate whether the vmclear
1143 * operation is enabled on all cpus. All disabled by
1146 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1148 static inline void crash_enable_local_vmclear(int cpu
)
1150 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1153 static inline void crash_disable_local_vmclear(int cpu
)
1155 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1158 static inline int crash_local_vmclear_enabled(int cpu
)
1160 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1163 static void crash_vmclear_local_loaded_vmcss(void)
1165 int cpu
= raw_smp_processor_id();
1166 struct loaded_vmcs
*v
;
1168 if (!crash_local_vmclear_enabled(cpu
))
1171 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1172 loaded_vmcss_on_cpu_link
)
1173 vmcs_clear(v
->vmcs
);
1176 static inline void crash_enable_local_vmclear(int cpu
) { }
1177 static inline void crash_disable_local_vmclear(int cpu
) { }
1178 #endif /* CONFIG_KEXEC */
1180 static void __loaded_vmcs_clear(void *arg
)
1182 struct loaded_vmcs
*loaded_vmcs
= arg
;
1183 int cpu
= raw_smp_processor_id();
1185 if (loaded_vmcs
->cpu
!= cpu
)
1186 return; /* vcpu migration can race with cpu offline */
1187 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1188 per_cpu(current_vmcs
, cpu
) = NULL
;
1189 crash_disable_local_vmclear(cpu
);
1190 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1193 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1194 * is before setting loaded_vmcs->vcpu to -1 which is done in
1195 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1196 * then adds the vmcs into percpu list before it is deleted.
1200 loaded_vmcs_init(loaded_vmcs
);
1201 crash_enable_local_vmclear(cpu
);
1204 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1206 int cpu
= loaded_vmcs
->cpu
;
1209 smp_call_function_single(cpu
,
1210 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1213 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1218 if (cpu_has_vmx_invvpid_single())
1219 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1222 static inline void vpid_sync_vcpu_global(void)
1224 if (cpu_has_vmx_invvpid_global())
1225 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1228 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1230 if (cpu_has_vmx_invvpid_single())
1231 vpid_sync_vcpu_single(vmx
);
1233 vpid_sync_vcpu_global();
1236 static inline void ept_sync_global(void)
1238 if (cpu_has_vmx_invept_global())
1239 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1242 static inline void ept_sync_context(u64 eptp
)
1245 if (cpu_has_vmx_invept_context())
1246 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1252 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1254 unsigned long value
;
1256 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1257 : "=a"(value
) : "d"(field
) : "cc");
1261 static __always_inline u16
vmcs_read16(unsigned long field
)
1263 return vmcs_readl(field
);
1266 static __always_inline u32
vmcs_read32(unsigned long field
)
1268 return vmcs_readl(field
);
1271 static __always_inline u64
vmcs_read64(unsigned long field
)
1273 #ifdef CONFIG_X86_64
1274 return vmcs_readl(field
);
1276 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1280 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1282 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1283 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1287 static void vmcs_writel(unsigned long field
, unsigned long value
)
1291 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1292 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1293 if (unlikely(error
))
1294 vmwrite_error(field
, value
);
1297 static void vmcs_write16(unsigned long field
, u16 value
)
1299 vmcs_writel(field
, value
);
1302 static void vmcs_write32(unsigned long field
, u32 value
)
1304 vmcs_writel(field
, value
);
1307 static void vmcs_write64(unsigned long field
, u64 value
)
1309 vmcs_writel(field
, value
);
1310 #ifndef CONFIG_X86_64
1312 vmcs_writel(field
+1, value
>> 32);
1316 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1318 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1321 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1323 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1326 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1328 vmx
->segment_cache
.bitmask
= 0;
1331 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1335 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1337 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1338 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1339 vmx
->segment_cache
.bitmask
= 0;
1341 ret
= vmx
->segment_cache
.bitmask
& mask
;
1342 vmx
->segment_cache
.bitmask
|= mask
;
1346 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1348 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1350 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1351 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1355 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1357 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1359 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1360 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1364 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1366 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1368 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1369 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1373 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1375 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1377 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1378 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1382 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1386 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1387 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1388 if ((vcpu
->guest_debug
&
1389 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1390 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1391 eb
|= 1u << BP_VECTOR
;
1392 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1395 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1396 if (vcpu
->fpu_active
)
1397 eb
&= ~(1u << NM_VECTOR
);
1399 /* When we are running a nested L2 guest and L1 specified for it a
1400 * certain exception bitmap, we must trap the same exceptions and pass
1401 * them to L1. When running L2, we will only handle the exceptions
1402 * specified above if L1 did not want them.
1404 if (is_guest_mode(vcpu
))
1405 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1407 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1410 static void clear_atomic_switch_msr_special(unsigned long entry
,
1413 vmcs_clear_bits(VM_ENTRY_CONTROLS
, entry
);
1414 vmcs_clear_bits(VM_EXIT_CONTROLS
, exit
);
1417 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1420 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1424 if (cpu_has_load_ia32_efer
) {
1425 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1426 VM_EXIT_LOAD_IA32_EFER
);
1430 case MSR_CORE_PERF_GLOBAL_CTRL
:
1431 if (cpu_has_load_perf_global_ctrl
) {
1432 clear_atomic_switch_msr_special(
1433 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1434 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1440 for (i
= 0; i
< m
->nr
; ++i
)
1441 if (m
->guest
[i
].index
== msr
)
1447 m
->guest
[i
] = m
->guest
[m
->nr
];
1448 m
->host
[i
] = m
->host
[m
->nr
];
1449 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1450 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1453 static void add_atomic_switch_msr_special(unsigned long entry
,
1454 unsigned long exit
, unsigned long guest_val_vmcs
,
1455 unsigned long host_val_vmcs
, u64 guest_val
, u64 host_val
)
1457 vmcs_write64(guest_val_vmcs
, guest_val
);
1458 vmcs_write64(host_val_vmcs
, host_val
);
1459 vmcs_set_bits(VM_ENTRY_CONTROLS
, entry
);
1460 vmcs_set_bits(VM_EXIT_CONTROLS
, exit
);
1463 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1464 u64 guest_val
, u64 host_val
)
1467 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1471 if (cpu_has_load_ia32_efer
) {
1472 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1473 VM_EXIT_LOAD_IA32_EFER
,
1476 guest_val
, host_val
);
1480 case MSR_CORE_PERF_GLOBAL_CTRL
:
1481 if (cpu_has_load_perf_global_ctrl
) {
1482 add_atomic_switch_msr_special(
1483 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1484 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1485 GUEST_IA32_PERF_GLOBAL_CTRL
,
1486 HOST_IA32_PERF_GLOBAL_CTRL
,
1487 guest_val
, host_val
);
1491 case MSR_IA32_PEBS_ENABLE
:
1492 /* PEBS needs a quiescent period after being disabled (to write
1493 * a record). Disabling PEBS through VMX MSR swapping doesn't
1494 * provide that period, so a CPU could write host's record into
1497 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1500 for (i
= 0; i
< m
->nr
; ++i
)
1501 if (m
->guest
[i
].index
== msr
)
1504 if (i
== NR_AUTOLOAD_MSRS
) {
1505 printk_once(KERN_WARNING
"Not enough mst switch entries. "
1506 "Can't add msr %x\n", msr
);
1508 } else if (i
== m
->nr
) {
1510 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1511 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1514 m
->guest
[i
].index
= msr
;
1515 m
->guest
[i
].value
= guest_val
;
1516 m
->host
[i
].index
= msr
;
1517 m
->host
[i
].value
= host_val
;
1520 static void reload_tss(void)
1523 * VT restores TR but not its size. Useless.
1525 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1526 struct desc_struct
*descs
;
1528 descs
= (void *)gdt
->address
;
1529 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1533 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1538 guest_efer
= vmx
->vcpu
.arch
.efer
;
1541 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1544 ignore_bits
= EFER_NX
| EFER_SCE
;
1545 #ifdef CONFIG_X86_64
1546 ignore_bits
|= EFER_LMA
| EFER_LME
;
1547 /* SCE is meaningful only in long mode on Intel */
1548 if (guest_efer
& EFER_LMA
)
1549 ignore_bits
&= ~(u64
)EFER_SCE
;
1551 guest_efer
&= ~ignore_bits
;
1552 guest_efer
|= host_efer
& ignore_bits
;
1553 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1554 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1556 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1557 /* On ept, can't emulate nx, and must switch nx atomically */
1558 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1559 guest_efer
= vmx
->vcpu
.arch
.efer
;
1560 if (!(guest_efer
& EFER_LMA
))
1561 guest_efer
&= ~EFER_LME
;
1562 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1569 static unsigned long segment_base(u16 selector
)
1571 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1572 struct desc_struct
*d
;
1573 unsigned long table_base
;
1576 if (!(selector
& ~3))
1579 table_base
= gdt
->address
;
1581 if (selector
& 4) { /* from ldt */
1582 u16 ldt_selector
= kvm_read_ldt();
1584 if (!(ldt_selector
& ~3))
1587 table_base
= segment_base(ldt_selector
);
1589 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1590 v
= get_desc_base(d
);
1591 #ifdef CONFIG_X86_64
1592 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1593 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1598 static inline unsigned long kvm_read_tr_base(void)
1601 asm("str %0" : "=g"(tr
));
1602 return segment_base(tr
);
1605 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1607 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1610 if (vmx
->host_state
.loaded
)
1613 vmx
->host_state
.loaded
= 1;
1615 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1616 * allow segment selectors with cpl > 0 or ti == 1.
1618 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1619 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1620 savesegment(fs
, vmx
->host_state
.fs_sel
);
1621 if (!(vmx
->host_state
.fs_sel
& 7)) {
1622 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1623 vmx
->host_state
.fs_reload_needed
= 0;
1625 vmcs_write16(HOST_FS_SELECTOR
, 0);
1626 vmx
->host_state
.fs_reload_needed
= 1;
1628 savesegment(gs
, vmx
->host_state
.gs_sel
);
1629 if (!(vmx
->host_state
.gs_sel
& 7))
1630 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1632 vmcs_write16(HOST_GS_SELECTOR
, 0);
1633 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1636 #ifdef CONFIG_X86_64
1637 savesegment(ds
, vmx
->host_state
.ds_sel
);
1638 savesegment(es
, vmx
->host_state
.es_sel
);
1641 #ifdef CONFIG_X86_64
1642 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1643 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1645 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1646 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1649 #ifdef CONFIG_X86_64
1650 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1651 if (is_long_mode(&vmx
->vcpu
))
1652 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1654 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1655 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1656 vmx
->guest_msrs
[i
].data
,
1657 vmx
->guest_msrs
[i
].mask
);
1660 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1662 if (!vmx
->host_state
.loaded
)
1665 ++vmx
->vcpu
.stat
.host_state_reload
;
1666 vmx
->host_state
.loaded
= 0;
1667 #ifdef CONFIG_X86_64
1668 if (is_long_mode(&vmx
->vcpu
))
1669 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1671 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1672 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1673 #ifdef CONFIG_X86_64
1674 load_gs_index(vmx
->host_state
.gs_sel
);
1676 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1679 if (vmx
->host_state
.fs_reload_needed
)
1680 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1681 #ifdef CONFIG_X86_64
1682 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1683 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1684 loadsegment(es
, vmx
->host_state
.es_sel
);
1688 #ifdef CONFIG_X86_64
1689 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1692 * If the FPU is not active (through the host task or
1693 * the guest vcpu), then restore the cr0.TS bit.
1695 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1697 load_gdt(&__get_cpu_var(host_gdt
));
1700 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1703 __vmx_load_host_state(vmx
);
1708 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1709 * vcpu mutex is already taken.
1711 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1713 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1714 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1717 kvm_cpu_vmxon(phys_addr
);
1718 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1719 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1721 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1722 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1723 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1726 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1727 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1728 unsigned long sysenter_esp
;
1730 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1731 local_irq_disable();
1732 crash_disable_local_vmclear(cpu
);
1735 * Read loaded_vmcs->cpu should be before fetching
1736 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1737 * See the comments in __loaded_vmcs_clear().
1741 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1742 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1743 crash_enable_local_vmclear(cpu
);
1747 * Linux uses per-cpu TSS and GDT, so set these when switching
1750 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1751 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1753 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1754 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1755 vmx
->loaded_vmcs
->cpu
= cpu
;
1759 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1761 __vmx_load_host_state(to_vmx(vcpu
));
1762 if (!vmm_exclusive
) {
1763 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1769 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1773 if (vcpu
->fpu_active
)
1775 vcpu
->fpu_active
= 1;
1776 cr0
= vmcs_readl(GUEST_CR0
);
1777 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1778 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1779 vmcs_writel(GUEST_CR0
, cr0
);
1780 update_exception_bitmap(vcpu
);
1781 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1782 if (is_guest_mode(vcpu
))
1783 vcpu
->arch
.cr0_guest_owned_bits
&=
1784 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1785 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1788 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1791 * Return the cr0 value that a nested guest would read. This is a combination
1792 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1793 * its hypervisor (cr0_read_shadow).
1795 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1797 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1798 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1800 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1802 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1803 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1806 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1808 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1809 * set this *before* calling this function.
1811 vmx_decache_cr0_guest_bits(vcpu
);
1812 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1813 update_exception_bitmap(vcpu
);
1814 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1815 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1816 if (is_guest_mode(vcpu
)) {
1818 * L1's specified read shadow might not contain the TS bit,
1819 * so now that we turned on shadowing of this bit, we need to
1820 * set this bit of the shadow. Like in nested_vmx_run we need
1821 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1822 * up-to-date here because we just decached cr0.TS (and we'll
1823 * only update vmcs12->guest_cr0 on nested exit).
1825 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1826 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1827 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1828 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1830 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1833 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1835 unsigned long rflags
, save_rflags
;
1837 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1838 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1839 rflags
= vmcs_readl(GUEST_RFLAGS
);
1840 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1841 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1842 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1843 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1845 to_vmx(vcpu
)->rflags
= rflags
;
1847 return to_vmx(vcpu
)->rflags
;
1850 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1852 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1853 to_vmx(vcpu
)->rflags
= rflags
;
1854 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1855 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1856 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1858 vmcs_writel(GUEST_RFLAGS
, rflags
);
1861 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1863 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1866 if (interruptibility
& GUEST_INTR_STATE_STI
)
1867 ret
|= KVM_X86_SHADOW_INT_STI
;
1868 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1869 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1874 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1876 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1877 u32 interruptibility
= interruptibility_old
;
1879 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1881 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1882 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1883 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1884 interruptibility
|= GUEST_INTR_STATE_STI
;
1886 if ((interruptibility
!= interruptibility_old
))
1887 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1890 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1894 rip
= kvm_rip_read(vcpu
);
1895 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1896 kvm_rip_write(vcpu
, rip
);
1898 /* skipping an emulated instruction also counts */
1899 vmx_set_interrupt_shadow(vcpu
, 0);
1903 * KVM wants to inject page-faults which it got to the guest. This function
1904 * checks whether in a nested guest, we need to inject them to L1 or L2.
1905 * This function assumes it is called with the exit reason in vmcs02 being
1906 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1909 static int nested_pf_handled(struct kvm_vcpu
*vcpu
)
1911 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1913 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1914 if (!(vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)))
1917 nested_vmx_vmexit(vcpu
);
1921 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1922 bool has_error_code
, u32 error_code
,
1925 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1926 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1928 if (nr
== PF_VECTOR
&& is_guest_mode(vcpu
) &&
1929 !vmx
->nested
.nested_run_pending
&& nested_pf_handled(vcpu
))
1932 if (has_error_code
) {
1933 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1934 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1937 if (vmx
->rmode
.vm86_active
) {
1939 if (kvm_exception_is_soft(nr
))
1940 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1941 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1942 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1946 if (kvm_exception_is_soft(nr
)) {
1947 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1948 vmx
->vcpu
.arch
.event_exit_inst_len
);
1949 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1951 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1953 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1956 static bool vmx_rdtscp_supported(void)
1958 return cpu_has_vmx_rdtscp();
1961 static bool vmx_invpcid_supported(void)
1963 return cpu_has_vmx_invpcid() && enable_ept
;
1967 * Swap MSR entry in host/guest MSR entry array.
1969 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1971 struct shared_msr_entry tmp
;
1973 tmp
= vmx
->guest_msrs
[to
];
1974 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1975 vmx
->guest_msrs
[from
] = tmp
;
1978 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
1980 unsigned long *msr_bitmap
;
1982 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
1983 if (is_long_mode(vcpu
))
1984 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
1986 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
1988 if (is_long_mode(vcpu
))
1989 msr_bitmap
= vmx_msr_bitmap_longmode
;
1991 msr_bitmap
= vmx_msr_bitmap_legacy
;
1994 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1998 * Set up the vmcs to automatically save and restore system
1999 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2000 * mode, as fiddling with msrs is very expensive.
2002 static void setup_msrs(struct vcpu_vmx
*vmx
)
2004 int save_nmsrs
, index
;
2007 #ifdef CONFIG_X86_64
2008 if (is_long_mode(&vmx
->vcpu
)) {
2009 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2011 move_msr_up(vmx
, index
, save_nmsrs
++);
2012 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2014 move_msr_up(vmx
, index
, save_nmsrs
++);
2015 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2017 move_msr_up(vmx
, index
, save_nmsrs
++);
2018 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2019 if (index
>= 0 && vmx
->rdtscp_enabled
)
2020 move_msr_up(vmx
, index
, save_nmsrs
++);
2022 * MSR_STAR is only needed on long mode guests, and only
2023 * if efer.sce is enabled.
2025 index
= __find_msr_index(vmx
, MSR_STAR
);
2026 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2027 move_msr_up(vmx
, index
, save_nmsrs
++);
2030 index
= __find_msr_index(vmx
, MSR_EFER
);
2031 if (index
>= 0 && update_transition_efer(vmx
, index
))
2032 move_msr_up(vmx
, index
, save_nmsrs
++);
2034 vmx
->save_nmsrs
= save_nmsrs
;
2036 if (cpu_has_vmx_msr_bitmap())
2037 vmx_set_msr_bitmap(&vmx
->vcpu
);
2041 * reads and returns guest's timestamp counter "register"
2042 * guest_tsc = host_tsc + tsc_offset -- 21.3
2044 static u64
guest_read_tsc(void)
2046 u64 host_tsc
, tsc_offset
;
2049 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2050 return host_tsc
+ tsc_offset
;
2054 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2055 * counter, even if a nested guest (L2) is currently running.
2057 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2061 tsc_offset
= is_guest_mode(vcpu
) ?
2062 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2063 vmcs_read64(TSC_OFFSET
);
2064 return host_tsc
+ tsc_offset
;
2068 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2069 * software catchup for faster rates on slower CPUs.
2071 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2076 if (user_tsc_khz
> tsc_khz
) {
2077 vcpu
->arch
.tsc_catchup
= 1;
2078 vcpu
->arch
.tsc_always_catchup
= 1;
2080 WARN(1, "user requested TSC rate below hardware speed\n");
2083 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2085 return vmcs_read64(TSC_OFFSET
);
2089 * writes 'offset' into guest's timestamp counter offset register
2091 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2093 if (is_guest_mode(vcpu
)) {
2095 * We're here if L1 chose not to trap WRMSR to TSC. According
2096 * to the spec, this should set L1's TSC; The offset that L1
2097 * set for L2 remains unchanged, and still needs to be added
2098 * to the newly set TSC to get L2's TSC.
2100 struct vmcs12
*vmcs12
;
2101 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2102 /* recalculate vmcs02.TSC_OFFSET: */
2103 vmcs12
= get_vmcs12(vcpu
);
2104 vmcs_write64(TSC_OFFSET
, offset
+
2105 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2106 vmcs12
->tsc_offset
: 0));
2108 vmcs_write64(TSC_OFFSET
, offset
);
2112 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2114 u64 offset
= vmcs_read64(TSC_OFFSET
);
2115 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2116 if (is_guest_mode(vcpu
)) {
2117 /* Even when running L2, the adjustment needs to apply to L1 */
2118 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2122 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2124 return target_tsc
- native_read_tsc();
2127 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2129 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2130 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2134 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2135 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2136 * all guests if the "nested" module option is off, and can also be disabled
2137 * for a single guest by disabling its VMX cpuid bit.
2139 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2141 return nested
&& guest_cpuid_has_vmx(vcpu
);
2145 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2146 * returned for the various VMX controls MSRs when nested VMX is enabled.
2147 * The same values should also be used to verify that vmcs12 control fields are
2148 * valid during nested entry from L1 to L2.
2149 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2150 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2151 * bit in the high half is on if the corresponding bit in the control field
2152 * may be on. See also vmx_control_verify().
2153 * TODO: allow these variables to be modified (downgraded) by module options
2156 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2157 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2158 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2159 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2160 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2161 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2162 static __init
void nested_vmx_setup_ctls_msrs(void)
2165 * Note that as a general rule, the high half of the MSRs (bits in
2166 * the control fields which may be 1) should be initialized by the
2167 * intersection of the underlying hardware's MSR (i.e., features which
2168 * can be supported) and the list of features we want to expose -
2169 * because they are known to be properly supported in our code.
2170 * Also, usually, the low half of the MSRs (bits which must be 1) can
2171 * be set to 0, meaning that L1 may turn off any of these bits. The
2172 * reason is that if one of these bits is necessary, it will appear
2173 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2174 * fields of vmcs01 and vmcs02, will turn these bits off - and
2175 * nested_vmx_exit_handled() will not pass related exits to L1.
2176 * These rules have exceptions below.
2179 /* pin-based controls */
2180 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2181 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2183 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2184 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2186 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2187 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2188 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
|
2189 PIN_BASED_VMX_PREEMPTION_TIMER
;
2190 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2194 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2197 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2198 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2199 #ifdef CONFIG_X86_64
2200 nested_vmx_exit_ctls_high
= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2202 nested_vmx_exit_ctls_high
= 0;
2204 nested_vmx_exit_ctls_high
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2206 /* entry controls */
2207 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2208 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2209 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2210 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2211 nested_vmx_entry_ctls_high
&=
2212 VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_IA32E_MODE
;
2213 nested_vmx_entry_ctls_high
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2215 /* cpu-based controls */
2216 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2217 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2218 nested_vmx_procbased_ctls_low
= 0;
2219 nested_vmx_procbased_ctls_high
&=
2220 CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2221 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2222 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2223 CPU_BASED_CR3_STORE_EXITING
|
2224 #ifdef CONFIG_X86_64
2225 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2227 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2228 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2229 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2230 CPU_BASED_PAUSE_EXITING
|
2231 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2233 * We can allow some features even when not supported by the
2234 * hardware. For example, L1 can specify an MSR bitmap - and we
2235 * can use it to avoid exits to L1 - even when L0 runs L2
2236 * without MSR bitmaps.
2238 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2240 /* secondary cpu-based controls */
2241 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2242 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2243 nested_vmx_secondary_ctls_low
= 0;
2244 nested_vmx_secondary_ctls_high
&=
2245 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2246 SECONDARY_EXEC_WBINVD_EXITING
;
2248 /* miscellaneous data */
2249 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2250 nested_vmx_misc_low
&= VMX_MISC_PREEMPTION_TIMER_RATE_MASK
|
2251 VMX_MISC_SAVE_EFER_LMA
;
2252 nested_vmx_misc_high
= 0;
2255 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2258 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2260 return ((control
& high
) | low
) == control
;
2263 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2265 return low
| ((u64
)high
<< 32);
2269 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2270 * also let it use VMX-specific MSRs.
2271 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2272 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2273 * like all other MSRs).
2275 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2277 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
2278 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
2280 * According to the spec, processors which do not support VMX
2281 * should throw a #GP(0) when VMX capability MSRs are read.
2283 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
2287 switch (msr_index
) {
2288 case MSR_IA32_FEATURE_CONTROL
:
2291 case MSR_IA32_VMX_BASIC
:
2293 * This MSR reports some information about VMX support. We
2294 * should return information about the VMX we emulate for the
2295 * guest, and the VMCS structure we give it - not about the
2296 * VMX support of the underlying hardware.
2298 *pdata
= VMCS12_REVISION
|
2299 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2300 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2302 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2303 case MSR_IA32_VMX_PINBASED_CTLS
:
2304 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2305 nested_vmx_pinbased_ctls_high
);
2307 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2308 case MSR_IA32_VMX_PROCBASED_CTLS
:
2309 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2310 nested_vmx_procbased_ctls_high
);
2312 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2313 case MSR_IA32_VMX_EXIT_CTLS
:
2314 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2315 nested_vmx_exit_ctls_high
);
2317 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2318 case MSR_IA32_VMX_ENTRY_CTLS
:
2319 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2320 nested_vmx_entry_ctls_high
);
2322 case MSR_IA32_VMX_MISC
:
2323 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2324 nested_vmx_misc_high
);
2327 * These MSRs specify bits which the guest must keep fixed (on or off)
2328 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2329 * We picked the standard core2 setting.
2331 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2332 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2333 case MSR_IA32_VMX_CR0_FIXED0
:
2334 *pdata
= VMXON_CR0_ALWAYSON
;
2336 case MSR_IA32_VMX_CR0_FIXED1
:
2339 case MSR_IA32_VMX_CR4_FIXED0
:
2340 *pdata
= VMXON_CR4_ALWAYSON
;
2342 case MSR_IA32_VMX_CR4_FIXED1
:
2345 case MSR_IA32_VMX_VMCS_ENUM
:
2348 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2349 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2350 nested_vmx_secondary_ctls_high
);
2352 case MSR_IA32_VMX_EPT_VPID_CAP
:
2353 /* Currently, no nested ept or nested vpid */
2363 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2365 if (!nested_vmx_allowed(vcpu
))
2368 if (msr_index
== MSR_IA32_FEATURE_CONTROL
)
2369 /* TODO: the right thing. */
2372 * No need to treat VMX capability MSRs specially: If we don't handle
2373 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2379 * Reads an msr value (of 'msr_index') into 'pdata'.
2380 * Returns 0 on success, non-0 otherwise.
2381 * Assumes vcpu_load() was already called.
2383 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2386 struct shared_msr_entry
*msr
;
2389 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2393 switch (msr_index
) {
2394 #ifdef CONFIG_X86_64
2396 data
= vmcs_readl(GUEST_FS_BASE
);
2399 data
= vmcs_readl(GUEST_GS_BASE
);
2401 case MSR_KERNEL_GS_BASE
:
2402 vmx_load_host_state(to_vmx(vcpu
));
2403 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2407 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2409 data
= guest_read_tsc();
2411 case MSR_IA32_SYSENTER_CS
:
2412 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2414 case MSR_IA32_SYSENTER_EIP
:
2415 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2417 case MSR_IA32_SYSENTER_ESP
:
2418 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2421 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2423 /* Otherwise falls through */
2425 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
2427 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2432 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2440 * Writes msr value into into the appropriate "register".
2441 * Returns 0 on success, non-0 otherwise.
2442 * Assumes vcpu_load() was already called.
2444 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2446 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2447 struct shared_msr_entry
*msr
;
2449 u32 msr_index
= msr_info
->index
;
2450 u64 data
= msr_info
->data
;
2452 switch (msr_index
) {
2454 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2456 #ifdef CONFIG_X86_64
2458 vmx_segment_cache_clear(vmx
);
2459 vmcs_writel(GUEST_FS_BASE
, data
);
2462 vmx_segment_cache_clear(vmx
);
2463 vmcs_writel(GUEST_GS_BASE
, data
);
2465 case MSR_KERNEL_GS_BASE
:
2466 vmx_load_host_state(vmx
);
2467 vmx
->msr_guest_kernel_gs_base
= data
;
2470 case MSR_IA32_SYSENTER_CS
:
2471 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2473 case MSR_IA32_SYSENTER_EIP
:
2474 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2476 case MSR_IA32_SYSENTER_ESP
:
2477 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2480 kvm_write_tsc(vcpu
, msr_info
);
2482 case MSR_IA32_CR_PAT
:
2483 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2484 vmcs_write64(GUEST_IA32_PAT
, data
);
2485 vcpu
->arch
.pat
= data
;
2488 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2490 case MSR_IA32_TSC_ADJUST
:
2491 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2494 if (!vmx
->rdtscp_enabled
)
2496 /* Check reserved bit, higher 32 bits should be zero */
2497 if ((data
>> 32) != 0)
2499 /* Otherwise falls through */
2501 if (vmx_set_vmx_msr(vcpu
, msr_index
, data
))
2503 msr
= find_msr_entry(vmx
, msr_index
);
2505 u64 old_msr_data
= msr
->data
;
2507 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2509 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
2513 msr
->data
= old_msr_data
;
2517 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2523 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2525 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2528 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2531 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2533 case VCPU_EXREG_PDPTR
:
2535 ept_save_pdptrs(vcpu
);
2542 static __init
int cpu_has_kvm_support(void)
2544 return cpu_has_vmx();
2547 static __init
int vmx_disabled_by_bios(void)
2551 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2552 if (msr
& FEATURE_CONTROL_LOCKED
) {
2553 /* launched w/ TXT and VMX disabled */
2554 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2557 /* launched w/o TXT and VMX only enabled w/ TXT */
2558 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2559 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2560 && !tboot_enabled()) {
2561 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2562 "activate TXT before enabling KVM\n");
2565 /* launched w/o TXT and VMX disabled */
2566 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2567 && !tboot_enabled())
2574 static void kvm_cpu_vmxon(u64 addr
)
2576 asm volatile (ASM_VMX_VMXON_RAX
2577 : : "a"(&addr
), "m"(addr
)
2581 static int hardware_enable(void *garbage
)
2583 int cpu
= raw_smp_processor_id();
2584 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2587 if (read_cr4() & X86_CR4_VMXE
)
2590 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2593 * Now we can enable the vmclear operation in kdump
2594 * since the loaded_vmcss_on_cpu list on this cpu
2595 * has been initialized.
2597 * Though the cpu is not in VMX operation now, there
2598 * is no problem to enable the vmclear operation
2599 * for the loaded_vmcss_on_cpu list is empty!
2601 crash_enable_local_vmclear(cpu
);
2603 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2605 test_bits
= FEATURE_CONTROL_LOCKED
;
2606 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2607 if (tboot_enabled())
2608 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2610 if ((old
& test_bits
) != test_bits
) {
2611 /* enable and lock */
2612 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2614 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2616 if (vmm_exclusive
) {
2617 kvm_cpu_vmxon(phys_addr
);
2621 native_store_gdt(&__get_cpu_var(host_gdt
));
2626 static void vmclear_local_loaded_vmcss(void)
2628 int cpu
= raw_smp_processor_id();
2629 struct loaded_vmcs
*v
, *n
;
2631 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2632 loaded_vmcss_on_cpu_link
)
2633 __loaded_vmcs_clear(v
);
2637 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2640 static void kvm_cpu_vmxoff(void)
2642 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2645 static void hardware_disable(void *garbage
)
2647 if (vmm_exclusive
) {
2648 vmclear_local_loaded_vmcss();
2651 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2654 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2655 u32 msr
, u32
*result
)
2657 u32 vmx_msr_low
, vmx_msr_high
;
2658 u32 ctl
= ctl_min
| ctl_opt
;
2660 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2662 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2663 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2665 /* Ensure minimum (required) set of control bits are supported. */
2673 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2675 u32 vmx_msr_low
, vmx_msr_high
;
2677 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2678 return vmx_msr_high
& ctl
;
2681 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2683 u32 vmx_msr_low
, vmx_msr_high
;
2684 u32 min
, opt
, min2
, opt2
;
2685 u32 _pin_based_exec_control
= 0;
2686 u32 _cpu_based_exec_control
= 0;
2687 u32 _cpu_based_2nd_exec_control
= 0;
2688 u32 _vmexit_control
= 0;
2689 u32 _vmentry_control
= 0;
2691 min
= CPU_BASED_HLT_EXITING
|
2692 #ifdef CONFIG_X86_64
2693 CPU_BASED_CR8_LOAD_EXITING
|
2694 CPU_BASED_CR8_STORE_EXITING
|
2696 CPU_BASED_CR3_LOAD_EXITING
|
2697 CPU_BASED_CR3_STORE_EXITING
|
2698 CPU_BASED_USE_IO_BITMAPS
|
2699 CPU_BASED_MOV_DR_EXITING
|
2700 CPU_BASED_USE_TSC_OFFSETING
|
2701 CPU_BASED_MWAIT_EXITING
|
2702 CPU_BASED_MONITOR_EXITING
|
2703 CPU_BASED_INVLPG_EXITING
|
2704 CPU_BASED_RDPMC_EXITING
;
2706 opt
= CPU_BASED_TPR_SHADOW
|
2707 CPU_BASED_USE_MSR_BITMAPS
|
2708 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2709 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2710 &_cpu_based_exec_control
) < 0)
2712 #ifdef CONFIG_X86_64
2713 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2714 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2715 ~CPU_BASED_CR8_STORE_EXITING
;
2717 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2719 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2720 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2721 SECONDARY_EXEC_WBINVD_EXITING
|
2722 SECONDARY_EXEC_ENABLE_VPID
|
2723 SECONDARY_EXEC_ENABLE_EPT
|
2724 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2725 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2726 SECONDARY_EXEC_RDTSCP
|
2727 SECONDARY_EXEC_ENABLE_INVPCID
|
2728 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2729 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2730 SECONDARY_EXEC_SHADOW_VMCS
;
2731 if (adjust_vmx_controls(min2
, opt2
,
2732 MSR_IA32_VMX_PROCBASED_CTLS2
,
2733 &_cpu_based_2nd_exec_control
) < 0)
2736 #ifndef CONFIG_X86_64
2737 if (!(_cpu_based_2nd_exec_control
&
2738 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2739 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2742 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2743 _cpu_based_2nd_exec_control
&= ~(
2744 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2745 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2746 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2748 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2749 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2751 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2752 CPU_BASED_CR3_STORE_EXITING
|
2753 CPU_BASED_INVLPG_EXITING
);
2754 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2755 vmx_capability
.ept
, vmx_capability
.vpid
);
2759 #ifdef CONFIG_X86_64
2760 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2762 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2763 VM_EXIT_ACK_INTR_ON_EXIT
;
2764 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2765 &_vmexit_control
) < 0)
2768 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2769 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2770 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2771 &_pin_based_exec_control
) < 0)
2774 if (!(_cpu_based_2nd_exec_control
&
2775 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2776 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2777 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2780 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2781 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2782 &_vmentry_control
) < 0)
2785 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2787 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2788 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2791 #ifdef CONFIG_X86_64
2792 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2793 if (vmx_msr_high
& (1u<<16))
2797 /* Require Write-Back (WB) memory type for VMCS accesses. */
2798 if (((vmx_msr_high
>> 18) & 15) != 6)
2801 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2802 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2803 vmcs_conf
->revision_id
= vmx_msr_low
;
2805 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2806 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2807 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2808 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2809 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2811 cpu_has_load_ia32_efer
=
2812 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2813 VM_ENTRY_LOAD_IA32_EFER
)
2814 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2815 VM_EXIT_LOAD_IA32_EFER
);
2817 cpu_has_load_perf_global_ctrl
=
2818 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2819 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2820 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2821 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2824 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2825 * but due to arrata below it can't be used. Workaround is to use
2826 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2828 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2833 * BC86,AAY89,BD102 (model 44)
2837 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2838 switch (boot_cpu_data
.x86_model
) {
2844 cpu_has_load_perf_global_ctrl
= false;
2845 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2846 "does not work properly. Using workaround\n");
2856 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2858 int node
= cpu_to_node(cpu
);
2862 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2865 vmcs
= page_address(pages
);
2866 memset(vmcs
, 0, vmcs_config
.size
);
2867 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2871 static struct vmcs
*alloc_vmcs(void)
2873 return alloc_vmcs_cpu(raw_smp_processor_id());
2876 static void free_vmcs(struct vmcs
*vmcs
)
2878 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2882 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2884 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2886 if (!loaded_vmcs
->vmcs
)
2888 loaded_vmcs_clear(loaded_vmcs
);
2889 free_vmcs(loaded_vmcs
->vmcs
);
2890 loaded_vmcs
->vmcs
= NULL
;
2893 static void free_kvm_area(void)
2897 for_each_possible_cpu(cpu
) {
2898 free_vmcs(per_cpu(vmxarea
, cpu
));
2899 per_cpu(vmxarea
, cpu
) = NULL
;
2903 static __init
int alloc_kvm_area(void)
2907 for_each_possible_cpu(cpu
) {
2910 vmcs
= alloc_vmcs_cpu(cpu
);
2916 per_cpu(vmxarea
, cpu
) = vmcs
;
2921 static __init
int hardware_setup(void)
2923 if (setup_vmcs_config(&vmcs_config
) < 0)
2926 if (boot_cpu_has(X86_FEATURE_NX
))
2927 kvm_enable_efer_bits(EFER_NX
);
2929 if (!cpu_has_vmx_vpid())
2931 if (!cpu_has_vmx_shadow_vmcs())
2932 enable_shadow_vmcs
= 0;
2934 if (!cpu_has_vmx_ept() ||
2935 !cpu_has_vmx_ept_4levels()) {
2937 enable_unrestricted_guest
= 0;
2938 enable_ept_ad_bits
= 0;
2941 if (!cpu_has_vmx_ept_ad_bits())
2942 enable_ept_ad_bits
= 0;
2944 if (!cpu_has_vmx_unrestricted_guest())
2945 enable_unrestricted_guest
= 0;
2947 if (!cpu_has_vmx_flexpriority())
2948 flexpriority_enabled
= 0;
2950 if (!cpu_has_vmx_tpr_shadow())
2951 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2953 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2954 kvm_disable_largepages();
2956 if (!cpu_has_vmx_ple())
2959 if (!cpu_has_vmx_apicv())
2963 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2965 kvm_x86_ops
->hwapic_irr_update
= NULL
;
2966 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
2967 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
2971 nested_vmx_setup_ctls_msrs();
2973 return alloc_kvm_area();
2976 static __exit
void hardware_unsetup(void)
2981 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2983 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2986 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
2987 struct kvm_segment
*save
)
2989 if (!emulate_invalid_guest_state
) {
2991 * CS and SS RPL should be equal during guest entry according
2992 * to VMX spec, but in reality it is not always so. Since vcpu
2993 * is in the middle of the transition from real mode to
2994 * protected mode it is safe to assume that RPL 0 is a good
2997 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
2998 save
->selector
&= ~SELECTOR_RPL_MASK
;
2999 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3002 vmx_set_segment(vcpu
, save
, seg
);
3005 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3007 unsigned long flags
;
3008 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3011 * Update real mode segment cache. It may be not up-to-date if sement
3012 * register was written while vcpu was in a guest mode.
3014 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3015 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3016 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3017 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3018 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3019 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3021 vmx
->rmode
.vm86_active
= 0;
3023 vmx_segment_cache_clear(vmx
);
3025 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3027 flags
= vmcs_readl(GUEST_RFLAGS
);
3028 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3029 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3030 vmcs_writel(GUEST_RFLAGS
, flags
);
3032 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3033 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3035 update_exception_bitmap(vcpu
);
3037 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3038 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3039 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3040 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3041 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3042 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3044 /* CPL is always 0 when CPU enters protected mode */
3045 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3049 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3051 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3052 struct kvm_segment var
= *save
;
3055 if (seg
== VCPU_SREG_CS
)
3058 if (!emulate_invalid_guest_state
) {
3059 var
.selector
= var
.base
>> 4;
3060 var
.base
= var
.base
& 0xffff0;
3070 if (save
->base
& 0xf)
3071 printk_once(KERN_WARNING
"kvm: segment base is not "
3072 "paragraph aligned when entering "
3073 "protected mode (seg=%d)", seg
);
3076 vmcs_write16(sf
->selector
, var
.selector
);
3077 vmcs_writel(sf
->base
, var
.base
);
3078 vmcs_write32(sf
->limit
, var
.limit
);
3079 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3082 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3084 unsigned long flags
;
3085 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3087 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3088 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3089 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3090 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3091 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3092 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3093 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3095 vmx
->rmode
.vm86_active
= 1;
3098 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3099 * vcpu. Warn the user that an update is overdue.
3101 if (!vcpu
->kvm
->arch
.tss_addr
)
3102 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3103 "called before entering vcpu\n");
3105 vmx_segment_cache_clear(vmx
);
3107 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3108 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3109 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3111 flags
= vmcs_readl(GUEST_RFLAGS
);
3112 vmx
->rmode
.save_rflags
= flags
;
3114 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3116 vmcs_writel(GUEST_RFLAGS
, flags
);
3117 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3118 update_exception_bitmap(vcpu
);
3120 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3121 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3122 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3123 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3124 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3125 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3127 kvm_mmu_reset_context(vcpu
);
3130 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3132 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3133 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3139 * Force kernel_gs_base reloading before EFER changes, as control
3140 * of this msr depends on is_long_mode().
3142 vmx_load_host_state(to_vmx(vcpu
));
3143 vcpu
->arch
.efer
= efer
;
3144 if (efer
& EFER_LMA
) {
3145 vmcs_write32(VM_ENTRY_CONTROLS
,
3146 vmcs_read32(VM_ENTRY_CONTROLS
) |
3147 VM_ENTRY_IA32E_MODE
);
3150 vmcs_write32(VM_ENTRY_CONTROLS
,
3151 vmcs_read32(VM_ENTRY_CONTROLS
) &
3152 ~VM_ENTRY_IA32E_MODE
);
3154 msr
->data
= efer
& ~EFER_LME
;
3159 #ifdef CONFIG_X86_64
3161 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3165 vmx_segment_cache_clear(to_vmx(vcpu
));
3167 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3168 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3169 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3171 vmcs_write32(GUEST_TR_AR_BYTES
,
3172 (guest_tr_ar
& ~AR_TYPE_MASK
)
3173 | AR_TYPE_BUSY_64_TSS
);
3175 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3178 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3180 vmcs_write32(VM_ENTRY_CONTROLS
,
3181 vmcs_read32(VM_ENTRY_CONTROLS
)
3182 & ~VM_ENTRY_IA32E_MODE
);
3183 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3188 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3190 vpid_sync_context(to_vmx(vcpu
));
3192 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3194 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3198 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3200 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3202 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3203 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3206 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3208 if (enable_ept
&& is_paging(vcpu
))
3209 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3210 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3213 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3215 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3217 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3218 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3221 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3223 if (!test_bit(VCPU_EXREG_PDPTR
,
3224 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3227 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3228 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
3229 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
3230 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
3231 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
3235 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3237 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3238 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3239 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3240 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3241 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3244 __set_bit(VCPU_EXREG_PDPTR
,
3245 (unsigned long *)&vcpu
->arch
.regs_avail
);
3246 __set_bit(VCPU_EXREG_PDPTR
,
3247 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3250 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3252 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3254 struct kvm_vcpu
*vcpu
)
3256 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3257 vmx_decache_cr3(vcpu
);
3258 if (!(cr0
& X86_CR0_PG
)) {
3259 /* From paging/starting to nonpaging */
3260 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3261 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3262 (CPU_BASED_CR3_LOAD_EXITING
|
3263 CPU_BASED_CR3_STORE_EXITING
));
3264 vcpu
->arch
.cr0
= cr0
;
3265 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3266 } else if (!is_paging(vcpu
)) {
3267 /* From nonpaging to paging */
3268 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3269 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3270 ~(CPU_BASED_CR3_LOAD_EXITING
|
3271 CPU_BASED_CR3_STORE_EXITING
));
3272 vcpu
->arch
.cr0
= cr0
;
3273 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3276 if (!(cr0
& X86_CR0_WP
))
3277 *hw_cr0
&= ~X86_CR0_WP
;
3280 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3282 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3283 unsigned long hw_cr0
;
3285 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3286 if (enable_unrestricted_guest
)
3287 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3289 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3291 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3294 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3298 #ifdef CONFIG_X86_64
3299 if (vcpu
->arch
.efer
& EFER_LME
) {
3300 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3302 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3308 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3310 if (!vcpu
->fpu_active
)
3311 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3313 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3314 vmcs_writel(GUEST_CR0
, hw_cr0
);
3315 vcpu
->arch
.cr0
= cr0
;
3317 /* depends on vcpu->arch.cr0 to be set to a new value */
3318 vmx
->emulation_required
= emulation_required(vcpu
);
3321 static u64
construct_eptp(unsigned long root_hpa
)
3325 /* TODO write the value reading from MSR */
3326 eptp
= VMX_EPT_DEFAULT_MT
|
3327 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3328 if (enable_ept_ad_bits
)
3329 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3330 eptp
|= (root_hpa
& PAGE_MASK
);
3335 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3337 unsigned long guest_cr3
;
3342 eptp
= construct_eptp(cr3
);
3343 vmcs_write64(EPT_POINTER
, eptp
);
3344 guest_cr3
= is_paging(vcpu
) ? kvm_read_cr3(vcpu
) :
3345 vcpu
->kvm
->arch
.ept_identity_map_addr
;
3346 ept_load_pdptrs(vcpu
);
3349 vmx_flush_tlb(vcpu
);
3350 vmcs_writel(GUEST_CR3
, guest_cr3
);
3353 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3355 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3356 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3358 if (cr4
& X86_CR4_VMXE
) {
3360 * To use VMXON (and later other VMX instructions), a guest
3361 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3362 * So basically the check on whether to allow nested VMX
3365 if (!nested_vmx_allowed(vcpu
))
3368 if (to_vmx(vcpu
)->nested
.vmxon
&&
3369 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3372 vcpu
->arch
.cr4
= cr4
;
3374 if (!is_paging(vcpu
)) {
3375 hw_cr4
&= ~X86_CR4_PAE
;
3376 hw_cr4
|= X86_CR4_PSE
;
3378 * SMEP is disabled if CPU is in non-paging mode in
3379 * hardware. However KVM always uses paging mode to
3380 * emulate guest non-paging mode with TDP.
3381 * To emulate this behavior, SMEP needs to be manually
3382 * disabled when guest switches to non-paging mode.
3384 hw_cr4
&= ~X86_CR4_SMEP
;
3385 } else if (!(cr4
& X86_CR4_PAE
)) {
3386 hw_cr4
&= ~X86_CR4_PAE
;
3390 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3391 vmcs_writel(GUEST_CR4
, hw_cr4
);
3395 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3396 struct kvm_segment
*var
, int seg
)
3398 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3401 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3402 *var
= vmx
->rmode
.segs
[seg
];
3403 if (seg
== VCPU_SREG_TR
3404 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3406 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3407 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3410 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3411 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3412 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3413 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3414 var
->unusable
= (ar
>> 16) & 1;
3415 var
->type
= ar
& 15;
3416 var
->s
= (ar
>> 4) & 1;
3417 var
->dpl
= (ar
>> 5) & 3;
3419 * Some userspaces do not preserve unusable property. Since usable
3420 * segment has to be present according to VMX spec we can use present
3421 * property to amend userspace bug by making unusable segment always
3422 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3423 * segment as unusable.
3425 var
->present
= !var
->unusable
;
3426 var
->avl
= (ar
>> 12) & 1;
3427 var
->l
= (ar
>> 13) & 1;
3428 var
->db
= (ar
>> 14) & 1;
3429 var
->g
= (ar
>> 15) & 1;
3432 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3434 struct kvm_segment s
;
3436 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3437 vmx_get_segment(vcpu
, &s
, seg
);
3440 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3443 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3445 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3447 if (!is_protmode(vcpu
))
3450 if (!is_long_mode(vcpu
)
3451 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3454 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3455 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3456 vmx
->cpl
= vmx_read_guest_seg_selector(vmx
, VCPU_SREG_CS
) & 3;
3463 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3467 if (var
->unusable
|| !var
->present
)
3470 ar
= var
->type
& 15;
3471 ar
|= (var
->s
& 1) << 4;
3472 ar
|= (var
->dpl
& 3) << 5;
3473 ar
|= (var
->present
& 1) << 7;
3474 ar
|= (var
->avl
& 1) << 12;
3475 ar
|= (var
->l
& 1) << 13;
3476 ar
|= (var
->db
& 1) << 14;
3477 ar
|= (var
->g
& 1) << 15;
3483 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3484 struct kvm_segment
*var
, int seg
)
3486 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3487 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3489 vmx_segment_cache_clear(vmx
);
3490 if (seg
== VCPU_SREG_CS
)
3491 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3493 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3494 vmx
->rmode
.segs
[seg
] = *var
;
3495 if (seg
== VCPU_SREG_TR
)
3496 vmcs_write16(sf
->selector
, var
->selector
);
3498 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3502 vmcs_writel(sf
->base
, var
->base
);
3503 vmcs_write32(sf
->limit
, var
->limit
);
3504 vmcs_write16(sf
->selector
, var
->selector
);
3507 * Fix the "Accessed" bit in AR field of segment registers for older
3509 * IA32 arch specifies that at the time of processor reset the
3510 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3511 * is setting it to 0 in the userland code. This causes invalid guest
3512 * state vmexit when "unrestricted guest" mode is turned on.
3513 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3514 * tree. Newer qemu binaries with that qemu fix would not need this
3517 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3518 var
->type
|= 0x1; /* Accessed */
3520 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3523 vmx
->emulation_required
|= emulation_required(vcpu
);
3526 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3528 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3530 *db
= (ar
>> 14) & 1;
3531 *l
= (ar
>> 13) & 1;
3534 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3536 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3537 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3540 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3542 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3543 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3546 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3548 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3549 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3552 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3554 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3555 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3558 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3560 struct kvm_segment var
;
3563 vmx_get_segment(vcpu
, &var
, seg
);
3565 if (seg
== VCPU_SREG_CS
)
3567 ar
= vmx_segment_access_rights(&var
);
3569 if (var
.base
!= (var
.selector
<< 4))
3571 if (var
.limit
!= 0xffff)
3579 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3581 struct kvm_segment cs
;
3582 unsigned int cs_rpl
;
3584 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3585 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3589 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3593 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3594 if (cs
.dpl
> cs_rpl
)
3597 if (cs
.dpl
!= cs_rpl
)
3603 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3607 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3609 struct kvm_segment ss
;
3610 unsigned int ss_rpl
;
3612 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3613 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3617 if (ss
.type
!= 3 && ss
.type
!= 7)
3621 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3629 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3631 struct kvm_segment var
;
3634 vmx_get_segment(vcpu
, &var
, seg
);
3635 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3643 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3644 if (var
.dpl
< rpl
) /* DPL < RPL */
3648 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3654 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3656 struct kvm_segment tr
;
3658 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3662 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3664 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3672 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3674 struct kvm_segment ldtr
;
3676 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3680 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3690 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3692 struct kvm_segment cs
, ss
;
3694 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3695 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3697 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3698 (ss
.selector
& SELECTOR_RPL_MASK
));
3702 * Check if guest state is valid. Returns true if valid, false if
3704 * We assume that registers are always usable
3706 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3708 if (enable_unrestricted_guest
)
3711 /* real mode guest state checks */
3712 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3713 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3715 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3717 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3719 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3721 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3723 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3726 /* protected mode guest state checks */
3727 if (!cs_ss_rpl_check(vcpu
))
3729 if (!code_segment_valid(vcpu
))
3731 if (!stack_segment_valid(vcpu
))
3733 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3735 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3737 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3739 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3741 if (!tr_valid(vcpu
))
3743 if (!ldtr_valid(vcpu
))
3747 * - Add checks on RIP
3748 * - Add checks on RFLAGS
3754 static int init_rmode_tss(struct kvm
*kvm
)
3758 int r
, idx
, ret
= 0;
3760 idx
= srcu_read_lock(&kvm
->srcu
);
3761 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3762 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3765 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3766 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3767 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3770 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3773 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3777 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3778 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3785 srcu_read_unlock(&kvm
->srcu
, idx
);
3789 static int init_rmode_identity_map(struct kvm
*kvm
)
3792 pfn_t identity_map_pfn
;
3797 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3798 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3799 "haven't been allocated!\n");
3802 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3805 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3806 idx
= srcu_read_lock(&kvm
->srcu
);
3807 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3810 /* Set up identity-mapping pagetable for EPT in real mode */
3811 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3812 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3813 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3814 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3815 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3819 kvm
->arch
.ept_identity_pagetable_done
= true;
3822 srcu_read_unlock(&kvm
->srcu
, idx
);
3826 static void seg_setup(int seg
)
3828 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3831 vmcs_write16(sf
->selector
, 0);
3832 vmcs_writel(sf
->base
, 0);
3833 vmcs_write32(sf
->limit
, 0xffff);
3835 if (seg
== VCPU_SREG_CS
)
3836 ar
|= 0x08; /* code segment */
3838 vmcs_write32(sf
->ar_bytes
, ar
);
3841 static int alloc_apic_access_page(struct kvm
*kvm
)
3844 struct kvm_userspace_memory_region kvm_userspace_mem
;
3847 mutex_lock(&kvm
->slots_lock
);
3848 if (kvm
->arch
.apic_access_page
)
3850 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3851 kvm_userspace_mem
.flags
= 0;
3852 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3853 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3854 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3858 page
= gfn_to_page(kvm
, 0xfee00);
3859 if (is_error_page(page
)) {
3864 kvm
->arch
.apic_access_page
= page
;
3866 mutex_unlock(&kvm
->slots_lock
);
3870 static int alloc_identity_pagetable(struct kvm
*kvm
)
3873 struct kvm_userspace_memory_region kvm_userspace_mem
;
3876 mutex_lock(&kvm
->slots_lock
);
3877 if (kvm
->arch
.ept_identity_pagetable
)
3879 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3880 kvm_userspace_mem
.flags
= 0;
3881 kvm_userspace_mem
.guest_phys_addr
=
3882 kvm
->arch
.ept_identity_map_addr
;
3883 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3884 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3888 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3889 if (is_error_page(page
)) {
3894 kvm
->arch
.ept_identity_pagetable
= page
;
3896 mutex_unlock(&kvm
->slots_lock
);
3900 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3907 spin_lock(&vmx_vpid_lock
);
3908 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3909 if (vpid
< VMX_NR_VPIDS
) {
3911 __set_bit(vpid
, vmx_vpid_bitmap
);
3913 spin_unlock(&vmx_vpid_lock
);
3916 static void free_vpid(struct vcpu_vmx
*vmx
)
3920 spin_lock(&vmx_vpid_lock
);
3922 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3923 spin_unlock(&vmx_vpid_lock
);
3926 #define MSR_TYPE_R 1
3927 #define MSR_TYPE_W 2
3928 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
3931 int f
= sizeof(unsigned long);
3933 if (!cpu_has_vmx_msr_bitmap())
3937 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3938 * have the write-low and read-high bitmap offsets the wrong way round.
3939 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3941 if (msr
<= 0x1fff) {
3942 if (type
& MSR_TYPE_R
)
3944 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
3946 if (type
& MSR_TYPE_W
)
3948 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
3950 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3952 if (type
& MSR_TYPE_R
)
3954 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
3956 if (type
& MSR_TYPE_W
)
3958 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
3963 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
3966 int f
= sizeof(unsigned long);
3968 if (!cpu_has_vmx_msr_bitmap())
3972 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3973 * have the write-low and read-high bitmap offsets the wrong way round.
3974 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3976 if (msr
<= 0x1fff) {
3977 if (type
& MSR_TYPE_R
)
3979 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
3981 if (type
& MSR_TYPE_W
)
3983 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
3985 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3987 if (type
& MSR_TYPE_R
)
3989 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
3991 if (type
& MSR_TYPE_W
)
3993 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
3998 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4001 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4002 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4003 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4004 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4007 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4009 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4011 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4015 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4017 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4019 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4023 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4025 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4027 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4031 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4033 return enable_apicv
&& irqchip_in_kernel(kvm
);
4037 * Send interrupt to vcpu via posted interrupt way.
4038 * 1. If target vcpu is running(non-root mode), send posted interrupt
4039 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4040 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4041 * interrupt from PIR in next vmentry.
4043 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4045 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4048 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4051 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4052 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4054 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4055 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4056 POSTED_INTR_VECTOR
);
4059 kvm_vcpu_kick(vcpu
);
4062 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4064 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4066 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4069 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4072 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4078 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4079 * will not change in the lifetime of the guest.
4080 * Note that host-state that does change is set elsewhere. E.g., host-state
4081 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4083 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4090 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4091 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4093 /* Save the most likely value for this task's CR4 in the VMCS. */
4095 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4096 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4098 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4099 #ifdef CONFIG_X86_64
4101 * Load null selectors, so we can avoid reloading them in
4102 * __vmx_load_host_state(), in case userspace uses the null selectors
4103 * too (the expected case).
4105 vmcs_write16(HOST_DS_SELECTOR
, 0);
4106 vmcs_write16(HOST_ES_SELECTOR
, 0);
4108 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4109 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4111 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4112 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4114 native_store_idt(&dt
);
4115 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4116 vmx
->host_idt_base
= dt
.address
;
4118 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4120 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4121 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4122 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4123 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4125 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4126 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4127 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4131 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4133 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4135 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4136 if (is_guest_mode(&vmx
->vcpu
))
4137 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4138 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4139 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4142 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4144 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4146 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4147 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4148 return pin_based_exec_ctrl
;
4151 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4153 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4154 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4155 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4156 #ifdef CONFIG_X86_64
4157 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4158 CPU_BASED_CR8_LOAD_EXITING
;
4162 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4163 CPU_BASED_CR3_LOAD_EXITING
|
4164 CPU_BASED_INVLPG_EXITING
;
4165 return exec_control
;
4168 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4170 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4171 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4172 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4174 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4176 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4177 enable_unrestricted_guest
= 0;
4178 /* Enable INVPCID for non-ept guests may cause performance regression. */
4179 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4181 if (!enable_unrestricted_guest
)
4182 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4184 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4185 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4186 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4187 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4188 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4189 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4191 We can NOT enable shadow_vmcs here because we don't have yet
4194 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4195 return exec_control
;
4198 static void ept_set_mmio_spte_mask(void)
4201 * EPT Misconfigurations can be generated if the value of bits 2:0
4202 * of an EPT paging-structure entry is 110b (write/execute).
4203 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
4206 kvm_mmu_set_mmio_spte_mask(0xffull
<< 49 | 0x6ull
);
4210 * Sets up the vmcs for emulated real mode.
4212 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4214 #ifdef CONFIG_X86_64
4220 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4221 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4223 if (enable_shadow_vmcs
) {
4224 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4225 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4227 if (cpu_has_vmx_msr_bitmap())
4228 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4230 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4233 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4235 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4237 if (cpu_has_secondary_exec_ctrls()) {
4238 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4239 vmx_secondary_exec_control(vmx
));
4242 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4243 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4244 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4245 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4246 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4248 vmcs_write16(GUEST_INTR_STATUS
, 0);
4250 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4251 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4255 vmcs_write32(PLE_GAP
, ple_gap
);
4256 vmcs_write32(PLE_WINDOW
, ple_window
);
4259 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4260 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4261 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4263 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4264 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4265 vmx_set_constant_host_state(vmx
);
4266 #ifdef CONFIG_X86_64
4267 rdmsrl(MSR_FS_BASE
, a
);
4268 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4269 rdmsrl(MSR_GS_BASE
, a
);
4270 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4272 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4273 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4276 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4277 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4278 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4279 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4280 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4282 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4283 u32 msr_low
, msr_high
;
4285 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4286 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4287 /* Write the default value follow host pat */
4288 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4289 /* Keep arch.pat sync with GUEST_IA32_PAT */
4290 vmx
->vcpu
.arch
.pat
= host_pat
;
4293 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
4294 u32 index
= vmx_msr_index
[i
];
4295 u32 data_low
, data_high
;
4298 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4300 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4302 vmx
->guest_msrs
[j
].index
= i
;
4303 vmx
->guest_msrs
[j
].data
= 0;
4304 vmx
->guest_msrs
[j
].mask
= -1ull;
4308 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
4310 /* 22.2.1, 20.8.1 */
4311 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
4313 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4314 set_cr4_guest_host_mask(vmx
);
4319 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4321 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4324 vmx
->rmode
.vm86_active
= 0;
4326 vmx
->soft_vnmi_blocked
= 0;
4328 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4329 kvm_set_cr8(&vmx
->vcpu
, 0);
4330 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4331 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4332 msr
|= MSR_IA32_APICBASE_BSP
;
4333 kvm_set_apic_base(&vmx
->vcpu
, msr
);
4335 vmx_segment_cache_clear(vmx
);
4337 seg_setup(VCPU_SREG_CS
);
4338 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4339 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4341 seg_setup(VCPU_SREG_DS
);
4342 seg_setup(VCPU_SREG_ES
);
4343 seg_setup(VCPU_SREG_FS
);
4344 seg_setup(VCPU_SREG_GS
);
4345 seg_setup(VCPU_SREG_SS
);
4347 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4348 vmcs_writel(GUEST_TR_BASE
, 0);
4349 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4350 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4352 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4353 vmcs_writel(GUEST_LDTR_BASE
, 0);
4354 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4355 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4357 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4358 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4359 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4361 vmcs_writel(GUEST_RFLAGS
, 0x02);
4362 kvm_rip_write(vcpu
, 0xfff0);
4364 vmcs_writel(GUEST_GDTR_BASE
, 0);
4365 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4367 vmcs_writel(GUEST_IDTR_BASE
, 0);
4368 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4370 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4371 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4372 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4374 /* Special registers */
4375 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4379 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4381 if (cpu_has_vmx_tpr_shadow()) {
4382 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4383 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4384 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4385 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4386 vmcs_write32(TPR_THRESHOLD
, 0);
4389 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4390 vmcs_write64(APIC_ACCESS_ADDR
,
4391 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4393 if (vmx_vm_has_apicv(vcpu
->kvm
))
4394 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4397 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4399 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4400 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4401 vmx_set_cr4(&vmx
->vcpu
, 0);
4402 vmx_set_efer(&vmx
->vcpu
, 0);
4403 vmx_fpu_activate(&vmx
->vcpu
);
4404 update_exception_bitmap(&vmx
->vcpu
);
4406 vpid_sync_context(vmx
);
4410 * In nested virtualization, check if L1 asked to exit on external interrupts.
4411 * For most existing hypervisors, this will always return true.
4413 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4415 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4416 PIN_BASED_EXT_INTR_MASK
;
4419 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4421 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4422 PIN_BASED_NMI_EXITING
;
4425 static int enable_irq_window(struct kvm_vcpu
*vcpu
)
4427 u32 cpu_based_vm_exec_control
;
4429 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
4431 * We get here if vmx_interrupt_allowed() said we can't
4432 * inject to L1 now because L2 must run. The caller will have
4433 * to make L2 exit right after entry, so we can inject to L1
4438 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4439 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4440 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4444 static int enable_nmi_window(struct kvm_vcpu
*vcpu
)
4446 u32 cpu_based_vm_exec_control
;
4448 if (!cpu_has_virtual_nmis())
4449 return enable_irq_window(vcpu
);
4451 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
)
4452 return enable_irq_window(vcpu
);
4454 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4455 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4456 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4460 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4462 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4464 int irq
= vcpu
->arch
.interrupt
.nr
;
4466 trace_kvm_inj_virq(irq
);
4468 ++vcpu
->stat
.irq_injections
;
4469 if (vmx
->rmode
.vm86_active
) {
4471 if (vcpu
->arch
.interrupt
.soft
)
4472 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4473 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4474 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4477 intr
= irq
| INTR_INFO_VALID_MASK
;
4478 if (vcpu
->arch
.interrupt
.soft
) {
4479 intr
|= INTR_TYPE_SOFT_INTR
;
4480 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4481 vmx
->vcpu
.arch
.event_exit_inst_len
);
4483 intr
|= INTR_TYPE_EXT_INTR
;
4484 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4487 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4489 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4491 if (is_guest_mode(vcpu
))
4494 if (!cpu_has_virtual_nmis()) {
4496 * Tracking the NMI-blocked state in software is built upon
4497 * finding the next open IRQ window. This, in turn, depends on
4498 * well-behaving guests: They have to keep IRQs disabled at
4499 * least as long as the NMI handler runs. Otherwise we may
4500 * cause NMI nesting, maybe breaking the guest. But as this is
4501 * highly unlikely, we can live with the residual risk.
4503 vmx
->soft_vnmi_blocked
= 1;
4504 vmx
->vnmi_blocked_time
= 0;
4507 ++vcpu
->stat
.nmi_injections
;
4508 vmx
->nmi_known_unmasked
= false;
4509 if (vmx
->rmode
.vm86_active
) {
4510 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4511 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4514 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4515 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4518 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4520 if (!cpu_has_virtual_nmis())
4521 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4522 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4524 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4527 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4529 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4531 if (!cpu_has_virtual_nmis()) {
4532 if (vmx
->soft_vnmi_blocked
!= masked
) {
4533 vmx
->soft_vnmi_blocked
= masked
;
4534 vmx
->vnmi_blocked_time
= 0;
4537 vmx
->nmi_known_unmasked
= !masked
;
4539 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4540 GUEST_INTR_STATE_NMI
);
4542 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4543 GUEST_INTR_STATE_NMI
);
4547 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4549 if (is_guest_mode(vcpu
)) {
4550 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4552 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4554 if (nested_exit_on_nmi(vcpu
)) {
4555 nested_vmx_vmexit(vcpu
);
4556 vmcs12
->vm_exit_reason
= EXIT_REASON_EXCEPTION_NMI
;
4557 vmcs12
->vm_exit_intr_info
= NMI_VECTOR
|
4558 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
;
4560 * The NMI-triggered VM exit counts as injection:
4561 * clear this one and block further NMIs.
4563 vcpu
->arch
.nmi_pending
= 0;
4564 vmx_set_nmi_mask(vcpu
, true);
4569 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4572 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4573 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4574 | GUEST_INTR_STATE_NMI
));
4577 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4579 if (is_guest_mode(vcpu
)) {
4580 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4582 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4584 if (nested_exit_on_intr(vcpu
)) {
4585 nested_vmx_vmexit(vcpu
);
4586 vmcs12
->vm_exit_reason
=
4587 EXIT_REASON_EXTERNAL_INTERRUPT
;
4588 vmcs12
->vm_exit_intr_info
= 0;
4590 * fall through to normal code, but now in L1, not L2
4595 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4596 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4597 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4600 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4603 struct kvm_userspace_memory_region tss_mem
= {
4604 .slot
= TSS_PRIVATE_MEMSLOT
,
4605 .guest_phys_addr
= addr
,
4606 .memory_size
= PAGE_SIZE
* 3,
4610 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4613 kvm
->arch
.tss_addr
= addr
;
4614 if (!init_rmode_tss(kvm
))
4620 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4625 * Update instruction length as we may reinject the exception
4626 * from user space while in guest debugging mode.
4628 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4629 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4630 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4634 if (vcpu
->guest_debug
&
4635 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4652 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4653 int vec
, u32 err_code
)
4656 * Instruction with address size override prefix opcode 0x67
4657 * Cause the #SS fault with 0 error code in VM86 mode.
4659 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4660 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4661 if (vcpu
->arch
.halt_request
) {
4662 vcpu
->arch
.halt_request
= 0;
4663 return kvm_emulate_halt(vcpu
);
4671 * Forward all other exceptions that are valid in real mode.
4672 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4673 * the required debugging infrastructure rework.
4675 kvm_queue_exception(vcpu
, vec
);
4680 * Trigger machine check on the host. We assume all the MSRs are already set up
4681 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4682 * We pass a fake environment to the machine check handler because we want
4683 * the guest to be always treated like user space, no matter what context
4684 * it used internally.
4686 static void kvm_machine_check(void)
4688 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4689 struct pt_regs regs
= {
4690 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4691 .flags
= X86_EFLAGS_IF
,
4694 do_machine_check(®s
, 0);
4698 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4700 /* already handled by vcpu_run */
4704 static int handle_exception(struct kvm_vcpu
*vcpu
)
4706 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4707 struct kvm_run
*kvm_run
= vcpu
->run
;
4708 u32 intr_info
, ex_no
, error_code
;
4709 unsigned long cr2
, rip
, dr6
;
4711 enum emulation_result er
;
4713 vect_info
= vmx
->idt_vectoring_info
;
4714 intr_info
= vmx
->exit_intr_info
;
4716 if (is_machine_check(intr_info
))
4717 return handle_machine_check(vcpu
);
4719 if (is_nmi(intr_info
))
4720 return 1; /* already handled by vmx_vcpu_run() */
4722 if (is_no_device(intr_info
)) {
4723 vmx_fpu_activate(vcpu
);
4727 if (is_invalid_opcode(intr_info
)) {
4728 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4729 if (er
!= EMULATE_DONE
)
4730 kvm_queue_exception(vcpu
, UD_VECTOR
);
4735 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4736 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4739 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4740 * MMIO, it is better to report an internal error.
4741 * See the comments in vmx_handle_exit.
4743 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4744 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4745 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4746 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4747 vcpu
->run
->internal
.ndata
= 2;
4748 vcpu
->run
->internal
.data
[0] = vect_info
;
4749 vcpu
->run
->internal
.data
[1] = intr_info
;
4753 if (is_page_fault(intr_info
)) {
4754 /* EPT won't cause page fault directly */
4756 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4757 trace_kvm_page_fault(cr2
, error_code
);
4759 if (kvm_event_needs_reinjection(vcpu
))
4760 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4761 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4764 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4766 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4767 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4771 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4772 if (!(vcpu
->guest_debug
&
4773 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4774 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
4775 kvm_queue_exception(vcpu
, DB_VECTOR
);
4778 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4779 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4783 * Update instruction length as we may reinject #BP from
4784 * user space while in guest debugging mode. Reading it for
4785 * #DB as well causes no harm, it is not used in that case.
4787 vmx
->vcpu
.arch
.event_exit_inst_len
=
4788 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4789 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4790 rip
= kvm_rip_read(vcpu
);
4791 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4792 kvm_run
->debug
.arch
.exception
= ex_no
;
4795 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4796 kvm_run
->ex
.exception
= ex_no
;
4797 kvm_run
->ex
.error_code
= error_code
;
4803 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4805 ++vcpu
->stat
.irq_exits
;
4809 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4811 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4815 static int handle_io(struct kvm_vcpu
*vcpu
)
4817 unsigned long exit_qualification
;
4818 int size
, in
, string
;
4821 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4822 string
= (exit_qualification
& 16) != 0;
4823 in
= (exit_qualification
& 8) != 0;
4825 ++vcpu
->stat
.io_exits
;
4828 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4830 port
= exit_qualification
>> 16;
4831 size
= (exit_qualification
& 7) + 1;
4832 skip_emulated_instruction(vcpu
);
4834 return kvm_fast_pio_out(vcpu
, size
, port
);
4838 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4841 * Patch in the VMCALL instruction:
4843 hypercall
[0] = 0x0f;
4844 hypercall
[1] = 0x01;
4845 hypercall
[2] = 0xc1;
4848 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4849 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4851 if (is_guest_mode(vcpu
)) {
4852 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4853 unsigned long orig_val
= val
;
4856 * We get here when L2 changed cr0 in a way that did not change
4857 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4858 * but did change L0 shadowed bits. So we first calculate the
4859 * effective cr0 value that L1 would like to write into the
4860 * hardware. It consists of the L2-owned bits from the new
4861 * value combined with the L1-owned bits from L1's guest_cr0.
4863 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
4864 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
4866 /* TODO: will have to take unrestricted guest mode into
4868 if ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
)
4871 if (kvm_set_cr0(vcpu
, val
))
4873 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
4876 if (to_vmx(vcpu
)->nested
.vmxon
&&
4877 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4879 return kvm_set_cr0(vcpu
, val
);
4883 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4885 if (is_guest_mode(vcpu
)) {
4886 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4887 unsigned long orig_val
= val
;
4889 /* analogously to handle_set_cr0 */
4890 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
4891 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
4892 if (kvm_set_cr4(vcpu
, val
))
4894 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
4897 return kvm_set_cr4(vcpu
, val
);
4900 /* called to set cr0 as approriate for clts instruction exit. */
4901 static void handle_clts(struct kvm_vcpu
*vcpu
)
4903 if (is_guest_mode(vcpu
)) {
4905 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4906 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4907 * just pretend it's off (also in arch.cr0 for fpu_activate).
4909 vmcs_writel(CR0_READ_SHADOW
,
4910 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4911 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4913 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4916 static int handle_cr(struct kvm_vcpu
*vcpu
)
4918 unsigned long exit_qualification
, val
;
4923 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4924 cr
= exit_qualification
& 15;
4925 reg
= (exit_qualification
>> 8) & 15;
4926 switch ((exit_qualification
>> 4) & 3) {
4927 case 0: /* mov to cr */
4928 val
= kvm_register_read(vcpu
, reg
);
4929 trace_kvm_cr_write(cr
, val
);
4932 err
= handle_set_cr0(vcpu
, val
);
4933 kvm_complete_insn_gp(vcpu
, err
);
4936 err
= kvm_set_cr3(vcpu
, val
);
4937 kvm_complete_insn_gp(vcpu
, err
);
4940 err
= handle_set_cr4(vcpu
, val
);
4941 kvm_complete_insn_gp(vcpu
, err
);
4944 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4945 u8 cr8
= kvm_register_read(vcpu
, reg
);
4946 err
= kvm_set_cr8(vcpu
, cr8
);
4947 kvm_complete_insn_gp(vcpu
, err
);
4948 if (irqchip_in_kernel(vcpu
->kvm
))
4950 if (cr8_prev
<= cr8
)
4952 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
4959 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
4960 skip_emulated_instruction(vcpu
);
4961 vmx_fpu_activate(vcpu
);
4963 case 1: /*mov from cr*/
4966 val
= kvm_read_cr3(vcpu
);
4967 kvm_register_write(vcpu
, reg
, val
);
4968 trace_kvm_cr_read(cr
, val
);
4969 skip_emulated_instruction(vcpu
);
4972 val
= kvm_get_cr8(vcpu
);
4973 kvm_register_write(vcpu
, reg
, val
);
4974 trace_kvm_cr_read(cr
, val
);
4975 skip_emulated_instruction(vcpu
);
4980 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
4981 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
4982 kvm_lmsw(vcpu
, val
);
4984 skip_emulated_instruction(vcpu
);
4989 vcpu
->run
->exit_reason
= 0;
4990 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
4991 (int)(exit_qualification
>> 4) & 3, cr
);
4995 static int handle_dr(struct kvm_vcpu
*vcpu
)
4997 unsigned long exit_qualification
;
5000 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5001 if (!kvm_require_cpl(vcpu
, 0))
5003 dr
= vmcs_readl(GUEST_DR7
);
5006 * As the vm-exit takes precedence over the debug trap, we
5007 * need to emulate the latter, either for the host or the
5008 * guest debugging itself.
5010 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5011 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5012 vcpu
->run
->debug
.arch
.dr7
= dr
;
5013 vcpu
->run
->debug
.arch
.pc
=
5014 vmcs_readl(GUEST_CS_BASE
) +
5015 vmcs_readl(GUEST_RIP
);
5016 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5017 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5020 vcpu
->arch
.dr7
&= ~DR7_GD
;
5021 vcpu
->arch
.dr6
|= DR6_BD
;
5022 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
5023 kvm_queue_exception(vcpu
, DB_VECTOR
);
5028 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5029 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5030 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5031 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5033 if (!kvm_get_dr(vcpu
, dr
, &val
))
5034 kvm_register_write(vcpu
, reg
, val
);
5036 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
5037 skip_emulated_instruction(vcpu
);
5041 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5043 vmcs_writel(GUEST_DR7
, val
);
5046 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5048 kvm_emulate_cpuid(vcpu
);
5052 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5054 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5057 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5058 trace_kvm_msr_read_ex(ecx
);
5059 kvm_inject_gp(vcpu
, 0);
5063 trace_kvm_msr_read(ecx
, data
);
5065 /* FIXME: handling of bits 32:63 of rax, rdx */
5066 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5067 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5068 skip_emulated_instruction(vcpu
);
5072 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5074 struct msr_data msr
;
5075 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5076 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5077 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5081 msr
.host_initiated
= false;
5082 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5083 trace_kvm_msr_write_ex(ecx
, data
);
5084 kvm_inject_gp(vcpu
, 0);
5088 trace_kvm_msr_write(ecx
, data
);
5089 skip_emulated_instruction(vcpu
);
5093 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5095 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5099 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5101 u32 cpu_based_vm_exec_control
;
5103 /* clear pending irq */
5104 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5105 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5106 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5108 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5110 ++vcpu
->stat
.irq_window_exits
;
5113 * If the user space waits to inject interrupts, exit as soon as
5116 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5117 vcpu
->run
->request_interrupt_window
&&
5118 !kvm_cpu_has_interrupt(vcpu
)) {
5119 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5125 static int handle_halt(struct kvm_vcpu
*vcpu
)
5127 skip_emulated_instruction(vcpu
);
5128 return kvm_emulate_halt(vcpu
);
5131 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5133 skip_emulated_instruction(vcpu
);
5134 kvm_emulate_hypercall(vcpu
);
5138 static int handle_invd(struct kvm_vcpu
*vcpu
)
5140 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5143 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5145 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5147 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5148 skip_emulated_instruction(vcpu
);
5152 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5156 err
= kvm_rdpmc(vcpu
);
5157 kvm_complete_insn_gp(vcpu
, err
);
5162 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5164 skip_emulated_instruction(vcpu
);
5165 kvm_emulate_wbinvd(vcpu
);
5169 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5171 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5172 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5174 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5175 skip_emulated_instruction(vcpu
);
5179 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5181 if (likely(fasteoi
)) {
5182 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5183 int access_type
, offset
;
5185 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5186 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5188 * Sane guest uses MOV to write EOI, with written value
5189 * not cared. So make a short-circuit here by avoiding
5190 * heavy instruction emulation.
5192 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5193 (offset
== APIC_EOI
)) {
5194 kvm_lapic_set_eoi(vcpu
);
5195 skip_emulated_instruction(vcpu
);
5199 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5202 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5204 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5205 int vector
= exit_qualification
& 0xff;
5207 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5208 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5212 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5214 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5215 u32 offset
= exit_qualification
& 0xfff;
5217 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5218 kvm_apic_write_nodecode(vcpu
, offset
);
5222 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5224 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5225 unsigned long exit_qualification
;
5226 bool has_error_code
= false;
5229 int reason
, type
, idt_v
, idt_index
;
5231 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5232 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5233 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5235 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5237 reason
= (u32
)exit_qualification
>> 30;
5238 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5240 case INTR_TYPE_NMI_INTR
:
5241 vcpu
->arch
.nmi_injected
= false;
5242 vmx_set_nmi_mask(vcpu
, true);
5244 case INTR_TYPE_EXT_INTR
:
5245 case INTR_TYPE_SOFT_INTR
:
5246 kvm_clear_interrupt_queue(vcpu
);
5248 case INTR_TYPE_HARD_EXCEPTION
:
5249 if (vmx
->idt_vectoring_info
&
5250 VECTORING_INFO_DELIVER_CODE_MASK
) {
5251 has_error_code
= true;
5253 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5256 case INTR_TYPE_SOFT_EXCEPTION
:
5257 kvm_clear_exception_queue(vcpu
);
5263 tss_selector
= exit_qualification
;
5265 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5266 type
!= INTR_TYPE_EXT_INTR
&&
5267 type
!= INTR_TYPE_NMI_INTR
))
5268 skip_emulated_instruction(vcpu
);
5270 if (kvm_task_switch(vcpu
, tss_selector
,
5271 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5272 has_error_code
, error_code
) == EMULATE_FAIL
) {
5273 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5274 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5275 vcpu
->run
->internal
.ndata
= 0;
5279 /* clear all local breakpoint enable flags */
5280 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
5283 * TODO: What about debug traps on tss switch?
5284 * Are we supposed to inject them and update dr6?
5290 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5292 unsigned long exit_qualification
;
5297 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5299 gla_validity
= (exit_qualification
>> 7) & 0x3;
5300 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5301 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5302 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5303 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5304 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5305 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5306 (long unsigned int)exit_qualification
);
5307 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5308 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5312 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5313 trace_kvm_page_fault(gpa
, exit_qualification
);
5315 /* It is a write fault? */
5316 error_code
= exit_qualification
& (1U << 1);
5317 /* ept page table is present? */
5318 error_code
|= (exit_qualification
>> 3) & 0x1;
5320 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5323 static u64
ept_rsvd_mask(u64 spte
, int level
)
5328 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5329 mask
|= (1ULL << i
);
5332 /* bits 7:3 reserved */
5334 else if (level
== 2) {
5335 if (spte
& (1ULL << 7))
5336 /* 2MB ref, bits 20:12 reserved */
5339 /* bits 6:3 reserved */
5346 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5349 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5351 /* 010b (write-only) */
5352 WARN_ON((spte
& 0x7) == 0x2);
5354 /* 110b (write/execute) */
5355 WARN_ON((spte
& 0x7) == 0x6);
5357 /* 100b (execute-only) and value not supported by logical processor */
5358 if (!cpu_has_vmx_ept_execute_only())
5359 WARN_ON((spte
& 0x7) == 0x4);
5363 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5365 if (rsvd_bits
!= 0) {
5366 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5367 __func__
, rsvd_bits
);
5371 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
5372 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5374 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5375 ept_mem_type
== 7) {
5376 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5377 __func__
, ept_mem_type
);
5384 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5387 int nr_sptes
, i
, ret
;
5390 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5392 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5393 if (likely(ret
== 1))
5394 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5399 /* It is the real ept misconfig */
5400 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5401 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5403 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5405 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5406 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5408 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5409 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5414 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5416 u32 cpu_based_vm_exec_control
;
5418 /* clear pending NMI */
5419 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5420 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5421 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5422 ++vcpu
->stat
.nmi_window_exits
;
5423 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5428 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5430 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5431 enum emulation_result err
= EMULATE_DONE
;
5434 bool intr_window_requested
;
5435 unsigned count
= 130;
5437 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5438 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5440 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5441 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5442 return handle_interrupt_window(&vmx
->vcpu
);
5444 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5447 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5449 if (err
== EMULATE_DO_MMIO
) {
5454 if (err
!= EMULATE_DONE
) {
5455 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5456 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5457 vcpu
->run
->internal
.ndata
= 0;
5461 if (vcpu
->arch
.halt_request
) {
5462 vcpu
->arch
.halt_request
= 0;
5463 ret
= kvm_emulate_halt(vcpu
);
5467 if (signal_pending(current
))
5473 vmx
->emulation_required
= emulation_required(vcpu
);
5479 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5480 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5482 static int handle_pause(struct kvm_vcpu
*vcpu
)
5484 skip_emulated_instruction(vcpu
);
5485 kvm_vcpu_on_spin(vcpu
);
5490 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
5492 kvm_queue_exception(vcpu
, UD_VECTOR
);
5497 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5498 * We could reuse a single VMCS for all the L2 guests, but we also want the
5499 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5500 * allows keeping them loaded on the processor, and in the future will allow
5501 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5502 * every entry if they never change.
5503 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5504 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5506 * The following functions allocate and free a vmcs02 in this pool.
5509 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5510 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5512 struct vmcs02_list
*item
;
5513 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5514 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5515 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5516 return &item
->vmcs02
;
5519 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5520 /* Recycle the least recently used VMCS. */
5521 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5522 struct vmcs02_list
, list
);
5523 item
->vmptr
= vmx
->nested
.current_vmptr
;
5524 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5525 return &item
->vmcs02
;
5528 /* Create a new VMCS */
5529 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5532 item
->vmcs02
.vmcs
= alloc_vmcs();
5533 if (!item
->vmcs02
.vmcs
) {
5537 loaded_vmcs_init(&item
->vmcs02
);
5538 item
->vmptr
= vmx
->nested
.current_vmptr
;
5539 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5540 vmx
->nested
.vmcs02_num
++;
5541 return &item
->vmcs02
;
5544 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5545 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5547 struct vmcs02_list
*item
;
5548 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5549 if (item
->vmptr
== vmptr
) {
5550 free_loaded_vmcs(&item
->vmcs02
);
5551 list_del(&item
->list
);
5553 vmx
->nested
.vmcs02_num
--;
5559 * Free all VMCSs saved for this vcpu, except the one pointed by
5560 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5561 * currently used, if running L2), and vmcs01 when running L2.
5563 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5565 struct vmcs02_list
*item
, *n
;
5566 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5567 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5568 free_loaded_vmcs(&item
->vmcs02
);
5569 list_del(&item
->list
);
5572 vmx
->nested
.vmcs02_num
= 0;
5574 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5575 free_loaded_vmcs(&vmx
->vmcs01
);
5578 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5579 u32 vm_instruction_error
);
5582 * Emulate the VMXON instruction.
5583 * Currently, we just remember that VMX is active, and do not save or even
5584 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5585 * do not currently need to store anything in that guest-allocated memory
5586 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5587 * argument is different from the VMXON pointer (which the spec says they do).
5589 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5591 struct kvm_segment cs
;
5592 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5593 struct vmcs
*shadow_vmcs
;
5595 /* The Intel VMX Instruction Reference lists a bunch of bits that
5596 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5597 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5598 * Otherwise, we should fail with #UD. We test these now:
5600 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5601 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5602 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5603 kvm_queue_exception(vcpu
, UD_VECTOR
);
5607 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5608 if (is_long_mode(vcpu
) && !cs
.l
) {
5609 kvm_queue_exception(vcpu
, UD_VECTOR
);
5613 if (vmx_get_cpl(vcpu
)) {
5614 kvm_inject_gp(vcpu
, 0);
5617 if (vmx
->nested
.vmxon
) {
5618 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
5619 skip_emulated_instruction(vcpu
);
5622 if (enable_shadow_vmcs
) {
5623 shadow_vmcs
= alloc_vmcs();
5626 /* mark vmcs as shadow */
5627 shadow_vmcs
->revision_id
|= (1u << 31);
5628 /* init shadow vmcs */
5629 vmcs_clear(shadow_vmcs
);
5630 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
5633 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5634 vmx
->nested
.vmcs02_num
= 0;
5636 vmx
->nested
.vmxon
= true;
5638 skip_emulated_instruction(vcpu
);
5643 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5644 * for running VMX instructions (except VMXON, whose prerequisites are
5645 * slightly different). It also specifies what exception to inject otherwise.
5647 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5649 struct kvm_segment cs
;
5650 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5652 if (!vmx
->nested
.vmxon
) {
5653 kvm_queue_exception(vcpu
, UD_VECTOR
);
5657 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5658 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5659 (is_long_mode(vcpu
) && !cs
.l
)) {
5660 kvm_queue_exception(vcpu
, UD_VECTOR
);
5664 if (vmx_get_cpl(vcpu
)) {
5665 kvm_inject_gp(vcpu
, 0);
5672 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
5675 if (enable_shadow_vmcs
) {
5676 if (vmx
->nested
.current_vmcs12
!= NULL
) {
5677 /* copy to memory all shadowed fields in case
5678 they were modified */
5679 copy_shadow_to_vmcs12(vmx
);
5680 vmx
->nested
.sync_shadow_vmcs
= false;
5681 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
5682 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5683 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
5684 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
5687 kunmap(vmx
->nested
.current_vmcs12_page
);
5688 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5692 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5693 * just stops using VMX.
5695 static void free_nested(struct vcpu_vmx
*vmx
)
5697 if (!vmx
->nested
.vmxon
)
5699 vmx
->nested
.vmxon
= false;
5700 if (vmx
->nested
.current_vmptr
!= -1ull) {
5701 nested_release_vmcs12(vmx
);
5702 vmx
->nested
.current_vmptr
= -1ull;
5703 vmx
->nested
.current_vmcs12
= NULL
;
5705 if (enable_shadow_vmcs
)
5706 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
5707 /* Unpin physical memory we referred to in current vmcs02 */
5708 if (vmx
->nested
.apic_access_page
) {
5709 nested_release_page(vmx
->nested
.apic_access_page
);
5710 vmx
->nested
.apic_access_page
= 0;
5713 nested_free_all_saved_vmcss(vmx
);
5716 /* Emulate the VMXOFF instruction */
5717 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5719 if (!nested_vmx_check_permission(vcpu
))
5721 free_nested(to_vmx(vcpu
));
5722 skip_emulated_instruction(vcpu
);
5727 * Decode the memory-address operand of a vmx instruction, as recorded on an
5728 * exit caused by such an instruction (run by a guest hypervisor).
5729 * On success, returns 0. When the operand is invalid, returns 1 and throws
5732 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5733 unsigned long exit_qualification
,
5734 u32 vmx_instruction_info
, gva_t
*ret
)
5737 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5738 * Execution", on an exit, vmx_instruction_info holds most of the
5739 * addressing components of the operand. Only the displacement part
5740 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5741 * For how an actual address is calculated from all these components,
5742 * refer to Vol. 1, "Operand Addressing".
5744 int scaling
= vmx_instruction_info
& 3;
5745 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5746 bool is_reg
= vmx_instruction_info
& (1u << 10);
5747 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5748 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5749 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5750 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5751 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5754 kvm_queue_exception(vcpu
, UD_VECTOR
);
5758 /* Addr = segment_base + offset */
5759 /* offset = base + [index * scale] + displacement */
5760 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5762 *ret
+= kvm_register_read(vcpu
, base_reg
);
5764 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5765 *ret
+= exit_qualification
; /* holds the displacement */
5767 if (addr_size
== 1) /* 32 bit */
5771 * TODO: throw #GP (and return 1) in various cases that the VM*
5772 * instructions require it - e.g., offset beyond segment limit,
5773 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5774 * address, and so on. Currently these are not checked.
5780 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5781 * set the success or error code of an emulated VMX instruction, as specified
5782 * by Vol 2B, VMX Instruction Reference, "Conventions".
5784 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5786 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5787 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5788 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5791 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5793 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5794 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5795 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5799 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5800 u32 vm_instruction_error
)
5802 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5804 * failValid writes the error number to the current VMCS, which
5805 * can't be done there isn't a current VMCS.
5807 nested_vmx_failInvalid(vcpu
);
5810 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5811 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5812 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5814 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5816 * We don't need to force a shadow sync because
5817 * VM_INSTRUCTION_ERROR is not shadowed
5821 /* Emulate the VMCLEAR instruction */
5822 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5824 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5827 struct vmcs12
*vmcs12
;
5829 struct x86_exception e
;
5831 if (!nested_vmx_check_permission(vcpu
))
5834 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5835 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5838 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5839 sizeof(vmptr
), &e
)) {
5840 kvm_inject_page_fault(vcpu
, &e
);
5844 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5845 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5846 skip_emulated_instruction(vcpu
);
5850 if (vmptr
== vmx
->nested
.current_vmptr
) {
5851 nested_release_vmcs12(vmx
);
5852 vmx
->nested
.current_vmptr
= -1ull;
5853 vmx
->nested
.current_vmcs12
= NULL
;
5856 page
= nested_get_page(vcpu
, vmptr
);
5859 * For accurate processor emulation, VMCLEAR beyond available
5860 * physical memory should do nothing at all. However, it is
5861 * possible that a nested vmx bug, not a guest hypervisor bug,
5862 * resulted in this case, so let's shut down before doing any
5865 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5868 vmcs12
= kmap(page
);
5869 vmcs12
->launch_state
= 0;
5871 nested_release_page(page
);
5873 nested_free_vmcs02(vmx
, vmptr
);
5875 skip_emulated_instruction(vcpu
);
5876 nested_vmx_succeed(vcpu
);
5880 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
5882 /* Emulate the VMLAUNCH instruction */
5883 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
5885 return nested_vmx_run(vcpu
, true);
5888 /* Emulate the VMRESUME instruction */
5889 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
5892 return nested_vmx_run(vcpu
, false);
5895 enum vmcs_field_type
{
5896 VMCS_FIELD_TYPE_U16
= 0,
5897 VMCS_FIELD_TYPE_U64
= 1,
5898 VMCS_FIELD_TYPE_U32
= 2,
5899 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
5902 static inline int vmcs_field_type(unsigned long field
)
5904 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
5905 return VMCS_FIELD_TYPE_U32
;
5906 return (field
>> 13) & 0x3 ;
5909 static inline int vmcs_field_readonly(unsigned long field
)
5911 return (((field
>> 10) & 0x3) == 1);
5915 * Read a vmcs12 field. Since these can have varying lengths and we return
5916 * one type, we chose the biggest type (u64) and zero-extend the return value
5917 * to that size. Note that the caller, handle_vmread, might need to use only
5918 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5919 * 64-bit fields are to be returned).
5921 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
5922 unsigned long field
, u64
*ret
)
5924 short offset
= vmcs_field_to_offset(field
);
5930 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
5932 switch (vmcs_field_type(field
)) {
5933 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5934 *ret
= *((natural_width
*)p
);
5936 case VMCS_FIELD_TYPE_U16
:
5939 case VMCS_FIELD_TYPE_U32
:
5942 case VMCS_FIELD_TYPE_U64
:
5946 return 0; /* can never happen. */
5951 static inline bool vmcs12_write_any(struct kvm_vcpu
*vcpu
,
5952 unsigned long field
, u64 field_value
){
5953 short offset
= vmcs_field_to_offset(field
);
5954 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
5958 switch (vmcs_field_type(field
)) {
5959 case VMCS_FIELD_TYPE_U16
:
5960 *(u16
*)p
= field_value
;
5962 case VMCS_FIELD_TYPE_U32
:
5963 *(u32
*)p
= field_value
;
5965 case VMCS_FIELD_TYPE_U64
:
5966 *(u64
*)p
= field_value
;
5968 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5969 *(natural_width
*)p
= field_value
;
5972 return false; /* can never happen. */
5977 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
5980 unsigned long field
;
5982 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
5983 unsigned long *fields
= (unsigned long *)shadow_read_write_fields
;
5984 int num_fields
= max_shadow_read_write_fields
;
5986 vmcs_load(shadow_vmcs
);
5988 for (i
= 0; i
< num_fields
; i
++) {
5990 switch (vmcs_field_type(field
)) {
5991 case VMCS_FIELD_TYPE_U16
:
5992 field_value
= vmcs_read16(field
);
5994 case VMCS_FIELD_TYPE_U32
:
5995 field_value
= vmcs_read32(field
);
5997 case VMCS_FIELD_TYPE_U64
:
5998 field_value
= vmcs_read64(field
);
6000 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6001 field_value
= vmcs_readl(field
);
6004 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6007 vmcs_clear(shadow_vmcs
);
6008 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6011 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6013 unsigned long *fields
[] = {
6014 (unsigned long *)shadow_read_write_fields
,
6015 (unsigned long *)shadow_read_only_fields
6017 int num_lists
= ARRAY_SIZE(fields
);
6018 int max_fields
[] = {
6019 max_shadow_read_write_fields
,
6020 max_shadow_read_only_fields
6023 unsigned long field
;
6024 u64 field_value
= 0;
6025 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6027 vmcs_load(shadow_vmcs
);
6029 for (q
= 0; q
< num_lists
; q
++) {
6030 for (i
= 0; i
< max_fields
[q
]; i
++) {
6031 field
= fields
[q
][i
];
6032 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6034 switch (vmcs_field_type(field
)) {
6035 case VMCS_FIELD_TYPE_U16
:
6036 vmcs_write16(field
, (u16
)field_value
);
6038 case VMCS_FIELD_TYPE_U32
:
6039 vmcs_write32(field
, (u32
)field_value
);
6041 case VMCS_FIELD_TYPE_U64
:
6042 vmcs_write64(field
, (u64
)field_value
);
6044 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6045 vmcs_writel(field
, (long)field_value
);
6051 vmcs_clear(shadow_vmcs
);
6052 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6056 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6057 * used before) all generate the same failure when it is missing.
6059 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6061 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6062 if (vmx
->nested
.current_vmptr
== -1ull) {
6063 nested_vmx_failInvalid(vcpu
);
6064 skip_emulated_instruction(vcpu
);
6070 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6072 unsigned long field
;
6074 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6075 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6078 if (!nested_vmx_check_permission(vcpu
) ||
6079 !nested_vmx_check_vmcs12(vcpu
))
6082 /* Decode instruction info and find the field to read */
6083 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6084 /* Read the field, zero-extended to a u64 field_value */
6085 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
6086 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6087 skip_emulated_instruction(vcpu
);
6091 * Now copy part of this value to register or memory, as requested.
6092 * Note that the number of bits actually copied is 32 or 64 depending
6093 * on the guest's mode (32 or 64 bit), not on the given field's length.
6095 if (vmx_instruction_info
& (1u << 10)) {
6096 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6099 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6100 vmx_instruction_info
, &gva
))
6102 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6103 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6104 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6107 nested_vmx_succeed(vcpu
);
6108 skip_emulated_instruction(vcpu
);
6113 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6115 unsigned long field
;
6117 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6118 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6119 /* The value to write might be 32 or 64 bits, depending on L1's long
6120 * mode, and eventually we need to write that into a field of several
6121 * possible lengths. The code below first zero-extends the value to 64
6122 * bit (field_value), and then copies only the approriate number of
6123 * bits into the vmcs12 field.
6125 u64 field_value
= 0;
6126 struct x86_exception e
;
6128 if (!nested_vmx_check_permission(vcpu
) ||
6129 !nested_vmx_check_vmcs12(vcpu
))
6132 if (vmx_instruction_info
& (1u << 10))
6133 field_value
= kvm_register_read(vcpu
,
6134 (((vmx_instruction_info
) >> 3) & 0xf));
6136 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6137 vmx_instruction_info
, &gva
))
6139 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6140 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
6141 kvm_inject_page_fault(vcpu
, &e
);
6147 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6148 if (vmcs_field_readonly(field
)) {
6149 nested_vmx_failValid(vcpu
,
6150 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6151 skip_emulated_instruction(vcpu
);
6155 if (!vmcs12_write_any(vcpu
, field
, field_value
)) {
6156 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6157 skip_emulated_instruction(vcpu
);
6161 nested_vmx_succeed(vcpu
);
6162 skip_emulated_instruction(vcpu
);
6166 /* Emulate the VMPTRLD instruction */
6167 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6169 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6172 struct x86_exception e
;
6175 if (!nested_vmx_check_permission(vcpu
))
6178 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6179 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6182 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6183 sizeof(vmptr
), &e
)) {
6184 kvm_inject_page_fault(vcpu
, &e
);
6188 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
6189 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
6190 skip_emulated_instruction(vcpu
);
6194 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6195 struct vmcs12
*new_vmcs12
;
6197 page
= nested_get_page(vcpu
, vmptr
);
6199 nested_vmx_failInvalid(vcpu
);
6200 skip_emulated_instruction(vcpu
);
6203 new_vmcs12
= kmap(page
);
6204 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6206 nested_release_page_clean(page
);
6207 nested_vmx_failValid(vcpu
,
6208 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6209 skip_emulated_instruction(vcpu
);
6212 if (vmx
->nested
.current_vmptr
!= -1ull)
6213 nested_release_vmcs12(vmx
);
6215 vmx
->nested
.current_vmptr
= vmptr
;
6216 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6217 vmx
->nested
.current_vmcs12_page
= page
;
6218 if (enable_shadow_vmcs
) {
6219 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6220 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6221 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6222 vmcs_write64(VMCS_LINK_POINTER
,
6223 __pa(vmx
->nested
.current_shadow_vmcs
));
6224 vmx
->nested
.sync_shadow_vmcs
= true;
6228 nested_vmx_succeed(vcpu
);
6229 skip_emulated_instruction(vcpu
);
6233 /* Emulate the VMPTRST instruction */
6234 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6236 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6237 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6239 struct x86_exception e
;
6241 if (!nested_vmx_check_permission(vcpu
))
6244 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6245 vmx_instruction_info
, &vmcs_gva
))
6247 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6248 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6249 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6251 kvm_inject_page_fault(vcpu
, &e
);
6254 nested_vmx_succeed(vcpu
);
6255 skip_emulated_instruction(vcpu
);
6259 static int handle_invept(struct kvm_vcpu
*vcpu
)
6261 kvm_queue_exception(vcpu
, UD_VECTOR
);
6265 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
6267 kvm_queue_exception(vcpu
, UD_VECTOR
);
6272 * The exit handlers return 1 if the exit was handled fully and guest execution
6273 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6274 * to be done to userspace and return 0.
6276 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6277 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6278 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6279 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6280 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6281 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6282 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6283 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6284 [EXIT_REASON_CPUID
] = handle_cpuid
,
6285 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6286 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6287 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6288 [EXIT_REASON_HLT
] = handle_halt
,
6289 [EXIT_REASON_INVD
] = handle_invd
,
6290 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6291 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6292 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6293 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6294 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6295 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6296 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6297 [EXIT_REASON_VMREAD
] = handle_vmread
,
6298 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6299 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6300 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6301 [EXIT_REASON_VMON
] = handle_vmon
,
6302 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6303 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6304 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6305 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6306 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6307 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6308 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6309 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6310 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6311 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6312 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6313 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
6314 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
6315 [EXIT_REASON_INVEPT
] = handle_invept
,
6316 [EXIT_REASON_INVVPID
] = handle_invvpid
,
6319 static const int kvm_vmx_max_exit_handlers
=
6320 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6322 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6323 struct vmcs12
*vmcs12
)
6325 unsigned long exit_qualification
;
6326 gpa_t bitmap
, last_bitmap
;
6331 if (nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
))
6334 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6337 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6339 port
= exit_qualification
>> 16;
6340 size
= (exit_qualification
& 7) + 1;
6342 last_bitmap
= (gpa_t
)-1;
6347 bitmap
= vmcs12
->io_bitmap_a
;
6348 else if (port
< 0x10000)
6349 bitmap
= vmcs12
->io_bitmap_b
;
6352 bitmap
+= (port
& 0x7fff) / 8;
6354 if (last_bitmap
!= bitmap
)
6355 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6357 if (b
& (1 << (port
& 7)))
6362 last_bitmap
= bitmap
;
6369 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6370 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6371 * disinterest in the current event (read or write a specific MSR) by using an
6372 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6374 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
6375 struct vmcs12
*vmcs12
, u32 exit_reason
)
6377 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6380 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
6384 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6385 * for the four combinations of read/write and low/high MSR numbers.
6386 * First we need to figure out which of the four to use:
6388 bitmap
= vmcs12
->msr_bitmap
;
6389 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6391 if (msr_index
>= 0xc0000000) {
6392 msr_index
-= 0xc0000000;
6396 /* Then read the msr_index'th bit from this bitmap: */
6397 if (msr_index
< 1024*8) {
6399 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6401 return 1 & (b
>> (msr_index
& 7));
6403 return 1; /* let L1 handle the wrong parameter */
6407 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6408 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6409 * intercept (via guest_host_mask etc.) the current event.
6411 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6412 struct vmcs12
*vmcs12
)
6414 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6415 int cr
= exit_qualification
& 15;
6416 int reg
= (exit_qualification
>> 8) & 15;
6417 unsigned long val
= kvm_register_read(vcpu
, reg
);
6419 switch ((exit_qualification
>> 4) & 3) {
6420 case 0: /* mov to cr */
6423 if (vmcs12
->cr0_guest_host_mask
&
6424 (val
^ vmcs12
->cr0_read_shadow
))
6428 if ((vmcs12
->cr3_target_count
>= 1 &&
6429 vmcs12
->cr3_target_value0
== val
) ||
6430 (vmcs12
->cr3_target_count
>= 2 &&
6431 vmcs12
->cr3_target_value1
== val
) ||
6432 (vmcs12
->cr3_target_count
>= 3 &&
6433 vmcs12
->cr3_target_value2
== val
) ||
6434 (vmcs12
->cr3_target_count
>= 4 &&
6435 vmcs12
->cr3_target_value3
== val
))
6437 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6441 if (vmcs12
->cr4_guest_host_mask
&
6442 (vmcs12
->cr4_read_shadow
^ val
))
6446 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6452 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6453 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6456 case 1: /* mov from cr */
6459 if (vmcs12
->cpu_based_vm_exec_control
&
6460 CPU_BASED_CR3_STORE_EXITING
)
6464 if (vmcs12
->cpu_based_vm_exec_control
&
6465 CPU_BASED_CR8_STORE_EXITING
)
6472 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6473 * cr0. Other attempted changes are ignored, with no exit.
6475 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6476 (val
^ vmcs12
->cr0_read_shadow
))
6478 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6479 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6488 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6489 * should handle it ourselves in L0 (and then continue L2). Only call this
6490 * when in is_guest_mode (L2).
6492 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6494 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6495 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6496 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6497 u32 exit_reason
= vmx
->exit_reason
;
6499 if (vmx
->nested
.nested_run_pending
)
6502 if (unlikely(vmx
->fail
)) {
6503 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6504 vmcs_read32(VM_INSTRUCTION_ERROR
));
6508 switch (exit_reason
) {
6509 case EXIT_REASON_EXCEPTION_NMI
:
6510 if (is_nmi(intr_info
))
6512 else if (is_page_fault(intr_info
))
6514 return vmcs12
->exception_bitmap
&
6515 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6516 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6518 case EXIT_REASON_TRIPLE_FAULT
:
6520 case EXIT_REASON_PENDING_INTERRUPT
:
6521 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
6522 case EXIT_REASON_NMI_WINDOW
:
6523 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
6524 case EXIT_REASON_TASK_SWITCH
:
6526 case EXIT_REASON_CPUID
:
6528 case EXIT_REASON_HLT
:
6529 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6530 case EXIT_REASON_INVD
:
6532 case EXIT_REASON_INVLPG
:
6533 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
6534 case EXIT_REASON_RDPMC
:
6535 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
6536 case EXIT_REASON_RDTSC
:
6537 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
6538 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
6539 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
6540 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
6541 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
6542 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
6543 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
6545 * VMX instructions trap unconditionally. This allows L1 to
6546 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6549 case EXIT_REASON_CR_ACCESS
:
6550 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
6551 case EXIT_REASON_DR_ACCESS
:
6552 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
6553 case EXIT_REASON_IO_INSTRUCTION
:
6554 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
6555 case EXIT_REASON_MSR_READ
:
6556 case EXIT_REASON_MSR_WRITE
:
6557 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
6558 case EXIT_REASON_INVALID_STATE
:
6560 case EXIT_REASON_MWAIT_INSTRUCTION
:
6561 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
6562 case EXIT_REASON_MONITOR_INSTRUCTION
:
6563 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
6564 case EXIT_REASON_PAUSE_INSTRUCTION
:
6565 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
6566 nested_cpu_has2(vmcs12
,
6567 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
6568 case EXIT_REASON_MCE_DURING_VMENTRY
:
6570 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
6572 case EXIT_REASON_APIC_ACCESS
:
6573 return nested_cpu_has2(vmcs12
,
6574 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
6575 case EXIT_REASON_EPT_VIOLATION
:
6576 case EXIT_REASON_EPT_MISCONFIG
:
6578 case EXIT_REASON_PREEMPTION_TIMER
:
6579 return vmcs12
->pin_based_vm_exec_control
&
6580 PIN_BASED_VMX_PREEMPTION_TIMER
;
6581 case EXIT_REASON_WBINVD
:
6582 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
6583 case EXIT_REASON_XSETBV
:
6590 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
6592 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
6593 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
6597 * The guest has exited. See if we can fix it or if we need userspace
6600 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
6602 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6603 u32 exit_reason
= vmx
->exit_reason
;
6604 u32 vectoring_info
= vmx
->idt_vectoring_info
;
6606 /* If guest state is invalid, start emulating */
6607 if (vmx
->emulation_required
)
6608 return handle_invalid_guest_state(vcpu
);
6611 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6612 * we did not inject a still-pending event to L1 now because of
6613 * nested_run_pending, we need to re-enable this bit.
6615 if (vmx
->nested
.nested_run_pending
)
6616 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6618 if (!is_guest_mode(vcpu
) && (exit_reason
== EXIT_REASON_VMLAUNCH
||
6619 exit_reason
== EXIT_REASON_VMRESUME
))
6620 vmx
->nested
.nested_run_pending
= 1;
6622 vmx
->nested
.nested_run_pending
= 0;
6624 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
6625 nested_vmx_vmexit(vcpu
);
6629 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
6630 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6631 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6636 if (unlikely(vmx
->fail
)) {
6637 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6638 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6639 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6645 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6646 * delivery event since it indicates guest is accessing MMIO.
6647 * The vm-exit can be triggered again after return to guest that
6648 * will cause infinite loop.
6650 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6651 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6652 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6653 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
6654 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6655 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
6656 vcpu
->run
->internal
.ndata
= 2;
6657 vcpu
->run
->internal
.data
[0] = vectoring_info
;
6658 vcpu
->run
->internal
.data
[1] = exit_reason
;
6662 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
6663 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
6664 get_vmcs12(vcpu
), vcpu
)))) {
6665 if (vmx_interrupt_allowed(vcpu
)) {
6666 vmx
->soft_vnmi_blocked
= 0;
6667 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
6668 vcpu
->arch
.nmi_pending
) {
6670 * This CPU don't support us in finding the end of an
6671 * NMI-blocked window if the guest runs with IRQs
6672 * disabled. So we pull the trigger after 1 s of
6673 * futile waiting, but inform the user about this.
6675 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6676 "state on VCPU %d after 1 s timeout\n",
6677 __func__
, vcpu
->vcpu_id
);
6678 vmx
->soft_vnmi_blocked
= 0;
6682 if (exit_reason
< kvm_vmx_max_exit_handlers
6683 && kvm_vmx_exit_handlers
[exit_reason
])
6684 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
6686 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
6687 kvm_queue_exception(vcpu
, UD_VECTOR
);
6692 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6694 if (irr
== -1 || tpr
< irr
) {
6695 vmcs_write32(TPR_THRESHOLD
, 0);
6699 vmcs_write32(TPR_THRESHOLD
, irr
);
6702 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
6704 u32 sec_exec_control
;
6706 /* Postpone execution until vmcs01 is the current VMCS. */
6707 if (is_guest_mode(vcpu
)) {
6708 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
6713 * There is not point to enable virtualize x2apic without enable
6716 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6717 !vmx_vm_has_apicv(vcpu
->kvm
))
6720 if (!vm_need_tpr_shadow(vcpu
->kvm
))
6723 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6726 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6727 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6729 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6730 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6732 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
6734 vmx_set_msr_bitmap(vcpu
);
6737 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
6742 if (!vmx_vm_has_apicv(kvm
))
6748 status
= vmcs_read16(GUEST_INTR_STATUS
);
6753 vmcs_write16(GUEST_INTR_STATUS
, status
);
6757 static void vmx_set_rvi(int vector
)
6762 status
= vmcs_read16(GUEST_INTR_STATUS
);
6763 old
= (u8
)status
& 0xff;
6764 if ((u8
)vector
!= old
) {
6766 status
|= (u8
)vector
;
6767 vmcs_write16(GUEST_INTR_STATUS
, status
);
6771 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
6776 vmx_set_rvi(max_irr
);
6779 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
6781 if (!vmx_vm_has_apicv(vcpu
->kvm
))
6784 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
6785 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
6786 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
6787 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
6790 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
6794 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
6795 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
6798 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6799 exit_intr_info
= vmx
->exit_intr_info
;
6801 /* Handle machine checks before interrupts are enabled */
6802 if (is_machine_check(exit_intr_info
))
6803 kvm_machine_check();
6805 /* We need to handle NMIs before interrupts are enabled */
6806 if (is_nmi(exit_intr_info
)) {
6807 kvm_before_handle_nmi(&vmx
->vcpu
);
6809 kvm_after_handle_nmi(&vmx
->vcpu
);
6813 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
6815 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6818 * If external interrupt exists, IF bit is set in rflags/eflags on the
6819 * interrupt stack frame, and interrupt will be enabled on a return
6820 * from interrupt handler.
6822 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
6823 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
6824 unsigned int vector
;
6825 unsigned long entry
;
6827 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6828 #ifdef CONFIG_X86_64
6832 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
6833 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
6834 entry
= gate_offset(*desc
);
6836 #ifdef CONFIG_X86_64
6837 "mov %%" _ASM_SP
", %[sp]\n\t"
6838 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
6843 "orl $0x200, (%%" _ASM_SP
")\n\t"
6844 __ASM_SIZE(push
) " $%c[cs]\n\t"
6845 "call *%[entry]\n\t"
6847 #ifdef CONFIG_X86_64
6852 [ss
]"i"(__KERNEL_DS
),
6853 [cs
]"i"(__KERNEL_CS
)
6859 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
6864 bool idtv_info_valid
;
6866 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6868 if (cpu_has_virtual_nmis()) {
6869 if (vmx
->nmi_known_unmasked
)
6872 * Can't use vmx->exit_intr_info since we're not sure what
6873 * the exit reason is.
6875 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6876 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
6877 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
6879 * SDM 3: 27.7.1.2 (September 2008)
6880 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6881 * a guest IRET fault.
6882 * SDM 3: 23.2.2 (September 2008)
6883 * Bit 12 is undefined in any of the following cases:
6884 * If the VM exit sets the valid bit in the IDT-vectoring
6885 * information field.
6886 * If the VM exit is due to a double fault.
6888 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
6889 vector
!= DF_VECTOR
&& !idtv_info_valid
)
6890 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
6891 GUEST_INTR_STATE_NMI
);
6893 vmx
->nmi_known_unmasked
=
6894 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
6895 & GUEST_INTR_STATE_NMI
);
6896 } else if (unlikely(vmx
->soft_vnmi_blocked
))
6897 vmx
->vnmi_blocked_time
+=
6898 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
6901 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
6902 u32 idt_vectoring_info
,
6903 int instr_len_field
,
6904 int error_code_field
)
6908 bool idtv_info_valid
;
6910 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6912 vcpu
->arch
.nmi_injected
= false;
6913 kvm_clear_exception_queue(vcpu
);
6914 kvm_clear_interrupt_queue(vcpu
);
6916 if (!idtv_info_valid
)
6919 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6921 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
6922 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
6925 case INTR_TYPE_NMI_INTR
:
6926 vcpu
->arch
.nmi_injected
= true;
6928 * SDM 3: 27.7.1.2 (September 2008)
6929 * Clear bit "block by NMI" before VM entry if a NMI
6932 vmx_set_nmi_mask(vcpu
, false);
6934 case INTR_TYPE_SOFT_EXCEPTION
:
6935 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
6937 case INTR_TYPE_HARD_EXCEPTION
:
6938 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
6939 u32 err
= vmcs_read32(error_code_field
);
6940 kvm_queue_exception_e(vcpu
, vector
, err
);
6942 kvm_queue_exception(vcpu
, vector
);
6944 case INTR_TYPE_SOFT_INTR
:
6945 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
6947 case INTR_TYPE_EXT_INTR
:
6948 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
6955 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
6957 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
6958 VM_EXIT_INSTRUCTION_LEN
,
6959 IDT_VECTORING_ERROR_CODE
);
6962 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
6964 __vmx_complete_interrupts(vcpu
,
6965 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
6966 VM_ENTRY_INSTRUCTION_LEN
,
6967 VM_ENTRY_EXCEPTION_ERROR_CODE
);
6969 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
6972 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
6975 struct perf_guest_switch_msr
*msrs
;
6977 msrs
= perf_guest_get_msrs(&nr_msrs
);
6982 for (i
= 0; i
< nr_msrs
; i
++)
6983 if (msrs
[i
].host
== msrs
[i
].guest
)
6984 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
6986 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
6990 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
6992 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6993 unsigned long debugctlmsr
, cr4
;
6995 /* Record the guest's net vcpu time for enforced NMI injections. */
6996 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
6997 vmx
->entry_time
= ktime_get();
6999 /* Don't enter VMX if guest state is invalid, let the exit handler
7000 start emulation until we arrive back to a valid state */
7001 if (vmx
->emulation_required
)
7004 if (vmx
->nested
.sync_shadow_vmcs
) {
7005 copy_vmcs12_to_shadow(vmx
);
7006 vmx
->nested
.sync_shadow_vmcs
= false;
7009 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7010 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7011 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7012 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7015 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
7016 vmcs_writel(HOST_CR4
, cr4
);
7017 vmx
->host_state
.vmcs_host_cr4
= cr4
;
7020 /* When single-stepping over STI and MOV SS, we must clear the
7021 * corresponding interruptibility bits in the guest state. Otherwise
7022 * vmentry fails as it then expects bit 14 (BS) in pending debug
7023 * exceptions being set, but that's not correct for the guest debugging
7025 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7026 vmx_set_interrupt_shadow(vcpu
, 0);
7028 atomic_switch_perf_msrs(vmx
);
7029 debugctlmsr
= get_debugctlmsr();
7031 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7033 /* Store host registers */
7034 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7035 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7036 "push %%" _ASM_CX
" \n\t"
7037 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7039 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7040 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7042 /* Reload cr2 if changed */
7043 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7044 "mov %%cr2, %%" _ASM_DX
" \n\t"
7045 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7047 "mov %%" _ASM_AX
", %%cr2 \n\t"
7049 /* Check if vmlaunch of vmresume is needed */
7050 "cmpl $0, %c[launched](%0) \n\t"
7051 /* Load guest registers. Don't clobber flags. */
7052 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7053 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7054 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7055 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7056 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7057 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7058 #ifdef CONFIG_X86_64
7059 "mov %c[r8](%0), %%r8 \n\t"
7060 "mov %c[r9](%0), %%r9 \n\t"
7061 "mov %c[r10](%0), %%r10 \n\t"
7062 "mov %c[r11](%0), %%r11 \n\t"
7063 "mov %c[r12](%0), %%r12 \n\t"
7064 "mov %c[r13](%0), %%r13 \n\t"
7065 "mov %c[r14](%0), %%r14 \n\t"
7066 "mov %c[r15](%0), %%r15 \n\t"
7068 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7070 /* Enter guest mode */
7072 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7074 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7076 /* Save guest registers, load host registers, keep flags */
7077 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7079 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7080 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7081 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7082 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7083 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7084 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7085 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7086 #ifdef CONFIG_X86_64
7087 "mov %%r8, %c[r8](%0) \n\t"
7088 "mov %%r9, %c[r9](%0) \n\t"
7089 "mov %%r10, %c[r10](%0) \n\t"
7090 "mov %%r11, %c[r11](%0) \n\t"
7091 "mov %%r12, %c[r12](%0) \n\t"
7092 "mov %%r13, %c[r13](%0) \n\t"
7093 "mov %%r14, %c[r14](%0) \n\t"
7094 "mov %%r15, %c[r15](%0) \n\t"
7096 "mov %%cr2, %%" _ASM_AX
" \n\t"
7097 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7099 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7100 "setbe %c[fail](%0) \n\t"
7101 ".pushsection .rodata \n\t"
7102 ".global vmx_return \n\t"
7103 "vmx_return: " _ASM_PTR
" 2b \n\t"
7105 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7106 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7107 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7108 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7109 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7110 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7111 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7112 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7113 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7114 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7115 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7116 #ifdef CONFIG_X86_64
7117 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7118 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7119 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7120 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7121 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7122 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7123 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7124 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7126 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7127 [wordsize
]"i"(sizeof(ulong
))
7129 #ifdef CONFIG_X86_64
7130 , "rax", "rbx", "rdi", "rsi"
7131 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7133 , "eax", "ebx", "edi", "esi"
7137 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7139 update_debugctlmsr(debugctlmsr
);
7141 #ifndef CONFIG_X86_64
7143 * The sysexit path does not restore ds/es, so we must set them to
7144 * a reasonable value ourselves.
7146 * We can't defer this to vmx_load_host_state() since that function
7147 * may be executed in interrupt context, which saves and restore segments
7148 * around it, nullifying its effect.
7150 loadsegment(ds
, __USER_DS
);
7151 loadsegment(es
, __USER_DS
);
7154 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7155 | (1 << VCPU_EXREG_RFLAGS
)
7156 | (1 << VCPU_EXREG_CPL
)
7157 | (1 << VCPU_EXREG_PDPTR
)
7158 | (1 << VCPU_EXREG_SEGMENTS
)
7159 | (1 << VCPU_EXREG_CR3
));
7160 vcpu
->arch
.regs_dirty
= 0;
7162 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7164 vmx
->loaded_vmcs
->launched
= 1;
7166 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7167 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7169 vmx_complete_atomic_exit(vmx
);
7170 vmx_recover_nmi_blocking(vmx
);
7171 vmx_complete_interrupts(vmx
);
7174 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7176 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7179 free_loaded_vmcs(vmx
->loaded_vmcs
);
7181 kfree(vmx
->guest_msrs
);
7182 kvm_vcpu_uninit(vcpu
);
7183 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7186 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7189 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7193 return ERR_PTR(-ENOMEM
);
7197 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7201 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7203 if (!vmx
->guest_msrs
) {
7207 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7208 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7209 if (!vmx
->loaded_vmcs
->vmcs
)
7212 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7213 loaded_vmcs_init(vmx
->loaded_vmcs
);
7218 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7219 vmx
->vcpu
.cpu
= cpu
;
7220 err
= vmx_vcpu_setup(vmx
);
7221 vmx_vcpu_put(&vmx
->vcpu
);
7225 if (vm_need_virtualize_apic_accesses(kvm
)) {
7226 err
= alloc_apic_access_page(kvm
);
7232 if (!kvm
->arch
.ept_identity_map_addr
)
7233 kvm
->arch
.ept_identity_map_addr
=
7234 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7236 if (alloc_identity_pagetable(kvm
) != 0)
7238 if (!init_rmode_identity_map(kvm
))
7242 vmx
->nested
.current_vmptr
= -1ull;
7243 vmx
->nested
.current_vmcs12
= NULL
;
7248 free_loaded_vmcs(vmx
->loaded_vmcs
);
7250 kfree(vmx
->guest_msrs
);
7252 kvm_vcpu_uninit(&vmx
->vcpu
);
7255 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7256 return ERR_PTR(err
);
7259 static void __init
vmx_check_processor_compat(void *rtn
)
7261 struct vmcs_config vmcs_conf
;
7264 if (setup_vmcs_config(&vmcs_conf
) < 0)
7266 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7267 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7268 smp_processor_id());
7273 static int get_ept_level(void)
7275 return VMX_EPT_DEFAULT_GAW
+ 1;
7278 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7282 /* For VT-d and EPT combination
7283 * 1. MMIO: always map as UC
7285 * a. VT-d without snooping control feature: can't guarantee the
7286 * result, try to trust guest.
7287 * b. VT-d with snooping control feature: snooping control feature of
7288 * VT-d engine can guarantee the cache correctness. Just set it
7289 * to WB to keep consistent with host. So the same as item 3.
7290 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7291 * consistent with host MTRR
7294 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
7295 else if (vcpu
->kvm
->arch
.iommu_domain
&&
7296 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
7297 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
7298 VMX_EPT_MT_EPTE_SHIFT
;
7300 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
7306 static int vmx_get_lpage_level(void)
7308 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
7309 return PT_DIRECTORY_LEVEL
;
7311 /* For shadow and EPT supported 1GB page */
7312 return PT_PDPE_LEVEL
;
7315 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
7317 struct kvm_cpuid_entry2
*best
;
7318 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7321 vmx
->rdtscp_enabled
= false;
7322 if (vmx_rdtscp_supported()) {
7323 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7324 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
7325 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
7326 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
7327 vmx
->rdtscp_enabled
= true;
7329 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7330 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7336 /* Exposing INVPCID only when PCID is exposed */
7337 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7338 if (vmx_invpcid_supported() &&
7339 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
7340 guest_cpuid_has_pcid(vcpu
)) {
7341 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7342 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
7343 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7346 if (cpu_has_secondary_exec_ctrls()) {
7347 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7348 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
7349 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7353 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
7357 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
7359 if (func
== 1 && nested
)
7360 entry
->ecx
|= bit(X86_FEATURE_VMX
);
7364 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7365 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7366 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7367 * guest in a way that will both be appropriate to L1's requests, and our
7368 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7369 * function also has additional necessary side-effects, like setting various
7370 * vcpu->arch fields.
7372 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7374 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7377 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
7378 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
7379 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
7380 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
7381 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
7382 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
7383 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
7384 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
7385 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
7386 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
7387 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
7388 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
7389 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
7390 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
7391 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
7392 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
7393 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
7394 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
7395 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
7396 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
7397 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
7398 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
7399 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
7400 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
7401 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
7402 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
7403 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
7404 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
7405 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
7406 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
7407 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
7408 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
7409 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
7410 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
7411 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
7412 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
7414 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
7415 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
7416 vmcs12
->vm_entry_intr_info_field
);
7417 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
7418 vmcs12
->vm_entry_exception_error_code
);
7419 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
7420 vmcs12
->vm_entry_instruction_len
);
7421 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
7422 vmcs12
->guest_interruptibility_info
);
7423 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
7424 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
7425 vmcs_writel(GUEST_RFLAGS
, vmcs12
->guest_rflags
);
7426 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
7427 vmcs12
->guest_pending_dbg_exceptions
);
7428 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
7429 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
7431 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7433 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
7434 (vmcs_config
.pin_based_exec_ctrl
|
7435 vmcs12
->pin_based_vm_exec_control
));
7437 if (vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
)
7438 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
,
7439 vmcs12
->vmx_preemption_timer_value
);
7442 * Whether page-faults are trapped is determined by a combination of
7443 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7444 * If enable_ept, L0 doesn't care about page faults and we should
7445 * set all of these to L1's desires. However, if !enable_ept, L0 does
7446 * care about (at least some) page faults, and because it is not easy
7447 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7448 * to exit on each and every L2 page fault. This is done by setting
7449 * MASK=MATCH=0 and (see below) EB.PF=1.
7450 * Note that below we don't need special code to set EB.PF beyond the
7451 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7452 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7453 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7455 * A problem with this approach (when !enable_ept) is that L1 may be
7456 * injected with more page faults than it asked for. This could have
7457 * caused problems, but in practice existing hypervisors don't care.
7458 * To fix this, we will need to emulate the PFEC checking (on the L1
7459 * page tables), using walk_addr(), when injecting PFs to L1.
7461 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
7462 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
7463 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
7464 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
7466 if (cpu_has_secondary_exec_ctrls()) {
7467 u32 exec_control
= vmx_secondary_exec_control(vmx
);
7468 if (!vmx
->rdtscp_enabled
)
7469 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7470 /* Take the following fields only from vmcs12 */
7471 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7472 if (nested_cpu_has(vmcs12
,
7473 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
7474 exec_control
|= vmcs12
->secondary_vm_exec_control
;
7476 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
7478 * Translate L1 physical address to host physical
7479 * address for vmcs02. Keep the page pinned, so this
7480 * physical address remains valid. We keep a reference
7481 * to it so we can release it later.
7483 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
7484 nested_release_page(vmx
->nested
.apic_access_page
);
7485 vmx
->nested
.apic_access_page
=
7486 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
7488 * If translation failed, no matter: This feature asks
7489 * to exit when accessing the given address, and if it
7490 * can never be accessed, this feature won't do
7493 if (!vmx
->nested
.apic_access_page
)
7495 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7497 vmcs_write64(APIC_ACCESS_ADDR
,
7498 page_to_phys(vmx
->nested
.apic_access_page
));
7501 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7506 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7507 * Some constant fields are set here by vmx_set_constant_host_state().
7508 * Other fields are different per CPU, and will be set later when
7509 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7511 vmx_set_constant_host_state(vmx
);
7514 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7515 * entry, but only if the current (host) sp changed from the value
7516 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7517 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7518 * here we just force the write to happen on entry.
7522 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
7523 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
7524 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
7525 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
7526 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
7528 * Merging of IO and MSR bitmaps not currently supported.
7529 * Rather, exit every time.
7531 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
7532 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
7533 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
7535 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
7537 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7538 * bitwise-or of what L1 wants to trap for L2, and what we want to
7539 * trap. Note that CR0.TS also needs updating - we do this later.
7541 update_exception_bitmap(vcpu
);
7542 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
7543 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7545 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7546 vmcs_write32(VM_EXIT_CONTROLS
,
7547 vmcs12
->vm_exit_controls
| vmcs_config
.vmexit_ctrl
);
7548 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs12
->vm_entry_controls
|
7549 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
7551 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)
7552 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
7553 else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
7554 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
7557 set_cr4_guest_host_mask(vmx
);
7559 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
7560 vmcs_write64(TSC_OFFSET
,
7561 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
7563 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7567 * Trivially support vpid by letting L2s share their parent
7568 * L1's vpid. TODO: move to a more elaborate solution, giving
7569 * each L2 its own vpid and exposing the vpid feature to L1.
7571 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
7572 vmx_flush_tlb(vcpu
);
7575 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
7576 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
7577 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
7578 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7580 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7581 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7582 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7585 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7586 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7587 * The CR0_READ_SHADOW is what L2 should have expected to read given
7588 * the specifications by L1; It's not enough to take
7589 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7590 * have more bits than L1 expected.
7592 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
7593 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
7595 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
7596 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
7598 /* shadow page tables on either EPT or shadow page tables */
7599 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
7600 kvm_mmu_reset_context(vcpu
);
7602 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
7603 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
7607 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7608 * for running an L2 nested guest.
7610 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
7612 struct vmcs12
*vmcs12
;
7613 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7615 struct loaded_vmcs
*vmcs02
;
7618 if (!nested_vmx_check_permission(vcpu
) ||
7619 !nested_vmx_check_vmcs12(vcpu
))
7622 skip_emulated_instruction(vcpu
);
7623 vmcs12
= get_vmcs12(vcpu
);
7625 if (enable_shadow_vmcs
)
7626 copy_shadow_to_vmcs12(vmx
);
7629 * The nested entry process starts with enforcing various prerequisites
7630 * on vmcs12 as required by the Intel SDM, and act appropriately when
7631 * they fail: As the SDM explains, some conditions should cause the
7632 * instruction to fail, while others will cause the instruction to seem
7633 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7634 * To speed up the normal (success) code path, we should avoid checking
7635 * for misconfigurations which will anyway be caught by the processor
7636 * when using the merged vmcs02.
7638 if (vmcs12
->launch_state
== launch
) {
7639 nested_vmx_failValid(vcpu
,
7640 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7641 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
7645 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
) {
7646 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7650 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
7651 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
7652 /*TODO: Also verify bits beyond physical address width are 0*/
7653 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7657 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
7658 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
7659 /*TODO: Also verify bits beyond physical address width are 0*/
7660 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7664 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
7665 vmcs12
->vm_exit_msr_load_count
> 0 ||
7666 vmcs12
->vm_exit_msr_store_count
> 0) {
7667 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7669 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7673 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
7674 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
7675 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
7676 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
7677 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
7678 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
7679 !vmx_control_verify(vmcs12
->vm_exit_controls
,
7680 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
7681 !vmx_control_verify(vmcs12
->vm_entry_controls
,
7682 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
7684 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7688 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
7689 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7690 nested_vmx_failValid(vcpu
,
7691 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
7695 if (((vmcs12
->guest_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
7696 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7697 nested_vmx_entry_failure(vcpu
, vmcs12
,
7698 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7701 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
7702 nested_vmx_entry_failure(vcpu
, vmcs12
,
7703 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
7708 * If the load IA32_EFER VM-entry control is 1, the following checks
7709 * are performed on the field for the IA32_EFER MSR:
7710 * - Bits reserved in the IA32_EFER MSR must be 0.
7711 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7712 * the IA-32e mode guest VM-exit control. It must also be identical
7713 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7716 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
7717 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
7718 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
7719 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
7720 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
7721 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
7722 nested_vmx_entry_failure(vcpu
, vmcs12
,
7723 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7729 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7730 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7731 * the values of the LMA and LME bits in the field must each be that of
7732 * the host address-space size VM-exit control.
7734 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
7735 ia32e
= (vmcs12
->vm_exit_controls
&
7736 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
7737 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
7738 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
7739 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
7740 nested_vmx_entry_failure(vcpu
, vmcs12
,
7741 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7747 * We're finally done with prerequisite checking, and can start with
7751 vmcs02
= nested_get_current_vmcs02(vmx
);
7755 enter_guest_mode(vcpu
);
7757 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
7760 vmx
->loaded_vmcs
= vmcs02
;
7762 vmx_vcpu_load(vcpu
, cpu
);
7766 vmx_segment_cache_clear(vmx
);
7768 vmcs12
->launch_state
= 1;
7770 prepare_vmcs02(vcpu
, vmcs12
);
7773 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7774 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7775 * returned as far as L1 is concerned. It will only return (and set
7776 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7782 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7783 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7784 * This function returns the new value we should put in vmcs12.guest_cr0.
7785 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7786 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7787 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7788 * didn't trap the bit, because if L1 did, so would L0).
7789 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7790 * been modified by L2, and L1 knows it. So just leave the old value of
7791 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7792 * isn't relevant, because if L0 traps this bit it can set it to anything.
7793 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7794 * changed these bits, and therefore they need to be updated, but L0
7795 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7796 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7798 static inline unsigned long
7799 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7802 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
7803 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
7804 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
7805 vcpu
->arch
.cr0_guest_owned_bits
));
7808 static inline unsigned long
7809 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7812 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
7813 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
7814 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
7815 vcpu
->arch
.cr4_guest_owned_bits
));
7818 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
7819 struct vmcs12
*vmcs12
)
7824 if (vcpu
->arch
.exception
.pending
) {
7825 nr
= vcpu
->arch
.exception
.nr
;
7826 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
7828 if (kvm_exception_is_soft(nr
)) {
7829 vmcs12
->vm_exit_instruction_len
=
7830 vcpu
->arch
.event_exit_inst_len
;
7831 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
7833 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
7835 if (vcpu
->arch
.exception
.has_error_code
) {
7836 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
7837 vmcs12
->idt_vectoring_error_code
=
7838 vcpu
->arch
.exception
.error_code
;
7841 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
7842 } else if (vcpu
->arch
.nmi_pending
) {
7843 vmcs12
->idt_vectoring_info_field
=
7844 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
7845 } else if (vcpu
->arch
.interrupt
.pending
) {
7846 nr
= vcpu
->arch
.interrupt
.nr
;
7847 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
7849 if (vcpu
->arch
.interrupt
.soft
) {
7850 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
7851 vmcs12
->vm_entry_instruction_len
=
7852 vcpu
->arch
.event_exit_inst_len
;
7854 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
7856 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
7861 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7862 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7863 * and this function updates it to reflect the changes to the guest state while
7864 * L2 was running (and perhaps made some exits which were handled directly by L0
7865 * without going back to L1), and to reflect the exit reason.
7866 * Note that we do not have to copy here all VMCS fields, just those that
7867 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7868 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7869 * which already writes to vmcs12 directly.
7871 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7873 /* update guest state fields: */
7874 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
7875 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
7877 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
7878 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
7879 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
7880 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
7882 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
7883 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
7884 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
7885 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
7886 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
7887 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
7888 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
7889 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
7890 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
7891 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
7892 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
7893 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
7894 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
7895 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
7896 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
7897 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
7898 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
7899 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
7900 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
7901 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
7902 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
7903 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
7904 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
7905 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
7906 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
7907 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
7908 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
7909 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
7910 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
7911 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
7912 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
7913 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
7914 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
7915 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
7916 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
7917 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
7919 vmcs12
->guest_interruptibility_info
=
7920 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
7921 vmcs12
->guest_pending_dbg_exceptions
=
7922 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
7924 vmcs12
->vm_entry_controls
=
7925 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
7926 (vmcs_read32(VM_ENTRY_CONTROLS
) & VM_ENTRY_IA32E_MODE
);
7928 /* TODO: These cannot have changed unless we have MSR bitmaps and
7929 * the relevant bit asks not to trap the change */
7930 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
7931 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
7932 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
7933 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
7934 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
7935 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
7937 /* update exit information fields: */
7939 vmcs12
->vm_exit_reason
= to_vmx(vcpu
)->exit_reason
;
7940 vmcs12
->exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7942 vmcs12
->vm_exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7943 if ((vmcs12
->vm_exit_intr_info
&
7944 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
7945 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
7946 vmcs12
->vm_exit_intr_error_code
=
7947 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
7948 vmcs12
->idt_vectoring_info_field
= 0;
7949 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
7950 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7952 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
7953 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7954 * instead of reading the real value. */
7955 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
7958 * Transfer the event that L0 or L1 may wanted to inject into
7959 * L2 to IDT_VECTORING_INFO_FIELD.
7961 vmcs12_save_pending_event(vcpu
, vmcs12
);
7965 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7966 * preserved above and would only end up incorrectly in L1.
7968 vcpu
->arch
.nmi_injected
= false;
7969 kvm_clear_exception_queue(vcpu
);
7970 kvm_clear_interrupt_queue(vcpu
);
7974 * A part of what we need to when the nested L2 guest exits and we want to
7975 * run its L1 parent, is to reset L1's guest state to the host state specified
7977 * This function is to be called not only on normal nested exit, but also on
7978 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7979 * Failures During or After Loading Guest State").
7980 * This function should be called when the active VMCS is L1's (vmcs01).
7982 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
7983 struct vmcs12
*vmcs12
)
7985 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
7986 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
7987 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
7988 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7990 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7991 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7993 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
7994 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
7995 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
7997 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7998 * actually changed, because it depends on the current state of
7999 * fpu_active (which may have changed).
8000 * Note that vmx_set_cr0 refers to efer set above.
8002 kvm_set_cr0(vcpu
, vmcs12
->host_cr0
);
8004 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8005 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8006 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8008 update_exception_bitmap(vcpu
);
8009 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
8010 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8013 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8014 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8016 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
8017 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
8019 /* shadow page tables on either EPT or shadow page tables */
8020 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
8021 kvm_mmu_reset_context(vcpu
);
8025 * Trivially support vpid by letting L2s share their parent
8026 * L1's vpid. TODO: move to a more elaborate solution, giving
8027 * each L2 its own vpid and exposing the vpid feature to L1.
8029 vmx_flush_tlb(vcpu
);
8033 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
8034 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
8035 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
8036 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
8037 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
8038 vmcs_writel(GUEST_TR_BASE
, vmcs12
->host_tr_base
);
8039 vmcs_writel(GUEST_GS_BASE
, vmcs12
->host_gs_base
);
8040 vmcs_writel(GUEST_FS_BASE
, vmcs12
->host_fs_base
);
8041 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->host_es_selector
);
8042 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->host_cs_selector
);
8043 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->host_ss_selector
);
8044 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->host_ds_selector
);
8045 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->host_fs_selector
);
8046 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->host_gs_selector
);
8047 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->host_tr_selector
);
8049 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
)
8050 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
8051 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8052 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
8053 vmcs12
->host_ia32_perf_global_ctrl
);
8055 kvm_set_dr(vcpu
, 7, 0x400);
8056 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
8060 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8061 * and modify vmcs12 to make it see what it would expect to see there if
8062 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8064 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
)
8066 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8068 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8070 /* trying to cancel vmlaunch/vmresume is a bug */
8071 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
8073 leave_guest_mode(vcpu
);
8074 prepare_vmcs12(vcpu
, vmcs12
);
8077 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8079 vmx_vcpu_load(vcpu
, cpu
);
8083 vmx_segment_cache_clear(vmx
);
8085 /* if no vmcs02 cache requested, remove the one we used */
8086 if (VMCS02_POOL_SIZE
== 0)
8087 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
8089 load_vmcs12_host_state(vcpu
, vmcs12
);
8091 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8092 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8094 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
8095 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
8096 vmx_set_virtual_x2apic_mode(vcpu
,
8097 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
8100 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8103 /* Unpin physical memory we referred to in vmcs02 */
8104 if (vmx
->nested
.apic_access_page
) {
8105 nested_release_page(vmx
->nested
.apic_access_page
);
8106 vmx
->nested
.apic_access_page
= 0;
8110 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8111 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8112 * success or failure flag accordingly.
8114 if (unlikely(vmx
->fail
)) {
8116 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
8118 nested_vmx_succeed(vcpu
);
8119 if (enable_shadow_vmcs
)
8120 vmx
->nested
.sync_shadow_vmcs
= true;
8124 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8125 * 23.7 "VM-entry failures during or after loading guest state" (this also
8126 * lists the acceptable exit-reason and exit-qualification parameters).
8127 * It should only be called before L2 actually succeeded to run, and when
8128 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8130 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
8131 struct vmcs12
*vmcs12
,
8132 u32 reason
, unsigned long qualification
)
8134 load_vmcs12_host_state(vcpu
, vmcs12
);
8135 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
8136 vmcs12
->exit_qualification
= qualification
;
8137 nested_vmx_succeed(vcpu
);
8138 if (enable_shadow_vmcs
)
8139 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
8142 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
8143 struct x86_instruction_info
*info
,
8144 enum x86_intercept_stage stage
)
8146 return X86EMUL_CONTINUE
;
8149 static struct kvm_x86_ops vmx_x86_ops
= {
8150 .cpu_has_kvm_support
= cpu_has_kvm_support
,
8151 .disabled_by_bios
= vmx_disabled_by_bios
,
8152 .hardware_setup
= hardware_setup
,
8153 .hardware_unsetup
= hardware_unsetup
,
8154 .check_processor_compatibility
= vmx_check_processor_compat
,
8155 .hardware_enable
= hardware_enable
,
8156 .hardware_disable
= hardware_disable
,
8157 .cpu_has_accelerated_tpr
= report_flexpriority
,
8159 .vcpu_create
= vmx_create_vcpu
,
8160 .vcpu_free
= vmx_free_vcpu
,
8161 .vcpu_reset
= vmx_vcpu_reset
,
8163 .prepare_guest_switch
= vmx_save_host_state
,
8164 .vcpu_load
= vmx_vcpu_load
,
8165 .vcpu_put
= vmx_vcpu_put
,
8167 .update_db_bp_intercept
= update_exception_bitmap
,
8168 .get_msr
= vmx_get_msr
,
8169 .set_msr
= vmx_set_msr
,
8170 .get_segment_base
= vmx_get_segment_base
,
8171 .get_segment
= vmx_get_segment
,
8172 .set_segment
= vmx_set_segment
,
8173 .get_cpl
= vmx_get_cpl
,
8174 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
8175 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
8176 .decache_cr3
= vmx_decache_cr3
,
8177 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
8178 .set_cr0
= vmx_set_cr0
,
8179 .set_cr3
= vmx_set_cr3
,
8180 .set_cr4
= vmx_set_cr4
,
8181 .set_efer
= vmx_set_efer
,
8182 .get_idt
= vmx_get_idt
,
8183 .set_idt
= vmx_set_idt
,
8184 .get_gdt
= vmx_get_gdt
,
8185 .set_gdt
= vmx_set_gdt
,
8186 .set_dr7
= vmx_set_dr7
,
8187 .cache_reg
= vmx_cache_reg
,
8188 .get_rflags
= vmx_get_rflags
,
8189 .set_rflags
= vmx_set_rflags
,
8190 .fpu_activate
= vmx_fpu_activate
,
8191 .fpu_deactivate
= vmx_fpu_deactivate
,
8193 .tlb_flush
= vmx_flush_tlb
,
8195 .run
= vmx_vcpu_run
,
8196 .handle_exit
= vmx_handle_exit
,
8197 .skip_emulated_instruction
= skip_emulated_instruction
,
8198 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
8199 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
8200 .patch_hypercall
= vmx_patch_hypercall
,
8201 .set_irq
= vmx_inject_irq
,
8202 .set_nmi
= vmx_inject_nmi
,
8203 .queue_exception
= vmx_queue_exception
,
8204 .cancel_injection
= vmx_cancel_injection
,
8205 .interrupt_allowed
= vmx_interrupt_allowed
,
8206 .nmi_allowed
= vmx_nmi_allowed
,
8207 .get_nmi_mask
= vmx_get_nmi_mask
,
8208 .set_nmi_mask
= vmx_set_nmi_mask
,
8209 .enable_nmi_window
= enable_nmi_window
,
8210 .enable_irq_window
= enable_irq_window
,
8211 .update_cr8_intercept
= update_cr8_intercept
,
8212 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
8213 .vm_has_apicv
= vmx_vm_has_apicv
,
8214 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
8215 .hwapic_irr_update
= vmx_hwapic_irr_update
,
8216 .hwapic_isr_update
= vmx_hwapic_isr_update
,
8217 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
8218 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
8220 .set_tss_addr
= vmx_set_tss_addr
,
8221 .get_tdp_level
= get_ept_level
,
8222 .get_mt_mask
= vmx_get_mt_mask
,
8224 .get_exit_info
= vmx_get_exit_info
,
8226 .get_lpage_level
= vmx_get_lpage_level
,
8228 .cpuid_update
= vmx_cpuid_update
,
8230 .rdtscp_supported
= vmx_rdtscp_supported
,
8231 .invpcid_supported
= vmx_invpcid_supported
,
8233 .set_supported_cpuid
= vmx_set_supported_cpuid
,
8235 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
8237 .set_tsc_khz
= vmx_set_tsc_khz
,
8238 .read_tsc_offset
= vmx_read_tsc_offset
,
8239 .write_tsc_offset
= vmx_write_tsc_offset
,
8240 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
8241 .compute_tsc_offset
= vmx_compute_tsc_offset
,
8242 .read_l1_tsc
= vmx_read_l1_tsc
,
8244 .set_tdp_cr3
= vmx_set_cr3
,
8246 .check_intercept
= vmx_check_intercept
,
8247 .handle_external_intr
= vmx_handle_external_intr
,
8250 static int __init
vmx_init(void)
8254 rdmsrl_safe(MSR_EFER
, &host_efer
);
8256 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
8257 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
8259 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8260 if (!vmx_io_bitmap_a
)
8265 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8266 if (!vmx_io_bitmap_b
)
8269 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8270 if (!vmx_msr_bitmap_legacy
)
8273 vmx_msr_bitmap_legacy_x2apic
=
8274 (unsigned long *)__get_free_page(GFP_KERNEL
);
8275 if (!vmx_msr_bitmap_legacy_x2apic
)
8278 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8279 if (!vmx_msr_bitmap_longmode
)
8282 vmx_msr_bitmap_longmode_x2apic
=
8283 (unsigned long *)__get_free_page(GFP_KERNEL
);
8284 if (!vmx_msr_bitmap_longmode_x2apic
)
8286 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8287 if (!vmx_vmread_bitmap
)
8290 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8291 if (!vmx_vmwrite_bitmap
)
8294 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
8295 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
8296 /* shadowed read/write fields */
8297 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
8298 clear_bit(shadow_read_write_fields
[i
], vmx_vmwrite_bitmap
);
8299 clear_bit(shadow_read_write_fields
[i
], vmx_vmread_bitmap
);
8301 /* shadowed read only fields */
8302 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
8303 clear_bit(shadow_read_only_fields
[i
], vmx_vmread_bitmap
);
8306 * Allow direct access to the PC debug port (it is often used for I/O
8307 * delays, but the vmexits simply slow things down).
8309 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
8310 clear_bit(0x80, vmx_io_bitmap_a
);
8312 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
8314 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
8315 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
8317 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
8319 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
8320 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
8325 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
8326 crash_vmclear_local_loaded_vmcss
);
8329 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
8330 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
8331 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
8332 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
8333 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
8334 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
8335 memcpy(vmx_msr_bitmap_legacy_x2apic
,
8336 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
8337 memcpy(vmx_msr_bitmap_longmode_x2apic
,
8338 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
8341 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8342 vmx_disable_intercept_msr_read_x2apic(msr
);
8344 /* According SDM, in x2apic mode, the whole id reg is used.
8345 * But in KVM, it only use the highest eight bits. Need to
8347 vmx_enable_intercept_msr_read_x2apic(0x802);
8349 vmx_enable_intercept_msr_read_x2apic(0x839);
8351 vmx_disable_intercept_msr_write_x2apic(0x808);
8353 vmx_disable_intercept_msr_write_x2apic(0x80b);
8355 vmx_disable_intercept_msr_write_x2apic(0x83f);
8359 kvm_mmu_set_mask_ptes(0ull,
8360 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
8361 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
8362 0ull, VMX_EPT_EXECUTABLE_MASK
);
8363 ept_set_mmio_spte_mask();
8371 free_page((unsigned long)vmx_vmwrite_bitmap
);
8373 free_page((unsigned long)vmx_vmread_bitmap
);
8375 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8377 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8379 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8381 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8383 free_page((unsigned long)vmx_io_bitmap_b
);
8385 free_page((unsigned long)vmx_io_bitmap_a
);
8389 static void __exit
vmx_exit(void)
8391 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8392 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8393 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8394 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8395 free_page((unsigned long)vmx_io_bitmap_b
);
8396 free_page((unsigned long)vmx_io_bitmap_a
);
8397 free_page((unsigned long)vmx_vmwrite_bitmap
);
8398 free_page((unsigned long)vmx_vmread_bitmap
);
8401 rcu_assign_pointer(crash_vmclear_loaded_vmcss
, NULL
);
8408 module_init(vmx_init
)
8409 module_exit(vmx_exit
)