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KVM: x86: Move TSC offset writes to common code
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
49
50 static int __read_mostly bypass_guest_pf = 1;
51 module_param(bypass_guest_pf, bool, S_IRUGO);
52
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
55
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
58
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
61
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
68
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
71
72 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74 #define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
77 (X86_CR0_WP | X86_CR0_NE)
78 #define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
80 #define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 | X86_CR4_OSXMMEXCPT)
83
84 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
86
87 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88
89 /*
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
99 */
100 #define KVM_VMX_DEFAULT_PLE_GAP 41
101 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103 module_param(ple_gap, int, S_IRUGO);
104
105 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106 module_param(ple_window, int, S_IRUGO);
107
108 #define NR_AUTOLOAD_MSRS 1
109
110 struct vmcs {
111 u32 revision_id;
112 u32 abort;
113 char data[0];
114 };
115
116 struct shared_msr_entry {
117 unsigned index;
118 u64 data;
119 u64 mask;
120 };
121
122 struct vcpu_vmx {
123 struct kvm_vcpu vcpu;
124 struct list_head local_vcpus_link;
125 unsigned long host_rsp;
126 int launched;
127 u8 fail;
128 u32 idt_vectoring_info;
129 struct shared_msr_entry *guest_msrs;
130 int nmsrs;
131 int save_nmsrs;
132 #ifdef CONFIG_X86_64
133 u64 msr_host_kernel_gs_base;
134 u64 msr_guest_kernel_gs_base;
135 #endif
136 struct vmcs *vmcs;
137 struct msr_autoload {
138 unsigned nr;
139 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
140 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
141 } msr_autoload;
142 struct {
143 int loaded;
144 u16 fs_sel, gs_sel, ldt_sel;
145 int gs_ldt_reload_needed;
146 int fs_reload_needed;
147 } host_state;
148 struct {
149 int vm86_active;
150 ulong save_rflags;
151 struct kvm_save_segment {
152 u16 selector;
153 unsigned long base;
154 u32 limit;
155 u32 ar;
156 } tr, es, ds, fs, gs;
157 struct {
158 bool pending;
159 u8 vector;
160 unsigned rip;
161 } irq;
162 } rmode;
163 int vpid;
164 bool emulation_required;
165
166 /* Support for vnmi-less CPUs */
167 int soft_vnmi_blocked;
168 ktime_t entry_time;
169 s64 vnmi_blocked_time;
170 u32 exit_reason;
171
172 bool rdtscp_enabled;
173 };
174
175 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
176 {
177 return container_of(vcpu, struct vcpu_vmx, vcpu);
178 }
179
180 static int init_rmode(struct kvm *kvm);
181 static u64 construct_eptp(unsigned long root_hpa);
182 static void kvm_cpu_vmxon(u64 addr);
183 static void kvm_cpu_vmxoff(void);
184
185 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
186 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
187 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
188 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
189
190 static unsigned long *vmx_io_bitmap_a;
191 static unsigned long *vmx_io_bitmap_b;
192 static unsigned long *vmx_msr_bitmap_legacy;
193 static unsigned long *vmx_msr_bitmap_longmode;
194
195 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
196 static DEFINE_SPINLOCK(vmx_vpid_lock);
197
198 static struct vmcs_config {
199 int size;
200 int order;
201 u32 revision_id;
202 u32 pin_based_exec_ctrl;
203 u32 cpu_based_exec_ctrl;
204 u32 cpu_based_2nd_exec_ctrl;
205 u32 vmexit_ctrl;
206 u32 vmentry_ctrl;
207 } vmcs_config;
208
209 static struct vmx_capability {
210 u32 ept;
211 u32 vpid;
212 } vmx_capability;
213
214 #define VMX_SEGMENT_FIELD(seg) \
215 [VCPU_SREG_##seg] = { \
216 .selector = GUEST_##seg##_SELECTOR, \
217 .base = GUEST_##seg##_BASE, \
218 .limit = GUEST_##seg##_LIMIT, \
219 .ar_bytes = GUEST_##seg##_AR_BYTES, \
220 }
221
222 static struct kvm_vmx_segment_field {
223 unsigned selector;
224 unsigned base;
225 unsigned limit;
226 unsigned ar_bytes;
227 } kvm_vmx_segment_fields[] = {
228 VMX_SEGMENT_FIELD(CS),
229 VMX_SEGMENT_FIELD(DS),
230 VMX_SEGMENT_FIELD(ES),
231 VMX_SEGMENT_FIELD(FS),
232 VMX_SEGMENT_FIELD(GS),
233 VMX_SEGMENT_FIELD(SS),
234 VMX_SEGMENT_FIELD(TR),
235 VMX_SEGMENT_FIELD(LDTR),
236 };
237
238 static u64 host_efer;
239
240 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
241
242 /*
243 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
244 * away by decrementing the array size.
245 */
246 static const u32 vmx_msr_index[] = {
247 #ifdef CONFIG_X86_64
248 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
249 #endif
250 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
251 };
252 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
253
254 static inline bool is_page_fault(u32 intr_info)
255 {
256 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
257 INTR_INFO_VALID_MASK)) ==
258 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
259 }
260
261 static inline bool is_no_device(u32 intr_info)
262 {
263 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
264 INTR_INFO_VALID_MASK)) ==
265 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
266 }
267
268 static inline bool is_invalid_opcode(u32 intr_info)
269 {
270 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
271 INTR_INFO_VALID_MASK)) ==
272 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
273 }
274
275 static inline bool is_external_interrupt(u32 intr_info)
276 {
277 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
278 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
279 }
280
281 static inline bool is_machine_check(u32 intr_info)
282 {
283 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
284 INTR_INFO_VALID_MASK)) ==
285 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
286 }
287
288 static inline bool cpu_has_vmx_msr_bitmap(void)
289 {
290 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
291 }
292
293 static inline bool cpu_has_vmx_tpr_shadow(void)
294 {
295 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
296 }
297
298 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
299 {
300 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
301 }
302
303 static inline bool cpu_has_secondary_exec_ctrls(void)
304 {
305 return vmcs_config.cpu_based_exec_ctrl &
306 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
307 }
308
309 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
310 {
311 return vmcs_config.cpu_based_2nd_exec_ctrl &
312 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
313 }
314
315 static inline bool cpu_has_vmx_flexpriority(void)
316 {
317 return cpu_has_vmx_tpr_shadow() &&
318 cpu_has_vmx_virtualize_apic_accesses();
319 }
320
321 static inline bool cpu_has_vmx_ept_execute_only(void)
322 {
323 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
324 }
325
326 static inline bool cpu_has_vmx_eptp_uncacheable(void)
327 {
328 return vmx_capability.ept & VMX_EPTP_UC_BIT;
329 }
330
331 static inline bool cpu_has_vmx_eptp_writeback(void)
332 {
333 return vmx_capability.ept & VMX_EPTP_WB_BIT;
334 }
335
336 static inline bool cpu_has_vmx_ept_2m_page(void)
337 {
338 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
339 }
340
341 static inline bool cpu_has_vmx_ept_1g_page(void)
342 {
343 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
344 }
345
346 static inline bool cpu_has_vmx_ept_4levels(void)
347 {
348 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
349 }
350
351 static inline bool cpu_has_vmx_invept_individual_addr(void)
352 {
353 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
354 }
355
356 static inline bool cpu_has_vmx_invept_context(void)
357 {
358 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
359 }
360
361 static inline bool cpu_has_vmx_invept_global(void)
362 {
363 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
364 }
365
366 static inline bool cpu_has_vmx_invvpid_single(void)
367 {
368 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
369 }
370
371 static inline bool cpu_has_vmx_invvpid_global(void)
372 {
373 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
374 }
375
376 static inline bool cpu_has_vmx_ept(void)
377 {
378 return vmcs_config.cpu_based_2nd_exec_ctrl &
379 SECONDARY_EXEC_ENABLE_EPT;
380 }
381
382 static inline bool cpu_has_vmx_unrestricted_guest(void)
383 {
384 return vmcs_config.cpu_based_2nd_exec_ctrl &
385 SECONDARY_EXEC_UNRESTRICTED_GUEST;
386 }
387
388 static inline bool cpu_has_vmx_ple(void)
389 {
390 return vmcs_config.cpu_based_2nd_exec_ctrl &
391 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
392 }
393
394 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
395 {
396 return flexpriority_enabled && irqchip_in_kernel(kvm);
397 }
398
399 static inline bool cpu_has_vmx_vpid(void)
400 {
401 return vmcs_config.cpu_based_2nd_exec_ctrl &
402 SECONDARY_EXEC_ENABLE_VPID;
403 }
404
405 static inline bool cpu_has_vmx_rdtscp(void)
406 {
407 return vmcs_config.cpu_based_2nd_exec_ctrl &
408 SECONDARY_EXEC_RDTSCP;
409 }
410
411 static inline bool cpu_has_virtual_nmis(void)
412 {
413 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
414 }
415
416 static inline bool cpu_has_vmx_wbinvd_exit(void)
417 {
418 return vmcs_config.cpu_based_2nd_exec_ctrl &
419 SECONDARY_EXEC_WBINVD_EXITING;
420 }
421
422 static inline bool report_flexpriority(void)
423 {
424 return flexpriority_enabled;
425 }
426
427 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
428 {
429 int i;
430
431 for (i = 0; i < vmx->nmsrs; ++i)
432 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
433 return i;
434 return -1;
435 }
436
437 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
438 {
439 struct {
440 u64 vpid : 16;
441 u64 rsvd : 48;
442 u64 gva;
443 } operand = { vpid, 0, gva };
444
445 asm volatile (__ex(ASM_VMX_INVVPID)
446 /* CF==1 or ZF==1 --> rc = -1 */
447 "; ja 1f ; ud2 ; 1:"
448 : : "a"(&operand), "c"(ext) : "cc", "memory");
449 }
450
451 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
452 {
453 struct {
454 u64 eptp, gpa;
455 } operand = {eptp, gpa};
456
457 asm volatile (__ex(ASM_VMX_INVEPT)
458 /* CF==1 or ZF==1 --> rc = -1 */
459 "; ja 1f ; ud2 ; 1:\n"
460 : : "a" (&operand), "c" (ext) : "cc", "memory");
461 }
462
463 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
464 {
465 int i;
466
467 i = __find_msr_index(vmx, msr);
468 if (i >= 0)
469 return &vmx->guest_msrs[i];
470 return NULL;
471 }
472
473 static void vmcs_clear(struct vmcs *vmcs)
474 {
475 u64 phys_addr = __pa(vmcs);
476 u8 error;
477
478 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
479 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
480 : "cc", "memory");
481 if (error)
482 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
483 vmcs, phys_addr);
484 }
485
486 static void vmcs_load(struct vmcs *vmcs)
487 {
488 u64 phys_addr = __pa(vmcs);
489 u8 error;
490
491 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
492 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
493 : "cc", "memory");
494 if (error)
495 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
496 vmcs, phys_addr);
497 }
498
499 static void __vcpu_clear(void *arg)
500 {
501 struct vcpu_vmx *vmx = arg;
502 int cpu = raw_smp_processor_id();
503
504 if (vmx->vcpu.cpu == cpu)
505 vmcs_clear(vmx->vmcs);
506 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
507 per_cpu(current_vmcs, cpu) = NULL;
508 rdtscll(vmx->vcpu.arch.host_tsc);
509 list_del(&vmx->local_vcpus_link);
510 vmx->vcpu.cpu = -1;
511 vmx->launched = 0;
512 }
513
514 static void vcpu_clear(struct vcpu_vmx *vmx)
515 {
516 if (vmx->vcpu.cpu == -1)
517 return;
518 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
519 }
520
521 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
522 {
523 if (vmx->vpid == 0)
524 return;
525
526 if (cpu_has_vmx_invvpid_single())
527 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
528 }
529
530 static inline void vpid_sync_vcpu_global(void)
531 {
532 if (cpu_has_vmx_invvpid_global())
533 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
534 }
535
536 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
537 {
538 if (cpu_has_vmx_invvpid_single())
539 vpid_sync_vcpu_single(vmx);
540 else
541 vpid_sync_vcpu_global();
542 }
543
544 static inline void ept_sync_global(void)
545 {
546 if (cpu_has_vmx_invept_global())
547 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
548 }
549
550 static inline void ept_sync_context(u64 eptp)
551 {
552 if (enable_ept) {
553 if (cpu_has_vmx_invept_context())
554 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
555 else
556 ept_sync_global();
557 }
558 }
559
560 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
561 {
562 if (enable_ept) {
563 if (cpu_has_vmx_invept_individual_addr())
564 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
565 eptp, gpa);
566 else
567 ept_sync_context(eptp);
568 }
569 }
570
571 static unsigned long vmcs_readl(unsigned long field)
572 {
573 unsigned long value;
574
575 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
576 : "=a"(value) : "d"(field) : "cc");
577 return value;
578 }
579
580 static u16 vmcs_read16(unsigned long field)
581 {
582 return vmcs_readl(field);
583 }
584
585 static u32 vmcs_read32(unsigned long field)
586 {
587 return vmcs_readl(field);
588 }
589
590 static u64 vmcs_read64(unsigned long field)
591 {
592 #ifdef CONFIG_X86_64
593 return vmcs_readl(field);
594 #else
595 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
596 #endif
597 }
598
599 static noinline void vmwrite_error(unsigned long field, unsigned long value)
600 {
601 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
602 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
603 dump_stack();
604 }
605
606 static void vmcs_writel(unsigned long field, unsigned long value)
607 {
608 u8 error;
609
610 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
611 : "=q"(error) : "a"(value), "d"(field) : "cc");
612 if (unlikely(error))
613 vmwrite_error(field, value);
614 }
615
616 static void vmcs_write16(unsigned long field, u16 value)
617 {
618 vmcs_writel(field, value);
619 }
620
621 static void vmcs_write32(unsigned long field, u32 value)
622 {
623 vmcs_writel(field, value);
624 }
625
626 static void vmcs_write64(unsigned long field, u64 value)
627 {
628 vmcs_writel(field, value);
629 #ifndef CONFIG_X86_64
630 asm volatile ("");
631 vmcs_writel(field+1, value >> 32);
632 #endif
633 }
634
635 static void vmcs_clear_bits(unsigned long field, u32 mask)
636 {
637 vmcs_writel(field, vmcs_readl(field) & ~mask);
638 }
639
640 static void vmcs_set_bits(unsigned long field, u32 mask)
641 {
642 vmcs_writel(field, vmcs_readl(field) | mask);
643 }
644
645 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
646 {
647 u32 eb;
648
649 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
650 (1u << NM_VECTOR) | (1u << DB_VECTOR);
651 if ((vcpu->guest_debug &
652 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
654 eb |= 1u << BP_VECTOR;
655 if (to_vmx(vcpu)->rmode.vm86_active)
656 eb = ~0;
657 if (enable_ept)
658 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
659 if (vcpu->fpu_active)
660 eb &= ~(1u << NM_VECTOR);
661 vmcs_write32(EXCEPTION_BITMAP, eb);
662 }
663
664 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
665 {
666 unsigned i;
667 struct msr_autoload *m = &vmx->msr_autoload;
668
669 for (i = 0; i < m->nr; ++i)
670 if (m->guest[i].index == msr)
671 break;
672
673 if (i == m->nr)
674 return;
675 --m->nr;
676 m->guest[i] = m->guest[m->nr];
677 m->host[i] = m->host[m->nr];
678 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
679 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
680 }
681
682 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
683 u64 guest_val, u64 host_val)
684 {
685 unsigned i;
686 struct msr_autoload *m = &vmx->msr_autoload;
687
688 for (i = 0; i < m->nr; ++i)
689 if (m->guest[i].index == msr)
690 break;
691
692 if (i == m->nr) {
693 ++m->nr;
694 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
695 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
696 }
697
698 m->guest[i].index = msr;
699 m->guest[i].value = guest_val;
700 m->host[i].index = msr;
701 m->host[i].value = host_val;
702 }
703
704 static void reload_tss(void)
705 {
706 /*
707 * VT restores TR but not its size. Useless.
708 */
709 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
710 struct desc_struct *descs;
711
712 descs = (void *)gdt->address;
713 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
714 load_TR_desc();
715 }
716
717 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
718 {
719 u64 guest_efer;
720 u64 ignore_bits;
721
722 guest_efer = vmx->vcpu.arch.efer;
723
724 /*
725 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
726 * outside long mode
727 */
728 ignore_bits = EFER_NX | EFER_SCE;
729 #ifdef CONFIG_X86_64
730 ignore_bits |= EFER_LMA | EFER_LME;
731 /* SCE is meaningful only in long mode on Intel */
732 if (guest_efer & EFER_LMA)
733 ignore_bits &= ~(u64)EFER_SCE;
734 #endif
735 guest_efer &= ~ignore_bits;
736 guest_efer |= host_efer & ignore_bits;
737 vmx->guest_msrs[efer_offset].data = guest_efer;
738 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
739
740 clear_atomic_switch_msr(vmx, MSR_EFER);
741 /* On ept, can't emulate nx, and must switch nx atomically */
742 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
743 guest_efer = vmx->vcpu.arch.efer;
744 if (!(guest_efer & EFER_LMA))
745 guest_efer &= ~EFER_LME;
746 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
747 return false;
748 }
749
750 return true;
751 }
752
753 static unsigned long segment_base(u16 selector)
754 {
755 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
756 struct desc_struct *d;
757 unsigned long table_base;
758 unsigned long v;
759
760 if (!(selector & ~3))
761 return 0;
762
763 table_base = gdt->address;
764
765 if (selector & 4) { /* from ldt */
766 u16 ldt_selector = kvm_read_ldt();
767
768 if (!(ldt_selector & ~3))
769 return 0;
770
771 table_base = segment_base(ldt_selector);
772 }
773 d = (struct desc_struct *)(table_base + (selector & ~7));
774 v = get_desc_base(d);
775 #ifdef CONFIG_X86_64
776 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
777 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
778 #endif
779 return v;
780 }
781
782 static inline unsigned long kvm_read_tr_base(void)
783 {
784 u16 tr;
785 asm("str %0" : "=g"(tr));
786 return segment_base(tr);
787 }
788
789 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
790 {
791 struct vcpu_vmx *vmx = to_vmx(vcpu);
792 int i;
793
794 if (vmx->host_state.loaded)
795 return;
796
797 vmx->host_state.loaded = 1;
798 /*
799 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
800 * allow segment selectors with cpl > 0 or ti == 1.
801 */
802 vmx->host_state.ldt_sel = kvm_read_ldt();
803 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
804 savesegment(fs, vmx->host_state.fs_sel);
805 if (!(vmx->host_state.fs_sel & 7)) {
806 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
807 vmx->host_state.fs_reload_needed = 0;
808 } else {
809 vmcs_write16(HOST_FS_SELECTOR, 0);
810 vmx->host_state.fs_reload_needed = 1;
811 }
812 savesegment(gs, vmx->host_state.gs_sel);
813 if (!(vmx->host_state.gs_sel & 7))
814 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
815 else {
816 vmcs_write16(HOST_GS_SELECTOR, 0);
817 vmx->host_state.gs_ldt_reload_needed = 1;
818 }
819
820 #ifdef CONFIG_X86_64
821 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
822 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
823 #else
824 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
825 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
826 #endif
827
828 #ifdef CONFIG_X86_64
829 if (is_long_mode(&vmx->vcpu)) {
830 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
831 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
832 }
833 #endif
834 for (i = 0; i < vmx->save_nmsrs; ++i)
835 kvm_set_shared_msr(vmx->guest_msrs[i].index,
836 vmx->guest_msrs[i].data,
837 vmx->guest_msrs[i].mask);
838 }
839
840 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
841 {
842 if (!vmx->host_state.loaded)
843 return;
844
845 ++vmx->vcpu.stat.host_state_reload;
846 vmx->host_state.loaded = 0;
847 if (vmx->host_state.fs_reload_needed)
848 loadsegment(fs, vmx->host_state.fs_sel);
849 if (vmx->host_state.gs_ldt_reload_needed) {
850 kvm_load_ldt(vmx->host_state.ldt_sel);
851 #ifdef CONFIG_X86_64
852 load_gs_index(vmx->host_state.gs_sel);
853 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
854 #else
855 loadsegment(gs, vmx->host_state.gs_sel);
856 #endif
857 }
858 reload_tss();
859 #ifdef CONFIG_X86_64
860 if (is_long_mode(&vmx->vcpu)) {
861 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
862 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
863 }
864 #endif
865 if (current_thread_info()->status & TS_USEDFPU)
866 clts();
867 load_gdt(&__get_cpu_var(host_gdt));
868 }
869
870 static void vmx_load_host_state(struct vcpu_vmx *vmx)
871 {
872 preempt_disable();
873 __vmx_load_host_state(vmx);
874 preempt_enable();
875 }
876
877 /*
878 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
879 * vcpu mutex is already taken.
880 */
881 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
882 {
883 struct vcpu_vmx *vmx = to_vmx(vcpu);
884 u64 tsc_this, delta, new_offset;
885 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
886
887 if (!vmm_exclusive)
888 kvm_cpu_vmxon(phys_addr);
889 else if (vcpu->cpu != cpu)
890 vcpu_clear(vmx);
891
892 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
893 per_cpu(current_vmcs, cpu) = vmx->vmcs;
894 vmcs_load(vmx->vmcs);
895 }
896
897 if (vcpu->cpu != cpu) {
898 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
899 unsigned long sysenter_esp;
900
901 kvm_migrate_timers(vcpu);
902 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
903 local_irq_disable();
904 list_add(&vmx->local_vcpus_link,
905 &per_cpu(vcpus_on_cpu, cpu));
906 local_irq_enable();
907
908 vcpu->cpu = cpu;
909 /*
910 * Linux uses per-cpu TSS and GDT, so set these when switching
911 * processors.
912 */
913 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
914 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
915
916 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
917 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
918
919 /*
920 * Make sure the time stamp counter is monotonous.
921 */
922 rdtscll(tsc_this);
923 if (tsc_this < vcpu->arch.host_tsc) {
924 delta = vcpu->arch.host_tsc - tsc_this;
925 new_offset = vmcs_read64(TSC_OFFSET) + delta;
926 vmcs_write64(TSC_OFFSET, new_offset);
927 }
928 }
929 }
930
931 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
932 {
933 __vmx_load_host_state(to_vmx(vcpu));
934 if (!vmm_exclusive) {
935 __vcpu_clear(to_vmx(vcpu));
936 kvm_cpu_vmxoff();
937 }
938 }
939
940 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
941 {
942 ulong cr0;
943
944 if (vcpu->fpu_active)
945 return;
946 vcpu->fpu_active = 1;
947 cr0 = vmcs_readl(GUEST_CR0);
948 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
949 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
950 vmcs_writel(GUEST_CR0, cr0);
951 update_exception_bitmap(vcpu);
952 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
953 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
954 }
955
956 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
957
958 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
959 {
960 vmx_decache_cr0_guest_bits(vcpu);
961 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
962 update_exception_bitmap(vcpu);
963 vcpu->arch.cr0_guest_owned_bits = 0;
964 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
965 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
966 }
967
968 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
969 {
970 unsigned long rflags, save_rflags;
971
972 rflags = vmcs_readl(GUEST_RFLAGS);
973 if (to_vmx(vcpu)->rmode.vm86_active) {
974 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
975 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
976 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
977 }
978 return rflags;
979 }
980
981 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
982 {
983 if (to_vmx(vcpu)->rmode.vm86_active) {
984 to_vmx(vcpu)->rmode.save_rflags = rflags;
985 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
986 }
987 vmcs_writel(GUEST_RFLAGS, rflags);
988 }
989
990 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
991 {
992 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
993 int ret = 0;
994
995 if (interruptibility & GUEST_INTR_STATE_STI)
996 ret |= KVM_X86_SHADOW_INT_STI;
997 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
998 ret |= KVM_X86_SHADOW_INT_MOV_SS;
999
1000 return ret & mask;
1001 }
1002
1003 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1004 {
1005 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1006 u32 interruptibility = interruptibility_old;
1007
1008 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1009
1010 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1011 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1012 else if (mask & KVM_X86_SHADOW_INT_STI)
1013 interruptibility |= GUEST_INTR_STATE_STI;
1014
1015 if ((interruptibility != interruptibility_old))
1016 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1017 }
1018
1019 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1020 {
1021 unsigned long rip;
1022
1023 rip = kvm_rip_read(vcpu);
1024 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1025 kvm_rip_write(vcpu, rip);
1026
1027 /* skipping an emulated instruction also counts */
1028 vmx_set_interrupt_shadow(vcpu, 0);
1029 }
1030
1031 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1032 bool has_error_code, u32 error_code,
1033 bool reinject)
1034 {
1035 struct vcpu_vmx *vmx = to_vmx(vcpu);
1036 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1037
1038 if (has_error_code) {
1039 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1040 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1041 }
1042
1043 if (vmx->rmode.vm86_active) {
1044 vmx->rmode.irq.pending = true;
1045 vmx->rmode.irq.vector = nr;
1046 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
1047 if (kvm_exception_is_soft(nr))
1048 vmx->rmode.irq.rip +=
1049 vmx->vcpu.arch.event_exit_inst_len;
1050 intr_info |= INTR_TYPE_SOFT_INTR;
1051 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1052 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1053 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1054 return;
1055 }
1056
1057 if (kvm_exception_is_soft(nr)) {
1058 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1059 vmx->vcpu.arch.event_exit_inst_len);
1060 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1061 } else
1062 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1063
1064 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1065 }
1066
1067 static bool vmx_rdtscp_supported(void)
1068 {
1069 return cpu_has_vmx_rdtscp();
1070 }
1071
1072 /*
1073 * Swap MSR entry in host/guest MSR entry array.
1074 */
1075 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1076 {
1077 struct shared_msr_entry tmp;
1078
1079 tmp = vmx->guest_msrs[to];
1080 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1081 vmx->guest_msrs[from] = tmp;
1082 }
1083
1084 /*
1085 * Set up the vmcs to automatically save and restore system
1086 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1087 * mode, as fiddling with msrs is very expensive.
1088 */
1089 static void setup_msrs(struct vcpu_vmx *vmx)
1090 {
1091 int save_nmsrs, index;
1092 unsigned long *msr_bitmap;
1093
1094 vmx_load_host_state(vmx);
1095 save_nmsrs = 0;
1096 #ifdef CONFIG_X86_64
1097 if (is_long_mode(&vmx->vcpu)) {
1098 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1099 if (index >= 0)
1100 move_msr_up(vmx, index, save_nmsrs++);
1101 index = __find_msr_index(vmx, MSR_LSTAR);
1102 if (index >= 0)
1103 move_msr_up(vmx, index, save_nmsrs++);
1104 index = __find_msr_index(vmx, MSR_CSTAR);
1105 if (index >= 0)
1106 move_msr_up(vmx, index, save_nmsrs++);
1107 index = __find_msr_index(vmx, MSR_TSC_AUX);
1108 if (index >= 0 && vmx->rdtscp_enabled)
1109 move_msr_up(vmx, index, save_nmsrs++);
1110 /*
1111 * MSR_STAR is only needed on long mode guests, and only
1112 * if efer.sce is enabled.
1113 */
1114 index = __find_msr_index(vmx, MSR_STAR);
1115 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1116 move_msr_up(vmx, index, save_nmsrs++);
1117 }
1118 #endif
1119 index = __find_msr_index(vmx, MSR_EFER);
1120 if (index >= 0 && update_transition_efer(vmx, index))
1121 move_msr_up(vmx, index, save_nmsrs++);
1122
1123 vmx->save_nmsrs = save_nmsrs;
1124
1125 if (cpu_has_vmx_msr_bitmap()) {
1126 if (is_long_mode(&vmx->vcpu))
1127 msr_bitmap = vmx_msr_bitmap_longmode;
1128 else
1129 msr_bitmap = vmx_msr_bitmap_legacy;
1130
1131 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1132 }
1133 }
1134
1135 /*
1136 * reads and returns guest's timestamp counter "register"
1137 * guest_tsc = host_tsc + tsc_offset -- 21.3
1138 */
1139 static u64 guest_read_tsc(void)
1140 {
1141 u64 host_tsc, tsc_offset;
1142
1143 rdtscll(host_tsc);
1144 tsc_offset = vmcs_read64(TSC_OFFSET);
1145 return host_tsc + tsc_offset;
1146 }
1147
1148 /*
1149 * writes 'offset' into guest's timestamp counter offset register
1150 */
1151 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1152 {
1153 vmcs_write64(TSC_OFFSET, offset);
1154 }
1155
1156 /*
1157 * Reads an msr value (of 'msr_index') into 'pdata'.
1158 * Returns 0 on success, non-0 otherwise.
1159 * Assumes vcpu_load() was already called.
1160 */
1161 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1162 {
1163 u64 data;
1164 struct shared_msr_entry *msr;
1165
1166 if (!pdata) {
1167 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1168 return -EINVAL;
1169 }
1170
1171 switch (msr_index) {
1172 #ifdef CONFIG_X86_64
1173 case MSR_FS_BASE:
1174 data = vmcs_readl(GUEST_FS_BASE);
1175 break;
1176 case MSR_GS_BASE:
1177 data = vmcs_readl(GUEST_GS_BASE);
1178 break;
1179 case MSR_KERNEL_GS_BASE:
1180 vmx_load_host_state(to_vmx(vcpu));
1181 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1182 break;
1183 #endif
1184 case MSR_EFER:
1185 return kvm_get_msr_common(vcpu, msr_index, pdata);
1186 case MSR_IA32_TSC:
1187 data = guest_read_tsc();
1188 break;
1189 case MSR_IA32_SYSENTER_CS:
1190 data = vmcs_read32(GUEST_SYSENTER_CS);
1191 break;
1192 case MSR_IA32_SYSENTER_EIP:
1193 data = vmcs_readl(GUEST_SYSENTER_EIP);
1194 break;
1195 case MSR_IA32_SYSENTER_ESP:
1196 data = vmcs_readl(GUEST_SYSENTER_ESP);
1197 break;
1198 case MSR_TSC_AUX:
1199 if (!to_vmx(vcpu)->rdtscp_enabled)
1200 return 1;
1201 /* Otherwise falls through */
1202 default:
1203 vmx_load_host_state(to_vmx(vcpu));
1204 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1205 if (msr) {
1206 vmx_load_host_state(to_vmx(vcpu));
1207 data = msr->data;
1208 break;
1209 }
1210 return kvm_get_msr_common(vcpu, msr_index, pdata);
1211 }
1212
1213 *pdata = data;
1214 return 0;
1215 }
1216
1217 /*
1218 * Writes msr value into into the appropriate "register".
1219 * Returns 0 on success, non-0 otherwise.
1220 * Assumes vcpu_load() was already called.
1221 */
1222 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1223 {
1224 struct vcpu_vmx *vmx = to_vmx(vcpu);
1225 struct shared_msr_entry *msr;
1226 int ret = 0;
1227
1228 switch (msr_index) {
1229 case MSR_EFER:
1230 vmx_load_host_state(vmx);
1231 ret = kvm_set_msr_common(vcpu, msr_index, data);
1232 break;
1233 #ifdef CONFIG_X86_64
1234 case MSR_FS_BASE:
1235 vmcs_writel(GUEST_FS_BASE, data);
1236 break;
1237 case MSR_GS_BASE:
1238 vmcs_writel(GUEST_GS_BASE, data);
1239 break;
1240 case MSR_KERNEL_GS_BASE:
1241 vmx_load_host_state(vmx);
1242 vmx->msr_guest_kernel_gs_base = data;
1243 break;
1244 #endif
1245 case MSR_IA32_SYSENTER_CS:
1246 vmcs_write32(GUEST_SYSENTER_CS, data);
1247 break;
1248 case MSR_IA32_SYSENTER_EIP:
1249 vmcs_writel(GUEST_SYSENTER_EIP, data);
1250 break;
1251 case MSR_IA32_SYSENTER_ESP:
1252 vmcs_writel(GUEST_SYSENTER_ESP, data);
1253 break;
1254 case MSR_IA32_TSC:
1255 kvm_write_tsc(vcpu, data);
1256 break;
1257 case MSR_IA32_CR_PAT:
1258 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1259 vmcs_write64(GUEST_IA32_PAT, data);
1260 vcpu->arch.pat = data;
1261 break;
1262 }
1263 ret = kvm_set_msr_common(vcpu, msr_index, data);
1264 break;
1265 case MSR_TSC_AUX:
1266 if (!vmx->rdtscp_enabled)
1267 return 1;
1268 /* Check reserved bit, higher 32 bits should be zero */
1269 if ((data >> 32) != 0)
1270 return 1;
1271 /* Otherwise falls through */
1272 default:
1273 msr = find_msr_entry(vmx, msr_index);
1274 if (msr) {
1275 vmx_load_host_state(vmx);
1276 msr->data = data;
1277 break;
1278 }
1279 ret = kvm_set_msr_common(vcpu, msr_index, data);
1280 }
1281
1282 return ret;
1283 }
1284
1285 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1286 {
1287 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1288 switch (reg) {
1289 case VCPU_REGS_RSP:
1290 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1291 break;
1292 case VCPU_REGS_RIP:
1293 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1294 break;
1295 case VCPU_EXREG_PDPTR:
1296 if (enable_ept)
1297 ept_save_pdptrs(vcpu);
1298 break;
1299 default:
1300 break;
1301 }
1302 }
1303
1304 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1305 {
1306 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1307 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1308 else
1309 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1310
1311 update_exception_bitmap(vcpu);
1312 }
1313
1314 static __init int cpu_has_kvm_support(void)
1315 {
1316 return cpu_has_vmx();
1317 }
1318
1319 static __init int vmx_disabled_by_bios(void)
1320 {
1321 u64 msr;
1322
1323 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1324 if (msr & FEATURE_CONTROL_LOCKED) {
1325 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1326 && tboot_enabled())
1327 return 1;
1328 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1329 && !tboot_enabled())
1330 return 1;
1331 }
1332
1333 return 0;
1334 /* locked but not enabled */
1335 }
1336
1337 static void kvm_cpu_vmxon(u64 addr)
1338 {
1339 asm volatile (ASM_VMX_VMXON_RAX
1340 : : "a"(&addr), "m"(addr)
1341 : "memory", "cc");
1342 }
1343
1344 static int hardware_enable(void *garbage)
1345 {
1346 int cpu = raw_smp_processor_id();
1347 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1348 u64 old, test_bits;
1349
1350 if (read_cr4() & X86_CR4_VMXE)
1351 return -EBUSY;
1352
1353 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1354 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1355
1356 test_bits = FEATURE_CONTROL_LOCKED;
1357 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1358 if (tboot_enabled())
1359 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1360
1361 if ((old & test_bits) != test_bits) {
1362 /* enable and lock */
1363 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1364 }
1365 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1366
1367 if (vmm_exclusive) {
1368 kvm_cpu_vmxon(phys_addr);
1369 ept_sync_global();
1370 }
1371
1372 store_gdt(&__get_cpu_var(host_gdt));
1373
1374 return 0;
1375 }
1376
1377 static void vmclear_local_vcpus(void)
1378 {
1379 int cpu = raw_smp_processor_id();
1380 struct vcpu_vmx *vmx, *n;
1381
1382 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1383 local_vcpus_link)
1384 __vcpu_clear(vmx);
1385 }
1386
1387
1388 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1389 * tricks.
1390 */
1391 static void kvm_cpu_vmxoff(void)
1392 {
1393 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1394 }
1395
1396 static void hardware_disable(void *garbage)
1397 {
1398 if (vmm_exclusive) {
1399 vmclear_local_vcpus();
1400 kvm_cpu_vmxoff();
1401 }
1402 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1403 }
1404
1405 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1406 u32 msr, u32 *result)
1407 {
1408 u32 vmx_msr_low, vmx_msr_high;
1409 u32 ctl = ctl_min | ctl_opt;
1410
1411 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1412
1413 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1414 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1415
1416 /* Ensure minimum (required) set of control bits are supported. */
1417 if (ctl_min & ~ctl)
1418 return -EIO;
1419
1420 *result = ctl;
1421 return 0;
1422 }
1423
1424 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1425 {
1426 u32 vmx_msr_low, vmx_msr_high;
1427 u32 min, opt, min2, opt2;
1428 u32 _pin_based_exec_control = 0;
1429 u32 _cpu_based_exec_control = 0;
1430 u32 _cpu_based_2nd_exec_control = 0;
1431 u32 _vmexit_control = 0;
1432 u32 _vmentry_control = 0;
1433
1434 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1435 opt = PIN_BASED_VIRTUAL_NMIS;
1436 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1437 &_pin_based_exec_control) < 0)
1438 return -EIO;
1439
1440 min = CPU_BASED_HLT_EXITING |
1441 #ifdef CONFIG_X86_64
1442 CPU_BASED_CR8_LOAD_EXITING |
1443 CPU_BASED_CR8_STORE_EXITING |
1444 #endif
1445 CPU_BASED_CR3_LOAD_EXITING |
1446 CPU_BASED_CR3_STORE_EXITING |
1447 CPU_BASED_USE_IO_BITMAPS |
1448 CPU_BASED_MOV_DR_EXITING |
1449 CPU_BASED_USE_TSC_OFFSETING |
1450 CPU_BASED_MWAIT_EXITING |
1451 CPU_BASED_MONITOR_EXITING |
1452 CPU_BASED_INVLPG_EXITING;
1453 opt = CPU_BASED_TPR_SHADOW |
1454 CPU_BASED_USE_MSR_BITMAPS |
1455 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1456 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1457 &_cpu_based_exec_control) < 0)
1458 return -EIO;
1459 #ifdef CONFIG_X86_64
1460 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1461 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1462 ~CPU_BASED_CR8_STORE_EXITING;
1463 #endif
1464 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1465 min2 = 0;
1466 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1467 SECONDARY_EXEC_WBINVD_EXITING |
1468 SECONDARY_EXEC_ENABLE_VPID |
1469 SECONDARY_EXEC_ENABLE_EPT |
1470 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1471 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1472 SECONDARY_EXEC_RDTSCP;
1473 if (adjust_vmx_controls(min2, opt2,
1474 MSR_IA32_VMX_PROCBASED_CTLS2,
1475 &_cpu_based_2nd_exec_control) < 0)
1476 return -EIO;
1477 }
1478 #ifndef CONFIG_X86_64
1479 if (!(_cpu_based_2nd_exec_control &
1480 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1481 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1482 #endif
1483 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1484 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1485 enabled */
1486 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1487 CPU_BASED_CR3_STORE_EXITING |
1488 CPU_BASED_INVLPG_EXITING);
1489 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1490 vmx_capability.ept, vmx_capability.vpid);
1491 }
1492
1493 min = 0;
1494 #ifdef CONFIG_X86_64
1495 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1496 #endif
1497 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1498 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1499 &_vmexit_control) < 0)
1500 return -EIO;
1501
1502 min = 0;
1503 opt = VM_ENTRY_LOAD_IA32_PAT;
1504 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1505 &_vmentry_control) < 0)
1506 return -EIO;
1507
1508 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1509
1510 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1511 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1512 return -EIO;
1513
1514 #ifdef CONFIG_X86_64
1515 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1516 if (vmx_msr_high & (1u<<16))
1517 return -EIO;
1518 #endif
1519
1520 /* Require Write-Back (WB) memory type for VMCS accesses. */
1521 if (((vmx_msr_high >> 18) & 15) != 6)
1522 return -EIO;
1523
1524 vmcs_conf->size = vmx_msr_high & 0x1fff;
1525 vmcs_conf->order = get_order(vmcs_config.size);
1526 vmcs_conf->revision_id = vmx_msr_low;
1527
1528 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1529 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1530 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1531 vmcs_conf->vmexit_ctrl = _vmexit_control;
1532 vmcs_conf->vmentry_ctrl = _vmentry_control;
1533
1534 return 0;
1535 }
1536
1537 static struct vmcs *alloc_vmcs_cpu(int cpu)
1538 {
1539 int node = cpu_to_node(cpu);
1540 struct page *pages;
1541 struct vmcs *vmcs;
1542
1543 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1544 if (!pages)
1545 return NULL;
1546 vmcs = page_address(pages);
1547 memset(vmcs, 0, vmcs_config.size);
1548 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1549 return vmcs;
1550 }
1551
1552 static struct vmcs *alloc_vmcs(void)
1553 {
1554 return alloc_vmcs_cpu(raw_smp_processor_id());
1555 }
1556
1557 static void free_vmcs(struct vmcs *vmcs)
1558 {
1559 free_pages((unsigned long)vmcs, vmcs_config.order);
1560 }
1561
1562 static void free_kvm_area(void)
1563 {
1564 int cpu;
1565
1566 for_each_possible_cpu(cpu) {
1567 free_vmcs(per_cpu(vmxarea, cpu));
1568 per_cpu(vmxarea, cpu) = NULL;
1569 }
1570 }
1571
1572 static __init int alloc_kvm_area(void)
1573 {
1574 int cpu;
1575
1576 for_each_possible_cpu(cpu) {
1577 struct vmcs *vmcs;
1578
1579 vmcs = alloc_vmcs_cpu(cpu);
1580 if (!vmcs) {
1581 free_kvm_area();
1582 return -ENOMEM;
1583 }
1584
1585 per_cpu(vmxarea, cpu) = vmcs;
1586 }
1587 return 0;
1588 }
1589
1590 static __init int hardware_setup(void)
1591 {
1592 if (setup_vmcs_config(&vmcs_config) < 0)
1593 return -EIO;
1594
1595 if (boot_cpu_has(X86_FEATURE_NX))
1596 kvm_enable_efer_bits(EFER_NX);
1597
1598 if (!cpu_has_vmx_vpid())
1599 enable_vpid = 0;
1600
1601 if (!cpu_has_vmx_ept() ||
1602 !cpu_has_vmx_ept_4levels()) {
1603 enable_ept = 0;
1604 enable_unrestricted_guest = 0;
1605 }
1606
1607 if (!cpu_has_vmx_unrestricted_guest())
1608 enable_unrestricted_guest = 0;
1609
1610 if (!cpu_has_vmx_flexpriority())
1611 flexpriority_enabled = 0;
1612
1613 if (!cpu_has_vmx_tpr_shadow())
1614 kvm_x86_ops->update_cr8_intercept = NULL;
1615
1616 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1617 kvm_disable_largepages();
1618
1619 if (!cpu_has_vmx_ple())
1620 ple_gap = 0;
1621
1622 return alloc_kvm_area();
1623 }
1624
1625 static __exit void hardware_unsetup(void)
1626 {
1627 free_kvm_area();
1628 }
1629
1630 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1631 {
1632 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1633
1634 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1635 vmcs_write16(sf->selector, save->selector);
1636 vmcs_writel(sf->base, save->base);
1637 vmcs_write32(sf->limit, save->limit);
1638 vmcs_write32(sf->ar_bytes, save->ar);
1639 } else {
1640 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1641 << AR_DPL_SHIFT;
1642 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1643 }
1644 }
1645
1646 static void enter_pmode(struct kvm_vcpu *vcpu)
1647 {
1648 unsigned long flags;
1649 struct vcpu_vmx *vmx = to_vmx(vcpu);
1650
1651 vmx->emulation_required = 1;
1652 vmx->rmode.vm86_active = 0;
1653
1654 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1655 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1656 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1657
1658 flags = vmcs_readl(GUEST_RFLAGS);
1659 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1660 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1661 vmcs_writel(GUEST_RFLAGS, flags);
1662
1663 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1664 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1665
1666 update_exception_bitmap(vcpu);
1667
1668 if (emulate_invalid_guest_state)
1669 return;
1670
1671 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1672 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1673 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1674 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1675
1676 vmcs_write16(GUEST_SS_SELECTOR, 0);
1677 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1678
1679 vmcs_write16(GUEST_CS_SELECTOR,
1680 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1681 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1682 }
1683
1684 static gva_t rmode_tss_base(struct kvm *kvm)
1685 {
1686 if (!kvm->arch.tss_addr) {
1687 struct kvm_memslots *slots;
1688 gfn_t base_gfn;
1689
1690 slots = kvm_memslots(kvm);
1691 base_gfn = slots->memslots[0].base_gfn +
1692 kvm->memslots->memslots[0].npages - 3;
1693 return base_gfn << PAGE_SHIFT;
1694 }
1695 return kvm->arch.tss_addr;
1696 }
1697
1698 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1699 {
1700 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1701
1702 save->selector = vmcs_read16(sf->selector);
1703 save->base = vmcs_readl(sf->base);
1704 save->limit = vmcs_read32(sf->limit);
1705 save->ar = vmcs_read32(sf->ar_bytes);
1706 vmcs_write16(sf->selector, save->base >> 4);
1707 vmcs_write32(sf->base, save->base & 0xfffff);
1708 vmcs_write32(sf->limit, 0xffff);
1709 vmcs_write32(sf->ar_bytes, 0xf3);
1710 }
1711
1712 static void enter_rmode(struct kvm_vcpu *vcpu)
1713 {
1714 unsigned long flags;
1715 struct vcpu_vmx *vmx = to_vmx(vcpu);
1716
1717 if (enable_unrestricted_guest)
1718 return;
1719
1720 vmx->emulation_required = 1;
1721 vmx->rmode.vm86_active = 1;
1722
1723 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1724 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1725
1726 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1727 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1728
1729 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1730 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1731
1732 flags = vmcs_readl(GUEST_RFLAGS);
1733 vmx->rmode.save_rflags = flags;
1734
1735 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1736
1737 vmcs_writel(GUEST_RFLAGS, flags);
1738 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1739 update_exception_bitmap(vcpu);
1740
1741 if (emulate_invalid_guest_state)
1742 goto continue_rmode;
1743
1744 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1745 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1746 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1747
1748 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1749 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1750 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1751 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1752 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1753
1754 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1755 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1756 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1757 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1758
1759 continue_rmode:
1760 kvm_mmu_reset_context(vcpu);
1761 init_rmode(vcpu->kvm);
1762 }
1763
1764 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1765 {
1766 struct vcpu_vmx *vmx = to_vmx(vcpu);
1767 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1768
1769 if (!msr)
1770 return;
1771
1772 /*
1773 * Force kernel_gs_base reloading before EFER changes, as control
1774 * of this msr depends on is_long_mode().
1775 */
1776 vmx_load_host_state(to_vmx(vcpu));
1777 vcpu->arch.efer = efer;
1778 if (efer & EFER_LMA) {
1779 vmcs_write32(VM_ENTRY_CONTROLS,
1780 vmcs_read32(VM_ENTRY_CONTROLS) |
1781 VM_ENTRY_IA32E_MODE);
1782 msr->data = efer;
1783 } else {
1784 vmcs_write32(VM_ENTRY_CONTROLS,
1785 vmcs_read32(VM_ENTRY_CONTROLS) &
1786 ~VM_ENTRY_IA32E_MODE);
1787
1788 msr->data = efer & ~EFER_LME;
1789 }
1790 setup_msrs(vmx);
1791 }
1792
1793 #ifdef CONFIG_X86_64
1794
1795 static void enter_lmode(struct kvm_vcpu *vcpu)
1796 {
1797 u32 guest_tr_ar;
1798
1799 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1800 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1801 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1802 __func__);
1803 vmcs_write32(GUEST_TR_AR_BYTES,
1804 (guest_tr_ar & ~AR_TYPE_MASK)
1805 | AR_TYPE_BUSY_64_TSS);
1806 }
1807 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1808 }
1809
1810 static void exit_lmode(struct kvm_vcpu *vcpu)
1811 {
1812 vmcs_write32(VM_ENTRY_CONTROLS,
1813 vmcs_read32(VM_ENTRY_CONTROLS)
1814 & ~VM_ENTRY_IA32E_MODE);
1815 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1816 }
1817
1818 #endif
1819
1820 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1821 {
1822 vpid_sync_context(to_vmx(vcpu));
1823 if (enable_ept) {
1824 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1825 return;
1826 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1827 }
1828 }
1829
1830 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1831 {
1832 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1833
1834 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1835 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1836 }
1837
1838 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1839 {
1840 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1841
1842 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1843 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1844 }
1845
1846 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1847 {
1848 if (!test_bit(VCPU_EXREG_PDPTR,
1849 (unsigned long *)&vcpu->arch.regs_dirty))
1850 return;
1851
1852 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1853 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1854 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1855 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1856 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1857 }
1858 }
1859
1860 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1861 {
1862 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1863 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1864 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1865 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1866 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1867 }
1868
1869 __set_bit(VCPU_EXREG_PDPTR,
1870 (unsigned long *)&vcpu->arch.regs_avail);
1871 __set_bit(VCPU_EXREG_PDPTR,
1872 (unsigned long *)&vcpu->arch.regs_dirty);
1873 }
1874
1875 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1876
1877 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1878 unsigned long cr0,
1879 struct kvm_vcpu *vcpu)
1880 {
1881 if (!(cr0 & X86_CR0_PG)) {
1882 /* From paging/starting to nonpaging */
1883 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1884 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1885 (CPU_BASED_CR3_LOAD_EXITING |
1886 CPU_BASED_CR3_STORE_EXITING));
1887 vcpu->arch.cr0 = cr0;
1888 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1889 } else if (!is_paging(vcpu)) {
1890 /* From nonpaging to paging */
1891 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1892 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1893 ~(CPU_BASED_CR3_LOAD_EXITING |
1894 CPU_BASED_CR3_STORE_EXITING));
1895 vcpu->arch.cr0 = cr0;
1896 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1897 }
1898
1899 if (!(cr0 & X86_CR0_WP))
1900 *hw_cr0 &= ~X86_CR0_WP;
1901 }
1902
1903 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1904 {
1905 struct vcpu_vmx *vmx = to_vmx(vcpu);
1906 unsigned long hw_cr0;
1907
1908 if (enable_unrestricted_guest)
1909 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1910 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1911 else
1912 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1913
1914 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1915 enter_pmode(vcpu);
1916
1917 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1918 enter_rmode(vcpu);
1919
1920 #ifdef CONFIG_X86_64
1921 if (vcpu->arch.efer & EFER_LME) {
1922 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1923 enter_lmode(vcpu);
1924 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1925 exit_lmode(vcpu);
1926 }
1927 #endif
1928
1929 if (enable_ept)
1930 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1931
1932 if (!vcpu->fpu_active)
1933 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1934
1935 vmcs_writel(CR0_READ_SHADOW, cr0);
1936 vmcs_writel(GUEST_CR0, hw_cr0);
1937 vcpu->arch.cr0 = cr0;
1938 }
1939
1940 static u64 construct_eptp(unsigned long root_hpa)
1941 {
1942 u64 eptp;
1943
1944 /* TODO write the value reading from MSR */
1945 eptp = VMX_EPT_DEFAULT_MT |
1946 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1947 eptp |= (root_hpa & PAGE_MASK);
1948
1949 return eptp;
1950 }
1951
1952 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1953 {
1954 unsigned long guest_cr3;
1955 u64 eptp;
1956
1957 guest_cr3 = cr3;
1958 if (enable_ept) {
1959 eptp = construct_eptp(cr3);
1960 vmcs_write64(EPT_POINTER, eptp);
1961 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1962 vcpu->kvm->arch.ept_identity_map_addr;
1963 ept_load_pdptrs(vcpu);
1964 }
1965
1966 vmx_flush_tlb(vcpu);
1967 vmcs_writel(GUEST_CR3, guest_cr3);
1968 }
1969
1970 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1971 {
1972 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1973 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1974
1975 vcpu->arch.cr4 = cr4;
1976 if (enable_ept) {
1977 if (!is_paging(vcpu)) {
1978 hw_cr4 &= ~X86_CR4_PAE;
1979 hw_cr4 |= X86_CR4_PSE;
1980 } else if (!(cr4 & X86_CR4_PAE)) {
1981 hw_cr4 &= ~X86_CR4_PAE;
1982 }
1983 }
1984
1985 vmcs_writel(CR4_READ_SHADOW, cr4);
1986 vmcs_writel(GUEST_CR4, hw_cr4);
1987 }
1988
1989 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1990 {
1991 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1992
1993 return vmcs_readl(sf->base);
1994 }
1995
1996 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1997 struct kvm_segment *var, int seg)
1998 {
1999 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2000 u32 ar;
2001
2002 var->base = vmcs_readl(sf->base);
2003 var->limit = vmcs_read32(sf->limit);
2004 var->selector = vmcs_read16(sf->selector);
2005 ar = vmcs_read32(sf->ar_bytes);
2006 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2007 ar = 0;
2008 var->type = ar & 15;
2009 var->s = (ar >> 4) & 1;
2010 var->dpl = (ar >> 5) & 3;
2011 var->present = (ar >> 7) & 1;
2012 var->avl = (ar >> 12) & 1;
2013 var->l = (ar >> 13) & 1;
2014 var->db = (ar >> 14) & 1;
2015 var->g = (ar >> 15) & 1;
2016 var->unusable = (ar >> 16) & 1;
2017 }
2018
2019 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2020 {
2021 if (!is_protmode(vcpu))
2022 return 0;
2023
2024 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2025 return 3;
2026
2027 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2028 }
2029
2030 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2031 {
2032 u32 ar;
2033
2034 if (var->unusable)
2035 ar = 1 << 16;
2036 else {
2037 ar = var->type & 15;
2038 ar |= (var->s & 1) << 4;
2039 ar |= (var->dpl & 3) << 5;
2040 ar |= (var->present & 1) << 7;
2041 ar |= (var->avl & 1) << 12;
2042 ar |= (var->l & 1) << 13;
2043 ar |= (var->db & 1) << 14;
2044 ar |= (var->g & 1) << 15;
2045 }
2046 if (ar == 0) /* a 0 value means unusable */
2047 ar = AR_UNUSABLE_MASK;
2048
2049 return ar;
2050 }
2051
2052 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2053 struct kvm_segment *var, int seg)
2054 {
2055 struct vcpu_vmx *vmx = to_vmx(vcpu);
2056 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2057 u32 ar;
2058
2059 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2060 vmx->rmode.tr.selector = var->selector;
2061 vmx->rmode.tr.base = var->base;
2062 vmx->rmode.tr.limit = var->limit;
2063 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2064 return;
2065 }
2066 vmcs_writel(sf->base, var->base);
2067 vmcs_write32(sf->limit, var->limit);
2068 vmcs_write16(sf->selector, var->selector);
2069 if (vmx->rmode.vm86_active && var->s) {
2070 /*
2071 * Hack real-mode segments into vm86 compatibility.
2072 */
2073 if (var->base == 0xffff0000 && var->selector == 0xf000)
2074 vmcs_writel(sf->base, 0xf0000);
2075 ar = 0xf3;
2076 } else
2077 ar = vmx_segment_access_rights(var);
2078
2079 /*
2080 * Fix the "Accessed" bit in AR field of segment registers for older
2081 * qemu binaries.
2082 * IA32 arch specifies that at the time of processor reset the
2083 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2084 * is setting it to 0 in the usedland code. This causes invalid guest
2085 * state vmexit when "unrestricted guest" mode is turned on.
2086 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2087 * tree. Newer qemu binaries with that qemu fix would not need this
2088 * kvm hack.
2089 */
2090 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2091 ar |= 0x1; /* Accessed */
2092
2093 vmcs_write32(sf->ar_bytes, ar);
2094 }
2095
2096 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2097 {
2098 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2099
2100 *db = (ar >> 14) & 1;
2101 *l = (ar >> 13) & 1;
2102 }
2103
2104 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2105 {
2106 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2107 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2108 }
2109
2110 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2111 {
2112 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2113 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2114 }
2115
2116 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2117 {
2118 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2119 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2120 }
2121
2122 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2123 {
2124 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2125 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2126 }
2127
2128 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2129 {
2130 struct kvm_segment var;
2131 u32 ar;
2132
2133 vmx_get_segment(vcpu, &var, seg);
2134 ar = vmx_segment_access_rights(&var);
2135
2136 if (var.base != (var.selector << 4))
2137 return false;
2138 if (var.limit != 0xffff)
2139 return false;
2140 if (ar != 0xf3)
2141 return false;
2142
2143 return true;
2144 }
2145
2146 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2147 {
2148 struct kvm_segment cs;
2149 unsigned int cs_rpl;
2150
2151 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2152 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2153
2154 if (cs.unusable)
2155 return false;
2156 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2157 return false;
2158 if (!cs.s)
2159 return false;
2160 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2161 if (cs.dpl > cs_rpl)
2162 return false;
2163 } else {
2164 if (cs.dpl != cs_rpl)
2165 return false;
2166 }
2167 if (!cs.present)
2168 return false;
2169
2170 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2171 return true;
2172 }
2173
2174 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2175 {
2176 struct kvm_segment ss;
2177 unsigned int ss_rpl;
2178
2179 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2180 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2181
2182 if (ss.unusable)
2183 return true;
2184 if (ss.type != 3 && ss.type != 7)
2185 return false;
2186 if (!ss.s)
2187 return false;
2188 if (ss.dpl != ss_rpl) /* DPL != RPL */
2189 return false;
2190 if (!ss.present)
2191 return false;
2192
2193 return true;
2194 }
2195
2196 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2197 {
2198 struct kvm_segment var;
2199 unsigned int rpl;
2200
2201 vmx_get_segment(vcpu, &var, seg);
2202 rpl = var.selector & SELECTOR_RPL_MASK;
2203
2204 if (var.unusable)
2205 return true;
2206 if (!var.s)
2207 return false;
2208 if (!var.present)
2209 return false;
2210 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2211 if (var.dpl < rpl) /* DPL < RPL */
2212 return false;
2213 }
2214
2215 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2216 * rights flags
2217 */
2218 return true;
2219 }
2220
2221 static bool tr_valid(struct kvm_vcpu *vcpu)
2222 {
2223 struct kvm_segment tr;
2224
2225 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2226
2227 if (tr.unusable)
2228 return false;
2229 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2230 return false;
2231 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2232 return false;
2233 if (!tr.present)
2234 return false;
2235
2236 return true;
2237 }
2238
2239 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2240 {
2241 struct kvm_segment ldtr;
2242
2243 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2244
2245 if (ldtr.unusable)
2246 return true;
2247 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2248 return false;
2249 if (ldtr.type != 2)
2250 return false;
2251 if (!ldtr.present)
2252 return false;
2253
2254 return true;
2255 }
2256
2257 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2258 {
2259 struct kvm_segment cs, ss;
2260
2261 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2262 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2263
2264 return ((cs.selector & SELECTOR_RPL_MASK) ==
2265 (ss.selector & SELECTOR_RPL_MASK));
2266 }
2267
2268 /*
2269 * Check if guest state is valid. Returns true if valid, false if
2270 * not.
2271 * We assume that registers are always usable
2272 */
2273 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2274 {
2275 /* real mode guest state checks */
2276 if (!is_protmode(vcpu)) {
2277 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2278 return false;
2279 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2280 return false;
2281 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2282 return false;
2283 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2284 return false;
2285 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2286 return false;
2287 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2288 return false;
2289 } else {
2290 /* protected mode guest state checks */
2291 if (!cs_ss_rpl_check(vcpu))
2292 return false;
2293 if (!code_segment_valid(vcpu))
2294 return false;
2295 if (!stack_segment_valid(vcpu))
2296 return false;
2297 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2298 return false;
2299 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2300 return false;
2301 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2302 return false;
2303 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2304 return false;
2305 if (!tr_valid(vcpu))
2306 return false;
2307 if (!ldtr_valid(vcpu))
2308 return false;
2309 }
2310 /* TODO:
2311 * - Add checks on RIP
2312 * - Add checks on RFLAGS
2313 */
2314
2315 return true;
2316 }
2317
2318 static int init_rmode_tss(struct kvm *kvm)
2319 {
2320 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2321 u16 data = 0;
2322 int ret = 0;
2323 int r;
2324
2325 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2326 if (r < 0)
2327 goto out;
2328 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2329 r = kvm_write_guest_page(kvm, fn++, &data,
2330 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2331 if (r < 0)
2332 goto out;
2333 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2334 if (r < 0)
2335 goto out;
2336 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2337 if (r < 0)
2338 goto out;
2339 data = ~0;
2340 r = kvm_write_guest_page(kvm, fn, &data,
2341 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2342 sizeof(u8));
2343 if (r < 0)
2344 goto out;
2345
2346 ret = 1;
2347 out:
2348 return ret;
2349 }
2350
2351 static int init_rmode_identity_map(struct kvm *kvm)
2352 {
2353 int i, r, ret;
2354 pfn_t identity_map_pfn;
2355 u32 tmp;
2356
2357 if (!enable_ept)
2358 return 1;
2359 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2360 printk(KERN_ERR "EPT: identity-mapping pagetable "
2361 "haven't been allocated!\n");
2362 return 0;
2363 }
2364 if (likely(kvm->arch.ept_identity_pagetable_done))
2365 return 1;
2366 ret = 0;
2367 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2368 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2369 if (r < 0)
2370 goto out;
2371 /* Set up identity-mapping pagetable for EPT in real mode */
2372 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2373 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2374 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2375 r = kvm_write_guest_page(kvm, identity_map_pfn,
2376 &tmp, i * sizeof(tmp), sizeof(tmp));
2377 if (r < 0)
2378 goto out;
2379 }
2380 kvm->arch.ept_identity_pagetable_done = true;
2381 ret = 1;
2382 out:
2383 return ret;
2384 }
2385
2386 static void seg_setup(int seg)
2387 {
2388 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2389 unsigned int ar;
2390
2391 vmcs_write16(sf->selector, 0);
2392 vmcs_writel(sf->base, 0);
2393 vmcs_write32(sf->limit, 0xffff);
2394 if (enable_unrestricted_guest) {
2395 ar = 0x93;
2396 if (seg == VCPU_SREG_CS)
2397 ar |= 0x08; /* code segment */
2398 } else
2399 ar = 0xf3;
2400
2401 vmcs_write32(sf->ar_bytes, ar);
2402 }
2403
2404 static int alloc_apic_access_page(struct kvm *kvm)
2405 {
2406 struct kvm_userspace_memory_region kvm_userspace_mem;
2407 int r = 0;
2408
2409 mutex_lock(&kvm->slots_lock);
2410 if (kvm->arch.apic_access_page)
2411 goto out;
2412 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2413 kvm_userspace_mem.flags = 0;
2414 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2415 kvm_userspace_mem.memory_size = PAGE_SIZE;
2416 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2417 if (r)
2418 goto out;
2419
2420 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2421 out:
2422 mutex_unlock(&kvm->slots_lock);
2423 return r;
2424 }
2425
2426 static int alloc_identity_pagetable(struct kvm *kvm)
2427 {
2428 struct kvm_userspace_memory_region kvm_userspace_mem;
2429 int r = 0;
2430
2431 mutex_lock(&kvm->slots_lock);
2432 if (kvm->arch.ept_identity_pagetable)
2433 goto out;
2434 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2435 kvm_userspace_mem.flags = 0;
2436 kvm_userspace_mem.guest_phys_addr =
2437 kvm->arch.ept_identity_map_addr;
2438 kvm_userspace_mem.memory_size = PAGE_SIZE;
2439 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2440 if (r)
2441 goto out;
2442
2443 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2444 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2445 out:
2446 mutex_unlock(&kvm->slots_lock);
2447 return r;
2448 }
2449
2450 static void allocate_vpid(struct vcpu_vmx *vmx)
2451 {
2452 int vpid;
2453
2454 vmx->vpid = 0;
2455 if (!enable_vpid)
2456 return;
2457 spin_lock(&vmx_vpid_lock);
2458 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2459 if (vpid < VMX_NR_VPIDS) {
2460 vmx->vpid = vpid;
2461 __set_bit(vpid, vmx_vpid_bitmap);
2462 }
2463 spin_unlock(&vmx_vpid_lock);
2464 }
2465
2466 static void free_vpid(struct vcpu_vmx *vmx)
2467 {
2468 if (!enable_vpid)
2469 return;
2470 spin_lock(&vmx_vpid_lock);
2471 if (vmx->vpid != 0)
2472 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2473 spin_unlock(&vmx_vpid_lock);
2474 }
2475
2476 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2477 {
2478 int f = sizeof(unsigned long);
2479
2480 if (!cpu_has_vmx_msr_bitmap())
2481 return;
2482
2483 /*
2484 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2485 * have the write-low and read-high bitmap offsets the wrong way round.
2486 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2487 */
2488 if (msr <= 0x1fff) {
2489 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2490 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2491 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2492 msr &= 0x1fff;
2493 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2494 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2495 }
2496 }
2497
2498 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2499 {
2500 if (!longmode_only)
2501 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2502 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2503 }
2504
2505 /*
2506 * Sets up the vmcs for emulated real mode.
2507 */
2508 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2509 {
2510 u32 host_sysenter_cs, msr_low, msr_high;
2511 u32 junk;
2512 u64 host_pat;
2513 unsigned long a;
2514 struct desc_ptr dt;
2515 int i;
2516 unsigned long kvm_vmx_return;
2517 u32 exec_control;
2518
2519 /* I/O */
2520 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2521 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2522
2523 if (cpu_has_vmx_msr_bitmap())
2524 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2525
2526 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2527
2528 /* Control */
2529 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2530 vmcs_config.pin_based_exec_ctrl);
2531
2532 exec_control = vmcs_config.cpu_based_exec_ctrl;
2533 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2534 exec_control &= ~CPU_BASED_TPR_SHADOW;
2535 #ifdef CONFIG_X86_64
2536 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2537 CPU_BASED_CR8_LOAD_EXITING;
2538 #endif
2539 }
2540 if (!enable_ept)
2541 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2542 CPU_BASED_CR3_LOAD_EXITING |
2543 CPU_BASED_INVLPG_EXITING;
2544 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2545
2546 if (cpu_has_secondary_exec_ctrls()) {
2547 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2548 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2549 exec_control &=
2550 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2551 if (vmx->vpid == 0)
2552 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2553 if (!enable_ept) {
2554 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2555 enable_unrestricted_guest = 0;
2556 }
2557 if (!enable_unrestricted_guest)
2558 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2559 if (!ple_gap)
2560 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2561 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2562 }
2563
2564 if (ple_gap) {
2565 vmcs_write32(PLE_GAP, ple_gap);
2566 vmcs_write32(PLE_WINDOW, ple_window);
2567 }
2568
2569 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2570 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2571 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2572
2573 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2574 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2575 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2576
2577 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2578 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2579 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2580 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2581 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
2582 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2583 #ifdef CONFIG_X86_64
2584 rdmsrl(MSR_FS_BASE, a);
2585 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2586 rdmsrl(MSR_GS_BASE, a);
2587 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2588 #else
2589 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2590 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2591 #endif
2592
2593 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2594
2595 native_store_idt(&dt);
2596 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2597
2598 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2599 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2600 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2601 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2602 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2603 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2604 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2605
2606 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2607 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2608 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2609 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2610 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2611 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2612
2613 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2614 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2615 host_pat = msr_low | ((u64) msr_high << 32);
2616 vmcs_write64(HOST_IA32_PAT, host_pat);
2617 }
2618 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2619 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2620 host_pat = msr_low | ((u64) msr_high << 32);
2621 /* Write the default value follow host pat */
2622 vmcs_write64(GUEST_IA32_PAT, host_pat);
2623 /* Keep arch.pat sync with GUEST_IA32_PAT */
2624 vmx->vcpu.arch.pat = host_pat;
2625 }
2626
2627 for (i = 0; i < NR_VMX_MSR; ++i) {
2628 u32 index = vmx_msr_index[i];
2629 u32 data_low, data_high;
2630 int j = vmx->nmsrs;
2631
2632 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2633 continue;
2634 if (wrmsr_safe(index, data_low, data_high) < 0)
2635 continue;
2636 vmx->guest_msrs[j].index = i;
2637 vmx->guest_msrs[j].data = 0;
2638 vmx->guest_msrs[j].mask = -1ull;
2639 ++vmx->nmsrs;
2640 }
2641
2642 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2643
2644 /* 22.2.1, 20.8.1 */
2645 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2646
2647 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2648 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2649 if (enable_ept)
2650 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2651 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2652
2653 kvm_write_tsc(&vmx->vcpu, 0);
2654
2655 return 0;
2656 }
2657
2658 static int init_rmode(struct kvm *kvm)
2659 {
2660 int idx, ret = 0;
2661
2662 idx = srcu_read_lock(&kvm->srcu);
2663 if (!init_rmode_tss(kvm))
2664 goto exit;
2665 if (!init_rmode_identity_map(kvm))
2666 goto exit;
2667
2668 ret = 1;
2669 exit:
2670 srcu_read_unlock(&kvm->srcu, idx);
2671 return ret;
2672 }
2673
2674 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2675 {
2676 struct vcpu_vmx *vmx = to_vmx(vcpu);
2677 u64 msr;
2678 int ret;
2679
2680 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2681 if (!init_rmode(vmx->vcpu.kvm)) {
2682 ret = -ENOMEM;
2683 goto out;
2684 }
2685
2686 vmx->rmode.vm86_active = 0;
2687
2688 vmx->soft_vnmi_blocked = 0;
2689
2690 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2691 kvm_set_cr8(&vmx->vcpu, 0);
2692 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2693 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2694 msr |= MSR_IA32_APICBASE_BSP;
2695 kvm_set_apic_base(&vmx->vcpu, msr);
2696
2697 ret = fx_init(&vmx->vcpu);
2698 if (ret != 0)
2699 goto out;
2700
2701 seg_setup(VCPU_SREG_CS);
2702 /*
2703 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2704 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2705 */
2706 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2707 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2708 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2709 } else {
2710 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2711 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2712 }
2713
2714 seg_setup(VCPU_SREG_DS);
2715 seg_setup(VCPU_SREG_ES);
2716 seg_setup(VCPU_SREG_FS);
2717 seg_setup(VCPU_SREG_GS);
2718 seg_setup(VCPU_SREG_SS);
2719
2720 vmcs_write16(GUEST_TR_SELECTOR, 0);
2721 vmcs_writel(GUEST_TR_BASE, 0);
2722 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2723 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2724
2725 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2726 vmcs_writel(GUEST_LDTR_BASE, 0);
2727 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2728 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2729
2730 vmcs_write32(GUEST_SYSENTER_CS, 0);
2731 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2732 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2733
2734 vmcs_writel(GUEST_RFLAGS, 0x02);
2735 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2736 kvm_rip_write(vcpu, 0xfff0);
2737 else
2738 kvm_rip_write(vcpu, 0);
2739 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2740
2741 vmcs_writel(GUEST_DR7, 0x400);
2742
2743 vmcs_writel(GUEST_GDTR_BASE, 0);
2744 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2745
2746 vmcs_writel(GUEST_IDTR_BASE, 0);
2747 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2748
2749 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2750 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2751 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2752
2753 /* Special registers */
2754 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2755
2756 setup_msrs(vmx);
2757
2758 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2759
2760 if (cpu_has_vmx_tpr_shadow()) {
2761 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2762 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2763 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2764 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2765 vmcs_write32(TPR_THRESHOLD, 0);
2766 }
2767
2768 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2769 vmcs_write64(APIC_ACCESS_ADDR,
2770 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2771
2772 if (vmx->vpid != 0)
2773 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2774
2775 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2776 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2777 vmx_set_cr4(&vmx->vcpu, 0);
2778 vmx_set_efer(&vmx->vcpu, 0);
2779 vmx_fpu_activate(&vmx->vcpu);
2780 update_exception_bitmap(&vmx->vcpu);
2781
2782 vpid_sync_context(vmx);
2783
2784 ret = 0;
2785
2786 /* HACK: Don't enable emulation on guest boot/reset */
2787 vmx->emulation_required = 0;
2788
2789 out:
2790 return ret;
2791 }
2792
2793 static void enable_irq_window(struct kvm_vcpu *vcpu)
2794 {
2795 u32 cpu_based_vm_exec_control;
2796
2797 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2798 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2799 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2800 }
2801
2802 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2803 {
2804 u32 cpu_based_vm_exec_control;
2805
2806 if (!cpu_has_virtual_nmis()) {
2807 enable_irq_window(vcpu);
2808 return;
2809 }
2810
2811 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2812 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2813 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2814 }
2815
2816 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2817 {
2818 struct vcpu_vmx *vmx = to_vmx(vcpu);
2819 uint32_t intr;
2820 int irq = vcpu->arch.interrupt.nr;
2821
2822 trace_kvm_inj_virq(irq);
2823
2824 ++vcpu->stat.irq_injections;
2825 if (vmx->rmode.vm86_active) {
2826 vmx->rmode.irq.pending = true;
2827 vmx->rmode.irq.vector = irq;
2828 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2829 if (vcpu->arch.interrupt.soft)
2830 vmx->rmode.irq.rip +=
2831 vmx->vcpu.arch.event_exit_inst_len;
2832 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2833 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2834 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2835 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2836 return;
2837 }
2838 intr = irq | INTR_INFO_VALID_MASK;
2839 if (vcpu->arch.interrupt.soft) {
2840 intr |= INTR_TYPE_SOFT_INTR;
2841 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2842 vmx->vcpu.arch.event_exit_inst_len);
2843 } else
2844 intr |= INTR_TYPE_EXT_INTR;
2845 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2846 }
2847
2848 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2849 {
2850 struct vcpu_vmx *vmx = to_vmx(vcpu);
2851
2852 if (!cpu_has_virtual_nmis()) {
2853 /*
2854 * Tracking the NMI-blocked state in software is built upon
2855 * finding the next open IRQ window. This, in turn, depends on
2856 * well-behaving guests: They have to keep IRQs disabled at
2857 * least as long as the NMI handler runs. Otherwise we may
2858 * cause NMI nesting, maybe breaking the guest. But as this is
2859 * highly unlikely, we can live with the residual risk.
2860 */
2861 vmx->soft_vnmi_blocked = 1;
2862 vmx->vnmi_blocked_time = 0;
2863 }
2864
2865 ++vcpu->stat.nmi_injections;
2866 if (vmx->rmode.vm86_active) {
2867 vmx->rmode.irq.pending = true;
2868 vmx->rmode.irq.vector = NMI_VECTOR;
2869 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2870 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2871 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2872 INTR_INFO_VALID_MASK);
2873 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2874 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2875 return;
2876 }
2877 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2878 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2879 }
2880
2881 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2882 {
2883 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2884 return 0;
2885
2886 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2887 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2888 }
2889
2890 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2891 {
2892 if (!cpu_has_virtual_nmis())
2893 return to_vmx(vcpu)->soft_vnmi_blocked;
2894 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2895 }
2896
2897 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2898 {
2899 struct vcpu_vmx *vmx = to_vmx(vcpu);
2900
2901 if (!cpu_has_virtual_nmis()) {
2902 if (vmx->soft_vnmi_blocked != masked) {
2903 vmx->soft_vnmi_blocked = masked;
2904 vmx->vnmi_blocked_time = 0;
2905 }
2906 } else {
2907 if (masked)
2908 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2909 GUEST_INTR_STATE_NMI);
2910 else
2911 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2912 GUEST_INTR_STATE_NMI);
2913 }
2914 }
2915
2916 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2917 {
2918 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2919 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2920 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2921 }
2922
2923 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2924 {
2925 int ret;
2926 struct kvm_userspace_memory_region tss_mem = {
2927 .slot = TSS_PRIVATE_MEMSLOT,
2928 .guest_phys_addr = addr,
2929 .memory_size = PAGE_SIZE * 3,
2930 .flags = 0,
2931 };
2932
2933 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2934 if (ret)
2935 return ret;
2936 kvm->arch.tss_addr = addr;
2937 return 0;
2938 }
2939
2940 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2941 int vec, u32 err_code)
2942 {
2943 /*
2944 * Instruction with address size override prefix opcode 0x67
2945 * Cause the #SS fault with 0 error code in VM86 mode.
2946 */
2947 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2948 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2949 return 1;
2950 /*
2951 * Forward all other exceptions that are valid in real mode.
2952 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2953 * the required debugging infrastructure rework.
2954 */
2955 switch (vec) {
2956 case DB_VECTOR:
2957 if (vcpu->guest_debug &
2958 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2959 return 0;
2960 kvm_queue_exception(vcpu, vec);
2961 return 1;
2962 case BP_VECTOR:
2963 /*
2964 * Update instruction length as we may reinject the exception
2965 * from user space while in guest debugging mode.
2966 */
2967 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2968 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2969 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2970 return 0;
2971 /* fall through */
2972 case DE_VECTOR:
2973 case OF_VECTOR:
2974 case BR_VECTOR:
2975 case UD_VECTOR:
2976 case DF_VECTOR:
2977 case SS_VECTOR:
2978 case GP_VECTOR:
2979 case MF_VECTOR:
2980 kvm_queue_exception(vcpu, vec);
2981 return 1;
2982 }
2983 return 0;
2984 }
2985
2986 /*
2987 * Trigger machine check on the host. We assume all the MSRs are already set up
2988 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2989 * We pass a fake environment to the machine check handler because we want
2990 * the guest to be always treated like user space, no matter what context
2991 * it used internally.
2992 */
2993 static void kvm_machine_check(void)
2994 {
2995 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2996 struct pt_regs regs = {
2997 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2998 .flags = X86_EFLAGS_IF,
2999 };
3000
3001 do_machine_check(&regs, 0);
3002 #endif
3003 }
3004
3005 static int handle_machine_check(struct kvm_vcpu *vcpu)
3006 {
3007 /* already handled by vcpu_run */
3008 return 1;
3009 }
3010
3011 static int handle_exception(struct kvm_vcpu *vcpu)
3012 {
3013 struct vcpu_vmx *vmx = to_vmx(vcpu);
3014 struct kvm_run *kvm_run = vcpu->run;
3015 u32 intr_info, ex_no, error_code;
3016 unsigned long cr2, rip, dr6;
3017 u32 vect_info;
3018 enum emulation_result er;
3019
3020 vect_info = vmx->idt_vectoring_info;
3021 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3022
3023 if (is_machine_check(intr_info))
3024 return handle_machine_check(vcpu);
3025
3026 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3027 !is_page_fault(intr_info)) {
3028 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3029 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3030 vcpu->run->internal.ndata = 2;
3031 vcpu->run->internal.data[0] = vect_info;
3032 vcpu->run->internal.data[1] = intr_info;
3033 return 0;
3034 }
3035
3036 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3037 return 1; /* already handled by vmx_vcpu_run() */
3038
3039 if (is_no_device(intr_info)) {
3040 vmx_fpu_activate(vcpu);
3041 return 1;
3042 }
3043
3044 if (is_invalid_opcode(intr_info)) {
3045 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3046 if (er != EMULATE_DONE)
3047 kvm_queue_exception(vcpu, UD_VECTOR);
3048 return 1;
3049 }
3050
3051 error_code = 0;
3052 rip = kvm_rip_read(vcpu);
3053 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3054 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3055 if (is_page_fault(intr_info)) {
3056 /* EPT won't cause page fault directly */
3057 if (enable_ept)
3058 BUG();
3059 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3060 trace_kvm_page_fault(cr2, error_code);
3061
3062 if (kvm_event_needs_reinjection(vcpu))
3063 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3064 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3065 }
3066
3067 if (vmx->rmode.vm86_active &&
3068 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3069 error_code)) {
3070 if (vcpu->arch.halt_request) {
3071 vcpu->arch.halt_request = 0;
3072 return kvm_emulate_halt(vcpu);
3073 }
3074 return 1;
3075 }
3076
3077 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3078 switch (ex_no) {
3079 case DB_VECTOR:
3080 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3081 if (!(vcpu->guest_debug &
3082 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3083 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3084 kvm_queue_exception(vcpu, DB_VECTOR);
3085 return 1;
3086 }
3087 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3088 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3089 /* fall through */
3090 case BP_VECTOR:
3091 /*
3092 * Update instruction length as we may reinject #BP from
3093 * user space while in guest debugging mode. Reading it for
3094 * #DB as well causes no harm, it is not used in that case.
3095 */
3096 vmx->vcpu.arch.event_exit_inst_len =
3097 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3098 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3099 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3100 kvm_run->debug.arch.exception = ex_no;
3101 break;
3102 default:
3103 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3104 kvm_run->ex.exception = ex_no;
3105 kvm_run->ex.error_code = error_code;
3106 break;
3107 }
3108 return 0;
3109 }
3110
3111 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3112 {
3113 ++vcpu->stat.irq_exits;
3114 return 1;
3115 }
3116
3117 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3118 {
3119 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3120 return 0;
3121 }
3122
3123 static int handle_io(struct kvm_vcpu *vcpu)
3124 {
3125 unsigned long exit_qualification;
3126 int size, in, string;
3127 unsigned port;
3128
3129 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3130 string = (exit_qualification & 16) != 0;
3131 in = (exit_qualification & 8) != 0;
3132
3133 ++vcpu->stat.io_exits;
3134
3135 if (string || in)
3136 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3137
3138 port = exit_qualification >> 16;
3139 size = (exit_qualification & 7) + 1;
3140 skip_emulated_instruction(vcpu);
3141
3142 return kvm_fast_pio_out(vcpu, size, port);
3143 }
3144
3145 static void
3146 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3147 {
3148 /*
3149 * Patch in the VMCALL instruction:
3150 */
3151 hypercall[0] = 0x0f;
3152 hypercall[1] = 0x01;
3153 hypercall[2] = 0xc1;
3154 }
3155
3156 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3157 {
3158 if (err)
3159 kvm_inject_gp(vcpu, 0);
3160 else
3161 skip_emulated_instruction(vcpu);
3162 }
3163
3164 static int handle_cr(struct kvm_vcpu *vcpu)
3165 {
3166 unsigned long exit_qualification, val;
3167 int cr;
3168 int reg;
3169 int err;
3170
3171 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3172 cr = exit_qualification & 15;
3173 reg = (exit_qualification >> 8) & 15;
3174 switch ((exit_qualification >> 4) & 3) {
3175 case 0: /* mov to cr */
3176 val = kvm_register_read(vcpu, reg);
3177 trace_kvm_cr_write(cr, val);
3178 switch (cr) {
3179 case 0:
3180 err = kvm_set_cr0(vcpu, val);
3181 complete_insn_gp(vcpu, err);
3182 return 1;
3183 case 3:
3184 err = kvm_set_cr3(vcpu, val);
3185 complete_insn_gp(vcpu, err);
3186 return 1;
3187 case 4:
3188 err = kvm_set_cr4(vcpu, val);
3189 complete_insn_gp(vcpu, err);
3190 return 1;
3191 case 8: {
3192 u8 cr8_prev = kvm_get_cr8(vcpu);
3193 u8 cr8 = kvm_register_read(vcpu, reg);
3194 kvm_set_cr8(vcpu, cr8);
3195 skip_emulated_instruction(vcpu);
3196 if (irqchip_in_kernel(vcpu->kvm))
3197 return 1;
3198 if (cr8_prev <= cr8)
3199 return 1;
3200 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3201 return 0;
3202 }
3203 };
3204 break;
3205 case 2: /* clts */
3206 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3207 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3208 skip_emulated_instruction(vcpu);
3209 vmx_fpu_activate(vcpu);
3210 return 1;
3211 case 1: /*mov from cr*/
3212 switch (cr) {
3213 case 3:
3214 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3215 trace_kvm_cr_read(cr, vcpu->arch.cr3);
3216 skip_emulated_instruction(vcpu);
3217 return 1;
3218 case 8:
3219 val = kvm_get_cr8(vcpu);
3220 kvm_register_write(vcpu, reg, val);
3221 trace_kvm_cr_read(cr, val);
3222 skip_emulated_instruction(vcpu);
3223 return 1;
3224 }
3225 break;
3226 case 3: /* lmsw */
3227 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3228 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3229 kvm_lmsw(vcpu, val);
3230
3231 skip_emulated_instruction(vcpu);
3232 return 1;
3233 default:
3234 break;
3235 }
3236 vcpu->run->exit_reason = 0;
3237 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3238 (int)(exit_qualification >> 4) & 3, cr);
3239 return 0;
3240 }
3241
3242 static int handle_dr(struct kvm_vcpu *vcpu)
3243 {
3244 unsigned long exit_qualification;
3245 int dr, reg;
3246
3247 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3248 if (!kvm_require_cpl(vcpu, 0))
3249 return 1;
3250 dr = vmcs_readl(GUEST_DR7);
3251 if (dr & DR7_GD) {
3252 /*
3253 * As the vm-exit takes precedence over the debug trap, we
3254 * need to emulate the latter, either for the host or the
3255 * guest debugging itself.
3256 */
3257 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3258 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3259 vcpu->run->debug.arch.dr7 = dr;
3260 vcpu->run->debug.arch.pc =
3261 vmcs_readl(GUEST_CS_BASE) +
3262 vmcs_readl(GUEST_RIP);
3263 vcpu->run->debug.arch.exception = DB_VECTOR;
3264 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3265 return 0;
3266 } else {
3267 vcpu->arch.dr7 &= ~DR7_GD;
3268 vcpu->arch.dr6 |= DR6_BD;
3269 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3270 kvm_queue_exception(vcpu, DB_VECTOR);
3271 return 1;
3272 }
3273 }
3274
3275 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3276 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3277 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3278 if (exit_qualification & TYPE_MOV_FROM_DR) {
3279 unsigned long val;
3280 if (!kvm_get_dr(vcpu, dr, &val))
3281 kvm_register_write(vcpu, reg, val);
3282 } else
3283 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3284 skip_emulated_instruction(vcpu);
3285 return 1;
3286 }
3287
3288 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3289 {
3290 vmcs_writel(GUEST_DR7, val);
3291 }
3292
3293 static int handle_cpuid(struct kvm_vcpu *vcpu)
3294 {
3295 kvm_emulate_cpuid(vcpu);
3296 return 1;
3297 }
3298
3299 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3300 {
3301 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3302 u64 data;
3303
3304 if (vmx_get_msr(vcpu, ecx, &data)) {
3305 trace_kvm_msr_read_ex(ecx);
3306 kvm_inject_gp(vcpu, 0);
3307 return 1;
3308 }
3309
3310 trace_kvm_msr_read(ecx, data);
3311
3312 /* FIXME: handling of bits 32:63 of rax, rdx */
3313 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3314 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3315 skip_emulated_instruction(vcpu);
3316 return 1;
3317 }
3318
3319 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3320 {
3321 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3322 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3323 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3324
3325 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3326 trace_kvm_msr_write_ex(ecx, data);
3327 kvm_inject_gp(vcpu, 0);
3328 return 1;
3329 }
3330
3331 trace_kvm_msr_write(ecx, data);
3332 skip_emulated_instruction(vcpu);
3333 return 1;
3334 }
3335
3336 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3337 {
3338 return 1;
3339 }
3340
3341 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3342 {
3343 u32 cpu_based_vm_exec_control;
3344
3345 /* clear pending irq */
3346 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3347 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3348 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3349
3350 ++vcpu->stat.irq_window_exits;
3351
3352 /*
3353 * If the user space waits to inject interrupts, exit as soon as
3354 * possible
3355 */
3356 if (!irqchip_in_kernel(vcpu->kvm) &&
3357 vcpu->run->request_interrupt_window &&
3358 !kvm_cpu_has_interrupt(vcpu)) {
3359 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3360 return 0;
3361 }
3362 return 1;
3363 }
3364
3365 static int handle_halt(struct kvm_vcpu *vcpu)
3366 {
3367 skip_emulated_instruction(vcpu);
3368 return kvm_emulate_halt(vcpu);
3369 }
3370
3371 static int handle_vmcall(struct kvm_vcpu *vcpu)
3372 {
3373 skip_emulated_instruction(vcpu);
3374 kvm_emulate_hypercall(vcpu);
3375 return 1;
3376 }
3377
3378 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3379 {
3380 kvm_queue_exception(vcpu, UD_VECTOR);
3381 return 1;
3382 }
3383
3384 static int handle_invlpg(struct kvm_vcpu *vcpu)
3385 {
3386 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3387
3388 kvm_mmu_invlpg(vcpu, exit_qualification);
3389 skip_emulated_instruction(vcpu);
3390 return 1;
3391 }
3392
3393 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3394 {
3395 skip_emulated_instruction(vcpu);
3396 kvm_emulate_wbinvd(vcpu);
3397 return 1;
3398 }
3399
3400 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3401 {
3402 u64 new_bv = kvm_read_edx_eax(vcpu);
3403 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3404
3405 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3406 skip_emulated_instruction(vcpu);
3407 return 1;
3408 }
3409
3410 static int handle_apic_access(struct kvm_vcpu *vcpu)
3411 {
3412 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3413 }
3414
3415 static int handle_task_switch(struct kvm_vcpu *vcpu)
3416 {
3417 struct vcpu_vmx *vmx = to_vmx(vcpu);
3418 unsigned long exit_qualification;
3419 bool has_error_code = false;
3420 u32 error_code = 0;
3421 u16 tss_selector;
3422 int reason, type, idt_v;
3423
3424 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3425 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3426
3427 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3428
3429 reason = (u32)exit_qualification >> 30;
3430 if (reason == TASK_SWITCH_GATE && idt_v) {
3431 switch (type) {
3432 case INTR_TYPE_NMI_INTR:
3433 vcpu->arch.nmi_injected = false;
3434 if (cpu_has_virtual_nmis())
3435 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3436 GUEST_INTR_STATE_NMI);
3437 break;
3438 case INTR_TYPE_EXT_INTR:
3439 case INTR_TYPE_SOFT_INTR:
3440 kvm_clear_interrupt_queue(vcpu);
3441 break;
3442 case INTR_TYPE_HARD_EXCEPTION:
3443 if (vmx->idt_vectoring_info &
3444 VECTORING_INFO_DELIVER_CODE_MASK) {
3445 has_error_code = true;
3446 error_code =
3447 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3448 }
3449 /* fall through */
3450 case INTR_TYPE_SOFT_EXCEPTION:
3451 kvm_clear_exception_queue(vcpu);
3452 break;
3453 default:
3454 break;
3455 }
3456 }
3457 tss_selector = exit_qualification;
3458
3459 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3460 type != INTR_TYPE_EXT_INTR &&
3461 type != INTR_TYPE_NMI_INTR))
3462 skip_emulated_instruction(vcpu);
3463
3464 if (kvm_task_switch(vcpu, tss_selector, reason,
3465 has_error_code, error_code) == EMULATE_FAIL) {
3466 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3467 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3468 vcpu->run->internal.ndata = 0;
3469 return 0;
3470 }
3471
3472 /* clear all local breakpoint enable flags */
3473 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3474
3475 /*
3476 * TODO: What about debug traps on tss switch?
3477 * Are we supposed to inject them and update dr6?
3478 */
3479
3480 return 1;
3481 }
3482
3483 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3484 {
3485 unsigned long exit_qualification;
3486 gpa_t gpa;
3487 int gla_validity;
3488
3489 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3490
3491 if (exit_qualification & (1 << 6)) {
3492 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3493 return -EINVAL;
3494 }
3495
3496 gla_validity = (exit_qualification >> 7) & 0x3;
3497 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3498 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3499 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3500 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3501 vmcs_readl(GUEST_LINEAR_ADDRESS));
3502 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3503 (long unsigned int)exit_qualification);
3504 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3505 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3506 return 0;
3507 }
3508
3509 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3510 trace_kvm_page_fault(gpa, exit_qualification);
3511 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3512 }
3513
3514 static u64 ept_rsvd_mask(u64 spte, int level)
3515 {
3516 int i;
3517 u64 mask = 0;
3518
3519 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3520 mask |= (1ULL << i);
3521
3522 if (level > 2)
3523 /* bits 7:3 reserved */
3524 mask |= 0xf8;
3525 else if (level == 2) {
3526 if (spte & (1ULL << 7))
3527 /* 2MB ref, bits 20:12 reserved */
3528 mask |= 0x1ff000;
3529 else
3530 /* bits 6:3 reserved */
3531 mask |= 0x78;
3532 }
3533
3534 return mask;
3535 }
3536
3537 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3538 int level)
3539 {
3540 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3541
3542 /* 010b (write-only) */
3543 WARN_ON((spte & 0x7) == 0x2);
3544
3545 /* 110b (write/execute) */
3546 WARN_ON((spte & 0x7) == 0x6);
3547
3548 /* 100b (execute-only) and value not supported by logical processor */
3549 if (!cpu_has_vmx_ept_execute_only())
3550 WARN_ON((spte & 0x7) == 0x4);
3551
3552 /* not 000b */
3553 if ((spte & 0x7)) {
3554 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3555
3556 if (rsvd_bits != 0) {
3557 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3558 __func__, rsvd_bits);
3559 WARN_ON(1);
3560 }
3561
3562 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3563 u64 ept_mem_type = (spte & 0x38) >> 3;
3564
3565 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3566 ept_mem_type == 7) {
3567 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3568 __func__, ept_mem_type);
3569 WARN_ON(1);
3570 }
3571 }
3572 }
3573 }
3574
3575 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3576 {
3577 u64 sptes[4];
3578 int nr_sptes, i;
3579 gpa_t gpa;
3580
3581 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3582
3583 printk(KERN_ERR "EPT: Misconfiguration.\n");
3584 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3585
3586 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3587
3588 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3589 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3590
3591 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3592 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3593
3594 return 0;
3595 }
3596
3597 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3598 {
3599 u32 cpu_based_vm_exec_control;
3600
3601 /* clear pending NMI */
3602 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3603 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3604 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3605 ++vcpu->stat.nmi_window_exits;
3606
3607 return 1;
3608 }
3609
3610 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3611 {
3612 struct vcpu_vmx *vmx = to_vmx(vcpu);
3613 enum emulation_result err = EMULATE_DONE;
3614 int ret = 1;
3615
3616 while (!guest_state_valid(vcpu)) {
3617 err = emulate_instruction(vcpu, 0, 0, 0);
3618
3619 if (err == EMULATE_DO_MMIO) {
3620 ret = 0;
3621 goto out;
3622 }
3623
3624 if (err != EMULATE_DONE)
3625 return 0;
3626
3627 if (signal_pending(current))
3628 goto out;
3629 if (need_resched())
3630 schedule();
3631 }
3632
3633 vmx->emulation_required = 0;
3634 out:
3635 return ret;
3636 }
3637
3638 /*
3639 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3640 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3641 */
3642 static int handle_pause(struct kvm_vcpu *vcpu)
3643 {
3644 skip_emulated_instruction(vcpu);
3645 kvm_vcpu_on_spin(vcpu);
3646
3647 return 1;
3648 }
3649
3650 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3651 {
3652 kvm_queue_exception(vcpu, UD_VECTOR);
3653 return 1;
3654 }
3655
3656 /*
3657 * The exit handlers return 1 if the exit was handled fully and guest execution
3658 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3659 * to be done to userspace and return 0.
3660 */
3661 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3662 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3663 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3664 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3665 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3666 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3667 [EXIT_REASON_CR_ACCESS] = handle_cr,
3668 [EXIT_REASON_DR_ACCESS] = handle_dr,
3669 [EXIT_REASON_CPUID] = handle_cpuid,
3670 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3671 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3672 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3673 [EXIT_REASON_HLT] = handle_halt,
3674 [EXIT_REASON_INVLPG] = handle_invlpg,
3675 [EXIT_REASON_VMCALL] = handle_vmcall,
3676 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3677 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3678 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3679 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3680 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3681 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3682 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3683 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3684 [EXIT_REASON_VMON] = handle_vmx_insn,
3685 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3686 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3687 [EXIT_REASON_WBINVD] = handle_wbinvd,
3688 [EXIT_REASON_XSETBV] = handle_xsetbv,
3689 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3690 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3691 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3692 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3693 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3694 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3695 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3696 };
3697
3698 static const int kvm_vmx_max_exit_handlers =
3699 ARRAY_SIZE(kvm_vmx_exit_handlers);
3700
3701 /*
3702 * The guest has exited. See if we can fix it or if we need userspace
3703 * assistance.
3704 */
3705 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3706 {
3707 struct vcpu_vmx *vmx = to_vmx(vcpu);
3708 u32 exit_reason = vmx->exit_reason;
3709 u32 vectoring_info = vmx->idt_vectoring_info;
3710
3711 trace_kvm_exit(exit_reason, vcpu);
3712
3713 /* If guest state is invalid, start emulating */
3714 if (vmx->emulation_required && emulate_invalid_guest_state)
3715 return handle_invalid_guest_state(vcpu);
3716
3717 /* Access CR3 don't cause VMExit in paging mode, so we need
3718 * to sync with guest real CR3. */
3719 if (enable_ept && is_paging(vcpu))
3720 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3721
3722 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3723 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3724 vcpu->run->fail_entry.hardware_entry_failure_reason
3725 = exit_reason;
3726 return 0;
3727 }
3728
3729 if (unlikely(vmx->fail)) {
3730 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3731 vcpu->run->fail_entry.hardware_entry_failure_reason
3732 = vmcs_read32(VM_INSTRUCTION_ERROR);
3733 return 0;
3734 }
3735
3736 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3737 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3738 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3739 exit_reason != EXIT_REASON_TASK_SWITCH))
3740 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3741 "(0x%x) and exit reason is 0x%x\n",
3742 __func__, vectoring_info, exit_reason);
3743
3744 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3745 if (vmx_interrupt_allowed(vcpu)) {
3746 vmx->soft_vnmi_blocked = 0;
3747 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3748 vcpu->arch.nmi_pending) {
3749 /*
3750 * This CPU don't support us in finding the end of an
3751 * NMI-blocked window if the guest runs with IRQs
3752 * disabled. So we pull the trigger after 1 s of
3753 * futile waiting, but inform the user about this.
3754 */
3755 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3756 "state on VCPU %d after 1 s timeout\n",
3757 __func__, vcpu->vcpu_id);
3758 vmx->soft_vnmi_blocked = 0;
3759 }
3760 }
3761
3762 if (exit_reason < kvm_vmx_max_exit_handlers
3763 && kvm_vmx_exit_handlers[exit_reason])
3764 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3765 else {
3766 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3767 vcpu->run->hw.hardware_exit_reason = exit_reason;
3768 }
3769 return 0;
3770 }
3771
3772 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3773 {
3774 if (irr == -1 || tpr < irr) {
3775 vmcs_write32(TPR_THRESHOLD, 0);
3776 return;
3777 }
3778
3779 vmcs_write32(TPR_THRESHOLD, irr);
3780 }
3781
3782 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3783 {
3784 u32 exit_intr_info;
3785 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3786 bool unblock_nmi;
3787 u8 vector;
3788 int type;
3789 bool idtv_info_valid;
3790
3791 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3792
3793 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3794
3795 /* Handle machine checks before interrupts are enabled */
3796 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3797 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3798 && is_machine_check(exit_intr_info)))
3799 kvm_machine_check();
3800
3801 /* We need to handle NMIs before interrupts are enabled */
3802 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3803 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3804 kvm_before_handle_nmi(&vmx->vcpu);
3805 asm("int $2");
3806 kvm_after_handle_nmi(&vmx->vcpu);
3807 }
3808
3809 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3810
3811 if (cpu_has_virtual_nmis()) {
3812 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3813 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3814 /*
3815 * SDM 3: 27.7.1.2 (September 2008)
3816 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3817 * a guest IRET fault.
3818 * SDM 3: 23.2.2 (September 2008)
3819 * Bit 12 is undefined in any of the following cases:
3820 * If the VM exit sets the valid bit in the IDT-vectoring
3821 * information field.
3822 * If the VM exit is due to a double fault.
3823 */
3824 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3825 vector != DF_VECTOR && !idtv_info_valid)
3826 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3827 GUEST_INTR_STATE_NMI);
3828 } else if (unlikely(vmx->soft_vnmi_blocked))
3829 vmx->vnmi_blocked_time +=
3830 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3831
3832 vmx->vcpu.arch.nmi_injected = false;
3833 kvm_clear_exception_queue(&vmx->vcpu);
3834 kvm_clear_interrupt_queue(&vmx->vcpu);
3835
3836 if (!idtv_info_valid)
3837 return;
3838
3839 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3840 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3841
3842 switch (type) {
3843 case INTR_TYPE_NMI_INTR:
3844 vmx->vcpu.arch.nmi_injected = true;
3845 /*
3846 * SDM 3: 27.7.1.2 (September 2008)
3847 * Clear bit "block by NMI" before VM entry if a NMI
3848 * delivery faulted.
3849 */
3850 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3851 GUEST_INTR_STATE_NMI);
3852 break;
3853 case INTR_TYPE_SOFT_EXCEPTION:
3854 vmx->vcpu.arch.event_exit_inst_len =
3855 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3856 /* fall through */
3857 case INTR_TYPE_HARD_EXCEPTION:
3858 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3859 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3860 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3861 } else
3862 kvm_queue_exception(&vmx->vcpu, vector);
3863 break;
3864 case INTR_TYPE_SOFT_INTR:
3865 vmx->vcpu.arch.event_exit_inst_len =
3866 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3867 /* fall through */
3868 case INTR_TYPE_EXT_INTR:
3869 kvm_queue_interrupt(&vmx->vcpu, vector,
3870 type == INTR_TYPE_SOFT_INTR);
3871 break;
3872 default:
3873 break;
3874 }
3875 }
3876
3877 /*
3878 * Failure to inject an interrupt should give us the information
3879 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3880 * when fetching the interrupt redirection bitmap in the real-mode
3881 * tss, this doesn't happen. So we do it ourselves.
3882 */
3883 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3884 {
3885 vmx->rmode.irq.pending = 0;
3886 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3887 return;
3888 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3889 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3890 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3891 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3892 return;
3893 }
3894 vmx->idt_vectoring_info =
3895 VECTORING_INFO_VALID_MASK
3896 | INTR_TYPE_EXT_INTR
3897 | vmx->rmode.irq.vector;
3898 }
3899
3900 #ifdef CONFIG_X86_64
3901 #define R "r"
3902 #define Q "q"
3903 #else
3904 #define R "e"
3905 #define Q "l"
3906 #endif
3907
3908 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3909 {
3910 struct vcpu_vmx *vmx = to_vmx(vcpu);
3911
3912 /* Record the guest's net vcpu time for enforced NMI injections. */
3913 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3914 vmx->entry_time = ktime_get();
3915
3916 /* Don't enter VMX if guest state is invalid, let the exit handler
3917 start emulation until we arrive back to a valid state */
3918 if (vmx->emulation_required && emulate_invalid_guest_state)
3919 return;
3920
3921 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3922 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3923 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3924 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3925
3926 /* When single-stepping over STI and MOV SS, we must clear the
3927 * corresponding interruptibility bits in the guest state. Otherwise
3928 * vmentry fails as it then expects bit 14 (BS) in pending debug
3929 * exceptions being set, but that's not correct for the guest debugging
3930 * case. */
3931 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3932 vmx_set_interrupt_shadow(vcpu, 0);
3933
3934 asm(
3935 /* Store host registers */
3936 "push %%"R"dx; push %%"R"bp;"
3937 "push %%"R"cx \n\t"
3938 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3939 "je 1f \n\t"
3940 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3941 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3942 "1: \n\t"
3943 /* Reload cr2 if changed */
3944 "mov %c[cr2](%0), %%"R"ax \n\t"
3945 "mov %%cr2, %%"R"dx \n\t"
3946 "cmp %%"R"ax, %%"R"dx \n\t"
3947 "je 2f \n\t"
3948 "mov %%"R"ax, %%cr2 \n\t"
3949 "2: \n\t"
3950 /* Check if vmlaunch of vmresume is needed */
3951 "cmpl $0, %c[launched](%0) \n\t"
3952 /* Load guest registers. Don't clobber flags. */
3953 "mov %c[rax](%0), %%"R"ax \n\t"
3954 "mov %c[rbx](%0), %%"R"bx \n\t"
3955 "mov %c[rdx](%0), %%"R"dx \n\t"
3956 "mov %c[rsi](%0), %%"R"si \n\t"
3957 "mov %c[rdi](%0), %%"R"di \n\t"
3958 "mov %c[rbp](%0), %%"R"bp \n\t"
3959 #ifdef CONFIG_X86_64
3960 "mov %c[r8](%0), %%r8 \n\t"
3961 "mov %c[r9](%0), %%r9 \n\t"
3962 "mov %c[r10](%0), %%r10 \n\t"
3963 "mov %c[r11](%0), %%r11 \n\t"
3964 "mov %c[r12](%0), %%r12 \n\t"
3965 "mov %c[r13](%0), %%r13 \n\t"
3966 "mov %c[r14](%0), %%r14 \n\t"
3967 "mov %c[r15](%0), %%r15 \n\t"
3968 #endif
3969 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3970
3971 /* Enter guest mode */
3972 "jne .Llaunched \n\t"
3973 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3974 "jmp .Lkvm_vmx_return \n\t"
3975 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3976 ".Lkvm_vmx_return: "
3977 /* Save guest registers, load host registers, keep flags */
3978 "xchg %0, (%%"R"sp) \n\t"
3979 "mov %%"R"ax, %c[rax](%0) \n\t"
3980 "mov %%"R"bx, %c[rbx](%0) \n\t"
3981 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3982 "mov %%"R"dx, %c[rdx](%0) \n\t"
3983 "mov %%"R"si, %c[rsi](%0) \n\t"
3984 "mov %%"R"di, %c[rdi](%0) \n\t"
3985 "mov %%"R"bp, %c[rbp](%0) \n\t"
3986 #ifdef CONFIG_X86_64
3987 "mov %%r8, %c[r8](%0) \n\t"
3988 "mov %%r9, %c[r9](%0) \n\t"
3989 "mov %%r10, %c[r10](%0) \n\t"
3990 "mov %%r11, %c[r11](%0) \n\t"
3991 "mov %%r12, %c[r12](%0) \n\t"
3992 "mov %%r13, %c[r13](%0) \n\t"
3993 "mov %%r14, %c[r14](%0) \n\t"
3994 "mov %%r15, %c[r15](%0) \n\t"
3995 #endif
3996 "mov %%cr2, %%"R"ax \n\t"
3997 "mov %%"R"ax, %c[cr2](%0) \n\t"
3998
3999 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
4000 "setbe %c[fail](%0) \n\t"
4001 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4002 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4003 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4004 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4005 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4006 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4007 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4008 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4009 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4010 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4011 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4012 #ifdef CONFIG_X86_64
4013 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4014 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4015 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4016 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4017 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4018 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4019 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4020 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4021 #endif
4022 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4023 : "cc", "memory"
4024 , R"bx", R"di", R"si"
4025 #ifdef CONFIG_X86_64
4026 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4027 #endif
4028 );
4029
4030 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4031 | (1 << VCPU_EXREG_PDPTR));
4032 vcpu->arch.regs_dirty = 0;
4033
4034 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4035 if (vmx->rmode.irq.pending)
4036 fixup_rmode_irq(vmx);
4037
4038 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4039 vmx->launched = 1;
4040
4041 vmx_complete_interrupts(vmx);
4042 }
4043
4044 #undef R
4045 #undef Q
4046
4047 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4048 {
4049 struct vcpu_vmx *vmx = to_vmx(vcpu);
4050
4051 if (vmx->vmcs) {
4052 vcpu_clear(vmx);
4053 free_vmcs(vmx->vmcs);
4054 vmx->vmcs = NULL;
4055 }
4056 }
4057
4058 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4059 {
4060 struct vcpu_vmx *vmx = to_vmx(vcpu);
4061
4062 free_vpid(vmx);
4063 vmx_free_vmcs(vcpu);
4064 kfree(vmx->guest_msrs);
4065 kvm_vcpu_uninit(vcpu);
4066 kmem_cache_free(kvm_vcpu_cache, vmx);
4067 }
4068
4069 static inline void vmcs_init(struct vmcs *vmcs)
4070 {
4071 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4072
4073 if (!vmm_exclusive)
4074 kvm_cpu_vmxon(phys_addr);
4075
4076 vmcs_clear(vmcs);
4077
4078 if (!vmm_exclusive)
4079 kvm_cpu_vmxoff();
4080 }
4081
4082 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4083 {
4084 int err;
4085 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4086 int cpu;
4087
4088 if (!vmx)
4089 return ERR_PTR(-ENOMEM);
4090
4091 allocate_vpid(vmx);
4092
4093 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4094 if (err)
4095 goto free_vcpu;
4096
4097 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4098 if (!vmx->guest_msrs) {
4099 err = -ENOMEM;
4100 goto uninit_vcpu;
4101 }
4102
4103 vmx->vmcs = alloc_vmcs();
4104 if (!vmx->vmcs)
4105 goto free_msrs;
4106
4107 vmcs_init(vmx->vmcs);
4108
4109 cpu = get_cpu();
4110 vmx_vcpu_load(&vmx->vcpu, cpu);
4111 err = vmx_vcpu_setup(vmx);
4112 vmx_vcpu_put(&vmx->vcpu);
4113 put_cpu();
4114 if (err)
4115 goto free_vmcs;
4116 if (vm_need_virtualize_apic_accesses(kvm))
4117 if (alloc_apic_access_page(kvm) != 0)
4118 goto free_vmcs;
4119
4120 if (enable_ept) {
4121 if (!kvm->arch.ept_identity_map_addr)
4122 kvm->arch.ept_identity_map_addr =
4123 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4124 if (alloc_identity_pagetable(kvm) != 0)
4125 goto free_vmcs;
4126 }
4127
4128 return &vmx->vcpu;
4129
4130 free_vmcs:
4131 free_vmcs(vmx->vmcs);
4132 free_msrs:
4133 kfree(vmx->guest_msrs);
4134 uninit_vcpu:
4135 kvm_vcpu_uninit(&vmx->vcpu);
4136 free_vcpu:
4137 free_vpid(vmx);
4138 kmem_cache_free(kvm_vcpu_cache, vmx);
4139 return ERR_PTR(err);
4140 }
4141
4142 static void __init vmx_check_processor_compat(void *rtn)
4143 {
4144 struct vmcs_config vmcs_conf;
4145
4146 *(int *)rtn = 0;
4147 if (setup_vmcs_config(&vmcs_conf) < 0)
4148 *(int *)rtn = -EIO;
4149 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4150 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4151 smp_processor_id());
4152 *(int *)rtn = -EIO;
4153 }
4154 }
4155
4156 static int get_ept_level(void)
4157 {
4158 return VMX_EPT_DEFAULT_GAW + 1;
4159 }
4160
4161 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4162 {
4163 u64 ret;
4164
4165 /* For VT-d and EPT combination
4166 * 1. MMIO: always map as UC
4167 * 2. EPT with VT-d:
4168 * a. VT-d without snooping control feature: can't guarantee the
4169 * result, try to trust guest.
4170 * b. VT-d with snooping control feature: snooping control feature of
4171 * VT-d engine can guarantee the cache correctness. Just set it
4172 * to WB to keep consistent with host. So the same as item 3.
4173 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4174 * consistent with host MTRR
4175 */
4176 if (is_mmio)
4177 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4178 else if (vcpu->kvm->arch.iommu_domain &&
4179 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4180 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4181 VMX_EPT_MT_EPTE_SHIFT;
4182 else
4183 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4184 | VMX_EPT_IPAT_BIT;
4185
4186 return ret;
4187 }
4188
4189 #define _ER(x) { EXIT_REASON_##x, #x }
4190
4191 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4192 _ER(EXCEPTION_NMI),
4193 _ER(EXTERNAL_INTERRUPT),
4194 _ER(TRIPLE_FAULT),
4195 _ER(PENDING_INTERRUPT),
4196 _ER(NMI_WINDOW),
4197 _ER(TASK_SWITCH),
4198 _ER(CPUID),
4199 _ER(HLT),
4200 _ER(INVLPG),
4201 _ER(RDPMC),
4202 _ER(RDTSC),
4203 _ER(VMCALL),
4204 _ER(VMCLEAR),
4205 _ER(VMLAUNCH),
4206 _ER(VMPTRLD),
4207 _ER(VMPTRST),
4208 _ER(VMREAD),
4209 _ER(VMRESUME),
4210 _ER(VMWRITE),
4211 _ER(VMOFF),
4212 _ER(VMON),
4213 _ER(CR_ACCESS),
4214 _ER(DR_ACCESS),
4215 _ER(IO_INSTRUCTION),
4216 _ER(MSR_READ),
4217 _ER(MSR_WRITE),
4218 _ER(MWAIT_INSTRUCTION),
4219 _ER(MONITOR_INSTRUCTION),
4220 _ER(PAUSE_INSTRUCTION),
4221 _ER(MCE_DURING_VMENTRY),
4222 _ER(TPR_BELOW_THRESHOLD),
4223 _ER(APIC_ACCESS),
4224 _ER(EPT_VIOLATION),
4225 _ER(EPT_MISCONFIG),
4226 _ER(WBINVD),
4227 { -1, NULL }
4228 };
4229
4230 #undef _ER
4231
4232 static int vmx_get_lpage_level(void)
4233 {
4234 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4235 return PT_DIRECTORY_LEVEL;
4236 else
4237 /* For shadow and EPT supported 1GB page */
4238 return PT_PDPE_LEVEL;
4239 }
4240
4241 static inline u32 bit(int bitno)
4242 {
4243 return 1 << (bitno & 31);
4244 }
4245
4246 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4247 {
4248 struct kvm_cpuid_entry2 *best;
4249 struct vcpu_vmx *vmx = to_vmx(vcpu);
4250 u32 exec_control;
4251
4252 vmx->rdtscp_enabled = false;
4253 if (vmx_rdtscp_supported()) {
4254 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4255 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4256 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4257 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4258 vmx->rdtscp_enabled = true;
4259 else {
4260 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4261 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4262 exec_control);
4263 }
4264 }
4265 }
4266 }
4267
4268 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4269 {
4270 }
4271
4272 static struct kvm_x86_ops vmx_x86_ops = {
4273 .cpu_has_kvm_support = cpu_has_kvm_support,
4274 .disabled_by_bios = vmx_disabled_by_bios,
4275 .hardware_setup = hardware_setup,
4276 .hardware_unsetup = hardware_unsetup,
4277 .check_processor_compatibility = vmx_check_processor_compat,
4278 .hardware_enable = hardware_enable,
4279 .hardware_disable = hardware_disable,
4280 .cpu_has_accelerated_tpr = report_flexpriority,
4281
4282 .vcpu_create = vmx_create_vcpu,
4283 .vcpu_free = vmx_free_vcpu,
4284 .vcpu_reset = vmx_vcpu_reset,
4285
4286 .prepare_guest_switch = vmx_save_host_state,
4287 .vcpu_load = vmx_vcpu_load,
4288 .vcpu_put = vmx_vcpu_put,
4289
4290 .set_guest_debug = set_guest_debug,
4291 .get_msr = vmx_get_msr,
4292 .set_msr = vmx_set_msr,
4293 .get_segment_base = vmx_get_segment_base,
4294 .get_segment = vmx_get_segment,
4295 .set_segment = vmx_set_segment,
4296 .get_cpl = vmx_get_cpl,
4297 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4298 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4299 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4300 .set_cr0 = vmx_set_cr0,
4301 .set_cr3 = vmx_set_cr3,
4302 .set_cr4 = vmx_set_cr4,
4303 .set_efer = vmx_set_efer,
4304 .get_idt = vmx_get_idt,
4305 .set_idt = vmx_set_idt,
4306 .get_gdt = vmx_get_gdt,
4307 .set_gdt = vmx_set_gdt,
4308 .set_dr7 = vmx_set_dr7,
4309 .cache_reg = vmx_cache_reg,
4310 .get_rflags = vmx_get_rflags,
4311 .set_rflags = vmx_set_rflags,
4312 .fpu_activate = vmx_fpu_activate,
4313 .fpu_deactivate = vmx_fpu_deactivate,
4314
4315 .tlb_flush = vmx_flush_tlb,
4316
4317 .run = vmx_vcpu_run,
4318 .handle_exit = vmx_handle_exit,
4319 .skip_emulated_instruction = skip_emulated_instruction,
4320 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4321 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4322 .patch_hypercall = vmx_patch_hypercall,
4323 .set_irq = vmx_inject_irq,
4324 .set_nmi = vmx_inject_nmi,
4325 .queue_exception = vmx_queue_exception,
4326 .interrupt_allowed = vmx_interrupt_allowed,
4327 .nmi_allowed = vmx_nmi_allowed,
4328 .get_nmi_mask = vmx_get_nmi_mask,
4329 .set_nmi_mask = vmx_set_nmi_mask,
4330 .enable_nmi_window = enable_nmi_window,
4331 .enable_irq_window = enable_irq_window,
4332 .update_cr8_intercept = update_cr8_intercept,
4333
4334 .set_tss_addr = vmx_set_tss_addr,
4335 .get_tdp_level = get_ept_level,
4336 .get_mt_mask = vmx_get_mt_mask,
4337
4338 .exit_reasons_str = vmx_exit_reasons_str,
4339 .get_lpage_level = vmx_get_lpage_level,
4340
4341 .cpuid_update = vmx_cpuid_update,
4342
4343 .rdtscp_supported = vmx_rdtscp_supported,
4344
4345 .set_supported_cpuid = vmx_set_supported_cpuid,
4346
4347 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4348
4349 .write_tsc_offset = vmx_write_tsc_offset,
4350 };
4351
4352 static int __init vmx_init(void)
4353 {
4354 int r, i;
4355
4356 rdmsrl_safe(MSR_EFER, &host_efer);
4357
4358 for (i = 0; i < NR_VMX_MSR; ++i)
4359 kvm_define_shared_msr(i, vmx_msr_index[i]);
4360
4361 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4362 if (!vmx_io_bitmap_a)
4363 return -ENOMEM;
4364
4365 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4366 if (!vmx_io_bitmap_b) {
4367 r = -ENOMEM;
4368 goto out;
4369 }
4370
4371 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4372 if (!vmx_msr_bitmap_legacy) {
4373 r = -ENOMEM;
4374 goto out1;
4375 }
4376
4377 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4378 if (!vmx_msr_bitmap_longmode) {
4379 r = -ENOMEM;
4380 goto out2;
4381 }
4382
4383 /*
4384 * Allow direct access to the PC debug port (it is often used for I/O
4385 * delays, but the vmexits simply slow things down).
4386 */
4387 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4388 clear_bit(0x80, vmx_io_bitmap_a);
4389
4390 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4391
4392 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4393 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4394
4395 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4396
4397 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4398 __alignof__(struct vcpu_vmx), THIS_MODULE);
4399 if (r)
4400 goto out3;
4401
4402 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4403 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4404 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4405 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4406 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4407 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4408
4409 if (enable_ept) {
4410 bypass_guest_pf = 0;
4411 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4412 VMX_EPT_WRITABLE_MASK);
4413 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4414 VMX_EPT_EXECUTABLE_MASK);
4415 kvm_enable_tdp();
4416 } else
4417 kvm_disable_tdp();
4418
4419 if (bypass_guest_pf)
4420 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4421
4422 return 0;
4423
4424 out3:
4425 free_page((unsigned long)vmx_msr_bitmap_longmode);
4426 out2:
4427 free_page((unsigned long)vmx_msr_bitmap_legacy);
4428 out1:
4429 free_page((unsigned long)vmx_io_bitmap_b);
4430 out:
4431 free_page((unsigned long)vmx_io_bitmap_a);
4432 return r;
4433 }
4434
4435 static void __exit vmx_exit(void)
4436 {
4437 free_page((unsigned long)vmx_msr_bitmap_legacy);
4438 free_page((unsigned long)vmx_msr_bitmap_longmode);
4439 free_page((unsigned long)vmx_io_bitmap_b);
4440 free_page((unsigned long)vmx_io_bitmap_a);
4441
4442 kvm_exit();
4443 }
4444
4445 module_init(vmx_init)
4446 module_exit(vmx_exit)
kernel source for telekom puls (alcatel/mediatek)