2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/module.h>
47 #include <linux/sched.h>
48 #include <linux/percpu.h>
49 #include <linux/bootmem.h>
50 #include <linux/err.h>
51 #include <linux/nmi.h>
52 #include <linux/tboot.h>
53 #include <linux/stackprotector.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
62 #include <asm/realmode.h>
65 #include <asm/pgtable.h>
66 #include <asm/tlbflush.h>
68 #include <asm/mwait.h>
70 #include <asm/io_apic.h>
72 #include <asm/fpu-internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
77 #include <asm/smpboot_hooks.h>
78 #include <asm/i8259.h>
80 #include <asm/realmode.h>
82 /* State of each CPU */
83 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
85 #ifdef CONFIG_HOTPLUG_CPU
87 * We need this for trampoline_base protection from concurrent accesses when
88 * off- and onlining cores wildly.
90 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex
);
92 void cpu_hotplug_driver_lock(void)
94 mutex_lock(&x86_cpu_hotplug_driver_mutex
);
97 void cpu_hotplug_driver_unlock(void)
99 mutex_unlock(&x86_cpu_hotplug_driver_mutex
);
102 ssize_t
arch_cpu_probe(const char *buf
, size_t count
) { return -1; }
103 ssize_t
arch_cpu_release(const char *buf
, size_t count
) { return -1; }
106 /* Number of siblings per CPU package */
107 int smp_num_siblings
= 1;
108 EXPORT_SYMBOL(smp_num_siblings
);
110 /* Last level cache ID of each logical CPU */
111 DEFINE_PER_CPU_READ_MOSTLY(u16
, cpu_llc_id
) = BAD_APICID
;
113 /* representing HT siblings of each logical CPU */
114 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_sibling_map
);
115 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map
);
117 /* representing HT and core siblings of each logical CPU */
118 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_core_map
);
119 EXPORT_PER_CPU_SYMBOL(cpu_core_map
);
121 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t
, cpu_llc_shared_map
);
123 /* Per CPU bogomips and other parameters */
124 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86
, cpu_info
);
125 EXPORT_PER_CPU_SYMBOL(cpu_info
);
127 atomic_t init_deasserted
;
130 * Report back to the Boot Processor during boot time or to the caller processor
133 static void __cpuinit
smp_callin(void)
136 unsigned long timeout
;
139 * If waken up by an INIT in an 82489DX configuration
140 * we may get here before an INIT-deassert IPI reaches
141 * our local APIC. We have to wait for the IPI or we'll
142 * lock up on an APIC access.
144 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
146 cpuid
= smp_processor_id();
147 if (apic
->wait_for_init_deassert
&& cpuid
!= 0)
148 apic
->wait_for_init_deassert(&init_deasserted
);
151 * (This works even if the APIC is not enabled.)
153 phys_id
= read_apic_id();
154 if (cpumask_test_cpu(cpuid
, cpu_callin_mask
)) {
155 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__
,
158 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
161 * STARTUP IPIs are fragile beasts as they might sometimes
162 * trigger some glue motherboard logic. Complete APIC bus
163 * silence for 1 second, this overestimates the time the
164 * boot CPU is spending to send the up to 2 STARTUP IPIs
165 * by a factor of two. This should be enough.
169 * Waiting 2s total for startup (udelay is not yet working)
171 timeout
= jiffies
+ 2*HZ
;
172 while (time_before(jiffies
, timeout
)) {
174 * Has the boot CPU finished it's STARTUP sequence?
176 if (cpumask_test_cpu(cpuid
, cpu_callout_mask
))
181 if (!time_before(jiffies
, timeout
)) {
182 panic("%s: CPU%d started up but did not get a callout!\n",
187 * the boot CPU has finished the init stage and is spinning
188 * on callin_map until we finish. We are free to set up this
189 * CPU, first the APIC. (this is probably redundant on most
193 pr_debug("CALLIN, before setup_local_APIC()\n");
194 if (apic
->smp_callin_clear_local_apic
)
195 apic
->smp_callin_clear_local_apic();
197 end_local_APIC_setup();
200 * Need to setup vector mappings before we enable interrupts.
202 setup_vector_irq(smp_processor_id());
205 * Save our processor parameters. Note: this information
206 * is needed for clock calibration.
208 smp_store_cpu_info(cpuid
);
212 * Update loops_per_jiffy in cpu_data. Previous call to
213 * smp_store_cpu_info() stored a value that is close but not as
214 * accurate as the value just calculated.
217 cpu_data(cpuid
).loops_per_jiffy
= loops_per_jiffy
;
218 pr_debug("Stack at about %p\n", &cpuid
);
221 * This must be done before setting cpu_online_mask
222 * or calling notify_cpu_starting.
224 set_cpu_sibling_map(raw_smp_processor_id());
227 notify_cpu_starting(cpuid
);
230 * Allow the master to continue.
232 cpumask_set_cpu(cpuid
, cpu_callin_mask
);
235 static int cpu0_logical_apicid
;
236 static int enable_start_cpu0
;
238 * Activate a secondary processor.
240 notrace
static void __cpuinit
start_secondary(void *unused
)
243 * Don't put *anything* before cpu_init(), SMP booting is too
244 * fragile that we want to limit the things done here to the
245 * most necessary things.
248 x86_cpuinit
.early_percpu_clock_init();
252 enable_start_cpu0
= 0;
255 /* switch away from the initial page table */
256 load_cr3(swapper_pg_dir
);
260 /* otherwise gcc will move up smp_processor_id before the cpu_init */
263 * Check TSC synchronization with the BP:
265 check_tsc_sync_target();
268 * Enable the espfix hack for this CPU
270 #ifdef CONFIG_X86_ESPFIX64
275 * We need to hold vector_lock so there the set of online cpus
276 * does not change while we are assigning vectors to cpus. Holding
277 * this lock ensures we don't half assign or remove an irq from a cpu.
280 set_cpu_online(smp_processor_id(), true);
281 unlock_vector_lock();
282 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
283 x86_platform
.nmi_init();
285 /* enable local interrupts */
288 /* to prevent fake stack check failure in clock setup */
289 boot_init_stack_canary();
291 x86_cpuinit
.setup_percpu_clockev();
294 cpu_startup_entry(CPUHP_ONLINE
);
297 void __init
smp_store_boot_cpu_info(void)
299 int id
= 0; /* CPU 0 */
300 struct cpuinfo_x86
*c
= &cpu_data(id
);
307 * The bootstrap kernel entry code has set these up. Save them for
310 void __cpuinit
smp_store_cpu_info(int id
)
312 struct cpuinfo_x86
*c
= &cpu_data(id
);
317 * During boot time, CPU0 has this setup already. Save the info when
318 * bringing up AP or offlined CPU0.
320 identify_secondary_cpu(c
);
323 static bool __cpuinit
324 topology_sane(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
, const char *name
)
326 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
328 return !WARN_ONCE(cpu_to_node(cpu1
) != cpu_to_node(cpu2
),
329 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
330 "[node: %d != %d]. Ignoring dependency.\n",
331 cpu1
, name
, cpu2
, cpu_to_node(cpu1
), cpu_to_node(cpu2
));
334 #define link_mask(_m, c1, c2) \
336 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
337 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
340 static bool __cpuinit
match_smt(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
342 if (cpu_has_topoext
) {
343 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
345 if (c
->phys_proc_id
== o
->phys_proc_id
&&
346 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
) &&
347 c
->compute_unit_id
== o
->compute_unit_id
)
348 return topology_sane(c
, o
, "smt");
350 } else if (c
->phys_proc_id
== o
->phys_proc_id
&&
351 c
->cpu_core_id
== o
->cpu_core_id
) {
352 return topology_sane(c
, o
, "smt");
358 static bool __cpuinit
match_llc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
360 int cpu1
= c
->cpu_index
, cpu2
= o
->cpu_index
;
362 if (per_cpu(cpu_llc_id
, cpu1
) != BAD_APICID
&&
363 per_cpu(cpu_llc_id
, cpu1
) == per_cpu(cpu_llc_id
, cpu2
))
364 return topology_sane(c
, o
, "llc");
369 static bool __cpuinit
match_mc(struct cpuinfo_x86
*c
, struct cpuinfo_x86
*o
)
371 if (c
->phys_proc_id
== o
->phys_proc_id
) {
372 if (cpu_has(c
, X86_FEATURE_AMD_DCM
))
375 return topology_sane(c
, o
, "mc");
380 void __cpuinit
set_cpu_sibling_map(int cpu
)
382 bool has_smt
= smp_num_siblings
> 1;
383 bool has_mp
= has_smt
|| boot_cpu_data
.x86_max_cores
> 1;
384 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
385 struct cpuinfo_x86
*o
;
388 cpumask_set_cpu(cpu
, cpu_sibling_setup_mask
);
391 cpumask_set_cpu(cpu
, cpu_sibling_mask(cpu
));
392 cpumask_set_cpu(cpu
, cpu_llc_shared_mask(cpu
));
393 cpumask_set_cpu(cpu
, cpu_core_mask(cpu
));
398 for_each_cpu(i
, cpu_sibling_setup_mask
) {
401 if ((i
== cpu
) || (has_smt
&& match_smt(c
, o
)))
402 link_mask(sibling
, cpu
, i
);
404 if ((i
== cpu
) || (has_mp
&& match_llc(c
, o
)))
405 link_mask(llc_shared
, cpu
, i
);
410 * This needs a separate iteration over the cpus because we rely on all
411 * cpu_sibling_mask links to be set-up.
413 for_each_cpu(i
, cpu_sibling_setup_mask
) {
416 if ((i
== cpu
) || (has_mp
&& match_mc(c
, o
))) {
417 link_mask(core
, cpu
, i
);
420 * Does this new cpu bringup a new core?
422 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1) {
424 * for each core in package, increment
425 * the booted_cores for this new cpu
427 if (cpumask_first(cpu_sibling_mask(i
)) == i
)
430 * increment the core count for all
431 * the other cpus in this package
434 cpu_data(i
).booted_cores
++;
435 } else if (i
!= cpu
&& !c
->booted_cores
)
436 c
->booted_cores
= cpu_data(i
).booted_cores
;
441 /* maps the cpu to the sched domain representing multi-core */
442 const struct cpumask
*cpu_coregroup_mask(int cpu
)
444 return cpu_llc_shared_mask(cpu
);
447 static void impress_friends(void)
450 unsigned long bogosum
= 0;
452 * Allow the user to impress friends.
454 pr_debug("Before bogomips\n");
455 for_each_possible_cpu(cpu
)
456 if (cpumask_test_cpu(cpu
, cpu_callout_mask
))
457 bogosum
+= cpu_data(cpu
).loops_per_jiffy
;
458 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
461 (bogosum
/(5000/HZ
))%100);
463 pr_debug("Before bogocount - setting activated=1\n");
466 void __inquire_remote_apic(int apicid
)
468 unsigned i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
469 const char * const names
[] = { "ID", "VERSION", "SPIV" };
473 pr_info("Inquiring remote APIC 0x%x...\n", apicid
);
475 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
476 pr_info("... APIC 0x%x %s: ", apicid
, names
[i
]);
481 status
= safe_apic_wait_icr_idle();
483 pr_cont("a previous APIC delivery may have failed\n");
485 apic_icr_write(APIC_DM_REMRD
| regs
[i
], apicid
);
490 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
491 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
494 case APIC_ICR_RR_VALID
:
495 status
= apic_read(APIC_RRR
);
496 pr_cont("%08x\n", status
);
505 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
506 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
507 * won't ... remember to clear down the APIC, etc later.
510 wakeup_secondary_cpu_via_nmi(int apicid
, unsigned long start_eip
)
512 unsigned long send_status
, accept_status
= 0;
516 /* Boot on the stack */
517 /* Kick the second */
518 apic_icr_write(APIC_DM_NMI
| apic
->dest_logical
, apicid
);
520 pr_debug("Waiting for send to finish...\n");
521 send_status
= safe_apic_wait_icr_idle();
524 * Give the other CPU some time to accept the IPI.
527 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
528 maxlvt
= lapic_get_maxlvt();
529 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
530 apic_write(APIC_ESR
, 0);
531 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
533 pr_debug("NMI sent\n");
536 pr_err("APIC never delivered???\n");
538 pr_err("APIC delivery error (%lx)\n", accept_status
);
540 return (send_status
| accept_status
);
544 wakeup_secondary_cpu_via_init(int phys_apicid
, unsigned long start_eip
)
546 unsigned long send_status
, accept_status
= 0;
547 int maxlvt
, num_starts
, j
;
549 maxlvt
= lapic_get_maxlvt();
552 * Be paranoid about clearing APIC errors.
554 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
555 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
556 apic_write(APIC_ESR
, 0);
560 pr_debug("Asserting INIT\n");
563 * Turn INIT on target chip
568 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
| APIC_DM_INIT
,
571 pr_debug("Waiting for send to finish...\n");
572 send_status
= safe_apic_wait_icr_idle();
576 pr_debug("Deasserting INIT\n");
580 apic_icr_write(APIC_INT_LEVELTRIG
| APIC_DM_INIT
, phys_apicid
);
582 pr_debug("Waiting for send to finish...\n");
583 send_status
= safe_apic_wait_icr_idle();
586 atomic_set(&init_deasserted
, 1);
589 * Should we send STARTUP IPIs ?
591 * Determine this based on the APIC version.
592 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
594 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
600 * Paravirt / VMI wants a startup IPI hook here to set up the
601 * target processor state.
603 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
607 * Run STARTUP IPI loop.
609 pr_debug("#startup loops: %d\n", num_starts
);
611 for (j
= 1; j
<= num_starts
; j
++) {
612 pr_debug("Sending STARTUP #%d\n", j
);
613 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
614 apic_write(APIC_ESR
, 0);
616 pr_debug("After apic_write\n");
623 /* Boot on the stack */
624 /* Kick the second */
625 apic_icr_write(APIC_DM_STARTUP
| (start_eip
>> 12),
629 * Give the other CPU some time to accept the IPI.
633 pr_debug("Startup point 1\n");
635 pr_debug("Waiting for send to finish...\n");
636 send_status
= safe_apic_wait_icr_idle();
639 * Give the other CPU some time to accept the IPI.
642 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
643 apic_write(APIC_ESR
, 0);
644 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
645 if (send_status
|| accept_status
)
648 pr_debug("After Startup\n");
651 pr_err("APIC never delivered???\n");
653 pr_err("APIC delivery error (%lx)\n", accept_status
);
655 return (send_status
| accept_status
);
658 /* reduce the number of lines printed when booting a large cpu count system */
659 static void __cpuinit
announce_cpu(int cpu
, int apicid
)
661 static int current_node
= -1;
662 int node
= early_cpu_to_node(cpu
);
664 if (system_state
== SYSTEM_BOOTING
) {
665 if (node
!= current_node
) {
666 if (current_node
> (-1))
669 pr_info("Booting Node %3d, Processors ", node
);
671 pr_cont(" #%d%s", cpu
, cpu
== (nr_cpu_ids
- 1) ? " OK\n" : "");
674 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
678 static int wakeup_cpu0_nmi(unsigned int cmd
, struct pt_regs
*regs
)
682 cpu
= smp_processor_id();
683 if (cpu
== 0 && !cpu_online(cpu
) && enable_start_cpu0
)
690 * Wake up AP by INIT, INIT, STARTUP sequence.
692 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
693 * boot-strap code which is not a desired behavior for waking up BSP. To
694 * void the boot-strap code, wake up CPU0 by NMI instead.
696 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
697 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
698 * We'll change this code in the future to wake up hard offlined CPU0 if
699 * real platform and request are available.
702 wakeup_cpu_via_init_nmi(int cpu
, unsigned long start_ip
, int apicid
,
703 int *cpu0_nmi_registered
)
709 * Wake up AP by INIT, INIT, STARTUP sequence.
712 return wakeup_secondary_cpu_via_init(apicid
, start_ip
);
715 * Wake up BSP by nmi.
717 * Register a NMI handler to help wake up CPU0.
719 boot_error
= register_nmi_handler(NMI_LOCAL
,
720 wakeup_cpu0_nmi
, 0, "wake_cpu0");
723 enable_start_cpu0
= 1;
724 *cpu0_nmi_registered
= 1;
725 if (apic
->dest_logical
== APIC_DEST_LOGICAL
)
726 id
= cpu0_logical_apicid
;
729 boot_error
= wakeup_secondary_cpu_via_nmi(id
, start_ip
);
736 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
737 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
738 * Returns zero if CPU booted OK, else error code from
739 * ->wakeup_secondary_cpu.
741 static int __cpuinit
do_boot_cpu(int apicid
, int cpu
, struct task_struct
*idle
)
743 volatile u32
*trampoline_status
=
744 (volatile u32
*) __va(real_mode_header
->trampoline_status
);
745 /* start_ip had better be page-aligned! */
746 unsigned long start_ip
= real_mode_header
->trampoline_start
;
748 unsigned long boot_error
= 0;
750 int cpu0_nmi_registered
= 0;
752 /* Just in case we booted with a single CPU. */
753 alternatives_enable_smp();
755 idle
->thread
.sp
= (unsigned long) (((struct pt_regs
*)
756 (THREAD_SIZE
+ task_stack_page(idle
))) - 1);
757 per_cpu(current_task
, cpu
) = idle
;
760 /* Stack for startup_32 can be just as for start_secondary onwards */
763 clear_tsk_thread_flag(idle
, TIF_FORK
);
764 initial_gs
= per_cpu_offset(cpu
);
765 per_cpu(kernel_stack
, cpu
) =
766 (unsigned long)task_stack_page(idle
) -
767 KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
769 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
770 initial_code
= (unsigned long)start_secondary
;
771 stack_start
= idle
->thread
.sp
;
773 /* So we see what's up */
774 announce_cpu(cpu
, apicid
);
777 * This grunge runs the startup process for
778 * the targeted processor.
781 atomic_set(&init_deasserted
, 0);
783 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
785 pr_debug("Setting warm reset code and vector.\n");
787 smpboot_setup_warm_reset_vector(start_ip
);
789 * Be paranoid about clearing APIC errors.
791 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
792 apic_write(APIC_ESR
, 0);
798 * Wake up a CPU in difference cases:
799 * - Use the method in the APIC driver if it's defined
801 * - Use an INIT boot APIC message for APs or NMI for BSP.
803 if (apic
->wakeup_secondary_cpu
)
804 boot_error
= apic
->wakeup_secondary_cpu(apicid
, start_ip
);
806 boot_error
= wakeup_cpu_via_init_nmi(cpu
, start_ip
, apicid
,
807 &cpu0_nmi_registered
);
811 * allow APs to start initializing.
813 pr_debug("Before Callout %d\n", cpu
);
814 cpumask_set_cpu(cpu
, cpu_callout_mask
);
815 pr_debug("After Callout %d\n", cpu
);
818 * Wait 5s total for a response
820 for (timeout
= 0; timeout
< 50000; timeout
++) {
821 if (cpumask_test_cpu(cpu
, cpu_callin_mask
))
822 break; /* It has booted */
825 * Allow other tasks to run while we wait for the
826 * AP to come online. This also gives a chance
827 * for the MTRR work(triggered by the AP coming online)
828 * to be completed in the stop machine context.
833 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
834 print_cpu_msr(&cpu_data(cpu
));
835 pr_debug("CPU%d: has booted.\n", cpu
);
838 if (*trampoline_status
== 0xA5A5A5A5)
839 /* trampoline started but...? */
840 pr_err("CPU%d: Stuck ??\n", cpu
);
842 /* trampoline code not run */
843 pr_err("CPU%d: Not responding\n", cpu
);
844 if (apic
->inquire_remote_apic
)
845 apic
->inquire_remote_apic(apicid
);
850 /* Try to put things back the way they were before ... */
851 numa_remove_cpu(cpu
); /* was set by numa_add_cpu */
853 /* was set by do_boot_cpu() */
854 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
856 /* was set by cpu_init() */
857 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
859 set_cpu_present(cpu
, false);
860 per_cpu(x86_cpu_to_apicid
, cpu
) = BAD_APICID
;
863 /* mark "stuck" area as not stuck */
864 *trampoline_status
= 0;
866 if (get_uv_system_type() != UV_NON_UNIQUE_APIC
) {
868 * Cleanup possible dangling ends...
870 smpboot_restore_warm_reset_vector();
873 * Clean up the nmi handler. Do this after the callin and callout sync
874 * to avoid impact of possible long unregister time.
876 if (cpu0_nmi_registered
)
877 unregister_nmi_handler(NMI_LOCAL
, "wake_cpu0");
882 int __cpuinit
native_cpu_up(unsigned int cpu
, struct task_struct
*tidle
)
884 int apicid
= apic
->cpu_present_to_apicid(cpu
);
888 WARN_ON(irqs_disabled());
890 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu
);
892 if (apicid
== BAD_APICID
||
893 !physid_isset(apicid
, phys_cpu_present_map
) ||
894 !apic
->apic_id_valid(apicid
)) {
895 pr_err("%s: bad cpu %d\n", __func__
, cpu
);
900 * Already booted CPU?
902 if (cpumask_test_cpu(cpu
, cpu_callin_mask
)) {
903 pr_debug("do_boot_cpu %d Already started\n", cpu
);
908 * Save current MTRR state in case it was changed since early boot
909 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
913 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
915 /* the FPU context is blank, nobody can own it */
916 __cpu_disable_lazy_restore(cpu
);
918 err
= do_boot_cpu(apicid
, cpu
, tidle
);
920 pr_debug("do_boot_cpu failed %d\n", err
);
925 * Check TSC synchronization with the AP (keep irqs disabled
928 local_irq_save(flags
);
929 check_tsc_sync_source(cpu
);
930 local_irq_restore(flags
);
932 while (!cpu_online(cpu
)) {
934 touch_nmi_watchdog();
941 * arch_disable_smp_support() - disables SMP support for x86 at runtime
943 void arch_disable_smp_support(void)
945 disable_ioapic_support();
949 * Fall back to non SMP mode after errors.
951 * RED-PEN audit/test this more. I bet there is more state messed up here.
953 static __init
void disable_smp(void)
955 init_cpu_present(cpumask_of(0));
956 init_cpu_possible(cpumask_of(0));
957 smpboot_clear_io_apic_irqs();
959 if (smp_found_config
)
960 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
962 physid_set_mask_of_physid(0, &phys_cpu_present_map
);
963 cpumask_set_cpu(0, cpu_sibling_mask(0));
964 cpumask_set_cpu(0, cpu_core_mask(0));
968 * Various sanity checks.
970 static int __init
smp_sanity_check(unsigned max_cpus
)
974 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
975 if (def_to_bigsmp
&& nr_cpu_ids
> 8) {
979 pr_warn("More than 8 CPUs detected - skipping them\n"
980 "Use CONFIG_X86_BIGSMP\n");
983 for_each_present_cpu(cpu
) {
985 set_cpu_present(cpu
, false);
990 for_each_possible_cpu(cpu
) {
992 set_cpu_possible(cpu
, false);
1000 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map
)) {
1001 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1002 hard_smp_processor_id());
1004 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1008 * If we couldn't find an SMP configuration at boot time,
1009 * get out of here now!
1011 if (!smp_found_config
&& !acpi_lapic
) {
1013 pr_notice("SMP motherboard not detected\n");
1015 if (APIC_init_uniprocessor())
1016 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1021 * Should not be necessary because the MP table should list the boot
1022 * CPU too, but we do it for the sake of robustness anyway.
1024 if (!apic
->check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1025 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1026 boot_cpu_physical_apicid
);
1027 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1032 * If we couldn't find a local APIC, then get out of here now!
1034 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) &&
1036 if (!disable_apic
) {
1037 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1038 boot_cpu_physical_apicid
);
1039 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1041 smpboot_clear_io_apic();
1042 disable_ioapic_support();
1046 verify_local_APIC();
1049 * If SMP should be disabled, then really disable it!
1052 pr_info("SMP mode deactivated\n");
1053 smpboot_clear_io_apic();
1057 bsp_end_local_APIC_setup();
1064 static void __init
smp_cpu_index_default(void)
1067 struct cpuinfo_x86
*c
;
1069 for_each_possible_cpu(i
) {
1071 /* mark all to hotplug */
1072 c
->cpu_index
= nr_cpu_ids
;
1077 * Prepare for SMP bootup. The MP table or ACPI has been read
1078 * earlier. Just do some sanity checking here and enable APIC mode.
1080 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1085 smp_cpu_index_default();
1088 * Setup boot CPU information
1090 smp_store_boot_cpu_info(); /* Final full version of the data */
1091 cpumask_copy(cpu_callin_mask
, cpumask_of(0));
1094 current_thread_info()->cpu
= 0; /* needed? */
1095 for_each_possible_cpu(i
) {
1096 zalloc_cpumask_var(&per_cpu(cpu_sibling_map
, i
), GFP_KERNEL
);
1097 zalloc_cpumask_var(&per_cpu(cpu_core_map
, i
), GFP_KERNEL
);
1098 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map
, i
), GFP_KERNEL
);
1100 set_cpu_sibling_map(0);
1103 if (smp_sanity_check(max_cpus
) < 0) {
1104 pr_info("SMP disabled\n");
1109 default_setup_apic_routing();
1112 if (read_apic_id() != boot_cpu_physical_apicid
) {
1113 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1114 read_apic_id(), boot_cpu_physical_apicid
);
1115 /* Or can we switch back to PIC here? */
1122 * Switch from PIC to APIC mode.
1127 cpu0_logical_apicid
= apic_read(APIC_LDR
);
1129 cpu0_logical_apicid
= GET_APIC_LOGICAL_ID(apic_read(APIC_LDR
));
1132 * Enable IO APIC before setting up error vector
1134 if (!skip_ioapic_setup
&& nr_ioapics
)
1137 bsp_end_local_APIC_setup();
1139 if (apic
->setup_portio_remap
)
1140 apic
->setup_portio_remap();
1142 smpboot_setup_io_apic();
1144 * Set up local APIC timer on boot CPU.
1147 pr_info("CPU%d: ", 0);
1148 print_cpu_info(&cpu_data(0));
1149 x86_init
.timers
.setup_percpu_clockev();
1154 set_mtrr_aps_delayed_init();
1159 void arch_enable_nonboot_cpus_begin(void)
1161 set_mtrr_aps_delayed_init();
1164 void arch_enable_nonboot_cpus_end(void)
1170 * Early setup to make printk work.
1172 void __init
native_smp_prepare_boot_cpu(void)
1174 int me
= smp_processor_id();
1175 switch_to_new_gdt(me
);
1176 /* already set me in cpu_online_mask in boot_cpu_init() */
1177 cpumask_set_cpu(me
, cpu_callout_mask
);
1178 per_cpu(cpu_state
, me
) = CPU_ONLINE
;
1181 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1183 pr_debug("Boot done\n");
1187 #ifdef CONFIG_X86_IO_APIC
1188 setup_ioapic_dest();
1193 static int __initdata setup_possible_cpus
= -1;
1194 static int __init
_setup_possible_cpus(char *str
)
1196 get_option(&str
, &setup_possible_cpus
);
1199 early_param("possible_cpus", _setup_possible_cpus
);
1203 * cpu_possible_mask should be static, it cannot change as cpu's
1204 * are onlined, or offlined. The reason is per-cpu data-structures
1205 * are allocated by some modules at init time, and dont expect to
1206 * do this dynamically on cpu arrival/departure.
1207 * cpu_present_mask on the other hand can change dynamically.
1208 * In case when cpu_hotplug is not compiled, then we resort to current
1209 * behaviour, which is cpu_possible == cpu_present.
1212 * Three ways to find out the number of additional hotplug CPUs:
1213 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1214 * - The user can overwrite it with possible_cpus=NUM
1215 * - Otherwise don't reserve additional CPUs.
1216 * We do this because additional CPUs waste a lot of memory.
1219 __init
void prefill_possible_map(void)
1223 /* no processor from mptable or madt */
1224 if (!num_processors
)
1227 i
= setup_max_cpus
?: 1;
1228 if (setup_possible_cpus
== -1) {
1229 possible
= num_processors
;
1230 #ifdef CONFIG_HOTPLUG_CPU
1232 possible
+= disabled_cpus
;
1238 possible
= setup_possible_cpus
;
1240 total_cpus
= max_t(int, possible
, num_processors
+ disabled_cpus
);
1242 /* nr_cpu_ids could be reduced via nr_cpus= */
1243 if (possible
> nr_cpu_ids
) {
1244 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1245 possible
, nr_cpu_ids
);
1246 possible
= nr_cpu_ids
;
1249 #ifdef CONFIG_HOTPLUG_CPU
1250 if (!setup_max_cpus
)
1253 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1254 possible
, setup_max_cpus
);
1258 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1259 possible
, max_t(int, possible
- num_processors
, 0));
1261 for (i
= 0; i
< possible
; i
++)
1262 set_cpu_possible(i
, true);
1263 for (; i
< NR_CPUS
; i
++)
1264 set_cpu_possible(i
, false);
1266 nr_cpu_ids
= possible
;
1269 #ifdef CONFIG_HOTPLUG_CPU
1271 static void remove_siblinginfo(int cpu
)
1274 struct cpuinfo_x86
*c
= &cpu_data(cpu
);
1276 for_each_cpu(sibling
, cpu_core_mask(cpu
)) {
1277 cpumask_clear_cpu(cpu
, cpu_core_mask(sibling
));
1279 * last thread sibling in this cpu core going down
1281 if (cpumask_weight(cpu_sibling_mask(cpu
)) == 1)
1282 cpu_data(sibling
).booted_cores
--;
1285 for_each_cpu(sibling
, cpu_sibling_mask(cpu
))
1286 cpumask_clear_cpu(cpu
, cpu_sibling_mask(sibling
));
1287 for_each_cpu(sibling
, cpu_llc_shared_mask(cpu
))
1288 cpumask_clear_cpu(cpu
, cpu_llc_shared_mask(sibling
));
1289 cpumask_clear(cpu_llc_shared_mask(cpu
));
1290 cpumask_clear(cpu_sibling_mask(cpu
));
1291 cpumask_clear(cpu_core_mask(cpu
));
1292 c
->phys_proc_id
= 0;
1294 cpumask_clear_cpu(cpu
, cpu_sibling_setup_mask
);
1297 static void __ref
remove_cpu_from_maps(int cpu
)
1299 set_cpu_online(cpu
, false);
1300 cpumask_clear_cpu(cpu
, cpu_callout_mask
);
1301 cpumask_clear_cpu(cpu
, cpu_callin_mask
);
1302 /* was set by cpu_init() */
1303 cpumask_clear_cpu(cpu
, cpu_initialized_mask
);
1304 numa_remove_cpu(cpu
);
1307 void cpu_disable_common(void)
1309 int cpu
= smp_processor_id();
1311 remove_siblinginfo(cpu
);
1313 /* It's now safe to remove this processor from the online map */
1315 remove_cpu_from_maps(cpu
);
1316 unlock_vector_lock();
1320 int native_cpu_disable(void)
1324 cpu_disable_common();
1328 void native_cpu_die(unsigned int cpu
)
1330 /* We don't do anything here: idle task is faking death itself. */
1333 for (i
= 0; i
< 10; i
++) {
1334 /* They ack this in play_dead by setting CPU_DEAD */
1335 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1336 if (system_state
== SYSTEM_RUNNING
)
1337 pr_info("CPU %u is now offline\n", cpu
);
1342 pr_err("CPU %u didn't die...\n", cpu
);
1345 void play_dead_common(void)
1348 reset_lazy_tlbstate();
1349 amd_e400_remove_cpu(raw_smp_processor_id());
1353 __this_cpu_write(cpu_state
, CPU_DEAD
);
1356 * With physical CPU hotplug, we should halt the cpu
1358 local_irq_disable();
1361 static bool wakeup_cpu0(void)
1363 if (smp_processor_id() == 0 && enable_start_cpu0
)
1370 * We need to flush the caches before going to sleep, lest we have
1371 * dirty data in our caches when we come back up.
1373 static inline void mwait_play_dead(void)
1375 unsigned int eax
, ebx
, ecx
, edx
;
1376 unsigned int highest_cstate
= 0;
1377 unsigned int highest_subcstate
= 0;
1381 if (!this_cpu_has(X86_FEATURE_MWAIT
))
1383 if (!this_cpu_has(X86_FEATURE_CLFLSH
))
1385 if (__this_cpu_read(cpu_info
.cpuid_level
) < CPUID_MWAIT_LEAF
)
1388 eax
= CPUID_MWAIT_LEAF
;
1390 native_cpuid(&eax
, &ebx
, &ecx
, &edx
);
1393 * eax will be 0 if EDX enumeration is not valid.
1394 * Initialized below to cstate, sub_cstate value when EDX is valid.
1396 if (!(ecx
& CPUID5_ECX_EXTENSIONS_SUPPORTED
)) {
1399 edx
>>= MWAIT_SUBSTATE_SIZE
;
1400 for (i
= 0; i
< 7 && edx
; i
++, edx
>>= MWAIT_SUBSTATE_SIZE
) {
1401 if (edx
& MWAIT_SUBSTATE_MASK
) {
1403 highest_subcstate
= edx
& MWAIT_SUBSTATE_MASK
;
1406 eax
= (highest_cstate
<< MWAIT_SUBSTATE_SIZE
) |
1407 (highest_subcstate
- 1);
1411 * This should be a memory location in a cache line which is
1412 * unlikely to be touched by other processors. The actual
1413 * content is immaterial as it is not actually modified in any way.
1415 mwait_ptr
= ¤t_thread_info()->flags
;
1421 * The CLFLUSH is a workaround for erratum AAI65 for
1422 * the Xeon 7400 series. It's not clear it is actually
1423 * needed, but it should be harmless in either case.
1424 * The WBINVD is insufficient due to the spurious-wakeup
1425 * case where we return around the loop.
1428 __monitor(mwait_ptr
, 0, 0);
1432 * If NMI wants to wake up CPU0, start CPU0.
1439 static inline void hlt_play_dead(void)
1441 if (__this_cpu_read(cpu_info
.x86
) >= 4)
1447 * If NMI wants to wake up CPU0, start CPU0.
1454 void native_play_dead(void)
1457 tboot_shutdown(TB_SHUTDOWN_WFS
);
1459 mwait_play_dead(); /* Only returns on failure */
1460 if (cpuidle_play_dead())
1464 #else /* ... !CONFIG_HOTPLUG_CPU */
1465 int native_cpu_disable(void)
1470 void native_cpu_die(unsigned int cpu
)
1472 /* We said "no" in __cpu_disable */
1476 void native_play_dead(void)