1 #include <linux/bitops.h>
2 #include <linux/types.h>
3 #include <linux/slab.h>
5 #include <asm/perf_event.h>
8 #include "perf_event.h"
10 /* The size of a BTS record in bytes: */
11 #define BTS_RECORD_SIZE 24
13 #define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14 #define PEBS_BUFFER_SIZE PAGE_SIZE
17 * pebs_record_32 for p4 and core not supported
19 struct pebs_record_32 {
27 struct pebs_record_core
{
32 u64 r12
, r13
, r14
, r15
;
35 struct pebs_record_nhm
{
40 u64 r12
, r13
, r14
, r15
;
41 u64 status
, dla
, dse
, lat
;
44 void init_debug_store_on_cpu(int cpu
)
46 struct debug_store
*ds
= per_cpu(cpu_hw_events
, cpu
).ds
;
51 wrmsr_on_cpu(cpu
, MSR_IA32_DS_AREA
,
52 (u32
)((u64
)(unsigned long)ds
),
53 (u32
)((u64
)(unsigned long)ds
>> 32));
56 void fini_debug_store_on_cpu(int cpu
)
58 if (!per_cpu(cpu_hw_events
, cpu
).ds
)
61 wrmsr_on_cpu(cpu
, MSR_IA32_DS_AREA
, 0, 0);
64 static int alloc_pebs_buffer(int cpu
)
66 struct debug_store
*ds
= per_cpu(cpu_hw_events
, cpu
).ds
;
67 int node
= cpu_to_node(cpu
);
68 int max
, thresh
= 1; /* always use a single PEBS record */
74 buffer
= kmalloc_node(PEBS_BUFFER_SIZE
, GFP_KERNEL
| __GFP_ZERO
, node
);
75 if (unlikely(!buffer
))
78 max
= PEBS_BUFFER_SIZE
/ x86_pmu
.pebs_record_size
;
80 ds
->pebs_buffer_base
= (u64
)(unsigned long)buffer
;
81 ds
->pebs_index
= ds
->pebs_buffer_base
;
82 ds
->pebs_absolute_maximum
= ds
->pebs_buffer_base
+
83 max
* x86_pmu
.pebs_record_size
;
85 ds
->pebs_interrupt_threshold
= ds
->pebs_buffer_base
+
86 thresh
* x86_pmu
.pebs_record_size
;
91 static void release_pebs_buffer(int cpu
)
93 struct debug_store
*ds
= per_cpu(cpu_hw_events
, cpu
).ds
;
95 if (!ds
|| !x86_pmu
.pebs
)
98 kfree((void *)(unsigned long)ds
->pebs_buffer_base
);
99 ds
->pebs_buffer_base
= 0;
102 static int alloc_bts_buffer(int cpu
)
104 struct debug_store
*ds
= per_cpu(cpu_hw_events
, cpu
).ds
;
105 int node
= cpu_to_node(cpu
);
112 buffer
= kmalloc_node(BTS_BUFFER_SIZE
, GFP_KERNEL
| __GFP_ZERO
, node
);
113 if (unlikely(!buffer
))
116 max
= BTS_BUFFER_SIZE
/ BTS_RECORD_SIZE
;
119 ds
->bts_buffer_base
= (u64
)(unsigned long)buffer
;
120 ds
->bts_index
= ds
->bts_buffer_base
;
121 ds
->bts_absolute_maximum
= ds
->bts_buffer_base
+
122 max
* BTS_RECORD_SIZE
;
123 ds
->bts_interrupt_threshold
= ds
->bts_absolute_maximum
-
124 thresh
* BTS_RECORD_SIZE
;
129 static void release_bts_buffer(int cpu
)
131 struct debug_store
*ds
= per_cpu(cpu_hw_events
, cpu
).ds
;
133 if (!ds
|| !x86_pmu
.bts
)
136 kfree((void *)(unsigned long)ds
->bts_buffer_base
);
137 ds
->bts_buffer_base
= 0;
140 static int alloc_ds_buffer(int cpu
)
142 int node
= cpu_to_node(cpu
);
143 struct debug_store
*ds
;
145 ds
= kmalloc_node(sizeof(*ds
), GFP_KERNEL
| __GFP_ZERO
, node
);
149 per_cpu(cpu_hw_events
, cpu
).ds
= ds
;
154 static void release_ds_buffer(int cpu
)
156 struct debug_store
*ds
= per_cpu(cpu_hw_events
, cpu
).ds
;
161 per_cpu(cpu_hw_events
, cpu
).ds
= NULL
;
165 void release_ds_buffers(void)
169 if (!x86_pmu
.bts
&& !x86_pmu
.pebs
)
173 for_each_online_cpu(cpu
)
174 fini_debug_store_on_cpu(cpu
);
176 for_each_possible_cpu(cpu
) {
177 release_pebs_buffer(cpu
);
178 release_bts_buffer(cpu
);
179 release_ds_buffer(cpu
);
184 void reserve_ds_buffers(void)
186 int bts_err
= 0, pebs_err
= 0;
189 x86_pmu
.bts_active
= 0;
190 x86_pmu
.pebs_active
= 0;
192 if (!x86_pmu
.bts
&& !x86_pmu
.pebs
)
203 for_each_possible_cpu(cpu
) {
204 if (alloc_ds_buffer(cpu
)) {
209 if (!bts_err
&& alloc_bts_buffer(cpu
))
212 if (!pebs_err
&& alloc_pebs_buffer(cpu
))
215 if (bts_err
&& pebs_err
)
220 for_each_possible_cpu(cpu
)
221 release_bts_buffer(cpu
);
225 for_each_possible_cpu(cpu
)
226 release_pebs_buffer(cpu
);
229 if (bts_err
&& pebs_err
) {
230 for_each_possible_cpu(cpu
)
231 release_ds_buffer(cpu
);
233 if (x86_pmu
.bts
&& !bts_err
)
234 x86_pmu
.bts_active
= 1;
236 if (x86_pmu
.pebs
&& !pebs_err
)
237 x86_pmu
.pebs_active
= 1;
239 for_each_online_cpu(cpu
)
240 init_debug_store_on_cpu(cpu
);
250 struct event_constraint bts_constraint
=
251 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS
, 0);
253 void intel_pmu_enable_bts(u64 config
)
255 unsigned long debugctlmsr
;
257 debugctlmsr
= get_debugctlmsr();
259 debugctlmsr
|= DEBUGCTLMSR_TR
;
260 debugctlmsr
|= DEBUGCTLMSR_BTS
;
261 debugctlmsr
|= DEBUGCTLMSR_BTINT
;
263 if (!(config
& ARCH_PERFMON_EVENTSEL_OS
))
264 debugctlmsr
|= DEBUGCTLMSR_BTS_OFF_OS
;
266 if (!(config
& ARCH_PERFMON_EVENTSEL_USR
))
267 debugctlmsr
|= DEBUGCTLMSR_BTS_OFF_USR
;
269 update_debugctlmsr(debugctlmsr
);
272 void intel_pmu_disable_bts(void)
274 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
275 unsigned long debugctlmsr
;
280 debugctlmsr
= get_debugctlmsr();
283 ~(DEBUGCTLMSR_TR
| DEBUGCTLMSR_BTS
| DEBUGCTLMSR_BTINT
|
284 DEBUGCTLMSR_BTS_OFF_OS
| DEBUGCTLMSR_BTS_OFF_USR
);
286 update_debugctlmsr(debugctlmsr
);
289 int intel_pmu_drain_bts_buffer(void)
291 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
292 struct debug_store
*ds
= cpuc
->ds
;
298 struct perf_event
*event
= cpuc
->events
[INTEL_PMC_IDX_FIXED_BTS
];
299 struct bts_record
*at
, *top
;
300 struct perf_output_handle handle
;
301 struct perf_event_header header
;
302 struct perf_sample_data data
;
308 if (!x86_pmu
.bts_active
)
311 at
= (struct bts_record
*)(unsigned long)ds
->bts_buffer_base
;
312 top
= (struct bts_record
*)(unsigned long)ds
->bts_index
;
317 memset(®s
, 0, sizeof(regs
));
319 ds
->bts_index
= ds
->bts_buffer_base
;
321 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
324 * Prepare a generic sample, i.e. fill in the invariant fields.
325 * We will overwrite the from and to address before we output
328 perf_prepare_sample(&header
, &data
, event
, ®s
);
330 if (perf_output_begin(&handle
, event
, header
.size
* (top
- at
)))
333 for (; at
< top
; at
++) {
337 perf_output_sample(&handle
, &header
, &data
, event
);
340 perf_output_end(&handle
);
342 /* There's new data available. */
343 event
->hw
.interrupts
++;
344 event
->pending_kill
= POLL_IN
;
351 struct event_constraint intel_core2_pebs_event_constraints
[] = {
352 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
353 INTEL_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
354 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
355 INTEL_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
356 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
360 struct event_constraint intel_atom_pebs_event_constraints
[] = {
361 INTEL_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
362 INTEL_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
363 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
367 struct event_constraint intel_nehalem_pebs_event_constraints
[] = {
368 INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
369 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
370 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
371 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
372 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
373 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
374 INTEL_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
375 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
376 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
377 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
378 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
382 struct event_constraint intel_westmere_pebs_event_constraints
[] = {
383 INTEL_EVENT_CONSTRAINT(0x0b, 0xf), /* MEM_INST_RETIRED.* */
384 INTEL_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
385 INTEL_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
386 INTEL_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
387 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
388 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
389 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
390 INTEL_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
391 INTEL_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
392 INTEL_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
393 INTEL_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
397 struct event_constraint intel_snb_pebs_event_constraints
[] = {
398 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
399 INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
400 INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
401 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
402 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
403 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.* */
404 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
405 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
406 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
407 INTEL_UEVENT_CONSTRAINT(0x02d4, 0xf), /* MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS */
411 struct event_constraint intel_ivb_pebs_event_constraints
[] = {
412 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
413 INTEL_UEVENT_CONSTRAINT(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
414 INTEL_UEVENT_CONSTRAINT(0x02c2, 0xf), /* UOPS_RETIRED.RETIRE_SLOTS */
415 INTEL_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
416 INTEL_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
417 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.* */
418 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
419 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
420 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
421 INTEL_EVENT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
425 struct event_constraint
*intel_pebs_constraints(struct perf_event
*event
)
427 struct event_constraint
*c
;
429 if (!event
->attr
.precise_ip
)
432 if (x86_pmu
.pebs_constraints
) {
433 for_each_event_constraint(c
, x86_pmu
.pebs_constraints
) {
434 if ((event
->hw
.config
& c
->cmask
) == c
->code
)
439 return &emptyconstraint
;
442 void intel_pmu_pebs_enable(struct perf_event
*event
)
444 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
445 struct hw_perf_event
*hwc
= &event
->hw
;
447 hwc
->config
&= ~ARCH_PERFMON_EVENTSEL_INT
;
449 cpuc
->pebs_enabled
|= 1ULL << hwc
->idx
;
452 void intel_pmu_pebs_disable(struct perf_event
*event
)
454 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
455 struct hw_perf_event
*hwc
= &event
->hw
;
457 cpuc
->pebs_enabled
&= ~(1ULL << hwc
->idx
);
459 wrmsrl(MSR_IA32_PEBS_ENABLE
, cpuc
->pebs_enabled
);
461 hwc
->config
|= ARCH_PERFMON_EVENTSEL_INT
;
464 void intel_pmu_pebs_enable_all(void)
466 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
468 if (cpuc
->pebs_enabled
)
469 wrmsrl(MSR_IA32_PEBS_ENABLE
, cpuc
->pebs_enabled
);
472 void intel_pmu_pebs_disable_all(void)
474 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
476 if (cpuc
->pebs_enabled
)
477 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
480 static int intel_pmu_pebs_fixup_ip(struct pt_regs
*regs
)
482 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
483 unsigned long from
= cpuc
->lbr_entries
[0].from
;
484 unsigned long old_to
, to
= cpuc
->lbr_entries
[0].to
;
485 unsigned long ip
= regs
->ip
;
489 * We don't need to fixup if the PEBS assist is fault like
491 if (!x86_pmu
.intel_cap
.pebs_trap
)
495 * No LBR entry, no basic block, no rewinding
497 if (!cpuc
->lbr_stack
.nr
|| !from
|| !to
)
501 * Basic blocks should never cross user/kernel boundaries
503 if (kernel_ip(ip
) != kernel_ip(to
))
507 * unsigned math, either ip is before the start (impossible) or
508 * the basic block is larger than 1 page (sanity)
510 if ((ip
- to
) > PAGE_SIZE
)
514 * We sampled a branch insn, rewind using the LBR stack
517 set_linear_ip(regs
, from
);
523 u8 buf
[MAX_INSN_SIZE
];
527 if (!kernel_ip(ip
)) {
528 int bytes
, size
= MAX_INSN_SIZE
;
530 bytes
= copy_from_user_nmi(buf
, (void __user
*)to
, size
);
539 is_64bit
= kernel_ip(to
) || !test_thread_flag(TIF_IA32
);
541 insn_init(&insn
, kaddr
, is_64bit
);
542 insn_get_length(&insn
);
547 set_linear_ip(regs
, old_to
);
552 * Even though we decoded the basic block, the instruction stream
553 * never matched the given IP, either the TO or the IP got corrupted.
558 static void __intel_pmu_pebs_event(struct perf_event
*event
,
559 struct pt_regs
*iregs
, void *__pebs
)
562 * We cast to pebs_record_core since that is a subset of
563 * both formats and we don't use the other fields in this
566 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
567 struct pebs_record_core
*pebs
= __pebs
;
568 struct perf_sample_data data
;
571 if (!intel_pmu_save_and_restart(event
))
574 perf_sample_data_init(&data
, 0, event
->hw
.last_period
);
577 * We use the interrupt regs as a base because the PEBS record
578 * does not contain a full regs set, specifically it seems to
579 * lack segment descriptors, which get used by things like
582 * In the simple case fix up only the IP and BP,SP regs, for
583 * PERF_SAMPLE_IP and PERF_SAMPLE_CALLCHAIN to function properly.
584 * A possible PERF_SAMPLE_REGS will have to transfer all regs.
587 regs
.flags
= pebs
->flags
;
588 set_linear_ip(®s
, pebs
->ip
);
592 if (event
->attr
.precise_ip
> 1 && intel_pmu_pebs_fixup_ip(®s
))
593 regs
.flags
|= PERF_EFLAGS_EXACT
;
595 regs
.flags
&= ~PERF_EFLAGS_EXACT
;
597 if (has_branch_stack(event
))
598 data
.br_stack
= &cpuc
->lbr_stack
;
600 if (perf_event_overflow(event
, &data
, ®s
))
601 x86_pmu_stop(event
, 0);
604 static void intel_pmu_drain_pebs_core(struct pt_regs
*iregs
)
606 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
607 struct debug_store
*ds
= cpuc
->ds
;
608 struct perf_event
*event
= cpuc
->events
[0]; /* PMC0 only */
609 struct pebs_record_core
*at
, *top
;
612 if (!x86_pmu
.pebs_active
)
615 at
= (struct pebs_record_core
*)(unsigned long)ds
->pebs_buffer_base
;
616 top
= (struct pebs_record_core
*)(unsigned long)ds
->pebs_index
;
619 * Whatever else happens, drain the thing
621 ds
->pebs_index
= ds
->pebs_buffer_base
;
623 if (!test_bit(0, cpuc
->active_mask
))
626 WARN_ON_ONCE(!event
);
628 if (!event
->attr
.precise_ip
)
636 * Should not happen, we program the threshold at 1 and do not
639 WARN_ONCE(n
> 1, "bad leftover pebs %d\n", n
);
642 __intel_pmu_pebs_event(event
, iregs
, at
);
645 static void intel_pmu_drain_pebs_nhm(struct pt_regs
*iregs
)
647 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
648 struct debug_store
*ds
= cpuc
->ds
;
649 struct pebs_record_nhm
*at
, *top
;
650 struct perf_event
*event
= NULL
;
654 if (!x86_pmu
.pebs_active
)
657 at
= (struct pebs_record_nhm
*)(unsigned long)ds
->pebs_buffer_base
;
658 top
= (struct pebs_record_nhm
*)(unsigned long)ds
->pebs_index
;
660 ds
->pebs_index
= ds
->pebs_buffer_base
;
667 * Should not happen, we program the threshold at 1 and do not
670 WARN_ONCE(n
> x86_pmu
.max_pebs_events
, "Unexpected number of pebs records %d\n", n
);
672 for ( ; at
< top
; at
++) {
673 for_each_set_bit(bit
, (unsigned long *)&at
->status
, x86_pmu
.max_pebs_events
) {
674 event
= cpuc
->events
[bit
];
675 if (!test_bit(bit
, cpuc
->active_mask
))
678 WARN_ON_ONCE(!event
);
680 if (!event
->attr
.precise_ip
)
683 if (__test_and_set_bit(bit
, (unsigned long *)&status
))
689 if (!event
|| bit
>= x86_pmu
.max_pebs_events
)
692 __intel_pmu_pebs_event(event
, iregs
, at
);
697 * BTS, PEBS probe and setup
700 void intel_ds_init(void)
703 * No support for 32bit formats
705 if (!boot_cpu_has(X86_FEATURE_DTES64
))
708 x86_pmu
.bts
= boot_cpu_has(X86_FEATURE_BTS
);
709 x86_pmu
.pebs
= boot_cpu_has(X86_FEATURE_PEBS
);
711 char pebs_type
= x86_pmu
.intel_cap
.pebs_trap
? '+' : '-';
712 int format
= x86_pmu
.intel_cap
.pebs_format
;
716 printk(KERN_CONT
"PEBS fmt0%c, ", pebs_type
);
717 x86_pmu
.pebs_record_size
= sizeof(struct pebs_record_core
);
718 x86_pmu
.drain_pebs
= intel_pmu_drain_pebs_core
;
722 printk(KERN_CONT
"PEBS fmt1%c, ", pebs_type
);
723 x86_pmu
.pebs_record_size
= sizeof(struct pebs_record_nhm
);
724 x86_pmu
.drain_pebs
= intel_pmu_drain_pebs_nhm
;
728 printk(KERN_CONT
"no PEBS fmt%d%c, ", format
, pebs_type
);
734 void perf_restore_debug_store(void)
736 struct debug_store
*ds
= __this_cpu_read(cpu_hw_events
.ds
);
738 if (!x86_pmu
.bts
&& !x86_pmu
.pebs
)
741 wrmsrl(MSR_IA32_DS_AREA
, (unsigned long)ds
);