arch/x86/kernel/cpu/mcheck/mce_intel_64.c

   1 /*
   2  * Intel specific MCE features.
   3  * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
   4  * Copyright (C) 2008, 2009 Intel Corporation
   5  * Author: Andi Kleen
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/percpu.h>
  11 #include <asm/processor.h>
  12 #include <asm/apic.h>
  13 #include <asm/msr.h>
  14 #include <asm/mce.h>
  15 #include <asm/hw_irq.h>
  16 #include <asm/idle.h>
  17 #include <asm/therm_throt.h>
  18 #include <asm/apic.h>
  19
  20 #include "mce.h"
  21
  22 asmlinkage void smp_thermal_interrupt(void)
  23 {
  24         __u64 msr_val;
  25
  26         ack_APIC_irq();
  27
  28         exit_idle();
  29         irq_enter();
  30
  31         rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
  32         if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT))
  33                 mce_log_therm_throt_event(msr_val);
  34
  35         inc_irq_stat(irq_thermal_count);
  36         irq_exit();
  37 }
  38
  39 /*
  40  * Support for Intel Correct Machine Check Interrupts. This allows
  41  * the CPU to raise an interrupt when a corrected machine check happened.
  42  * Normally we pick those up using a regular polling timer.
  43  * Also supports reliable discovery of shared banks.
  44  */
  45
  46 static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
  47
  48 /*
  49  * cmci_discover_lock protects against parallel discovery attempts
  50  * which could race against each other.
  51  */
  52 static DEFINE_SPINLOCK(cmci_discover_lock);
  53
  54 #define CMCI_THRESHOLD 1
  55
  56 static int cmci_supported(int *banks)
  57 {
  58         u64 cap;
  59
  60         if (mce_cmci_disabled || mce_ignore_ce)
  61                 return 0;
  62
  63         /*
  64          * Vendor check is not strictly needed, but the initial
  65          * initialization is vendor keyed and this
  66          * makes sure none of the backdoors are entered otherwise.
  67          */
  68         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
  69                 return 0;
  70         if (!cpu_has_apic || lapic_get_maxlvt() < 6)
  71                 return 0;
  72         rdmsrl(MSR_IA32_MCG_CAP, cap);
  73         *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
  74         return !!(cap & MCG_CMCI_P);
  75 }
  76
  77 /*
  78  * The interrupt handler. This is called on every event.
  79  * Just call the poller directly to log any events.
  80  * This could in theory increase the threshold under high load,
  81  * but doesn't for now.
  82  */
  83 static void intel_threshold_interrupt(void)
  84 {
  85         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
  86         mce_notify_irq();
  87 }
  88
  89 static void print_update(char *type, int *hdr, int num)
  90 {
  91         if (*hdr == 0)
  92                 printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
  93         *hdr = 1;
  94         printk(KERN_CONT " %s:%d", type, num);
  95 }
  96
  97 /*
  98  * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
  99  * on this CPU. Use the algorithm recommended in the SDM to discover shared
 100  * banks.
 101  */
 102 static void cmci_discover(int banks, int boot)
 103 {
 104         unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
 105         unsigned long flags;
 106         int hdr = 0;
 107         int i;
 108
 109         spin_lock_irqsave(&cmci_discover_lock, flags);
 110         for (i = 0; i < banks; i++) {
 111                 u64 val;
 112
 113                 if (test_bit(i, owned))
 114                         continue;
 115
 116                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 117
 118                 /* Already owned by someone else? */
 119                 if (val & CMCI_EN) {
 120                         if (test_and_clear_bit(i, owned) || boot)
 121                                 print_update("SHD", &hdr, i);
 122                         __clear_bit(i, __get_cpu_var(mce_poll_banks));
 123                         continue;
 124                 }
 125
 126                 val |= CMCI_EN | CMCI_THRESHOLD;
 127                 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
 128                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 129
 130                 /* Did the enable bit stick? -- the bank supports CMCI */
 131                 if (val & CMCI_EN) {
 132                         if (!test_and_set_bit(i, owned) || boot)
 133                                 print_update("CMCI", &hdr, i);
 134                         __clear_bit(i, __get_cpu_var(mce_poll_banks));
 135                 } else {
 136                         WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
 137                 }
 138         }
 139         spin_unlock_irqrestore(&cmci_discover_lock, flags);
 140         if (hdr)
 141                 printk(KERN_CONT "\n");
 142 }
 143
 144 /*
 145  * Just in case we missed an event during initialization check
 146  * all the CMCI owned banks.
 147  */
 148 void cmci_recheck(void)
 149 {
 150         unsigned long flags;
 151         int banks;
 152
 153         if (!mce_available(&current_cpu_data) || !cmci_supported(&banks))
 154                 return;
 155         local_irq_save(flags);
 156         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
 157         local_irq_restore(flags);
 158 }
 159
 160 /*
 161  * Disable CMCI on this CPU for all banks it owns when it goes down.
 162  * This allows other CPUs to claim the banks on rediscovery.
 163  */
 164 void cmci_clear(void)
 165 {
 166         unsigned long flags;
 167         int i;
 168         int banks;
 169         u64 val;
 170
 171         if (!cmci_supported(&banks))
 172                 return;
 173         spin_lock_irqsave(&cmci_discover_lock, flags);
 174         for (i = 0; i < banks; i++) {
 175                 if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
 176                         continue;
 177                 /* Disable CMCI */
 178                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 179                 val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
 180                 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
 181                 __clear_bit(i, __get_cpu_var(mce_banks_owned));
 182         }
 183         spin_unlock_irqrestore(&cmci_discover_lock, flags);
 184 }
 185
 186 /*
 187  * After a CPU went down cycle through all the others and rediscover
 188  * Must run in process context.
 189  */
 190 void cmci_rediscover(int dying)
 191 {
 192         int banks;
 193         int cpu;
 194         cpumask_var_t old;
 195
 196         if (!cmci_supported(&banks))
 197                 return;
 198         if (!alloc_cpumask_var(&old, GFP_KERNEL))
 199                 return;
 200         cpumask_copy(old, &current->cpus_allowed);
 201
 202         for_each_online_cpu(cpu) {
 203                 if (cpu == dying)
 204                         continue;
 205                 if (set_cpus_allowed_ptr(current, cpumask_of(cpu)))
 206                         continue;
 207                 /* Recheck banks in case CPUs don't all have the same */
 208                 if (cmci_supported(&banks))
 209                         cmci_discover(banks, 0);
 210         }
 211
 212         set_cpus_allowed_ptr(current, old);
 213         free_cpumask_var(old);
 214 }
 215
 216 /*
 217  * Reenable CMCI on this CPU in case a CPU down failed.
 218  */
 219 void cmci_reenable(void)
 220 {
 221         int banks;
 222         if (cmci_supported(&banks))
 223                 cmci_discover(banks, 0);
 224 }
 225
 226 static void intel_init_cmci(void)
 227 {
 228         int banks;
 229
 230         if (!cmci_supported(&banks))
 231                 return;
 232
 233         mce_threshold_vector = intel_threshold_interrupt;
 234         cmci_discover(banks, 1);
 235         /*
 236          * For CPU #0 this runs with still disabled APIC, but that's
 237          * ok because only the vector is set up. We still do another
 238          * check for the banks later for CPU #0 just to make sure
 239          * to not miss any events.
 240          */
 241         apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
 242         cmci_recheck();
 243 }
 244
 245 void mce_intel_feature_init(struct cpuinfo_x86 *c)
 246 {
 247         intel_init_thermal(c);
 248         intel_init_cmci();
 249 }