arch/x86/kernel/cpu/mcheck/mce_intel_64.c

   1 /*
   2  * Intel specific MCE features.
   3  * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
   4  * Copyright (C) 2008, 2009 Intel Corporation
   5  * Author: Andi Kleen
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/percpu.h>
  11 #include <asm/processor.h>
  12 #include <asm/apic.h>
  13 #include <asm/msr.h>
  14 #include <asm/mce.h>
  15 #include <asm/hw_irq.h>
  16 #include <asm/idle.h>
  17 #include <asm/therm_throt.h>
  18 #include <asm/apic.h>
  19
  20 asmlinkage void smp_thermal_interrupt(void)
  21 {
  22         __u64 msr_val;
  23
  24         ack_APIC_irq();
  25
  26         exit_idle();
  27         irq_enter();
  28
  29         rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
  30         if (therm_throt_process(msr_val & 1))
  31                 mce_log_therm_throt_event(msr_val);
  32
  33         inc_irq_stat(irq_thermal_count);
  34         irq_exit();
  35 }
  36
  37 static void intel_init_thermal(struct cpuinfo_x86 *c)
  38 {
  39         u32 l, h;
  40         int tm2 = 0;
  41         unsigned int cpu = smp_processor_id();
  42
  43         if (!cpu_has(c, X86_FEATURE_ACPI))
  44                 return;
  45
  46         if (!cpu_has(c, X86_FEATURE_ACC))
  47                 return;
  48
  49         /* first check if TM1 is already enabled by the BIOS, in which
  50          * case there might be some SMM goo which handles it, so we can't even
  51          * put a handler since it might be delivered via SMI already.
  52          */
  53         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  54         h = apic_read(APIC_LVTTHMR);
  55         if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
  56                 printk(KERN_DEBUG
  57                        "CPU%d: Thermal monitoring handled by SMI\n", cpu);
  58                 return;
  59         }
  60
  61         if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
  62                 tm2 = 1;
  63
  64         if (h & APIC_VECTOR_MASK) {
  65                 printk(KERN_DEBUG
  66                        "CPU%d: Thermal LVT vector (%#x) already "
  67                        "installed\n", cpu, (h & APIC_VECTOR_MASK));
  68                 return;
  69         }
  70
  71         h = THERMAL_APIC_VECTOR;
  72         h |= (APIC_DM_FIXED | APIC_LVT_MASKED);
  73         apic_write(APIC_LVTTHMR, h);
  74
  75         rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
  76         wrmsr(MSR_IA32_THERM_INTERRUPT, l | 0x03, h);
  77
  78         rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  79         wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
  80
  81         l = apic_read(APIC_LVTTHMR);
  82         apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
  83         printk(KERN_INFO "CPU%d: Thermal monitoring enabled (%s)\n",
  84                 cpu, tm2 ? "TM2" : "TM1");
  85
  86         /* enable thermal throttle processing */
  87         atomic_set(&therm_throt_en, 1);
  88         return;
  89 }
  90
  91 /*
  92  * Support for Intel Correct Machine Check Interrupts. This allows
  93  * the CPU to raise an interrupt when a corrected machine check happened.
  94  * Normally we pick those up using a regular polling timer.
  95  * Also supports reliable discovery of shared banks.
  96  */
  97
  98 static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
  99
 100 /*
 101  * cmci_discover_lock protects against parallel discovery attempts
 102  * which could race against each other.
 103  */
 104 static DEFINE_SPINLOCK(cmci_discover_lock);
 105
 106 #define CMCI_THRESHOLD 1
 107
 108 static int cmci_supported(int *banks)
 109 {
 110         u64 cap;
 111
 112         /*
 113          * Vendor check is not strictly needed, but the initial
 114          * initialization is vendor keyed and this
 115          * makes sure none of the backdoors are entered otherwise.
 116          */
 117         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
 118                 return 0;
 119         if (!cpu_has_apic || lapic_get_maxlvt() < 6)
 120                 return 0;
 121         rdmsrl(MSR_IA32_MCG_CAP, cap);
 122         *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
 123         return !!(cap & MCG_CMCI_P);
 124 }
 125
 126 /*
 127  * The interrupt handler. This is called on every event.
 128  * Just call the poller directly to log any events.
 129  * This could in theory increase the threshold under high load,
 130  * but doesn't for now.
 131  */
 132 static void intel_threshold_interrupt(void)
 133 {
 134         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
 135         mce_notify_user();
 136 }
 137
 138 static void print_update(char *type, int *hdr, int num)
 139 {
 140         if (*hdr == 0)
 141                 printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
 142         *hdr = 1;
 143         printk(KERN_CONT " %s:%d", type, num);
 144 }
 145
 146 /*
 147  * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
 148  * on this CPU. Use the algorithm recommended in the SDM to discover shared
 149  * banks.
 150  */
 151 static void cmci_discover(int banks, int boot)
 152 {
 153         unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
 154         unsigned long flags;
 155         int hdr = 0;
 156         int i;
 157
 158         spin_lock_irqsave(&cmci_discover_lock, flags);
 159         for (i = 0; i < banks; i++) {
 160                 u64 val;
 161
 162                 if (test_bit(i, owned))
 163                         continue;
 164
 165                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 166
 167                 /* Already owned by someone else? */
 168                 if (val & CMCI_EN) {
 169                         if (test_and_clear_bit(i, owned) || boot)
 170                                 print_update("SHD", &hdr, i);
 171                         __clear_bit(i, __get_cpu_var(mce_poll_banks));
 172                         continue;
 173                 }
 174
 175                 val |= CMCI_EN | CMCI_THRESHOLD;
 176                 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
 177                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 178
 179                 /* Did the enable bit stick? -- the bank supports CMCI */
 180                 if (val & CMCI_EN) {
 181                         if (!test_and_set_bit(i, owned) || boot)
 182                                 print_update("CMCI", &hdr, i);
 183                         __clear_bit(i, __get_cpu_var(mce_poll_banks));
 184                 } else {
 185                         WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
 186                 }
 187         }
 188         spin_unlock_irqrestore(&cmci_discover_lock, flags);
 189         if (hdr)
 190                 printk(KERN_CONT "\n");
 191 }
 192
 193 /*
 194  * Just in case we missed an event during initialization check
 195  * all the CMCI owned banks.
 196  */
 197 void cmci_recheck(void)
 198 {
 199         unsigned long flags;
 200         int banks;
 201
 202         if (!mce_available(&current_cpu_data) || !cmci_supported(&banks))
 203                 return;
 204         local_irq_save(flags);
 205         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
 206         local_irq_restore(flags);
 207 }
 208
 209 /*
 210  * Disable CMCI on this CPU for all banks it owns when it goes down.
 211  * This allows other CPUs to claim the banks on rediscovery.
 212  */
 213 void cmci_clear(void)
 214 {
 215         unsigned long flags;
 216         int i;
 217         int banks;
 218         u64 val;
 219
 220         if (!cmci_supported(&banks))
 221                 return;
 222         spin_lock_irqsave(&cmci_discover_lock, flags);
 223         for (i = 0; i < banks; i++) {
 224                 if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
 225                         continue;
 226                 /* Disable CMCI */
 227                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 228                 val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
 229                 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
 230                 __clear_bit(i, __get_cpu_var(mce_banks_owned));
 231         }
 232         spin_unlock_irqrestore(&cmci_discover_lock, flags);
 233 }
 234
 235 /*
 236  * After a CPU went down cycle through all the others and rediscover
 237  * Must run in process context.
 238  */
 239 void cmci_rediscover(int dying)
 240 {
 241         int banks;
 242         int cpu;
 243         cpumask_var_t old;
 244
 245         if (!cmci_supported(&banks))
 246                 return;
 247         if (!alloc_cpumask_var(&old, GFP_KERNEL))
 248                 return;
 249         cpumask_copy(old, &current->cpus_allowed);
 250
 251         for_each_online_cpu (cpu) {
 252                 if (cpu == dying)
 253                         continue;
 254                 if (set_cpus_allowed_ptr(current, cpumask_of(cpu)))
 255                         continue;
 256                 /* Recheck banks in case CPUs don't all have the same */
 257                 if (cmci_supported(&banks))
 258                         cmci_discover(banks, 0);
 259         }
 260
 261         set_cpus_allowed_ptr(current, old);
 262         free_cpumask_var(old);
 263 }
 264
 265 /*
 266  * Reenable CMCI on this CPU in case a CPU down failed.
 267  */
 268 void cmci_reenable(void)
 269 {
 270         int banks;
 271         if (cmci_supported(&banks))
 272                 cmci_discover(banks, 0);
 273 }
 274
 275 static void intel_init_cmci(void)
 276 {
 277         int banks;
 278
 279         if (!cmci_supported(&banks))
 280                 return;
 281
 282         mce_threshold_vector = intel_threshold_interrupt;
 283         cmci_discover(banks, 1);
 284         /*
 285          * For CPU #0 this runs with still disabled APIC, but that's
 286          * ok because only the vector is set up. We still do another
 287          * check for the banks later for CPU #0 just to make sure
 288          * to not miss any events.
 289          */
 290         apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
 291         cmci_recheck();
 292 }
 293
 294 void mce_intel_feature_init(struct cpuinfo_x86 *c)
 295 {
 296         intel_init_thermal(c);
 297         intel_init_cmci();
 298 }