arch/x86/kernel/cpu/mcheck/mce_intel_64.c

   1 /*
   2  * Intel specific MCE features.
   3  * Copyright 2004 Zwane Mwaikambo <zwane@linuxpower.ca>
   4  * Copyright (C) 2008, 2009 Intel Corporation
   5  * Author: Andi Kleen
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/percpu.h>
  11 #include <asm/processor.h>
  12 #include <asm/apic.h>
  13 #include <asm/msr.h>
  14 #include <asm/mce.h>
  15 #include <asm/hw_irq.h>
  16 #include <asm/idle.h>
  17 #include <asm/therm_throt.h>
  18
  19 #include "mce.h"
  20
  21 asmlinkage void smp_thermal_interrupt(void)
  22 {
  23         __u64 msr_val;
  24
  25         ack_APIC_irq();
  26
  27         exit_idle();
  28         irq_enter();
  29
  30         rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
  31         if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT))
  32                 mce_log_therm_throt_event(msr_val);
  33
  34         inc_irq_stat(irq_thermal_count);
  35         irq_exit();
  36 }
  37
  38 /*
  39  * Support for Intel Correct Machine Check Interrupts. This allows
  40  * the CPU to raise an interrupt when a corrected machine check happened.
  41  * Normally we pick those up using a regular polling timer.
  42  * Also supports reliable discovery of shared banks.
  43  */
  44
  45 static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned);
  46
  47 /*
  48  * cmci_discover_lock protects against parallel discovery attempts
  49  * which could race against each other.
  50  */
  51 static DEFINE_SPINLOCK(cmci_discover_lock);
  52
  53 #define CMCI_THRESHOLD 1
  54
  55 static int cmci_supported(int *banks)
  56 {
  57         u64 cap;
  58
  59         if (mce_cmci_disabled || mce_ignore_ce)
  60                 return 0;
  61
  62         /*
  63          * Vendor check is not strictly needed, but the initial
  64          * initialization is vendor keyed and this
  65          * makes sure none of the backdoors are entered otherwise.
  66          */
  67         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
  68                 return 0;
  69         if (!cpu_has_apic || lapic_get_maxlvt() < 6)
  70                 return 0;
  71         rdmsrl(MSR_IA32_MCG_CAP, cap);
  72         *banks = min_t(unsigned, MAX_NR_BANKS, cap & 0xff);
  73         return !!(cap & MCG_CMCI_P);
  74 }
  75
  76 /*
  77  * The interrupt handler. This is called on every event.
  78  * Just call the poller directly to log any events.
  79  * This could in theory increase the threshold under high load,
  80  * but doesn't for now.
  81  */
  82 static void intel_threshold_interrupt(void)
  83 {
  84         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
  85         mce_notify_irq();
  86 }
  87
  88 static void print_update(char *type, int *hdr, int num)
  89 {
  90         if (*hdr == 0)
  91                 printk(KERN_INFO "CPU %d MCA banks", smp_processor_id());
  92         *hdr = 1;
  93         printk(KERN_CONT " %s:%d", type, num);
  94 }
  95
  96 /*
  97  * Enable CMCI (Corrected Machine Check Interrupt) for available MCE banks
  98  * on this CPU. Use the algorithm recommended in the SDM to discover shared
  99  * banks.
 100  */
 101 static void cmci_discover(int banks, int boot)
 102 {
 103         unsigned long *owned = (void *)&__get_cpu_var(mce_banks_owned);
 104         unsigned long flags;
 105         int hdr = 0;
 106         int i;
 107
 108         spin_lock_irqsave(&cmci_discover_lock, flags);
 109         for (i = 0; i < banks; i++) {
 110                 u64 val;
 111
 112                 if (test_bit(i, owned))
 113                         continue;
 114
 115                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 116
 117                 /* Already owned by someone else? */
 118                 if (val & CMCI_EN) {
 119                         if (test_and_clear_bit(i, owned) || boot)
 120                                 print_update("SHD", &hdr, i);
 121                         __clear_bit(i, __get_cpu_var(mce_poll_banks));
 122                         continue;
 123                 }
 124
 125                 val |= CMCI_EN | CMCI_THRESHOLD;
 126                 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
 127                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 128
 129                 /* Did the enable bit stick? -- the bank supports CMCI */
 130                 if (val & CMCI_EN) {
 131                         if (!test_and_set_bit(i, owned) || boot)
 132                                 print_update("CMCI", &hdr, i);
 133                         __clear_bit(i, __get_cpu_var(mce_poll_banks));
 134                 } else {
 135                         WARN_ON(!test_bit(i, __get_cpu_var(mce_poll_banks)));
 136                 }
 137         }
 138         spin_unlock_irqrestore(&cmci_discover_lock, flags);
 139         if (hdr)
 140                 printk(KERN_CONT "\n");
 141 }
 142
 143 /*
 144  * Just in case we missed an event during initialization check
 145  * all the CMCI owned banks.
 146  */
 147 void cmci_recheck(void)
 148 {
 149         unsigned long flags;
 150         int banks;
 151
 152         if (!mce_available(&current_cpu_data) || !cmci_supported(&banks))
 153                 return;
 154         local_irq_save(flags);
 155         machine_check_poll(MCP_TIMESTAMP, &__get_cpu_var(mce_banks_owned));
 156         local_irq_restore(flags);
 157 }
 158
 159 /*
 160  * Disable CMCI on this CPU for all banks it owns when it goes down.
 161  * This allows other CPUs to claim the banks on rediscovery.
 162  */
 163 void cmci_clear(void)
 164 {
 165         unsigned long flags;
 166         int i;
 167         int banks;
 168         u64 val;
 169
 170         if (!cmci_supported(&banks))
 171                 return;
 172         spin_lock_irqsave(&cmci_discover_lock, flags);
 173         for (i = 0; i < banks; i++) {
 174                 if (!test_bit(i, __get_cpu_var(mce_banks_owned)))
 175                         continue;
 176                 /* Disable CMCI */
 177                 rdmsrl(MSR_IA32_MC0_CTL2 + i, val);
 178                 val &= ~(CMCI_EN|CMCI_THRESHOLD_MASK);
 179                 wrmsrl(MSR_IA32_MC0_CTL2 + i, val);
 180                 __clear_bit(i, __get_cpu_var(mce_banks_owned));
 181         }
 182         spin_unlock_irqrestore(&cmci_discover_lock, flags);
 183 }
 184
 185 /*
 186  * After a CPU went down cycle through all the others and rediscover
 187  * Must run in process context.
 188  */
 189 void cmci_rediscover(int dying)
 190 {
 191         int banks;
 192         int cpu;
 193         cpumask_var_t old;
 194
 195         if (!cmci_supported(&banks))
 196                 return;
 197         if (!alloc_cpumask_var(&old, GFP_KERNEL))
 198                 return;
 199         cpumask_copy(old, &current->cpus_allowed);
 200
 201         for_each_online_cpu(cpu) {
 202                 if (cpu == dying)
 203                         continue;
 204                 if (set_cpus_allowed_ptr(current, cpumask_of(cpu)))
 205                         continue;
 206                 /* Recheck banks in case CPUs don't all have the same */
 207                 if (cmci_supported(&banks))
 208                         cmci_discover(banks, 0);
 209         }
 210
 211         set_cpus_allowed_ptr(current, old);
 212         free_cpumask_var(old);
 213 }
 214
 215 /*
 216  * Reenable CMCI on this CPU in case a CPU down failed.
 217  */
 218 void cmci_reenable(void)
 219 {
 220         int banks;
 221         if (cmci_supported(&banks))
 222                 cmci_discover(banks, 0);
 223 }
 224
 225 static void intel_init_cmci(void)
 226 {
 227         int banks;
 228
 229         if (!cmci_supported(&banks))
 230                 return;
 231
 232         mce_threshold_vector = intel_threshold_interrupt;
 233         cmci_discover(banks, 1);
 234         /*
 235          * For CPU #0 this runs with still disabled APIC, but that's
 236          * ok because only the vector is set up. We still do another
 237          * check for the banks later for CPU #0 just to make sure
 238          * to not miss any events.
 239          */
 240         apic_write(APIC_LVTCMCI, THRESHOLD_APIC_VECTOR|APIC_DM_FIXED);
 241         cmci_recheck();
 242 }
 243
 244 void mce_intel_feature_init(struct cpuinfo_x86 *c)
 245 {
 246         intel_init_thermal(c);
 247         intel_init_cmci();
 248 }