2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
40 #include <asm/processor.h>
41 #include <asm/hw_irq.h>
48 #include "mce-internal.h"
50 static DEFINE_MUTEX(mce_read_mutex
);
52 #define rcu_dereference_check_mce(p) \
53 rcu_dereference_check((p), \
54 rcu_read_lock_sched_held() || \
55 lockdep_is_held(&mce_read_mutex))
57 #define CREATE_TRACE_POINTS
58 #include <trace/events/mce.h>
60 int mce_disabled __read_mostly
;
62 #define MISC_MCELOG_MINOR 227
64 #define SPINUNIT 100 /* 100ns */
68 DEFINE_PER_CPU(unsigned, mce_exception_count
);
72 * 0: always panic on uncorrected errors, log corrected errors
73 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
74 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
75 * 3: never panic or SIGBUS, log all errors (for testing only)
77 static int tolerant __read_mostly
= 1;
78 static int banks __read_mostly
;
79 static int rip_msr __read_mostly
;
80 static int mce_bootlog __read_mostly
= -1;
81 static int monarch_timeout __read_mostly
= -1;
82 static int mce_panic_timeout __read_mostly
;
83 static int mce_dont_log_ce __read_mostly
;
84 int mce_cmci_disabled __read_mostly
;
85 int mce_ignore_ce __read_mostly
;
86 int mce_ser __read_mostly
;
88 struct mce_bank
*mce_banks __read_mostly
;
90 /* User mode helper program triggered by machine check event */
91 static unsigned long mce_need_notify
;
92 static char mce_helper
[128];
93 static char *mce_helper_argv
[2] = { mce_helper
, NULL
};
95 static DECLARE_WAIT_QUEUE_HEAD(mce_wait
);
96 static DEFINE_PER_CPU(struct mce
, mces_seen
);
97 static int cpu_missing
;
100 * CPU/chipset specific EDAC code can register a notifier call here to print
101 * MCE errors in a human-readable form.
103 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain
);
104 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain
);
106 static int default_decode_mce(struct notifier_block
*nb
, unsigned long val
,
109 pr_emerg("No human readable MCE decoding support on this CPU type.\n");
110 pr_emerg("Run the message through 'mcelog --ascii' to decode.\n");
115 static struct notifier_block mce_dec_nb
= {
116 .notifier_call
= default_decode_mce
,
120 /* MCA banks polled by the period polling timer for corrected events */
121 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
122 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
125 static DEFINE_PER_CPU(struct work_struct
, mce_work
);
127 /* Do initial initialization of a struct mce */
128 void mce_setup(struct mce
*m
)
130 memset(m
, 0, sizeof(struct mce
));
131 m
->cpu
= m
->extcpu
= smp_processor_id();
133 /* We hope get_seconds stays lockless */
134 m
->time
= get_seconds();
135 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
136 m
->cpuid
= cpuid_eax(1);
138 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
140 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
141 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
144 DEFINE_PER_CPU(struct mce
, injectm
);
145 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
148 * Lockless MCE logging infrastructure.
149 * This avoids deadlocks on printk locks without having to break locks. Also
150 * separate MCEs from kernel messages to avoid bogus bug reports.
153 static struct mce_log mcelog
= {
154 .signature
= MCE_LOG_SIGNATURE
,
156 .recordlen
= sizeof(struct mce
),
159 void mce_log(struct mce
*mce
)
161 unsigned next
, entry
;
163 /* Emit the trace record: */
164 trace_mce_record(mce
);
169 entry
= rcu_dereference_check_mce(mcelog
.next
);
172 * When the buffer fills up discard new entries.
173 * Assume that the earlier errors are the more
176 if (entry
>= MCE_LOG_LEN
) {
177 set_bit(MCE_OVERFLOW
,
178 (unsigned long *)&mcelog
.flags
);
181 /* Old left over entry. Skip: */
182 if (mcelog
.entry
[entry
].finished
) {
190 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
193 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
195 mcelog
.entry
[entry
].finished
= 1;
199 set_bit(0, &mce_need_notify
);
202 static void print_mce(struct mce
*m
)
204 pr_emerg("CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
205 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
208 pr_emerg("RIP%s %02x:<%016Lx> ",
209 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
212 if (m
->cs
== __KERNEL_CS
)
213 print_symbol("{%s}", m
->ip
);
217 pr_emerg("TSC %llx ", m
->tsc
);
219 pr_cont("ADDR %llx ", m
->addr
);
221 pr_cont("MISC %llx ", m
->misc
);
224 pr_emerg("PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
225 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
, m
->apicid
);
228 * Print out human-readable details about the MCE error,
229 * (if the CPU has an implementation for that)
231 atomic_notifier_call_chain(&x86_mce_decoder_chain
, 0, m
);
234 static void print_mce_head(void)
236 pr_emerg("\nHARDWARE ERROR\n");
239 static void print_mce_tail(void)
241 pr_emerg("This is not a software problem!\n");
244 #define PANIC_TIMEOUT 5 /* 5 seconds */
246 static atomic_t mce_paniced
;
248 static int fake_panic
;
249 static atomic_t mce_fake_paniced
;
251 /* Panic in progress. Enable interrupts and wait for final IPI */
252 static void wait_for_panic(void)
254 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
258 while (timeout
-- > 0)
260 if (panic_timeout
== 0)
261 panic_timeout
= mce_panic_timeout
;
262 panic("Panicing machine check CPU died");
265 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
271 * Make sure only one CPU runs in machine check panic
273 if (atomic_inc_return(&mce_paniced
) > 1)
280 /* Don't log too much for fake panic */
281 if (atomic_inc_return(&mce_fake_paniced
) > 1)
285 /* First print corrected ones that are still unlogged */
286 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
287 struct mce
*m
= &mcelog
.entry
[i
];
288 if (!(m
->status
& MCI_STATUS_VAL
))
290 if (!(m
->status
& MCI_STATUS_UC
)) {
293 apei_err
= apei_write_mce(m
);
296 /* Now print uncorrected but with the final one last */
297 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
298 struct mce
*m
= &mcelog
.entry
[i
];
299 if (!(m
->status
& MCI_STATUS_VAL
))
301 if (!(m
->status
& MCI_STATUS_UC
))
303 if (!final
|| memcmp(m
, final
, sizeof(struct mce
))) {
306 apei_err
= apei_write_mce(m
);
312 apei_err
= apei_write_mce(final
);
315 printk(KERN_EMERG
"Some CPUs didn't answer in synchronization\n");
318 printk(KERN_EMERG
"Machine check: %s\n", exp
);
320 if (panic_timeout
== 0)
321 panic_timeout
= mce_panic_timeout
;
324 printk(KERN_EMERG
"Fake kernel panic: %s\n", msg
);
327 /* Support code for software error injection */
329 static int msr_to_offset(u32 msr
)
331 unsigned bank
= __get_cpu_var(injectm
.bank
);
334 return offsetof(struct mce
, ip
);
335 if (msr
== MSR_IA32_MCx_STATUS(bank
))
336 return offsetof(struct mce
, status
);
337 if (msr
== MSR_IA32_MCx_ADDR(bank
))
338 return offsetof(struct mce
, addr
);
339 if (msr
== MSR_IA32_MCx_MISC(bank
))
340 return offsetof(struct mce
, misc
);
341 if (msr
== MSR_IA32_MCG_STATUS
)
342 return offsetof(struct mce
, mcgstatus
);
346 /* MSR access wrappers used for error injection */
347 static u64
mce_rdmsrl(u32 msr
)
351 if (__get_cpu_var(injectm
).finished
) {
352 int offset
= msr_to_offset(msr
);
356 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
359 if (rdmsrl_safe(msr
, &v
)) {
360 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr
);
362 * Return zero in case the access faulted. This should
363 * not happen normally but can happen if the CPU does
364 * something weird, or if the code is buggy.
372 static void mce_wrmsrl(u32 msr
, u64 v
)
374 if (__get_cpu_var(injectm
).finished
) {
375 int offset
= msr_to_offset(msr
);
378 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
385 * Simple lockless ring to communicate PFNs from the exception handler with the
386 * process context work function. This is vastly simplified because there's
387 * only a single reader and a single writer.
389 #define MCE_RING_SIZE 16 /* we use one entry less */
392 unsigned short start
;
394 unsigned long ring
[MCE_RING_SIZE
];
396 static DEFINE_PER_CPU(struct mce_ring
, mce_ring
);
398 /* Runs with CPU affinity in workqueue */
399 static int mce_ring_empty(void)
401 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
403 return r
->start
== r
->end
;
406 static int mce_ring_get(unsigned long *pfn
)
413 r
= &__get_cpu_var(mce_ring
);
414 if (r
->start
== r
->end
)
416 *pfn
= r
->ring
[r
->start
];
417 r
->start
= (r
->start
+ 1) % MCE_RING_SIZE
;
424 /* Always runs in MCE context with preempt off */
425 static int mce_ring_add(unsigned long pfn
)
427 struct mce_ring
*r
= &__get_cpu_var(mce_ring
);
430 next
= (r
->end
+ 1) % MCE_RING_SIZE
;
431 if (next
== r
->start
)
433 r
->ring
[r
->end
] = pfn
;
439 int mce_available(struct cpuinfo_x86
*c
)
443 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
446 static void mce_schedule_work(void)
448 if (!mce_ring_empty()) {
449 struct work_struct
*work
= &__get_cpu_var(mce_work
);
450 if (!work_pending(work
))
456 * Get the address of the instruction at the time of the machine check
459 static inline void mce_get_rip(struct mce
*m
, struct pt_regs
*regs
)
462 if (regs
&& (m
->mcgstatus
& (MCG_STATUS_RIPV
|MCG_STATUS_EIPV
))) {
470 m
->ip
= mce_rdmsrl(rip_msr
);
473 #ifdef CONFIG_X86_LOCAL_APIC
475 * Called after interrupts have been reenabled again
476 * when a MCE happened during an interrupts off region
479 asmlinkage
void smp_mce_self_interrupt(struct pt_regs
*regs
)
490 static void mce_report_event(struct pt_regs
*regs
)
492 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
495 * Triggering the work queue here is just an insurance
496 * policy in case the syscall exit notify handler
497 * doesn't run soon enough or ends up running on the
498 * wrong CPU (can happen when audit sleeps)
504 #ifdef CONFIG_X86_LOCAL_APIC
506 * Without APIC do not notify. The event will be picked
513 * When interrupts are disabled we cannot use
514 * kernel services safely. Trigger an self interrupt
515 * through the APIC to instead do the notification
516 * after interrupts are reenabled again.
518 apic
->send_IPI_self(MCE_SELF_VECTOR
);
521 * Wait for idle afterwards again so that we don't leave the
522 * APIC in a non idle state because the normal APIC writes
525 apic_wait_icr_idle();
529 DEFINE_PER_CPU(unsigned, mce_poll_count
);
532 * Poll for corrected events or events that happened before reset.
533 * Those are just logged through /dev/mcelog.
535 * This is executed in standard interrupt context.
537 * Note: spec recommends to panic for fatal unsignalled
538 * errors here. However this would be quite problematic --
539 * we would need to reimplement the Monarch handling and
540 * it would mess up the exclusion between exception handler
541 * and poll hander -- * so we skip this for now.
542 * These cases should not happen anyways, or only when the CPU
543 * is already totally * confused. In this case it's likely it will
544 * not fully execute the machine check handler either.
546 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
551 percpu_inc(mce_poll_count
);
555 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
556 for (i
= 0; i
< banks
; i
++) {
557 if (!mce_banks
[i
].ctl
|| !test_bit(i
, *b
))
566 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
567 if (!(m
.status
& MCI_STATUS_VAL
))
571 * Uncorrected or signalled events are handled by the exception
572 * handler when it is enabled, so don't process those here.
574 * TBD do the same check for MCI_STATUS_EN here?
576 if (!(flags
& MCP_UC
) &&
577 (m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)))
580 if (m
.status
& MCI_STATUS_MISCV
)
581 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
582 if (m
.status
& MCI_STATUS_ADDRV
)
583 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
585 if (!(flags
& MCP_TIMESTAMP
))
588 * Don't get the IP here because it's unlikely to
589 * have anything to do with the actual error location.
591 if (!(flags
& MCP_DONTLOG
) && !mce_dont_log_ce
) {
593 add_taint(TAINT_MACHINE_CHECK
);
597 * Clear state for this bank.
599 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
603 * Don't clear MCG_STATUS here because it's only defined for
609 EXPORT_SYMBOL_GPL(machine_check_poll
);
612 * Do a quick check if any of the events requires a panic.
613 * This decides if we keep the events around or clear them.
615 static int mce_no_way_out(struct mce
*m
, char **msg
)
619 for (i
= 0; i
< banks
; i
++) {
620 m
->status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
621 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
628 * Variable to establish order between CPUs while scanning.
629 * Each CPU spins initially until executing is equal its number.
631 static atomic_t mce_executing
;
634 * Defines order of CPUs on entry. First CPU becomes Monarch.
636 static atomic_t mce_callin
;
639 * Check if a timeout waiting for other CPUs happened.
641 static int mce_timed_out(u64
*t
)
644 * The others already did panic for some reason.
645 * Bail out like in a timeout.
646 * rmb() to tell the compiler that system_state
647 * might have been modified by someone else.
650 if (atomic_read(&mce_paniced
))
652 if (!monarch_timeout
)
654 if ((s64
)*t
< SPINUNIT
) {
655 /* CHECKME: Make panic default for 1 too? */
657 mce_panic("Timeout synchronizing machine check over CPUs",
664 touch_nmi_watchdog();
669 * The Monarch's reign. The Monarch is the CPU who entered
670 * the machine check handler first. It waits for the others to
671 * raise the exception too and then grades them. When any
672 * error is fatal panic. Only then let the others continue.
674 * The other CPUs entering the MCE handler will be controlled by the
675 * Monarch. They are called Subjects.
677 * This way we prevent any potential data corruption in a unrecoverable case
678 * and also makes sure always all CPU's errors are examined.
680 * Also this detects the case of a machine check event coming from outer
681 * space (not detected by any CPUs) In this case some external agent wants
682 * us to shut down, so panic too.
684 * The other CPUs might still decide to panic if the handler happens
685 * in a unrecoverable place, but in this case the system is in a semi-stable
686 * state and won't corrupt anything by itself. It's ok to let the others
687 * continue for a bit first.
689 * All the spin loops have timeouts; when a timeout happens a CPU
690 * typically elects itself to be Monarch.
692 static void mce_reign(void)
695 struct mce
*m
= NULL
;
696 int global_worst
= 0;
701 * This CPU is the Monarch and the other CPUs have run
702 * through their handlers.
703 * Grade the severity of the errors of all the CPUs.
705 for_each_possible_cpu(cpu
) {
706 int severity
= mce_severity(&per_cpu(mces_seen
, cpu
), tolerant
,
708 if (severity
> global_worst
) {
710 global_worst
= severity
;
711 m
= &per_cpu(mces_seen
, cpu
);
716 * Cannot recover? Panic here then.
717 * This dumps all the mces in the log buffer and stops the
720 if (m
&& global_worst
>= MCE_PANIC_SEVERITY
&& tolerant
< 3)
721 mce_panic("Fatal Machine check", m
, msg
);
724 * For UC somewhere we let the CPU who detects it handle it.
725 * Also must let continue the others, otherwise the handling
726 * CPU could deadlock on a lock.
730 * No machine check event found. Must be some external
731 * source or one CPU is hung. Panic.
733 if (global_worst
<= MCE_KEEP_SEVERITY
&& tolerant
< 3)
734 mce_panic("Machine check from unknown source", NULL
, NULL
);
737 * Now clear all the mces_seen so that they don't reappear on
740 for_each_possible_cpu(cpu
)
741 memset(&per_cpu(mces_seen
, cpu
), 0, sizeof(struct mce
));
744 static atomic_t global_nwo
;
747 * Start of Monarch synchronization. This waits until all CPUs have
748 * entered the exception handler and then determines if any of them
749 * saw a fatal event that requires panic. Then it executes them
750 * in the entry order.
751 * TBD double check parallel CPU hotunplug
753 static int mce_start(int *no_way_out
)
756 int cpus
= num_online_cpus();
757 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
762 atomic_add(*no_way_out
, &global_nwo
);
764 * global_nwo should be updated before mce_callin
767 order
= atomic_inc_return(&mce_callin
);
772 while (atomic_read(&mce_callin
) != cpus
) {
773 if (mce_timed_out(&timeout
)) {
774 atomic_set(&global_nwo
, 0);
781 * mce_callin should be read before global_nwo
787 * Monarch: Starts executing now, the others wait.
789 atomic_set(&mce_executing
, 1);
792 * Subject: Now start the scanning loop one by one in
793 * the original callin order.
794 * This way when there are any shared banks it will be
795 * only seen by one CPU before cleared, avoiding duplicates.
797 while (atomic_read(&mce_executing
) < order
) {
798 if (mce_timed_out(&timeout
)) {
799 atomic_set(&global_nwo
, 0);
807 * Cache the global no_way_out state.
809 *no_way_out
= atomic_read(&global_nwo
);
815 * Synchronize between CPUs after main scanning loop.
816 * This invokes the bulk of the Monarch processing.
818 static int mce_end(int order
)
821 u64 timeout
= (u64
)monarch_timeout
* NSEC_PER_USEC
;
829 * Allow others to run.
831 atomic_inc(&mce_executing
);
834 /* CHECKME: Can this race with a parallel hotplug? */
835 int cpus
= num_online_cpus();
838 * Monarch: Wait for everyone to go through their scanning
841 while (atomic_read(&mce_executing
) <= cpus
) {
842 if (mce_timed_out(&timeout
))
852 * Subject: Wait for Monarch to finish.
854 while (atomic_read(&mce_executing
) != 0) {
855 if (mce_timed_out(&timeout
))
861 * Don't reset anything. That's done by the Monarch.
867 * Reset all global state.
870 atomic_set(&global_nwo
, 0);
871 atomic_set(&mce_callin
, 0);
875 * Let others run again.
877 atomic_set(&mce_executing
, 0);
882 * Check if the address reported by the CPU is in a format we can parse.
883 * It would be possible to add code for most other cases, but all would
884 * be somewhat complicated (e.g. segment offset would require an instruction
885 * parser). So only support physical addresses upto page granuality for now.
887 static int mce_usable_address(struct mce
*m
)
889 if (!(m
->status
& MCI_STATUS_MISCV
) || !(m
->status
& MCI_STATUS_ADDRV
))
891 if ((m
->misc
& 0x3f) > PAGE_SHIFT
)
893 if (((m
->misc
>> 6) & 7) != MCM_ADDR_PHYS
)
898 static void mce_clear_state(unsigned long *toclear
)
902 for (i
= 0; i
< banks
; i
++) {
903 if (test_bit(i
, toclear
))
904 mce_wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
909 * The actual machine check handler. This only handles real
910 * exceptions when something got corrupted coming in through int 18.
912 * This is executed in NMI context not subject to normal locking rules. This
913 * implies that most kernel services cannot be safely used. Don't even
914 * think about putting a printk in there!
916 * On Intel systems this is entered on all CPUs in parallel through
917 * MCE broadcast. However some CPUs might be broken beyond repair,
918 * so be always careful when synchronizing with others.
920 void do_machine_check(struct pt_regs
*regs
, long error_code
)
922 struct mce m
, *final
;
927 * Establish sequential order between the CPUs entering the machine
932 * If no_way_out gets set, there is no safe way to recover from this
933 * MCE. If tolerant is cranked up, we'll try anyway.
937 * If kill_it gets set, there might be a way to recover from this
941 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
942 char *msg
= "Unknown";
944 atomic_inc(&mce_entry
);
946 percpu_inc(mce_exception_count
);
948 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
949 18, SIGKILL
) == NOTIFY_STOP
)
956 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
957 final
= &__get_cpu_var(mces_seen
);
960 no_way_out
= mce_no_way_out(&m
, &msg
);
965 * When no restart IP must always kill or panic.
967 if (!(m
.mcgstatus
& MCG_STATUS_RIPV
))
971 * Go through all the banks in exclusion of the other CPUs.
972 * This way we don't report duplicated events on shared banks
973 * because the first one to see it will clear it.
975 order
= mce_start(&no_way_out
);
976 for (i
= 0; i
< banks
; i
++) {
977 __clear_bit(i
, toclear
);
978 if (!mce_banks
[i
].ctl
)
985 m
.status
= mce_rdmsrl(MSR_IA32_MCx_STATUS(i
));
986 if ((m
.status
& MCI_STATUS_VAL
) == 0)
990 * Non uncorrected or non signaled errors are handled by
991 * machine_check_poll. Leave them alone, unless this panics.
993 if (!(m
.status
& (mce_ser
? MCI_STATUS_S
: MCI_STATUS_UC
)) &&
998 * Set taint even when machine check was not enabled.
1000 add_taint(TAINT_MACHINE_CHECK
);
1002 severity
= mce_severity(&m
, tolerant
, NULL
);
1005 * When machine check was for corrected handler don't touch,
1006 * unless we're panicing.
1008 if (severity
== MCE_KEEP_SEVERITY
&& !no_way_out
)
1010 __set_bit(i
, toclear
);
1011 if (severity
== MCE_NO_SEVERITY
) {
1013 * Machine check event was not enabled. Clear, but
1020 * Kill on action required.
1022 if (severity
== MCE_AR_SEVERITY
)
1025 if (m
.status
& MCI_STATUS_MISCV
)
1026 m
.misc
= mce_rdmsrl(MSR_IA32_MCx_MISC(i
));
1027 if (m
.status
& MCI_STATUS_ADDRV
)
1028 m
.addr
= mce_rdmsrl(MSR_IA32_MCx_ADDR(i
));
1031 * Action optional error. Queue address for later processing.
1032 * When the ring overflows we just ignore the AO error.
1033 * RED-PEN add some logging mechanism when
1034 * usable_address or mce_add_ring fails.
1035 * RED-PEN don't ignore overflow for tolerant == 0
1037 if (severity
== MCE_AO_SEVERITY
&& mce_usable_address(&m
))
1038 mce_ring_add(m
.addr
>> PAGE_SHIFT
);
1040 mce_get_rip(&m
, regs
);
1043 if (severity
> worst
) {
1050 mce_clear_state(toclear
);
1053 * Do most of the synchronization with other CPUs.
1054 * When there's any problem use only local no_way_out state.
1056 if (mce_end(order
) < 0)
1057 no_way_out
= worst
>= MCE_PANIC_SEVERITY
;
1060 * If we have decided that we just CAN'T continue, and the user
1061 * has not set tolerant to an insane level, give up and die.
1063 * This is mainly used in the case when the system doesn't
1064 * support MCE broadcasting or it has been disabled.
1066 if (no_way_out
&& tolerant
< 3)
1067 mce_panic("Fatal machine check on current CPU", final
, msg
);
1070 * If the error seems to be unrecoverable, something should be
1071 * done. Try to kill as little as possible. If we can kill just
1072 * one task, do that. If the user has set the tolerance very
1073 * high, don't try to do anything at all.
1076 if (kill_it
&& tolerant
< 3)
1077 force_sig(SIGBUS
, current
);
1079 /* notify userspace ASAP */
1080 set_thread_flag(TIF_MCE_NOTIFY
);
1083 mce_report_event(regs
);
1084 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
1086 atomic_dec(&mce_entry
);
1089 EXPORT_SYMBOL_GPL(do_machine_check
);
1091 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1092 void __attribute__((weak
)) memory_failure(unsigned long pfn
, int vector
)
1094 printk(KERN_ERR
"Action optional memory failure at %lx ignored\n", pfn
);
1098 * Called after mce notification in process context. This code
1099 * is allowed to sleep. Call the high level VM handler to process
1100 * any corrupted pages.
1101 * Assume that the work queue code only calls this one at a time
1103 * Note we don't disable preemption, so this code might run on the wrong
1104 * CPU. In this case the event is picked up by the scheduled work queue.
1105 * This is merely a fast path to expedite processing in some common
1108 void mce_notify_process(void)
1112 while (mce_ring_get(&pfn
))
1113 memory_failure(pfn
, MCE_VECTOR
);
1116 static void mce_process_work(struct work_struct
*dummy
)
1118 mce_notify_process();
1121 #ifdef CONFIG_X86_MCE_INTEL
1123 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1124 * @cpu: The CPU on which the event occurred.
1125 * @status: Event status information
1127 * This function should be called by the thermal interrupt after the
1128 * event has been processed and the decision was made to log the event
1131 * The status parameter will be saved to the 'status' field of 'struct mce'
1132 * and historically has been the register value of the
1133 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1135 void mce_log_therm_throt_event(__u64 status
)
1140 m
.bank
= MCE_THERMAL_BANK
;
1144 #endif /* CONFIG_X86_MCE_INTEL */
1147 * Periodic polling timer for "silent" machine check errors. If the
1148 * poller finds an MCE, poll 2x faster. When the poller finds no more
1149 * errors, poll 2x slower (up to check_interval seconds).
1151 static int check_interval
= 5 * 60; /* 5 minutes */
1153 static DEFINE_PER_CPU(int, mce_next_interval
); /* in jiffies */
1154 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
1156 static void mce_start_timer(unsigned long data
)
1158 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
1161 WARN_ON(smp_processor_id() != data
);
1163 if (mce_available(¤t_cpu_data
)) {
1164 machine_check_poll(MCP_TIMESTAMP
,
1165 &__get_cpu_var(mce_poll_banks
));
1169 * Alert userspace if needed. If we logged an MCE, reduce the
1170 * polling interval, otherwise increase the polling interval.
1172 n
= &__get_cpu_var(mce_next_interval
);
1173 if (mce_notify_irq())
1174 *n
= max(*n
/2, HZ
/100);
1176 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
1178 t
->expires
= jiffies
+ *n
;
1179 add_timer_on(t
, smp_processor_id());
1182 static void mce_do_trigger(struct work_struct
*work
)
1184 call_usermodehelper(mce_helper
, mce_helper_argv
, NULL
, UMH_NO_WAIT
);
1187 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
1190 * Notify the user(s) about new machine check events.
1191 * Can be called from interrupt context, but not from machine check/NMI
1194 int mce_notify_irq(void)
1196 /* Not more than two messages every minute */
1197 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
1199 clear_thread_flag(TIF_MCE_NOTIFY
);
1201 if (test_and_clear_bit(0, &mce_need_notify
)) {
1202 wake_up_interruptible(&mce_wait
);
1205 * There is no risk of missing notifications because
1206 * work_pending is always cleared before the function is
1209 if (mce_helper
[0] && !work_pending(&mce_trigger_work
))
1210 schedule_work(&mce_trigger_work
);
1212 if (__ratelimit(&ratelimit
))
1213 printk(KERN_INFO
"Machine check events logged\n");
1219 EXPORT_SYMBOL_GPL(mce_notify_irq
);
1221 static int __cpuinit
__mcheck_cpu_mce_banks_init(void)
1225 mce_banks
= kzalloc(banks
* sizeof(struct mce_bank
), GFP_KERNEL
);
1228 for (i
= 0; i
< banks
; i
++) {
1229 struct mce_bank
*b
= &mce_banks
[i
];
1238 * Initialize Machine Checks for a CPU.
1240 static int __cpuinit
__mcheck_cpu_cap_init(void)
1245 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1247 b
= cap
& MCG_BANKCNT_MASK
;
1249 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
1251 if (b
> MAX_NR_BANKS
) {
1253 "MCE: Using only %u machine check banks out of %u\n",
1258 /* Don't support asymmetric configurations today */
1259 WARN_ON(banks
!= 0 && b
!= banks
);
1262 int err
= __mcheck_cpu_mce_banks_init();
1268 /* Use accurate RIP reporting if available. */
1269 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
1270 rip_msr
= MSR_IA32_MCG_EIP
;
1272 if (cap
& MCG_SER_P
)
1278 static void __mcheck_cpu_init_generic(void)
1280 mce_banks_t all_banks
;
1285 * Log the machine checks left over from the previous reset.
1287 bitmap_fill(all_banks
, MAX_NR_BANKS
);
1288 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
1290 set_in_cr4(X86_CR4_MCE
);
1292 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
1293 if (cap
& MCG_CTL_P
)
1294 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
1296 for (i
= 0; i
< banks
; i
++) {
1297 struct mce_bank
*b
= &mce_banks
[i
];
1301 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
1302 wrmsrl(MSR_IA32_MCx_STATUS(i
), 0);
1306 /* Add per CPU specific workarounds here */
1307 static int __cpuinit
__mcheck_cpu_apply_quirks(struct cpuinfo_x86
*c
)
1309 if (c
->x86_vendor
== X86_VENDOR_UNKNOWN
) {
1310 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1314 /* This should be disabled by the BIOS, but isn't always */
1315 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
1316 if (c
->x86
== 15 && banks
> 4) {
1318 * disable GART TBL walk error reporting, which
1319 * trips off incorrectly with the IOMMU & 3ware
1322 clear_bit(10, (unsigned long *)&mce_banks
[4].ctl
);
1324 if (c
->x86
<= 17 && mce_bootlog
< 0) {
1326 * Lots of broken BIOS around that don't clear them
1327 * by default and leave crap in there. Don't log:
1332 * Various K7s with broken bank 0 around. Always disable
1335 if (c
->x86
== 6 && banks
> 0)
1336 mce_banks
[0].ctl
= 0;
1339 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
1341 * SDM documents that on family 6 bank 0 should not be written
1342 * because it aliases to another special BIOS controlled
1344 * But it's not aliased anymore on model 0x1a+
1345 * Don't ignore bank 0 completely because there could be a
1346 * valid event later, merely don't write CTL0.
1349 if (c
->x86
== 6 && c
->x86_model
< 0x1A && banks
> 0)
1350 mce_banks
[0].init
= 0;
1353 * All newer Intel systems support MCE broadcasting. Enable
1354 * synchronization with a one second timeout.
1356 if ((c
->x86
> 6 || (c
->x86
== 6 && c
->x86_model
>= 0xe)) &&
1357 monarch_timeout
< 0)
1358 monarch_timeout
= USEC_PER_SEC
;
1361 * There are also broken BIOSes on some Pentium M and
1364 if (c
->x86
== 6 && c
->x86_model
<= 13 && mce_bootlog
< 0)
1367 if (monarch_timeout
< 0)
1368 monarch_timeout
= 0;
1369 if (mce_bootlog
!= 0)
1370 mce_panic_timeout
= 30;
1375 static void __cpuinit
__mcheck_cpu_ancient_init(struct cpuinfo_x86
*c
)
1379 switch (c
->x86_vendor
) {
1380 case X86_VENDOR_INTEL
:
1381 intel_p5_mcheck_init(c
);
1383 case X86_VENDOR_CENTAUR
:
1384 winchip_mcheck_init(c
);
1389 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86
*c
)
1391 switch (c
->x86_vendor
) {
1392 case X86_VENDOR_INTEL
:
1393 mce_intel_feature_init(c
);
1395 case X86_VENDOR_AMD
:
1396 mce_amd_feature_init(c
);
1403 static void __mcheck_cpu_init_timer(void)
1405 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
1406 int *n
= &__get_cpu_var(mce_next_interval
);
1408 setup_timer(t
, mce_start_timer
, smp_processor_id());
1413 *n
= check_interval
* HZ
;
1416 t
->expires
= round_jiffies(jiffies
+ *n
);
1417 add_timer_on(t
, smp_processor_id());
1420 /* Handle unconfigured int18 (should never happen) */
1421 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
1423 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
1424 smp_processor_id());
1427 /* Call the installed machine check handler for this CPU setup. */
1428 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
1429 unexpected_machine_check
;
1432 * Called for each booted CPU to set up machine checks.
1433 * Must be called with preempt off:
1435 void __cpuinit
mcheck_cpu_init(struct cpuinfo_x86
*c
)
1440 __mcheck_cpu_ancient_init(c
);
1442 if (!mce_available(c
))
1445 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c
) < 0) {
1450 machine_check_vector
= do_machine_check
;
1452 __mcheck_cpu_init_generic();
1453 __mcheck_cpu_init_vendor(c
);
1454 __mcheck_cpu_init_timer();
1455 INIT_WORK(&__get_cpu_var(mce_work
), mce_process_work
);
1460 * Character device to read and clear the MCE log.
1463 static DEFINE_SPINLOCK(mce_state_lock
);
1464 static int open_count
; /* #times opened */
1465 static int open_exclu
; /* already open exclusive? */
1467 static int mce_open(struct inode
*inode
, struct file
*file
)
1469 spin_lock(&mce_state_lock
);
1471 if (open_exclu
|| (open_count
&& (file
->f_flags
& O_EXCL
))) {
1472 spin_unlock(&mce_state_lock
);
1477 if (file
->f_flags
& O_EXCL
)
1481 spin_unlock(&mce_state_lock
);
1483 return nonseekable_open(inode
, file
);
1486 static int mce_release(struct inode
*inode
, struct file
*file
)
1488 spin_lock(&mce_state_lock
);
1493 spin_unlock(&mce_state_lock
);
1498 static void collect_tscs(void *data
)
1500 unsigned long *cpu_tsc
= (unsigned long *)data
;
1502 rdtscll(cpu_tsc
[smp_processor_id()]);
1505 static int mce_apei_read_done
;
1507 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1508 static int __mce_read_apei(char __user
**ubuf
, size_t usize
)
1514 if (usize
< sizeof(struct mce
))
1517 rc
= apei_read_mce(&m
, &record_id
);
1518 /* Error or no more MCE record */
1520 mce_apei_read_done
= 1;
1524 if (copy_to_user(*ubuf
, &m
, sizeof(struct mce
)))
1527 * In fact, we should have cleared the record after that has
1528 * been flushed to the disk or sent to network in
1529 * /sbin/mcelog, but we have no interface to support that now,
1530 * so just clear it to avoid duplication.
1532 rc
= apei_clear_mce(record_id
);
1534 mce_apei_read_done
= 1;
1537 *ubuf
+= sizeof(struct mce
);
1542 static ssize_t
mce_read(struct file
*filp
, char __user
*ubuf
, size_t usize
,
1545 char __user
*buf
= ubuf
;
1546 unsigned long *cpu_tsc
;
1547 unsigned prev
, next
;
1550 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
1554 mutex_lock(&mce_read_mutex
);
1556 if (!mce_apei_read_done
) {
1557 err
= __mce_read_apei(&buf
, usize
);
1558 if (err
|| buf
!= ubuf
)
1562 next
= rcu_dereference_check_mce(mcelog
.next
);
1564 /* Only supports full reads right now */
1566 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
))
1572 for (i
= prev
; i
< next
; i
++) {
1573 unsigned long start
= jiffies
;
1575 while (!mcelog
.entry
[i
].finished
) {
1576 if (time_after_eq(jiffies
, start
+ 2)) {
1577 memset(mcelog
.entry
+ i
, 0,
1578 sizeof(struct mce
));
1584 err
|= copy_to_user(buf
, mcelog
.entry
+ i
,
1585 sizeof(struct mce
));
1586 buf
+= sizeof(struct mce
);
1591 memset(mcelog
.entry
+ prev
, 0,
1592 (next
- prev
) * sizeof(struct mce
));
1594 next
= cmpxchg(&mcelog
.next
, prev
, 0);
1595 } while (next
!= prev
);
1597 synchronize_sched();
1600 * Collect entries that were still getting written before the
1603 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1605 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1606 if (mcelog
.entry
[i
].finished
&&
1607 mcelog
.entry
[i
].tsc
< cpu_tsc
[mcelog
.entry
[i
].cpu
]) {
1608 err
|= copy_to_user(buf
, mcelog
.entry
+i
,
1609 sizeof(struct mce
));
1611 buf
+= sizeof(struct mce
);
1612 memset(&mcelog
.entry
[i
], 0, sizeof(struct mce
));
1620 mutex_unlock(&mce_read_mutex
);
1623 return err
? err
: buf
- ubuf
;
1626 static unsigned int mce_poll(struct file
*file
, poll_table
*wait
)
1628 poll_wait(file
, &mce_wait
, wait
);
1629 if (rcu_dereference_check_mce(mcelog
.next
))
1630 return POLLIN
| POLLRDNORM
;
1631 if (!mce_apei_read_done
&& apei_check_mce())
1632 return POLLIN
| POLLRDNORM
;
1636 static long mce_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
1638 int __user
*p
= (int __user
*)arg
;
1640 if (!capable(CAP_SYS_ADMIN
))
1644 case MCE_GET_RECORD_LEN
:
1645 return put_user(sizeof(struct mce
), p
);
1646 case MCE_GET_LOG_LEN
:
1647 return put_user(MCE_LOG_LEN
, p
);
1648 case MCE_GETCLEAR_FLAGS
: {
1652 flags
= mcelog
.flags
;
1653 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1655 return put_user(flags
, p
);
1662 /* Modified in mce-inject.c, so not static or const */
1663 struct file_operations mce_chrdev_ops
= {
1665 .release
= mce_release
,
1668 .unlocked_ioctl
= mce_ioctl
,
1670 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
1672 static struct miscdevice mce_log_device
= {
1679 * mce=off Disables machine check
1680 * mce=no_cmci Disables CMCI
1681 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1682 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1683 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1684 * monarchtimeout is how long to wait for other CPUs on machine
1685 * check, or 0 to not wait
1686 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1687 * mce=nobootlog Don't log MCEs from before booting.
1689 static int __init
mcheck_enable(char *str
)
1697 if (!strcmp(str
, "off"))
1699 else if (!strcmp(str
, "no_cmci"))
1700 mce_cmci_disabled
= 1;
1701 else if (!strcmp(str
, "dont_log_ce"))
1702 mce_dont_log_ce
= 1;
1703 else if (!strcmp(str
, "ignore_ce"))
1705 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1706 mce_bootlog
= (str
[0] == 'b');
1707 else if (isdigit(str
[0])) {
1708 get_option(&str
, &tolerant
);
1711 get_option(&str
, &monarch_timeout
);
1714 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1720 __setup("mce", mcheck_enable
);
1722 int __init
mcheck_init(void)
1724 atomic_notifier_chain_register(&x86_mce_decoder_chain
, &mce_dec_nb
);
1726 mcheck_intel_therm_init();
1736 * Disable machine checks on suspend and shutdown. We can't really handle
1739 static int mce_disable_error_reporting(void)
1743 for (i
= 0; i
< banks
; i
++) {
1744 struct mce_bank
*b
= &mce_banks
[i
];
1747 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
1752 static int mce_suspend(struct sys_device
*dev
, pm_message_t state
)
1754 return mce_disable_error_reporting();
1757 static int mce_shutdown(struct sys_device
*dev
)
1759 return mce_disable_error_reporting();
1763 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1764 * Only one CPU is active at this time, the others get re-added later using
1767 static int mce_resume(struct sys_device
*dev
)
1769 __mcheck_cpu_init_generic();
1770 __mcheck_cpu_init_vendor(¤t_cpu_data
);
1775 static void mce_cpu_restart(void *data
)
1777 del_timer_sync(&__get_cpu_var(mce_timer
));
1778 if (!mce_available(¤t_cpu_data
))
1780 __mcheck_cpu_init_generic();
1781 __mcheck_cpu_init_timer();
1784 /* Reinit MCEs after user configuration changes */
1785 static void mce_restart(void)
1787 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1790 /* Toggle features for corrected errors */
1791 static void mce_disable_ce(void *all
)
1793 if (!mce_available(¤t_cpu_data
))
1796 del_timer_sync(&__get_cpu_var(mce_timer
));
1800 static void mce_enable_ce(void *all
)
1802 if (!mce_available(¤t_cpu_data
))
1807 __mcheck_cpu_init_timer();
1810 static struct sysdev_class mce_sysclass
= {
1811 .suspend
= mce_suspend
,
1812 .shutdown
= mce_shutdown
,
1813 .resume
= mce_resume
,
1814 .name
= "machinecheck",
1817 DEFINE_PER_CPU(struct sys_device
, mce_dev
);
1820 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1822 static inline struct mce_bank
*attr_to_bank(struct sysdev_attribute
*attr
)
1824 return container_of(attr
, struct mce_bank
, attr
);
1827 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1830 return sprintf(buf
, "%llx\n", attr_to_bank(attr
)->ctl
);
1833 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1834 const char *buf
, size_t size
)
1838 if (strict_strtoull(buf
, 0, &new) < 0)
1841 attr_to_bank(attr
)->ctl
= new;
1848 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1850 strcpy(buf
, mce_helper
);
1852 return strlen(mce_helper
) + 1;
1855 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1856 const char *buf
, size_t siz
)
1860 strncpy(mce_helper
, buf
, sizeof(mce_helper
));
1861 mce_helper
[sizeof(mce_helper
)-1] = 0;
1862 p
= strchr(mce_helper
, '\n');
1867 return strlen(mce_helper
) + !!p
;
1870 static ssize_t
set_ignore_ce(struct sys_device
*s
,
1871 struct sysdev_attribute
*attr
,
1872 const char *buf
, size_t size
)
1876 if (strict_strtoull(buf
, 0, &new) < 0)
1879 if (mce_ignore_ce
^ !!new) {
1881 /* disable ce features */
1882 on_each_cpu(mce_disable_ce
, (void *)1, 1);
1885 /* enable ce features */
1887 on_each_cpu(mce_enable_ce
, (void *)1, 1);
1893 static ssize_t
set_cmci_disabled(struct sys_device
*s
,
1894 struct sysdev_attribute
*attr
,
1895 const char *buf
, size_t size
)
1899 if (strict_strtoull(buf
, 0, &new) < 0)
1902 if (mce_cmci_disabled
^ !!new) {
1905 on_each_cpu(mce_disable_ce
, NULL
, 1);
1906 mce_cmci_disabled
= 1;
1909 mce_cmci_disabled
= 0;
1910 on_each_cpu(mce_enable_ce
, NULL
, 1);
1916 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1917 struct sysdev_attribute
*attr
,
1918 const char *buf
, size_t size
)
1920 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1925 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1926 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1927 static SYSDEV_INT_ATTR(monarch_timeout
, 0644, monarch_timeout
);
1928 static SYSDEV_INT_ATTR(dont_log_ce
, 0644, mce_dont_log_ce
);
1930 static struct sysdev_ext_attribute attr_check_interval
= {
1931 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1932 store_int_with_restart
),
1936 static struct sysdev_ext_attribute attr_ignore_ce
= {
1937 _SYSDEV_ATTR(ignore_ce
, 0644, sysdev_show_int
, set_ignore_ce
),
1941 static struct sysdev_ext_attribute attr_cmci_disabled
= {
1942 _SYSDEV_ATTR(cmci_disabled
, 0644, sysdev_show_int
, set_cmci_disabled
),
1946 static struct sysdev_attribute
*mce_attrs
[] = {
1947 &attr_tolerant
.attr
,
1948 &attr_check_interval
.attr
,
1950 &attr_monarch_timeout
.attr
,
1951 &attr_dont_log_ce
.attr
,
1952 &attr_ignore_ce
.attr
,
1953 &attr_cmci_disabled
.attr
,
1957 static cpumask_var_t mce_dev_initialized
;
1959 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1960 static __cpuinit
int mce_create_device(unsigned int cpu
)
1965 if (!mce_available(&boot_cpu_data
))
1968 memset(&per_cpu(mce_dev
, cpu
).kobj
, 0, sizeof(struct kobject
));
1969 per_cpu(mce_dev
, cpu
).id
= cpu
;
1970 per_cpu(mce_dev
, cpu
).cls
= &mce_sysclass
;
1972 err
= sysdev_register(&per_cpu(mce_dev
, cpu
));
1976 for (i
= 0; mce_attrs
[i
]; i
++) {
1977 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1981 for (j
= 0; j
< banks
; j
++) {
1982 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
),
1983 &mce_banks
[j
].attr
);
1987 cpumask_set_cpu(cpu
, mce_dev_initialized
);
1992 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &mce_banks
[j
].attr
);
1995 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1997 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
2002 static __cpuinit
void mce_remove_device(unsigned int cpu
)
2006 if (!cpumask_test_cpu(cpu
, mce_dev_initialized
))
2009 for (i
= 0; mce_attrs
[i
]; i
++)
2010 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
2012 for (i
= 0; i
< banks
; i
++)
2013 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &mce_banks
[i
].attr
);
2015 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
2016 cpumask_clear_cpu(cpu
, mce_dev_initialized
);
2019 /* Make sure there are no machine checks on offlined CPUs. */
2020 static void __cpuinit
mce_disable_cpu(void *h
)
2022 unsigned long action
= *(unsigned long *)h
;
2025 if (!mce_available(¤t_cpu_data
))
2028 if (!(action
& CPU_TASKS_FROZEN
))
2030 for (i
= 0; i
< banks
; i
++) {
2031 struct mce_bank
*b
= &mce_banks
[i
];
2034 wrmsrl(MSR_IA32_MCx_CTL(i
), 0);
2038 static void __cpuinit
mce_reenable_cpu(void *h
)
2040 unsigned long action
= *(unsigned long *)h
;
2043 if (!mce_available(¤t_cpu_data
))
2046 if (!(action
& CPU_TASKS_FROZEN
))
2048 for (i
= 0; i
< banks
; i
++) {
2049 struct mce_bank
*b
= &mce_banks
[i
];
2052 wrmsrl(MSR_IA32_MCx_CTL(i
), b
->ctl
);
2056 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2057 static int __cpuinit
2058 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
2060 unsigned int cpu
= (unsigned long)hcpu
;
2061 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
2065 case CPU_ONLINE_FROZEN
:
2066 mce_create_device(cpu
);
2067 if (threshold_cpu_callback
)
2068 threshold_cpu_callback(action
, cpu
);
2071 case CPU_DEAD_FROZEN
:
2072 if (threshold_cpu_callback
)
2073 threshold_cpu_callback(action
, cpu
);
2074 mce_remove_device(cpu
);
2076 case CPU_DOWN_PREPARE
:
2077 case CPU_DOWN_PREPARE_FROZEN
:
2079 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
2081 case CPU_DOWN_FAILED
:
2082 case CPU_DOWN_FAILED_FROZEN
:
2083 if (!mce_ignore_ce
&& check_interval
) {
2084 t
->expires
= round_jiffies(jiffies
+
2085 __get_cpu_var(mce_next_interval
));
2086 add_timer_on(t
, cpu
);
2088 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
2091 /* intentionally ignoring frozen here */
2092 cmci_rediscover(cpu
);
2098 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
2099 .notifier_call
= mce_cpu_callback
,
2102 static __init
void mce_init_banks(void)
2106 for (i
= 0; i
< banks
; i
++) {
2107 struct mce_bank
*b
= &mce_banks
[i
];
2108 struct sysdev_attribute
*a
= &b
->attr
;
2110 sysfs_attr_init(&a
->attr
);
2111 a
->attr
.name
= b
->attrname
;
2112 snprintf(b
->attrname
, ATTR_LEN
, "bank%d", i
);
2114 a
->attr
.mode
= 0644;
2115 a
->show
= show_bank
;
2116 a
->store
= set_bank
;
2120 static __init
int mcheck_init_device(void)
2125 if (!mce_available(&boot_cpu_data
))
2128 zalloc_cpumask_var(&mce_dev_initialized
, GFP_KERNEL
);
2132 err
= sysdev_class_register(&mce_sysclass
);
2136 for_each_online_cpu(i
) {
2137 err
= mce_create_device(i
);
2142 register_hotcpu_notifier(&mce_cpu_notifier
);
2143 misc_register(&mce_log_device
);
2148 device_initcall(mcheck_init_device
);
2151 * Old style boot options parsing. Only for compatibility.
2153 static int __init
mcheck_disable(char *str
)
2158 __setup("nomce", mcheck_disable
);
2160 #ifdef CONFIG_DEBUG_FS
2161 struct dentry
*mce_get_debugfs_dir(void)
2163 static struct dentry
*dmce
;
2166 dmce
= debugfs_create_dir("mce", NULL
);
2171 static void mce_reset(void)
2174 atomic_set(&mce_fake_paniced
, 0);
2175 atomic_set(&mce_executing
, 0);
2176 atomic_set(&mce_callin
, 0);
2177 atomic_set(&global_nwo
, 0);
2180 static int fake_panic_get(void *data
, u64
*val
)
2186 static int fake_panic_set(void *data
, u64 val
)
2193 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops
, fake_panic_get
,
2194 fake_panic_set
, "%llu\n");
2196 static int __init
mcheck_debugfs_init(void)
2198 struct dentry
*dmce
, *ffake_panic
;
2200 dmce
= mce_get_debugfs_dir();
2203 ffake_panic
= debugfs_create_file("fake_panic", 0444, dmce
, NULL
,
2210 late_initcall(mcheck_debugfs_init
);