projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
locking, lockdep: Convert sprintf_symbol to %pS
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / cpu / intel_cacheinfo.c
1 /*
2 * Routines to indentify caches on Intel CPU.
3 *
4 * Changes:
5 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
6 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
7 * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
8 */
9
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/compiler.h>
14 #include <linux/cpu.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
17
18 #include <asm/processor.h>
19 #include <linux/smp.h>
20 #include <asm/amd_nb.h>
21 #include <asm/smp.h>
22
23 #define LVL_1_INST 1
24 #define LVL_1_DATA 2
25 #define LVL_2 3
26 #define LVL_3 4
27 #define LVL_TRACE 5
28
29 struct _cache_table {
30 unsigned char descriptor;
31 char cache_type;
32 short size;
33 };
34
35 #define MB(x) ((x) * 1024)
36
37 /* All the cache descriptor types we care about (no TLB or
38 trace cache entries) */
39
40 static const struct _cache_table __cpuinitconst cache_table[] =
41 {
42 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
43 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
44 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
45 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
46 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
47 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
48 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
49 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
50 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
51 { 0x25, LVL_3, MB(2) }, /* 8-way set assoc, sectored cache, 64 byte line size */
52 { 0x29, LVL_3, MB(4) }, /* 8-way set assoc, sectored cache, 64 byte line size */
53 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
54 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
55 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
56 { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
57 { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
58 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
59 { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
60 { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
61 { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */
62 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
63 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
64 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
65 { 0x44, LVL_2, MB(1) }, /* 4-way set assoc, 32 byte line size */
66 { 0x45, LVL_2, MB(2) }, /* 4-way set assoc, 32 byte line size */
67 { 0x46, LVL_3, MB(4) }, /* 4-way set assoc, 64 byte line size */
68 { 0x47, LVL_3, MB(8) }, /* 8-way set assoc, 64 byte line size */
69 { 0x49, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
70 { 0x4a, LVL_3, MB(6) }, /* 12-way set assoc, 64 byte line size */
71 { 0x4b, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
72 { 0x4c, LVL_3, MB(12) }, /* 12-way set assoc, 64 byte line size */
73 { 0x4d, LVL_3, MB(16) }, /* 16-way set assoc, 64 byte line size */
74 { 0x4e, LVL_2, MB(6) }, /* 24-way set assoc, 64 byte line size */
75 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
76 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
77 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
78 { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
79 { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
80 { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
81 { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
82 { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
83 { 0x78, LVL_2, MB(1) }, /* 4-way set assoc, 64 byte line size */
84 { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
85 { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
86 { 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
87 { 0x7c, LVL_2, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
88 { 0x7d, LVL_2, MB(2) }, /* 8-way set assoc, 64 byte line size */
89 { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
90 { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
91 { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
92 { 0x84, LVL_2, MB(1) }, /* 8-way set assoc, 32 byte line size */
93 { 0x85, LVL_2, MB(2) }, /* 8-way set assoc, 32 byte line size */
94 { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
95 { 0x87, LVL_2, MB(1) }, /* 8-way set assoc, 64 byte line size */
96 { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */
97 { 0xd1, LVL_3, MB(1) }, /* 4-way set assoc, 64 byte line size */
98 { 0xd2, LVL_3, MB(2) }, /* 4-way set assoc, 64 byte line size */
99 { 0xd6, LVL_3, MB(1) }, /* 8-way set assoc, 64 byte line size */
100 { 0xd7, LVL_3, MB(2) }, /* 8-way set assoc, 64 byte line size */
101 { 0xd8, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
102 { 0xdc, LVL_3, MB(2) }, /* 12-way set assoc, 64 byte line size */
103 { 0xdd, LVL_3, MB(4) }, /* 12-way set assoc, 64 byte line size */
104 { 0xde, LVL_3, MB(8) }, /* 12-way set assoc, 64 byte line size */
105 { 0xe2, LVL_3, MB(2) }, /* 16-way set assoc, 64 byte line size */
106 { 0xe3, LVL_3, MB(4) }, /* 16-way set assoc, 64 byte line size */
107 { 0xe4, LVL_3, MB(8) }, /* 16-way set assoc, 64 byte line size */
108 { 0xea, LVL_3, MB(12) }, /* 24-way set assoc, 64 byte line size */
109 { 0xeb, LVL_3, MB(18) }, /* 24-way set assoc, 64 byte line size */
110 { 0xec, LVL_3, MB(24) }, /* 24-way set assoc, 64 byte line size */
111 { 0x00, 0, 0}
112 };
113
114
115 enum _cache_type {
116 CACHE_TYPE_NULL = 0,
117 CACHE_TYPE_DATA = 1,
118 CACHE_TYPE_INST = 2,
119 CACHE_TYPE_UNIFIED = 3
120 };
121
122 union _cpuid4_leaf_eax {
123 struct {
124 enum _cache_type type:5;
125 unsigned int level:3;
126 unsigned int is_self_initializing:1;
127 unsigned int is_fully_associative:1;
128 unsigned int reserved:4;
129 unsigned int num_threads_sharing:12;
130 unsigned int num_cores_on_die:6;
131 } split;
132 u32 full;
133 };
134
135 union _cpuid4_leaf_ebx {
136 struct {
137 unsigned int coherency_line_size:12;
138 unsigned int physical_line_partition:10;
139 unsigned int ways_of_associativity:10;
140 } split;
141 u32 full;
142 };
143
144 union _cpuid4_leaf_ecx {
145 struct {
146 unsigned int number_of_sets:32;
147 } split;
148 u32 full;
149 };
150
151 struct amd_l3_cache {
152 struct pci_dev *dev;
153 bool can_disable;
154 unsigned indices;
155 u8 subcaches[4];
156 };
157
158 struct _cpuid4_info {
159 union _cpuid4_leaf_eax eax;
160 union _cpuid4_leaf_ebx ebx;
161 union _cpuid4_leaf_ecx ecx;
162 unsigned long size;
163 struct amd_l3_cache *l3;
164 DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
165 };
166
167 /* subset of above _cpuid4_info w/o shared_cpu_map */
168 struct _cpuid4_info_regs {
169 union _cpuid4_leaf_eax eax;
170 union _cpuid4_leaf_ebx ebx;
171 union _cpuid4_leaf_ecx ecx;
172 unsigned long size;
173 struct amd_l3_cache *l3;
174 };
175
176 unsigned short num_cache_leaves;
177
178 /* AMD doesn't have CPUID4. Emulate it here to report the same
179 information to the user. This makes some assumptions about the machine:
180 L2 not shared, no SMT etc. that is currently true on AMD CPUs.
181
182 In theory the TLBs could be reported as fake type (they are in "dummy").
183 Maybe later */
184 union l1_cache {
185 struct {
186 unsigned line_size:8;
187 unsigned lines_per_tag:8;
188 unsigned assoc:8;
189 unsigned size_in_kb:8;
190 };
191 unsigned val;
192 };
193
194 union l2_cache {
195 struct {
196 unsigned line_size:8;
197 unsigned lines_per_tag:4;
198 unsigned assoc:4;
199 unsigned size_in_kb:16;
200 };
201 unsigned val;
202 };
203
204 union l3_cache {
205 struct {
206 unsigned line_size:8;
207 unsigned lines_per_tag:4;
208 unsigned assoc:4;
209 unsigned res:2;
210 unsigned size_encoded:14;
211 };
212 unsigned val;
213 };
214
215 static const unsigned short __cpuinitconst assocs[] = {
216 [1] = 1,
217 [2] = 2,
218 [4] = 4,
219 [6] = 8,
220 [8] = 16,
221 [0xa] = 32,
222 [0xb] = 48,
223 [0xc] = 64,
224 [0xd] = 96,
225 [0xe] = 128,
226 [0xf] = 0xffff /* fully associative - no way to show this currently */
227 };
228
229 static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
230 static const unsigned char __cpuinitconst types[] = { 1, 2, 3, 3 };
231
232 static void __cpuinit
233 amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
234 union _cpuid4_leaf_ebx *ebx,
235 union _cpuid4_leaf_ecx *ecx)
236 {
237 unsigned dummy;
238 unsigned line_size, lines_per_tag, assoc, size_in_kb;
239 union l1_cache l1i, l1d;
240 union l2_cache l2;
241 union l3_cache l3;
242 union l1_cache *l1 = &l1d;
243
244 eax->full = 0;
245 ebx->full = 0;
246 ecx->full = 0;
247
248 cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
249 cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
250
251 switch (leaf) {
252 case 1:
253 l1 = &l1i;
254 case 0:
255 if (!l1->val)
256 return;
257 assoc = assocs[l1->assoc];
258 line_size = l1->line_size;
259 lines_per_tag = l1->lines_per_tag;
260 size_in_kb = l1->size_in_kb;
261 break;
262 case 2:
263 if (!l2.val)
264 return;
265 assoc = assocs[l2.assoc];
266 line_size = l2.line_size;
267 lines_per_tag = l2.lines_per_tag;
268 /* cpu_data has errata corrections for K7 applied */
269 size_in_kb = current_cpu_data.x86_cache_size;
270 break;
271 case 3:
272 if (!l3.val)
273 return;
274 assoc = assocs[l3.assoc];
275 line_size = l3.line_size;
276 lines_per_tag = l3.lines_per_tag;
277 size_in_kb = l3.size_encoded * 512;
278 if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
279 size_in_kb = size_in_kb >> 1;
280 assoc = assoc >> 1;
281 }
282 break;
283 default:
284 return;
285 }
286
287 eax->split.is_self_initializing = 1;
288 eax->split.type = types[leaf];
289 eax->split.level = levels[leaf];
290 eax->split.num_threads_sharing = 0;
291 eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
292
293
294 if (assoc == 0xffff)
295 eax->split.is_fully_associative = 1;
296 ebx->split.coherency_line_size = line_size - 1;
297 ebx->split.ways_of_associativity = assoc - 1;
298 ebx->split.physical_line_partition = lines_per_tag - 1;
299 ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
300 (ebx->split.ways_of_associativity + 1) - 1;
301 }
302
303 struct _cache_attr {
304 struct attribute attr;
305 ssize_t (*show)(struct _cpuid4_info *, char *);
306 ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
307 };
308
309 #ifdef CONFIG_AMD_NB
310
311 /*
312 * L3 cache descriptors
313 */
314 static struct amd_l3_cache **__cpuinitdata l3_caches;
315
316 static void __cpuinit amd_calc_l3_indices(struct amd_l3_cache *l3)
317 {
318 unsigned int sc0, sc1, sc2, sc3;
319 u32 val = 0;
320
321 pci_read_config_dword(l3->dev, 0x1C4, &val);
322
323 /* calculate subcache sizes */
324 l3->subcaches[0] = sc0 = !(val & BIT(0));
325 l3->subcaches[1] = sc1 = !(val & BIT(4));
326 l3->subcaches[2] = sc2 = !(val & BIT(8)) + !(val & BIT(9));
327 l3->subcaches[3] = sc3 = !(val & BIT(12)) + !(val & BIT(13));
328
329 l3->indices = (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
330 l3->indices = (max(max3(sc0, sc1, sc2), sc3) << 10) - 1;
331 }
332
333 static struct amd_l3_cache * __cpuinit amd_init_l3_cache(int node)
334 {
335 struct amd_l3_cache *l3;
336 struct pci_dev *dev = node_to_k8_nb_misc(node);
337
338 l3 = kzalloc(sizeof(struct amd_l3_cache), GFP_ATOMIC);
339 if (!l3) {
340 printk(KERN_WARNING "Error allocating L3 struct\n");
341 return NULL;
342 }
343
344 l3->dev = dev;
345
346 amd_calc_l3_indices(l3);
347
348 return l3;
349 }
350
351 static void __cpuinit amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf,
352 int index)
353 {
354 int node;
355
356 if (boot_cpu_data.x86 != 0x10)
357 return;
358
359 if (index < 3)
360 return;
361
362 /* see errata #382 and #388 */
363 if (boot_cpu_data.x86_model < 0x8)
364 return;
365
366 if ((boot_cpu_data.x86_model == 0x8 ||
367 boot_cpu_data.x86_model == 0x9)
368 &&
369 boot_cpu_data.x86_mask < 0x1)
370 return;
371
372 /* not in virtualized environments */
373 if (k8_northbridges.num == 0)
374 return;
375
376 /*
377 * Strictly speaking, the amount in @size below is leaked since it is
378 * never freed but this is done only on shutdown so it doesn't matter.
379 */
380 if (!l3_caches) {
381 int size = k8_northbridges.num * sizeof(struct amd_l3_cache *);
382
383 l3_caches = kzalloc(size, GFP_ATOMIC);
384 if (!l3_caches)
385 return;
386 }
387
388 node = amd_get_nb_id(smp_processor_id());
389
390 if (!l3_caches[node]) {
391 l3_caches[node] = amd_init_l3_cache(node);
392 l3_caches[node]->can_disable = true;
393 }
394
395 WARN_ON(!l3_caches[node]);
396
397 this_leaf->l3 = l3_caches[node];
398 }
399
400 /*
401 * check whether a slot used for disabling an L3 index is occupied.
402 * @l3: L3 cache descriptor
403 * @slot: slot number (0..1)
404 *
405 * @returns: the disabled index if used or negative value if slot free.
406 */
407 int amd_get_l3_disable_slot(struct amd_l3_cache *l3, unsigned slot)
408 {
409 unsigned int reg = 0;
410
411 pci_read_config_dword(l3->dev, 0x1BC + slot * 4, &reg);
412
413 /* check whether this slot is activated already */
414 if (reg & (3UL << 30))
415 return reg & 0xfff;
416
417 return -1;
418 }
419
420 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
421 unsigned int slot)
422 {
423 int index;
424
425 if (!this_leaf->l3 || !this_leaf->l3->can_disable)
426 return -EINVAL;
427
428 index = amd_get_l3_disable_slot(this_leaf->l3, slot);
429 if (index >= 0)
430 return sprintf(buf, "%d\n", index);
431
432 return sprintf(buf, "FREE\n");
433 }
434
435 #define SHOW_CACHE_DISABLE(slot) \
436 static ssize_t \
437 show_cache_disable_##slot(struct _cpuid4_info *this_leaf, char *buf) \
438 { \
439 return show_cache_disable(this_leaf, buf, slot); \
440 }
441 SHOW_CACHE_DISABLE(0)
442 SHOW_CACHE_DISABLE(1)
443
444 static void amd_l3_disable_index(struct amd_l3_cache *l3, int cpu,
445 unsigned slot, unsigned long idx)
446 {
447 int i;
448
449 idx |= BIT(30);
450
451 /*
452 * disable index in all 4 subcaches
453 */
454 for (i = 0; i < 4; i++) {
455 u32 reg = idx | (i << 20);
456
457 if (!l3->subcaches[i])
458 continue;
459
460 pci_write_config_dword(l3->dev, 0x1BC + slot * 4, reg);
461
462 /*
463 * We need to WBINVD on a core on the node containing the L3
464 * cache which indices we disable therefore a simple wbinvd()
465 * is not sufficient.
466 */
467 wbinvd_on_cpu(cpu);
468
469 reg |= BIT(31);
470 pci_write_config_dword(l3->dev, 0x1BC + slot * 4, reg);
471 }
472 }
473
474 /*
475 * disable a L3 cache index by using a disable-slot
476 *
477 * @l3: L3 cache descriptor
478 * @cpu: A CPU on the node containing the L3 cache
479 * @slot: slot number (0..1)
480 * @index: index to disable
481 *
482 * @return: 0 on success, error status on failure
483 */
484 int amd_set_l3_disable_slot(struct amd_l3_cache *l3, int cpu, unsigned slot,
485 unsigned long index)
486 {
487 int ret = 0;
488
489 #define SUBCACHE_MASK (3UL << 20)
490 #define SUBCACHE_INDEX 0xfff
491
492 /*
493 * check whether this slot is already used or
494 * the index is already disabled
495 */
496 ret = amd_get_l3_disable_slot(l3, slot);
497 if (ret >= 0)
498 return -EINVAL;
499
500 /*
501 * check whether the other slot has disabled the
502 * same index already
503 */
504 if (index == amd_get_l3_disable_slot(l3, !slot))
505 return -EINVAL;
506
507 /* do not allow writes outside of allowed bits */
508 if ((index & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
509 ((index & SUBCACHE_INDEX) > l3->indices))
510 return -EINVAL;
511
512 amd_l3_disable_index(l3, cpu, slot, index);
513
514 return 0;
515 }
516
517 static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
518 const char *buf, size_t count,
519 unsigned int slot)
520 {
521 unsigned long val = 0;
522 int cpu, err = 0;
523
524 if (!capable(CAP_SYS_ADMIN))
525 return -EPERM;
526
527 if (!this_leaf->l3 || !this_leaf->l3->can_disable)
528 return -EINVAL;
529
530 cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
531
532 if (strict_strtoul(buf, 10, &val) < 0)
533 return -EINVAL;
534
535 err = amd_set_l3_disable_slot(this_leaf->l3, cpu, slot, val);
536 if (err) {
537 if (err == -EEXIST)
538 printk(KERN_WARNING "L3 disable slot %d in use!\n",
539 slot);
540 return err;
541 }
542 return count;
543 }
544
545 #define STORE_CACHE_DISABLE(slot) \
546 static ssize_t \
547 store_cache_disable_##slot(struct _cpuid4_info *this_leaf, \
548 const char *buf, size_t count) \
549 { \
550 return store_cache_disable(this_leaf, buf, count, slot); \
551 }
552 STORE_CACHE_DISABLE(0)
553 STORE_CACHE_DISABLE(1)
554
555 static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
556 show_cache_disable_0, store_cache_disable_0);
557 static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
558 show_cache_disable_1, store_cache_disable_1);
559
560 #else /* CONFIG_AMD_NB */
561 static void __cpuinit
562 amd_check_l3_disable(struct _cpuid4_info_regs *this_leaf, int index)
563 {
564 };
565 #endif /* CONFIG_AMD_NB */
566
567 static int
568 __cpuinit cpuid4_cache_lookup_regs(int index,
569 struct _cpuid4_info_regs *this_leaf)
570 {
571 union _cpuid4_leaf_eax eax;
572 union _cpuid4_leaf_ebx ebx;
573 union _cpuid4_leaf_ecx ecx;
574 unsigned edx;
575
576 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
577 amd_cpuid4(index, &eax, &ebx, &ecx);
578 amd_check_l3_disable(this_leaf, index);
579 } else {
580 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
581 }
582
583 if (eax.split.type == CACHE_TYPE_NULL)
584 return -EIO; /* better error ? */
585
586 this_leaf->eax = eax;
587 this_leaf->ebx = ebx;
588 this_leaf->ecx = ecx;
589 this_leaf->size = (ecx.split.number_of_sets + 1) *
590 (ebx.split.coherency_line_size + 1) *
591 (ebx.split.physical_line_partition + 1) *
592 (ebx.split.ways_of_associativity + 1);
593 return 0;
594 }
595
596 static int __cpuinit find_num_cache_leaves(void)
597 {
598 unsigned int eax, ebx, ecx, edx;
599 union _cpuid4_leaf_eax cache_eax;
600 int i = -1;
601
602 do {
603 ++i;
604 /* Do cpuid(4) loop to find out num_cache_leaves */
605 cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
606 cache_eax.full = eax;
607 } while (cache_eax.split.type != CACHE_TYPE_NULL);
608 return i;
609 }
610
611 unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
612 {
613 /* Cache sizes */
614 unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
615 unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
616 unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
617 unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
618 #ifdef CONFIG_X86_HT
619 unsigned int cpu = c->cpu_index;
620 #endif
621
622 if (c->cpuid_level > 3) {
623 static int is_initialized;
624
625 if (is_initialized == 0) {
626 /* Init num_cache_leaves from boot CPU */
627 num_cache_leaves = find_num_cache_leaves();
628 is_initialized++;
629 }
630
631 /*
632 * Whenever possible use cpuid(4), deterministic cache
633 * parameters cpuid leaf to find the cache details
634 */
635 for (i = 0; i < num_cache_leaves; i++) {
636 struct _cpuid4_info_regs this_leaf;
637 int retval;
638
639 retval = cpuid4_cache_lookup_regs(i, &this_leaf);
640 if (retval >= 0) {
641 switch (this_leaf.eax.split.level) {
642 case 1:
643 if (this_leaf.eax.split.type ==
644 CACHE_TYPE_DATA)
645 new_l1d = this_leaf.size/1024;
646 else if (this_leaf.eax.split.type ==
647 CACHE_TYPE_INST)
648 new_l1i = this_leaf.size/1024;
649 break;
650 case 2:
651 new_l2 = this_leaf.size/1024;
652 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
653 index_msb = get_count_order(num_threads_sharing);
654 l2_id = c->apicid >> index_msb;
655 break;
656 case 3:
657 new_l3 = this_leaf.size/1024;
658 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
659 index_msb = get_count_order(
660 num_threads_sharing);
661 l3_id = c->apicid >> index_msb;
662 break;
663 default:
664 break;
665 }
666 }
667 }
668 }
669 /*
670 * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
671 * trace cache
672 */
673 if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
674 /* supports eax=2 call */
675 int j, n;
676 unsigned int regs[4];
677 unsigned char *dp = (unsigned char *)regs;
678 int only_trace = 0;
679
680 if (num_cache_leaves != 0 && c->x86 == 15)
681 only_trace = 1;
682
683 /* Number of times to iterate */
684 n = cpuid_eax(2) & 0xFF;
685
686 for (i = 0 ; i < n ; i++) {
687 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
688
689 /* If bit 31 is set, this is an unknown format */
690 for (j = 0 ; j < 3 ; j++)
691 if (regs[j] & (1 << 31))
692 regs[j] = 0;
693
694 /* Byte 0 is level count, not a descriptor */
695 for (j = 1 ; j < 16 ; j++) {
696 unsigned char des = dp[j];
697 unsigned char k = 0;
698
699 /* look up this descriptor in the table */
700 while (cache_table[k].descriptor != 0) {
701 if (cache_table[k].descriptor == des) {
702 if (only_trace && cache_table[k].cache_type != LVL_TRACE)
703 break;
704 switch (cache_table[k].cache_type) {
705 case LVL_1_INST:
706 l1i += cache_table[k].size;
707 break;
708 case LVL_1_DATA:
709 l1d += cache_table[k].size;
710 break;
711 case LVL_2:
712 l2 += cache_table[k].size;
713 break;
714 case LVL_3:
715 l3 += cache_table[k].size;
716 break;
717 case LVL_TRACE:
718 trace += cache_table[k].size;
719 break;
720 }
721
722 break;
723 }
724
725 k++;
726 }
727 }
728 }
729 }
730
731 if (new_l1d)
732 l1d = new_l1d;
733
734 if (new_l1i)
735 l1i = new_l1i;
736
737 if (new_l2) {
738 l2 = new_l2;
739 #ifdef CONFIG_X86_HT
740 per_cpu(cpu_llc_id, cpu) = l2_id;
741 #endif
742 }
743
744 if (new_l3) {
745 l3 = new_l3;
746 #ifdef CONFIG_X86_HT
747 per_cpu(cpu_llc_id, cpu) = l3_id;
748 #endif
749 }
750
751 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
752
753 return l2;
754 }
755
756 #ifdef CONFIG_SYSFS
757
758 /* pointer to _cpuid4_info array (for each cache leaf) */
759 static DEFINE_PER_CPU(struct _cpuid4_info *, ici_cpuid4_info);
760 #define CPUID4_INFO_IDX(x, y) (&((per_cpu(ici_cpuid4_info, x))[y]))
761
762 #ifdef CONFIG_SMP
763 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
764 {
765 struct _cpuid4_info *this_leaf, *sibling_leaf;
766 unsigned long num_threads_sharing;
767 int index_msb, i, sibling;
768 struct cpuinfo_x86 *c = &cpu_data(cpu);
769
770 if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
771 for_each_cpu(i, c->llc_shared_map) {
772 if (!per_cpu(ici_cpuid4_info, i))
773 continue;
774 this_leaf = CPUID4_INFO_IDX(i, index);
775 for_each_cpu(sibling, c->llc_shared_map) {
776 if (!cpu_online(sibling))
777 continue;
778 set_bit(sibling, this_leaf->shared_cpu_map);
779 }
780 }
781 return;
782 }
783 this_leaf = CPUID4_INFO_IDX(cpu, index);
784 num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
785
786 if (num_threads_sharing == 1)
787 cpumask_set_cpu(cpu, to_cpumask(this_leaf->shared_cpu_map));
788 else {
789 index_msb = get_count_order(num_threads_sharing);
790
791 for_each_online_cpu(i) {
792 if (cpu_data(i).apicid >> index_msb ==
793 c->apicid >> index_msb) {
794 cpumask_set_cpu(i,
795 to_cpumask(this_leaf->shared_cpu_map));
796 if (i != cpu && per_cpu(ici_cpuid4_info, i)) {
797 sibling_leaf =
798 CPUID4_INFO_IDX(i, index);
799 cpumask_set_cpu(cpu, to_cpumask(
800 sibling_leaf->shared_cpu_map));
801 }
802 }
803 }
804 }
805 }
806 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
807 {
808 struct _cpuid4_info *this_leaf, *sibling_leaf;
809 int sibling;
810
811 this_leaf = CPUID4_INFO_IDX(cpu, index);
812 for_each_cpu(sibling, to_cpumask(this_leaf->shared_cpu_map)) {
813 sibling_leaf = CPUID4_INFO_IDX(sibling, index);
814 cpumask_clear_cpu(cpu,
815 to_cpumask(sibling_leaf->shared_cpu_map));
816 }
817 }
818 #else
819 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
820 {
821 }
822
823 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
824 {
825 }
826 #endif
827
828 static void __cpuinit free_cache_attributes(unsigned int cpu)
829 {
830 int i;
831
832 for (i = 0; i < num_cache_leaves; i++)
833 cache_remove_shared_cpu_map(cpu, i);
834
835 kfree(per_cpu(ici_cpuid4_info, cpu)->l3);
836 kfree(per_cpu(ici_cpuid4_info, cpu));
837 per_cpu(ici_cpuid4_info, cpu) = NULL;
838 }
839
840 static int
841 __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
842 {
843 struct _cpuid4_info_regs *leaf_regs =
844 (struct _cpuid4_info_regs *)this_leaf;
845
846 return cpuid4_cache_lookup_regs(index, leaf_regs);
847 }
848
849 static void __cpuinit get_cpu_leaves(void *_retval)
850 {
851 int j, *retval = _retval, cpu = smp_processor_id();
852
853 /* Do cpuid and store the results */
854 for (j = 0; j < num_cache_leaves; j++) {
855 struct _cpuid4_info *this_leaf;
856 this_leaf = CPUID4_INFO_IDX(cpu, j);
857 *retval = cpuid4_cache_lookup(j, this_leaf);
858 if (unlikely(*retval < 0)) {
859 int i;
860
861 for (i = 0; i < j; i++)
862 cache_remove_shared_cpu_map(cpu, i);
863 break;
864 }
865 cache_shared_cpu_map_setup(cpu, j);
866 }
867 }
868
869 static int __cpuinit detect_cache_attributes(unsigned int cpu)
870 {
871 int retval;
872
873 if (num_cache_leaves == 0)
874 return -ENOENT;
875
876 per_cpu(ici_cpuid4_info, cpu) = kzalloc(
877 sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
878 if (per_cpu(ici_cpuid4_info, cpu) == NULL)
879 return -ENOMEM;
880
881 smp_call_function_single(cpu, get_cpu_leaves, &retval, true);
882 if (retval) {
883 kfree(per_cpu(ici_cpuid4_info, cpu));
884 per_cpu(ici_cpuid4_info, cpu) = NULL;
885 }
886
887 return retval;
888 }
889
890 #include <linux/kobject.h>
891 #include <linux/sysfs.h>
892
893 extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
894
895 /* pointer to kobject for cpuX/cache */
896 static DEFINE_PER_CPU(struct kobject *, ici_cache_kobject);
897
898 struct _index_kobject {
899 struct kobject kobj;
900 unsigned int cpu;
901 unsigned short index;
902 };
903
904 /* pointer to array of kobjects for cpuX/cache/indexY */
905 static DEFINE_PER_CPU(struct _index_kobject *, ici_index_kobject);
906 #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(ici_index_kobject, x))[y]))
907
908 #define show_one_plus(file_name, object, val) \
909 static ssize_t show_##file_name \
910 (struct _cpuid4_info *this_leaf, char *buf) \
911 { \
912 return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \
913 }
914
915 show_one_plus(level, eax.split.level, 0);
916 show_one_plus(coherency_line_size, ebx.split.coherency_line_size, 1);
917 show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
918 show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
919 show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
920
921 static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
922 {
923 return sprintf(buf, "%luK\n", this_leaf->size / 1024);
924 }
925
926 static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
927 int type, char *buf)
928 {
929 ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
930 int n = 0;
931
932 if (len > 1) {
933 const struct cpumask *mask;
934
935 mask = to_cpumask(this_leaf->shared_cpu_map);
936 n = type ?
937 cpulist_scnprintf(buf, len-2, mask) :
938 cpumask_scnprintf(buf, len-2, mask);
939 buf[n++] = '\n';
940 buf[n] = '\0';
941 }
942 return n;
943 }
944
945 static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
946 {
947 return show_shared_cpu_map_func(leaf, 0, buf);
948 }
949
950 static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
951 {
952 return show_shared_cpu_map_func(leaf, 1, buf);
953 }
954
955 static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
956 {
957 switch (this_leaf->eax.split.type) {
958 case CACHE_TYPE_DATA:
959 return sprintf(buf, "Data\n");
960 case CACHE_TYPE_INST:
961 return sprintf(buf, "Instruction\n");
962 case CACHE_TYPE_UNIFIED:
963 return sprintf(buf, "Unified\n");
964 default:
965 return sprintf(buf, "Unknown\n");
966 }
967 }
968
969 #define to_object(k) container_of(k, struct _index_kobject, kobj)
970 #define to_attr(a) container_of(a, struct _cache_attr, attr)
971
972 #define define_one_ro(_name) \
973 static struct _cache_attr _name = \
974 __ATTR(_name, 0444, show_##_name, NULL)
975
976 define_one_ro(level);
977 define_one_ro(type);
978 define_one_ro(coherency_line_size);
979 define_one_ro(physical_line_partition);
980 define_one_ro(ways_of_associativity);
981 define_one_ro(number_of_sets);
982 define_one_ro(size);
983 define_one_ro(shared_cpu_map);
984 define_one_ro(shared_cpu_list);
985
986 #define DEFAULT_SYSFS_CACHE_ATTRS \
987 &type.attr, \
988 &level.attr, \
989 &coherency_line_size.attr, \
990 &physical_line_partition.attr, \
991 &ways_of_associativity.attr, \
992 &number_of_sets.attr, \
993 &size.attr, \
994 &shared_cpu_map.attr, \
995 &shared_cpu_list.attr
996
997 static struct attribute *default_attrs[] = {
998 DEFAULT_SYSFS_CACHE_ATTRS,
999 NULL
1000 };
1001
1002 static struct attribute *default_l3_attrs[] = {
1003 DEFAULT_SYSFS_CACHE_ATTRS,
1004 #ifdef CONFIG_AMD_NB
1005 &cache_disable_0.attr,
1006 &cache_disable_1.attr,
1007 #endif
1008 NULL
1009 };
1010
1011 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1012 {
1013 struct _cache_attr *fattr = to_attr(attr);
1014 struct _index_kobject *this_leaf = to_object(kobj);
1015 ssize_t ret;
1016
1017 ret = fattr->show ?
1018 fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
1019 buf) :
1020 0;
1021 return ret;
1022 }
1023
1024 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1025 const char *buf, size_t count)
1026 {
1027 struct _cache_attr *fattr = to_attr(attr);
1028 struct _index_kobject *this_leaf = to_object(kobj);
1029 ssize_t ret;
1030
1031 ret = fattr->store ?
1032 fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
1033 buf, count) :
1034 0;
1035 return ret;
1036 }
1037
1038 static const struct sysfs_ops sysfs_ops = {
1039 .show = show,
1040 .store = store,
1041 };
1042
1043 static struct kobj_type ktype_cache = {
1044 .sysfs_ops = &sysfs_ops,
1045 .default_attrs = default_attrs,
1046 };
1047
1048 static struct kobj_type ktype_percpu_entry = {
1049 .sysfs_ops = &sysfs_ops,
1050 };
1051
1052 static void __cpuinit cpuid4_cache_sysfs_exit(unsigned int cpu)
1053 {
1054 kfree(per_cpu(ici_cache_kobject, cpu));
1055 kfree(per_cpu(ici_index_kobject, cpu));
1056 per_cpu(ici_cache_kobject, cpu) = NULL;
1057 per_cpu(ici_index_kobject, cpu) = NULL;
1058 free_cache_attributes(cpu);
1059 }
1060
1061 static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
1062 {
1063 int err;
1064
1065 if (num_cache_leaves == 0)
1066 return -ENOENT;
1067
1068 err = detect_cache_attributes(cpu);
1069 if (err)
1070 return err;
1071
1072 /* Allocate all required memory */
1073 per_cpu(ici_cache_kobject, cpu) =
1074 kzalloc(sizeof(struct kobject), GFP_KERNEL);
1075 if (unlikely(per_cpu(ici_cache_kobject, cpu) == NULL))
1076 goto err_out;
1077
1078 per_cpu(ici_index_kobject, cpu) = kzalloc(
1079 sizeof(struct _index_kobject) * num_cache_leaves, GFP_KERNEL);
1080 if (unlikely(per_cpu(ici_index_kobject, cpu) == NULL))
1081 goto err_out;
1082
1083 return 0;
1084
1085 err_out:
1086 cpuid4_cache_sysfs_exit(cpu);
1087 return -ENOMEM;
1088 }
1089
1090 static DECLARE_BITMAP(cache_dev_map, NR_CPUS);
1091
1092 /* Add/Remove cache interface for CPU device */
1093 static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
1094 {
1095 unsigned int cpu = sys_dev->id;
1096 unsigned long i, j;
1097 struct _index_kobject *this_object;
1098 struct _cpuid4_info *this_leaf;
1099 int retval;
1100
1101 retval = cpuid4_cache_sysfs_init(cpu);
1102 if (unlikely(retval < 0))
1103 return retval;
1104
1105 retval = kobject_init_and_add(per_cpu(ici_cache_kobject, cpu),
1106 &ktype_percpu_entry,
1107 &sys_dev->kobj, "%s", "cache");
1108 if (retval < 0) {
1109 cpuid4_cache_sysfs_exit(cpu);
1110 return retval;
1111 }
1112
1113 for (i = 0; i < num_cache_leaves; i++) {
1114 this_object = INDEX_KOBJECT_PTR(cpu, i);
1115 this_object->cpu = cpu;
1116 this_object->index = i;
1117
1118 this_leaf = CPUID4_INFO_IDX(cpu, i);
1119
1120 if (this_leaf->l3 && this_leaf->l3->can_disable)
1121 ktype_cache.default_attrs = default_l3_attrs;
1122 else
1123 ktype_cache.default_attrs = default_attrs;
1124
1125 retval = kobject_init_and_add(&(this_object->kobj),
1126 &ktype_cache,
1127 per_cpu(ici_cache_kobject, cpu),
1128 "index%1lu", i);
1129 if (unlikely(retval)) {
1130 for (j = 0; j < i; j++)
1131 kobject_put(&(INDEX_KOBJECT_PTR(cpu, j)->kobj));
1132 kobject_put(per_cpu(ici_cache_kobject, cpu));
1133 cpuid4_cache_sysfs_exit(cpu);
1134 return retval;
1135 }
1136 kobject_uevent(&(this_object->kobj), KOBJ_ADD);
1137 }
1138 cpumask_set_cpu(cpu, to_cpumask(cache_dev_map));
1139
1140 kobject_uevent(per_cpu(ici_cache_kobject, cpu), KOBJ_ADD);
1141 return 0;
1142 }
1143
1144 static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
1145 {
1146 unsigned int cpu = sys_dev->id;
1147 unsigned long i;
1148
1149 if (per_cpu(ici_cpuid4_info, cpu) == NULL)
1150 return;
1151 if (!cpumask_test_cpu(cpu, to_cpumask(cache_dev_map)))
1152 return;
1153 cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map));
1154
1155 for (i = 0; i < num_cache_leaves; i++)
1156 kobject_put(&(INDEX_KOBJECT_PTR(cpu, i)->kobj));
1157 kobject_put(per_cpu(ici_cache_kobject, cpu));
1158 cpuid4_cache_sysfs_exit(cpu);
1159 }
1160
1161 static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb,
1162 unsigned long action, void *hcpu)
1163 {
1164 unsigned int cpu = (unsigned long)hcpu;
1165 struct sys_device *sys_dev;
1166
1167 sys_dev = get_cpu_sysdev(cpu);
1168 switch (action) {
1169 case CPU_ONLINE:
1170 case CPU_ONLINE_FROZEN:
1171 cache_add_dev(sys_dev);
1172 break;
1173 case CPU_DEAD:
1174 case CPU_DEAD_FROZEN:
1175 cache_remove_dev(sys_dev);
1176 break;
1177 }
1178 return NOTIFY_OK;
1179 }
1180
1181 static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier = {
1182 .notifier_call = cacheinfo_cpu_callback,
1183 };
1184
1185 static int __cpuinit cache_sysfs_init(void)
1186 {
1187 int i;
1188
1189 if (num_cache_leaves == 0)
1190 return 0;
1191
1192 for_each_online_cpu(i) {
1193 int err;
1194 struct sys_device *sys_dev = get_cpu_sysdev(i);
1195
1196 err = cache_add_dev(sys_dev);
1197 if (err)
1198 return err;
1199 }
1200 register_hotcpu_notifier(&cacheinfo_cpu_notifier);
1201 return 0;
1202 }
1203
1204 device_initcall(cache_sysfs_init);
1205
1206 #endif
kernel source for telekom puls (alcatel/mediatek)