arch/x86/kernel/cpu/intel.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3
   4 #include <linux/string.h>
   5 #include <linux/bitops.h>
   6 #include <linux/smp.h>
   7 #include <linux/thread_info.h>
   8 #include <linux/module.h>
   9
  10 #include <asm/processor.h>
  11 #include <asm/pgtable.h>
  12 #include <asm/msr.h>
  13 #include <asm/uaccess.h>
  14 #include <asm/ds.h>
  15 #include <asm/bugs.h>
  16
  17 #ifdef CONFIG_X86_64
  18 #include <asm/topology.h>
  19 #include <asm/numa_64.h>
  20 #endif
  21
  22 #include "cpu.h"
  23
  24 #ifdef CONFIG_X86_LOCAL_APIC
  25 #include <asm/mpspec.h>
  26 #include <asm/apic.h>
  27 #include <mach_apic.h>
  28 #endif
  29
  30 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
  31 {
  32         if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
  33                 (c->x86 == 0x6 && c->x86_model >= 0x0e))
  34                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  35
  36 #ifdef CONFIG_X86_64
  37         set_cpu_cap(c, X86_FEATURE_SYSENTER32);
  38 #else
  39         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  40         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  41                 c->x86_cache_alignment = 128;
  42 #endif
  43
  44         /*
  45          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
  46          * with P/T states and does not stop in deep C-states
  47          */
  48         if (c->x86_power & (1 << 8)) {
  49                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
  50                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
  51         }
  52
  53 }
  54
  55 #ifdef CONFIG_X86_32
  56 /*
  57  *      Early probe support logic for ppro memory erratum #50
  58  *
  59  *      This is called before we do cpu ident work
  60  */
  61
  62 int __cpuinit ppro_with_ram_bug(void)
  63 {
  64         /* Uses data from early_cpu_detect now */
  65         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
  66             boot_cpu_data.x86 == 6 &&
  67             boot_cpu_data.x86_model == 1 &&
  68             boot_cpu_data.x86_mask < 8) {
  69                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
  70                 return 1;
  71         }
  72         return 0;
  73 }
  74
  75 #ifdef CONFIG_X86_F00F_BUG
  76 static void __cpuinit trap_init_f00f_bug(void)
  77 {
  78         __set_fixmap(FIX_F00F_IDT, __pa(&idt_table), PAGE_KERNEL_RO);
  79
  80         /*
  81          * Update the IDT descriptor and reload the IDT so that
  82          * it uses the read-only mapped virtual address.
  83          */
  84         idt_descr.address = fix_to_virt(FIX_F00F_IDT);
  85         load_idt(&idt_descr);
  86 }
  87 #endif
  88
  89 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
  90 {
  91         unsigned long lo, hi;
  92
  93 #ifdef CONFIG_X86_F00F_BUG
  94         /*
  95          * All current models of Pentium and Pentium with MMX technology CPUs
  96          * have the F0 0F bug, which lets nonprivileged users lock up the system.
  97          * Note that the workaround only should be initialized once...
  98          */
  99         c->f00f_bug = 0;
 100         if (!paravirt_enabled() && c->x86 == 5) {
 101                 static int f00f_workaround_enabled;
 102
 103                 c->f00f_bug = 1;
 104                 if (!f00f_workaround_enabled) {
 105                         trap_init_f00f_bug();
 106                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 107                         f00f_workaround_enabled = 1;
 108                 }
 109         }
 110 #endif
 111
 112         /*
 113          * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
 114          * model 3 mask 3
 115          */
 116         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 117                 clear_cpu_cap(c, X86_FEATURE_SEP);
 118
 119         /*
 120          * P4 Xeon errata 037 workaround.
 121          * Hardware prefetcher may cause stale data to be loaded into the cache.
 122          */
 123         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
 124                 rdmsr(MSR_IA32_MISC_ENABLE, lo, hi);
 125                 if ((lo & (1<<9)) == 0) {
 126                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
 127                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
 128                         lo |= (1<<9);   /* Disable hw prefetching */
 129                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
 130                 }
 131         }
 132
 133         /*
 134          * See if we have a good local APIC by checking for buggy Pentia,
 135          * i.e. all B steppings and the C2 stepping of P54C when using their
 136          * integrated APIC (see 11AP erratum in "Pentium Processor
 137          * Specification Update").
 138          */
 139         if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
 140             (c->x86_mask < 0x6 || c->x86_mask == 0xb))
 141                 set_cpu_cap(c, X86_FEATURE_11AP);
 142
 143
 144 #ifdef CONFIG_X86_INTEL_USERCOPY
 145         /*
 146          * Set up the preferred alignment for movsl bulk memory moves
 147          */
 148         switch (c->x86) {
 149         case 4:         /* 486: untested */
 150                 break;
 151         case 5:         /* Old Pentia: untested */
 152                 break;
 153         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 154                 movsl_mask.mask = 7;
 155                 break;
 156         case 15:        /* P4 is OK down to 8-byte alignment */
 157                 movsl_mask.mask = 7;
 158                 break;
 159         }
 160 #endif
 161
 162 #ifdef CONFIG_X86_NUMAQ
 163         numaq_tsc_disable();
 164 #endif
 165 }
 166 #else
 167 static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 168 {
 169 }
 170 #endif
 171
 172 static void __cpuinit srat_detect_node(void)
 173 {
 174 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 175         unsigned node;
 176         int cpu = smp_processor_id();
 177         int apicid = hard_smp_processor_id();
 178
 179         /* Don't do the funky fallback heuristics the AMD version employs
 180            for now. */
 181         node = apicid_to_node[apicid];
 182         if (node == NUMA_NO_NODE || !node_online(node))
 183                 node = first_node(node_online_map);
 184         numa_set_node(cpu, node);
 185
 186         printk(KERN_INFO "CPU %d/0x%x -> Node %d\n", cpu, apicid, node);
 187 #endif
 188 }
 189
 190 /*
 191  * find out the number of processor cores on the die
 192  */
 193 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
 194 {
 195         unsigned int eax, ebx, ecx, edx;
 196
 197         if (c->cpuid_level < 4)
 198                 return 1;
 199
 200         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
 201         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
 202         if (eax & 0x1f)
 203                 return ((eax >> 26) + 1);
 204         else
 205                 return 1;
 206 }
 207
 208 static void __cpuinit detect_vmx_virtcap(struct cpuinfo_x86 *c)
 209 {
 210         /* Intel VMX MSR indicated features */
 211 #define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW    0x00200000
 212 #define X86_VMX_FEATURE_PROC_CTLS_VNMI          0x00400000
 213 #define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS      0x80000000
 214 #define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC    0x00000001
 215 #define X86_VMX_FEATURE_PROC_CTLS2_EPT          0x00000002
 216 #define X86_VMX_FEATURE_PROC_CTLS2_VPID         0x00000020
 217
 218         u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
 219
 220         clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 221         clear_cpu_cap(c, X86_FEATURE_VNMI);
 222         clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 223         clear_cpu_cap(c, X86_FEATURE_EPT);
 224         clear_cpu_cap(c, X86_FEATURE_VPID);
 225
 226         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
 227         msr_ctl = vmx_msr_high | vmx_msr_low;
 228         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
 229                 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
 230         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
 231                 set_cpu_cap(c, X86_FEATURE_VNMI);
 232         if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
 233                 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
 234                       vmx_msr_low, vmx_msr_high);
 235                 msr_ctl2 = vmx_msr_high | vmx_msr_low;
 236                 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
 237                     (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
 238                         set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
 239                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
 240                         set_cpu_cap(c, X86_FEATURE_EPT);
 241                 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
 242                         set_cpu_cap(c, X86_FEATURE_VPID);
 243         }
 244 }
 245
 246 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 247 {
 248         unsigned int l2 = 0;
 249
 250         early_init_intel(c);
 251
 252         intel_workarounds(c);
 253
 254         /*
 255          * Detect the extended topology information if available. This
 256          * will reinitialise the initial_apicid which will be used
 257          * in init_intel_cacheinfo()
 258          */
 259         detect_extended_topology(c);
 260
 261         l2 = init_intel_cacheinfo(c);
 262         if (c->cpuid_level > 9) {
 263                 unsigned eax = cpuid_eax(10);
 264                 /* Check for version and the number of counters */
 265                 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
 266                         set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
 267         }
 268
 269         if (cpu_has_xmm2)
 270                 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
 271         if (cpu_has_ds) {
 272                 unsigned int l1;
 273                 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
 274                 if (!(l1 & (1<<11)))
 275                         set_cpu_cap(c, X86_FEATURE_BTS);
 276                 if (!(l1 & (1<<12)))
 277                         set_cpu_cap(c, X86_FEATURE_PEBS);
 278                 ds_init_intel(c);
 279         }
 280
 281 #ifdef CONFIG_X86_64
 282         if (c->x86 == 15)
 283                 c->x86_cache_alignment = c->x86_clflush_size * 2;
 284         if (c->x86 == 6)
 285                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 286 #else
 287         /*
 288          * Names for the Pentium II/Celeron processors
 289          * detectable only by also checking the cache size.
 290          * Dixon is NOT a Celeron.
 291          */
 292         if (c->x86 == 6) {
 293                 char *p = NULL;
 294
 295                 switch (c->x86_model) {
 296                 case 5:
 297                         if (c->x86_mask == 0) {
 298                                 if (l2 == 0)
 299                                         p = "Celeron (Covington)";
 300                                 else if (l2 == 256)
 301                                         p = "Mobile Pentium II (Dixon)";
 302                         }
 303                         break;
 304
 305                 case 6:
 306                         if (l2 == 128)
 307                                 p = "Celeron (Mendocino)";
 308                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 309                                 p = "Celeron-A";
 310                         break;
 311
 312                 case 8:
 313                         if (l2 == 128)
 314                                 p = "Celeron (Coppermine)";
 315                         break;
 316                 }
 317
 318                 if (p)
 319                         strcpy(c->x86_model_id, p);
 320         }
 321
 322         if (c->x86 == 15)
 323                 set_cpu_cap(c, X86_FEATURE_P4);
 324         if (c->x86 == 6)
 325                 set_cpu_cap(c, X86_FEATURE_P3);
 326 #endif
 327
 328         if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
 329                 /*
 330                  * let's use the legacy cpuid vector 0x1 and 0x4 for topology
 331                  * detection.
 332                  */
 333                 c->x86_max_cores = intel_num_cpu_cores(c);
 334 #ifdef CONFIG_X86_32
 335                 detect_ht(c);
 336 #endif
 337         }
 338
 339         /* Work around errata */
 340         srat_detect_node();
 341
 342         if (cpu_has(c, X86_FEATURE_VMX))
 343                 detect_vmx_virtcap(c);
 344 }
 345
 346 #ifdef CONFIG_X86_32
 347 static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 348 {
 349         /*
 350          * Intel PIII Tualatin. This comes in two flavours.
 351          * One has 256kb of cache, the other 512. We have no way
 352          * to determine which, so we use a boottime override
 353          * for the 512kb model, and assume 256 otherwise.
 354          */
 355         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 356                 size = 256;
 357         return size;
 358 }
 359 #endif
 360
 361 static struct cpu_dev intel_cpu_dev __cpuinitdata = {
 362         .c_vendor       = "Intel",
 363         .c_ident        = { "GenuineIntel" },
 364 #ifdef CONFIG_X86_32
 365         .c_models = {
 366                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 367                   {
 368                           [0] = "486 DX-25/33",
 369                           [1] = "486 DX-50",
 370                           [2] = "486 SX",
 371                           [3] = "486 DX/2",
 372                           [4] = "486 SL",
 373                           [5] = "486 SX/2",
 374                           [7] = "486 DX/2-WB",
 375                           [8] = "486 DX/4",
 376                           [9] = "486 DX/4-WB"
 377                   }
 378                 },
 379                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 380                   {
 381                           [0] = "Pentium 60/66 A-step",
 382                           [1] = "Pentium 60/66",
 383                           [2] = "Pentium 75 - 200",
 384                           [3] = "OverDrive PODP5V83",
 385                           [4] = "Pentium MMX",
 386                           [7] = "Mobile Pentium 75 - 200",
 387                           [8] = "Mobile Pentium MMX"
 388                   }
 389                 },
 390                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 391                   {
 392                           [0] = "Pentium Pro A-step",
 393                           [1] = "Pentium Pro",
 394                           [3] = "Pentium II (Klamath)",
 395                           [4] = "Pentium II (Deschutes)",
 396                           [5] = "Pentium II (Deschutes)",
 397                           [6] = "Mobile Pentium II",
 398                           [7] = "Pentium III (Katmai)",
 399                           [8] = "Pentium III (Coppermine)",
 400                           [10] = "Pentium III (Cascades)",
 401                           [11] = "Pentium III (Tualatin)",
 402                   }
 403                 },
 404                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 405                   {
 406                           [0] = "Pentium 4 (Unknown)",
 407                           [1] = "Pentium 4 (Willamette)",
 408                           [2] = "Pentium 4 (Northwood)",
 409                           [4] = "Pentium 4 (Foster)",
 410                           [5] = "Pentium 4 (Foster)",
 411                   }
 412                 },
 413         },
 414         .c_size_cache   = intel_size_cache,
 415 #endif
 416         .c_early_init   = early_init_intel,
 417         .c_init         = init_intel,
 418         .c_x86_vendor   = X86_VENDOR_INTEL,
 419 };
 420
 421 cpu_dev_register(intel_cpu_dev);
 422