2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
71 #ifdef CONFIG_IRQ_REMAP
72 static void irq_remap_modify_chip_defaults(struct irq_chip
*chip
);
73 static inline bool irq_remapped(struct irq_cfg
*cfg
)
75 return cfg
->irq_2_iommu
.iommu
!= NULL
;
78 static inline bool irq_remapped(struct irq_cfg
*cfg
)
82 static inline void irq_remap_modify_chip_defaults(struct irq_chip
*chip
)
88 * Is the SiS APIC rmw bug present ?
89 * -1 = don't know, 0 = no, 1 = yes
91 int sis_apic_bug
= -1;
93 static DEFINE_RAW_SPINLOCK(ioapic_lock
);
94 static DEFINE_RAW_SPINLOCK(vector_lock
);
96 static struct ioapic
{
98 * # of IRQ routing registers
102 * Saved state during suspend/resume, or while enabling intr-remap.
104 struct IO_APIC_route_entry
*saved_registers
;
105 /* I/O APIC config */
106 struct mpc_ioapic mp_config
;
107 /* IO APIC gsi routing info */
108 struct mp_ioapic_gsi gsi_config
;
109 DECLARE_BITMAP(pin_programmed
, MP_MAX_IOAPIC_PIN
+ 1);
110 } ioapics
[MAX_IO_APICS
];
112 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
114 int mpc_ioapic_id(int ioapic_idx
)
116 return ioapics
[ioapic_idx
].mp_config
.apicid
;
119 unsigned int mpc_ioapic_addr(int ioapic_idx
)
121 return ioapics
[ioapic_idx
].mp_config
.apicaddr
;
124 struct mp_ioapic_gsi
*mp_ioapic_gsi_routing(int ioapic_idx
)
126 return &ioapics
[ioapic_idx
].gsi_config
;
131 /* The one past the highest gsi number used */
134 /* MP IRQ source entries */
135 struct mpc_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
137 /* # of MP IRQ source entries */
141 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
144 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
147 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
149 int skip_ioapic_setup
;
152 * disable_ioapic_support() - disables ioapic support at runtime
154 void disable_ioapic_support(void)
158 noioapicreroute
= -1;
160 skip_ioapic_setup
= 1;
163 static int __init
parse_noapic(char *str
)
165 /* disable IO-APIC */
166 disable_ioapic_support();
169 early_param("noapic", parse_noapic
);
171 static int io_apic_setup_irq_pin(unsigned int irq
, int node
,
172 struct io_apic_irq_attr
*attr
);
174 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
175 void mp_save_irq(struct mpc_intsrc
*m
)
179 apic_printk(APIC_VERBOSE
, "Int: type %d, pol %d, trig %d, bus %02x,"
180 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
181 m
->irqtype
, m
->irqflag
& 3, (m
->irqflag
>> 2) & 3, m
->srcbus
,
182 m
->srcbusirq
, m
->dstapic
, m
->dstirq
);
184 for (i
= 0; i
< mp_irq_entries
; i
++) {
185 if (!memcmp(&mp_irqs
[i
], m
, sizeof(*m
)))
189 memcpy(&mp_irqs
[mp_irq_entries
], m
, sizeof(*m
));
190 if (++mp_irq_entries
== MAX_IRQ_SOURCES
)
191 panic("Max # of irq sources exceeded!!\n");
194 struct irq_pin_list
{
196 struct irq_pin_list
*next
;
199 static struct irq_pin_list
*alloc_irq_pin_list(int node
)
201 return kzalloc_node(sizeof(struct irq_pin_list
), GFP_KERNEL
, node
);
205 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
206 static struct irq_cfg irq_cfgx
[NR_IRQS_LEGACY
];
208 int __init
arch_early_irq_init(void)
213 if (!legacy_pic
->nr_legacy_irqs
)
216 for (i
= 0; i
< nr_ioapics
; i
++) {
217 ioapics
[i
].saved_registers
=
218 kzalloc(sizeof(struct IO_APIC_route_entry
) *
219 ioapics
[i
].nr_registers
, GFP_KERNEL
);
220 if (!ioapics
[i
].saved_registers
)
221 pr_err("IOAPIC %d: suspend/resume impossible!\n", i
);
225 count
= ARRAY_SIZE(irq_cfgx
);
226 node
= cpu_to_node(0);
228 /* Make sure the legacy interrupts are marked in the bitmap */
229 irq_reserve_irqs(0, legacy_pic
->nr_legacy_irqs
);
231 for (i
= 0; i
< count
; i
++) {
232 irq_set_chip_data(i
, &cfg
[i
]);
233 zalloc_cpumask_var_node(&cfg
[i
].domain
, GFP_KERNEL
, node
);
234 zalloc_cpumask_var_node(&cfg
[i
].old_domain
, GFP_KERNEL
, node
);
236 * For legacy IRQ's, start with assigning irq0 to irq15 to
237 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
239 if (i
< legacy_pic
->nr_legacy_irqs
) {
240 cfg
[i
].vector
= IRQ0_VECTOR
+ i
;
241 cpumask_set_cpu(0, cfg
[i
].domain
);
248 static struct irq_cfg
*irq_cfg(unsigned int irq
)
250 return irq_get_chip_data(irq
);
253 static struct irq_cfg
*alloc_irq_cfg(unsigned int irq
, int node
)
257 cfg
= kzalloc_node(sizeof(*cfg
), GFP_KERNEL
, node
);
260 if (!zalloc_cpumask_var_node(&cfg
->domain
, GFP_KERNEL
, node
))
262 if (!zalloc_cpumask_var_node(&cfg
->old_domain
, GFP_KERNEL
, node
))
266 free_cpumask_var(cfg
->domain
);
272 static void free_irq_cfg(unsigned int at
, struct irq_cfg
*cfg
)
276 irq_set_chip_data(at
, NULL
);
277 free_cpumask_var(cfg
->domain
);
278 free_cpumask_var(cfg
->old_domain
);
282 static struct irq_cfg
*alloc_irq_and_cfg_at(unsigned int at
, int node
)
284 int res
= irq_alloc_desc_at(at
, node
);
290 cfg
= irq_get_chip_data(at
);
295 cfg
= alloc_irq_cfg(at
, node
);
297 irq_set_chip_data(at
, cfg
);
303 static int alloc_irq_from(unsigned int from
, int node
)
305 return irq_alloc_desc_from(from
, node
);
308 static void free_irq_at(unsigned int at
, struct irq_cfg
*cfg
)
310 free_irq_cfg(at
, cfg
);
317 unsigned int unused
[3];
319 unsigned int unused2
[11];
323 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
325 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
326 + (mpc_ioapic_addr(idx
) & ~PAGE_MASK
);
329 static inline void io_apic_eoi(unsigned int apic
, unsigned int vector
)
331 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
332 writel(vector
, &io_apic
->eoi
);
335 unsigned int native_io_apic_read(unsigned int apic
, unsigned int reg
)
337 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
338 writel(reg
, &io_apic
->index
);
339 return readl(&io_apic
->data
);
342 void native_io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
344 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
346 writel(reg
, &io_apic
->index
);
347 writel(value
, &io_apic
->data
);
351 * Re-write a value: to be used for read-modify-write
352 * cycles where the read already set up the index register.
354 * Older SiS APIC requires we rewrite the index register
356 void native_io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
358 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
361 writel(reg
, &io_apic
->index
);
362 writel(value
, &io_apic
->data
);
366 struct { u32 w1
, w2
; };
367 struct IO_APIC_route_entry entry
;
370 static struct IO_APIC_route_entry
__ioapic_read_entry(int apic
, int pin
)
372 union entry_union eu
;
374 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
375 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
380 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
382 union entry_union eu
;
385 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
386 eu
.entry
= __ioapic_read_entry(apic
, pin
);
387 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
393 * When we write a new IO APIC routing entry, we need to write the high
394 * word first! If the mask bit in the low word is clear, we will enable
395 * the interrupt, and we need to make sure the entry is fully populated
396 * before that happens.
398 static void __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
400 union entry_union eu
= {{0, 0}};
403 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
404 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
407 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
411 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
412 __ioapic_write_entry(apic
, pin
, e
);
413 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
417 * When we mask an IO APIC routing entry, we need to write the low
418 * word first, in order to set the mask bit before we change the
421 static void ioapic_mask_entry(int apic
, int pin
)
424 union entry_union eu
= { .entry
.mask
= 1 };
426 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
427 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
428 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
429 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
433 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
434 * shared ISA-space IRQs, so we have to support them. We are super
435 * fast in the common case, and fast for shared ISA-space IRQs.
437 static int __add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
439 struct irq_pin_list
**last
, *entry
;
441 /* don't allow duplicates */
442 last
= &cfg
->irq_2_pin
;
443 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
444 if (entry
->apic
== apic
&& entry
->pin
== pin
)
449 entry
= alloc_irq_pin_list(node
);
451 printk(KERN_ERR
"can not alloc irq_pin_list (%d,%d,%d)\n",
462 static void add_pin_to_irq_node(struct irq_cfg
*cfg
, int node
, int apic
, int pin
)
464 if (__add_pin_to_irq_node(cfg
, node
, apic
, pin
))
465 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
469 * Reroute an IRQ to a different pin.
471 static void __init
replace_pin_at_irq_node(struct irq_cfg
*cfg
, int node
,
472 int oldapic
, int oldpin
,
473 int newapic
, int newpin
)
475 struct irq_pin_list
*entry
;
477 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
478 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
479 entry
->apic
= newapic
;
481 /* every one is different, right? */
486 /* old apic/pin didn't exist, so just add new ones */
487 add_pin_to_irq_node(cfg
, node
, newapic
, newpin
);
490 static void __io_apic_modify_irq(struct irq_pin_list
*entry
,
491 int mask_and
, int mask_or
,
492 void (*final
)(struct irq_pin_list
*entry
))
494 unsigned int reg
, pin
;
497 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
500 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
505 static void io_apic_modify_irq(struct irq_cfg
*cfg
,
506 int mask_and
, int mask_or
,
507 void (*final
)(struct irq_pin_list
*entry
))
509 struct irq_pin_list
*entry
;
511 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
512 __io_apic_modify_irq(entry
, mask_and
, mask_or
, final
);
515 static void io_apic_sync(struct irq_pin_list
*entry
)
518 * Synchronize the IO-APIC and the CPU by doing
519 * a dummy read from the IO-APIC
521 struct io_apic __iomem
*io_apic
;
523 io_apic
= io_apic_base(entry
->apic
);
524 readl(&io_apic
->data
);
527 static void mask_ioapic(struct irq_cfg
*cfg
)
531 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
532 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
533 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
536 static void mask_ioapic_irq(struct irq_data
*data
)
538 mask_ioapic(data
->chip_data
);
541 static void __unmask_ioapic(struct irq_cfg
*cfg
)
543 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
546 static void unmask_ioapic(struct irq_cfg
*cfg
)
550 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
551 __unmask_ioapic(cfg
);
552 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
555 static void unmask_ioapic_irq(struct irq_data
*data
)
557 unmask_ioapic(data
->chip_data
);
561 * IO-APIC versions below 0x20 don't support EOI register.
562 * For the record, here is the information about various versions:
564 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
565 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
568 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
569 * version as 0x2. This is an error with documentation and these ICH chips
570 * use io-apic's of version 0x20.
572 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
573 * Otherwise, we simulate the EOI message manually by changing the trigger
574 * mode to edge and then back to level, with RTE being masked during this.
576 static void __eoi_ioapic_pin(int apic
, int pin
, int vector
, struct irq_cfg
*cfg
)
578 if (mpc_ioapic_ver(apic
) >= 0x20) {
580 * Intr-remapping uses pin number as the virtual vector
581 * in the RTE. Actual vector is programmed in
582 * intr-remapping table entry. Hence for the io-apic
583 * EOI we use the pin number.
585 if (cfg
&& irq_remapped(cfg
))
586 io_apic_eoi(apic
, pin
);
588 io_apic_eoi(apic
, vector
);
590 struct IO_APIC_route_entry entry
, entry1
;
592 entry
= entry1
= __ioapic_read_entry(apic
, pin
);
595 * Mask the entry and change the trigger mode to edge.
598 entry1
.trigger
= IOAPIC_EDGE
;
600 __ioapic_write_entry(apic
, pin
, entry1
);
603 * Restore the previous level triggered entry.
605 __ioapic_write_entry(apic
, pin
, entry
);
609 static void eoi_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
)
611 struct irq_pin_list
*entry
;
614 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
615 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
616 __eoi_ioapic_pin(entry
->apic
, entry
->pin
, cfg
->vector
, cfg
);
617 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
620 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
622 struct IO_APIC_route_entry entry
;
624 /* Check delivery_mode to be sure we're not clearing an SMI pin */
625 entry
= ioapic_read_entry(apic
, pin
);
626 if (entry
.delivery_mode
== dest_SMI
)
630 * Make sure the entry is masked and re-read the contents to check
631 * if it is a level triggered pin and if the remote-IRR is set.
635 ioapic_write_entry(apic
, pin
, entry
);
636 entry
= ioapic_read_entry(apic
, pin
);
643 * Make sure the trigger mode is set to level. Explicit EOI
644 * doesn't clear the remote-IRR if the trigger mode is not
647 if (!entry
.trigger
) {
648 entry
.trigger
= IOAPIC_LEVEL
;
649 ioapic_write_entry(apic
, pin
, entry
);
652 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
653 __eoi_ioapic_pin(apic
, pin
, entry
.vector
, NULL
);
654 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
658 * Clear the rest of the bits in the IO-APIC RTE except for the mask
661 ioapic_mask_entry(apic
, pin
);
662 entry
= ioapic_read_entry(apic
, pin
);
664 printk(KERN_ERR
"Unable to reset IRR for apic: %d, pin :%d\n",
665 mpc_ioapic_id(apic
), pin
);
668 static void clear_IO_APIC (void)
672 for (apic
= 0; apic
< nr_ioapics
; apic
++)
673 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++)
674 clear_IO_APIC_pin(apic
, pin
);
679 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
680 * specific CPU-side IRQs.
684 static int pirq_entries
[MAX_PIRQS
] = {
685 [0 ... MAX_PIRQS
- 1] = -1
688 static int __init
ioapic_pirq_setup(char *str
)
691 int ints
[MAX_PIRQS
+1];
693 get_options(str
, ARRAY_SIZE(ints
), ints
);
695 apic_printk(APIC_VERBOSE
, KERN_INFO
696 "PIRQ redirection, working around broken MP-BIOS.\n");
698 if (ints
[0] < MAX_PIRQS
)
701 for (i
= 0; i
< max
; i
++) {
702 apic_printk(APIC_VERBOSE
, KERN_DEBUG
703 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
705 * PIRQs are mapped upside down, usually.
707 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
712 __setup("pirq=", ioapic_pirq_setup
);
713 #endif /* CONFIG_X86_32 */
716 * Saves all the IO-APIC RTE's
718 int save_ioapic_entries(void)
723 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
724 if (!ioapics
[apic
].saved_registers
) {
729 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++)
730 ioapics
[apic
].saved_registers
[pin
] =
731 ioapic_read_entry(apic
, pin
);
738 * Mask all IO APIC entries.
740 void mask_ioapic_entries(void)
744 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
745 if (!ioapics
[apic
].saved_registers
)
748 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++) {
749 struct IO_APIC_route_entry entry
;
751 entry
= ioapics
[apic
].saved_registers
[pin
];
754 ioapic_write_entry(apic
, pin
, entry
);
761 * Restore IO APIC entries which was saved in the ioapic structure.
763 int restore_ioapic_entries(void)
767 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
768 if (!ioapics
[apic
].saved_registers
)
771 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++)
772 ioapic_write_entry(apic
, pin
,
773 ioapics
[apic
].saved_registers
[pin
]);
779 * Find the IRQ entry number of a certain pin.
781 static int find_irq_entry(int ioapic_idx
, int pin
, int type
)
785 for (i
= 0; i
< mp_irq_entries
; i
++)
786 if (mp_irqs
[i
].irqtype
== type
&&
787 (mp_irqs
[i
].dstapic
== mpc_ioapic_id(ioapic_idx
) ||
788 mp_irqs
[i
].dstapic
== MP_APIC_ALL
) &&
789 mp_irqs
[i
].dstirq
== pin
)
796 * Find the pin to which IRQ[irq] (ISA) is connected
798 static int __init
find_isa_irq_pin(int irq
, int type
)
802 for (i
= 0; i
< mp_irq_entries
; i
++) {
803 int lbus
= mp_irqs
[i
].srcbus
;
805 if (test_bit(lbus
, mp_bus_not_pci
) &&
806 (mp_irqs
[i
].irqtype
== type
) &&
807 (mp_irqs
[i
].srcbusirq
== irq
))
809 return mp_irqs
[i
].dstirq
;
814 static int __init
find_isa_irq_apic(int irq
, int type
)
818 for (i
= 0; i
< mp_irq_entries
; i
++) {
819 int lbus
= mp_irqs
[i
].srcbus
;
821 if (test_bit(lbus
, mp_bus_not_pci
) &&
822 (mp_irqs
[i
].irqtype
== type
) &&
823 (mp_irqs
[i
].srcbusirq
== irq
))
827 if (i
< mp_irq_entries
) {
830 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++)
831 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
)
840 * EISA Edge/Level control register, ELCR
842 static int EISA_ELCR(unsigned int irq
)
844 if (irq
< legacy_pic
->nr_legacy_irqs
) {
845 unsigned int port
= 0x4d0 + (irq
>> 3);
846 return (inb(port
) >> (irq
& 7)) & 1;
848 apic_printk(APIC_VERBOSE
, KERN_INFO
849 "Broken MPtable reports ISA irq %d\n", irq
);
855 /* ISA interrupts are always polarity zero edge triggered,
856 * when listed as conforming in the MP table. */
858 #define default_ISA_trigger(idx) (0)
859 #define default_ISA_polarity(idx) (0)
861 /* EISA interrupts are always polarity zero and can be edge or level
862 * trigger depending on the ELCR value. If an interrupt is listed as
863 * EISA conforming in the MP table, that means its trigger type must
864 * be read in from the ELCR */
866 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
867 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
869 /* PCI interrupts are always polarity one level triggered,
870 * when listed as conforming in the MP table. */
872 #define default_PCI_trigger(idx) (1)
873 #define default_PCI_polarity(idx) (1)
875 static int irq_polarity(int idx
)
877 int bus
= mp_irqs
[idx
].srcbus
;
881 * Determine IRQ line polarity (high active or low active):
883 switch (mp_irqs
[idx
].irqflag
& 3)
885 case 0: /* conforms, ie. bus-type dependent polarity */
886 if (test_bit(bus
, mp_bus_not_pci
))
887 polarity
= default_ISA_polarity(idx
);
889 polarity
= default_PCI_polarity(idx
);
891 case 1: /* high active */
896 case 2: /* reserved */
898 printk(KERN_WARNING
"broken BIOS!!\n");
902 case 3: /* low active */
907 default: /* invalid */
909 printk(KERN_WARNING
"broken BIOS!!\n");
917 static int irq_trigger(int idx
)
919 int bus
= mp_irqs
[idx
].srcbus
;
923 * Determine IRQ trigger mode (edge or level sensitive):
925 switch ((mp_irqs
[idx
].irqflag
>>2) & 3)
927 case 0: /* conforms, ie. bus-type dependent */
928 if (test_bit(bus
, mp_bus_not_pci
))
929 trigger
= default_ISA_trigger(idx
);
931 trigger
= default_PCI_trigger(idx
);
933 switch (mp_bus_id_to_type
[bus
]) {
934 case MP_BUS_ISA
: /* ISA pin */
936 /* set before the switch */
939 case MP_BUS_EISA
: /* EISA pin */
941 trigger
= default_EISA_trigger(idx
);
944 case MP_BUS_PCI
: /* PCI pin */
946 /* set before the switch */
951 printk(KERN_WARNING
"broken BIOS!!\n");
963 case 2: /* reserved */
965 printk(KERN_WARNING
"broken BIOS!!\n");
974 default: /* invalid */
976 printk(KERN_WARNING
"broken BIOS!!\n");
984 static int pin_2_irq(int idx
, int apic
, int pin
)
987 int bus
= mp_irqs
[idx
].srcbus
;
988 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(apic
);
991 * Debugging check, we are in big trouble if this message pops up!
993 if (mp_irqs
[idx
].dstirq
!= pin
)
994 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
996 if (test_bit(bus
, mp_bus_not_pci
)) {
997 irq
= mp_irqs
[idx
].srcbusirq
;
999 u32 gsi
= gsi_cfg
->gsi_base
+ pin
;
1001 if (gsi
>= NR_IRQS_LEGACY
)
1004 irq
= gsi_top
+ gsi
;
1007 #ifdef CONFIG_X86_32
1009 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1011 if ((pin
>= 16) && (pin
<= 23)) {
1012 if (pirq_entries
[pin
-16] != -1) {
1013 if (!pirq_entries
[pin
-16]) {
1014 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1015 "disabling PIRQ%d\n", pin
-16);
1017 irq
= pirq_entries
[pin
-16];
1018 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1019 "using PIRQ%d -> IRQ %d\n",
1030 * Find a specific PCI IRQ entry.
1031 * Not an __init, possibly needed by modules
1033 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
,
1034 struct io_apic_irq_attr
*irq_attr
)
1036 int ioapic_idx
, i
, best_guess
= -1;
1038 apic_printk(APIC_DEBUG
,
1039 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1041 if (test_bit(bus
, mp_bus_not_pci
)) {
1042 apic_printk(APIC_VERBOSE
,
1043 "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1046 for (i
= 0; i
< mp_irq_entries
; i
++) {
1047 int lbus
= mp_irqs
[i
].srcbus
;
1049 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++)
1050 if (mpc_ioapic_id(ioapic_idx
) == mp_irqs
[i
].dstapic
||
1051 mp_irqs
[i
].dstapic
== MP_APIC_ALL
)
1054 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1055 !mp_irqs
[i
].irqtype
&&
1057 (slot
== ((mp_irqs
[i
].srcbusirq
>> 2) & 0x1f))) {
1058 int irq
= pin_2_irq(i
, ioapic_idx
, mp_irqs
[i
].dstirq
);
1060 if (!(ioapic_idx
|| IO_APIC_IRQ(irq
)))
1063 if (pin
== (mp_irqs
[i
].srcbusirq
& 3)) {
1064 set_io_apic_irq_attr(irq_attr
, ioapic_idx
,
1071 * Use the first all-but-pin matching entry as a
1072 * best-guess fuzzy result for broken mptables.
1074 if (best_guess
< 0) {
1075 set_io_apic_irq_attr(irq_attr
, ioapic_idx
,
1085 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1087 void lock_vector_lock(void)
1089 /* Used to the online set of cpus does not change
1090 * during assign_irq_vector.
1092 raw_spin_lock(&vector_lock
);
1095 void unlock_vector_lock(void)
1097 raw_spin_unlock(&vector_lock
);
1101 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1104 * NOTE! The local APIC isn't very good at handling
1105 * multiple interrupts at the same interrupt level.
1106 * As the interrupt level is determined by taking the
1107 * vector number and shifting that right by 4, we
1108 * want to spread these out a bit so that they don't
1109 * all fall in the same interrupt level.
1111 * Also, we've got to be careful not to trash gate
1112 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1114 static int current_vector
= FIRST_EXTERNAL_VECTOR
+ VECTOR_OFFSET_START
;
1115 static int current_offset
= VECTOR_OFFSET_START
% 16;
1116 unsigned int old_vector
;
1118 cpumask_var_t tmp_mask
;
1120 if (cfg
->move_in_progress
)
1123 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1126 old_vector
= cfg
->vector
;
1128 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1129 if (cpumask_subset(tmp_mask
, cfg
->domain
)) {
1130 free_cpumask_var(tmp_mask
);
1135 /* Only try and allocate irqs on cpus that are present */
1137 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1142 more_domains
= apic
->vector_allocation_domain(cpu
, tmp_mask
);
1144 if (cpumask_subset(tmp_mask
, cfg
->domain
)) {
1145 free_cpumask_var(tmp_mask
);
1149 vector
= current_vector
;
1150 offset
= current_offset
;
1153 if (vector
>= first_system_vector
) {
1154 offset
= (offset
+ 1) % 16;
1155 vector
= FIRST_EXTERNAL_VECTOR
+ offset
;
1158 if (unlikely(current_vector
== vector
)) {
1165 if (test_bit(vector
, used_vectors
))
1168 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1169 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1172 current_vector
= vector
;
1173 current_offset
= offset
;
1175 cfg
->move_in_progress
= 1;
1176 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1178 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1179 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1180 cfg
->vector
= vector
;
1181 cpumask_copy(cfg
->domain
, tmp_mask
);
1185 free_cpumask_var(tmp_mask
);
1189 int assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1192 unsigned long flags
;
1194 raw_spin_lock_irqsave(&vector_lock
, flags
);
1195 err
= __assign_irq_vector(irq
, cfg
, mask
);
1196 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
1200 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1204 BUG_ON(!cfg
->vector
);
1206 vector
= cfg
->vector
;
1207 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1208 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1211 cpumask_clear(cfg
->domain
);
1213 if (likely(!cfg
->move_in_progress
))
1215 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1216 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1218 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1220 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1224 cfg
->move_in_progress
= 0;
1227 void __setup_vector_irq(int cpu
)
1229 /* Initialize vector_irq on a new cpu */
1231 struct irq_cfg
*cfg
;
1234 * vector_lock will make sure that we don't run into irq vector
1235 * assignments that might be happening on another cpu in parallel,
1236 * while we setup our initial vector to irq mappings.
1238 raw_spin_lock(&vector_lock
);
1239 /* Mark the inuse vectors */
1240 for_each_active_irq(irq
) {
1241 cfg
= irq_get_chip_data(irq
);
1245 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1246 * will be part of the irq_cfg's domain.
1248 if (irq
< legacy_pic
->nr_legacy_irqs
&& !IO_APIC_IRQ(irq
))
1249 cpumask_set_cpu(cpu
, cfg
->domain
);
1251 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1253 vector
= cfg
->vector
;
1254 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1256 /* Mark the free vectors */
1257 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1258 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1263 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1264 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1266 raw_spin_unlock(&vector_lock
);
1269 static struct irq_chip ioapic_chip
;
1271 #ifdef CONFIG_X86_32
1272 static inline int IO_APIC_irq_trigger(int irq
)
1276 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1277 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++) {
1278 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1279 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1280 return irq_trigger(idx
);
1284 * nonexistent IRQs are edge default
1289 static inline int IO_APIC_irq_trigger(int irq
)
1295 static void ioapic_register_intr(unsigned int irq
, struct irq_cfg
*cfg
,
1296 unsigned long trigger
)
1298 struct irq_chip
*chip
= &ioapic_chip
;
1299 irq_flow_handler_t hdl
;
1302 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1303 trigger
== IOAPIC_LEVEL
) {
1304 irq_set_status_flags(irq
, IRQ_LEVEL
);
1307 irq_clear_status_flags(irq
, IRQ_LEVEL
);
1311 if (irq_remapped(cfg
)) {
1312 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
1313 irq_remap_modify_chip_defaults(chip
);
1314 fasteoi
= trigger
!= 0;
1317 hdl
= fasteoi
? handle_fasteoi_irq
: handle_edge_irq
;
1318 irq_set_chip_and_handler_name(irq
, chip
, hdl
,
1319 fasteoi
? "fasteoi" : "edge");
1322 static int setup_ioapic_entry(int irq
, struct IO_APIC_route_entry
*entry
,
1323 unsigned int destination
, int vector
,
1324 struct io_apic_irq_attr
*attr
)
1326 if (irq_remapping_enabled
)
1327 return setup_ioapic_remapped_entry(irq
, entry
, destination
,
1330 memset(entry
, 0, sizeof(*entry
));
1332 entry
->delivery_mode
= apic
->irq_delivery_mode
;
1333 entry
->dest_mode
= apic
->irq_dest_mode
;
1334 entry
->dest
= destination
;
1335 entry
->vector
= vector
;
1336 entry
->mask
= 0; /* enable IRQ */
1337 entry
->trigger
= attr
->trigger
;
1338 entry
->polarity
= attr
->polarity
;
1341 * Mask level triggered irqs.
1342 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1350 static void setup_ioapic_irq(unsigned int irq
, struct irq_cfg
*cfg
,
1351 struct io_apic_irq_attr
*attr
)
1353 struct IO_APIC_route_entry entry
;
1356 if (!IO_APIC_IRQ(irq
))
1359 if (assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
1362 if (apic
->cpu_mask_to_apicid_and(cfg
->domain
, apic
->target_cpus(),
1364 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n",
1365 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1366 __clear_irq_vector(irq
, cfg
);
1371 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1372 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1373 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1374 attr
->ioapic
, mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
,
1375 cfg
->vector
, irq
, attr
->trigger
, attr
->polarity
, dest
);
1377 if (setup_ioapic_entry(irq
, &entry
, dest
, cfg
->vector
, attr
)) {
1378 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1379 mpc_ioapic_id(attr
->ioapic
), attr
->ioapic_pin
);
1380 __clear_irq_vector(irq
, cfg
);
1385 ioapic_register_intr(irq
, cfg
, attr
->trigger
);
1386 if (irq
< legacy_pic
->nr_legacy_irqs
)
1387 legacy_pic
->mask(irq
);
1389 ioapic_write_entry(attr
->ioapic
, attr
->ioapic_pin
, entry
);
1392 static bool __init
io_apic_pin_not_connected(int idx
, int ioapic_idx
, int pin
)
1397 apic_printk(APIC_VERBOSE
, KERN_DEBUG
" apic %d pin %d not connected\n",
1398 mpc_ioapic_id(ioapic_idx
), pin
);
1402 static void __init
__io_apic_setup_irqs(unsigned int ioapic_idx
)
1404 int idx
, node
= cpu_to_node(0);
1405 struct io_apic_irq_attr attr
;
1406 unsigned int pin
, irq
;
1408 for (pin
= 0; pin
< ioapics
[ioapic_idx
].nr_registers
; pin
++) {
1409 idx
= find_irq_entry(ioapic_idx
, pin
, mp_INT
);
1410 if (io_apic_pin_not_connected(idx
, ioapic_idx
, pin
))
1413 irq
= pin_2_irq(idx
, ioapic_idx
, pin
);
1415 if ((ioapic_idx
> 0) && (irq
> 16))
1419 * Skip the timer IRQ if there's a quirk handler
1420 * installed and if it returns 1:
1422 if (apic
->multi_timer_check
&&
1423 apic
->multi_timer_check(ioapic_idx
, irq
))
1426 set_io_apic_irq_attr(&attr
, ioapic_idx
, pin
, irq_trigger(idx
),
1429 io_apic_setup_irq_pin(irq
, node
, &attr
);
1433 static void __init
setup_IO_APIC_irqs(void)
1435 unsigned int ioapic_idx
;
1437 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1439 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++)
1440 __io_apic_setup_irqs(ioapic_idx
);
1444 * for the gsit that is not in first ioapic
1445 * but could not use acpi_register_gsi()
1446 * like some special sci in IBM x3330
1448 void setup_IO_APIC_irq_extra(u32 gsi
)
1450 int ioapic_idx
= 0, pin
, idx
, irq
, node
= cpu_to_node(0);
1451 struct io_apic_irq_attr attr
;
1454 * Convert 'gsi' to 'ioapic.pin'.
1456 ioapic_idx
= mp_find_ioapic(gsi
);
1460 pin
= mp_find_ioapic_pin(ioapic_idx
, gsi
);
1461 idx
= find_irq_entry(ioapic_idx
, pin
, mp_INT
);
1465 irq
= pin_2_irq(idx
, ioapic_idx
, pin
);
1467 /* Only handle the non legacy irqs on secondary ioapics */
1468 if (ioapic_idx
== 0 || irq
< NR_IRQS_LEGACY
)
1471 set_io_apic_irq_attr(&attr
, ioapic_idx
, pin
, irq_trigger(idx
),
1474 io_apic_setup_irq_pin_once(irq
, node
, &attr
);
1478 * Set up the timer pin, possibly with the 8259A-master behind.
1480 static void __init
setup_timer_IRQ0_pin(unsigned int ioapic_idx
,
1481 unsigned int pin
, int vector
)
1483 struct IO_APIC_route_entry entry
;
1486 if (irq_remapping_enabled
)
1489 memset(&entry
, 0, sizeof(entry
));
1492 * We use logical delivery to get the timer IRQ
1495 if (unlikely(apic
->cpu_mask_to_apicid_and(apic
->target_cpus(),
1496 apic
->target_cpus(), &dest
)))
1499 entry
.dest_mode
= apic
->irq_dest_mode
;
1500 entry
.mask
= 0; /* don't mask IRQ for edge */
1502 entry
.delivery_mode
= apic
->irq_delivery_mode
;
1505 entry
.vector
= vector
;
1508 * The timer IRQ doesn't have to know that behind the
1509 * scene we may have a 8259A-master in AEOI mode ...
1511 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,
1515 * Add it to the IO-APIC irq-routing table:
1517 ioapic_write_entry(ioapic_idx
, pin
, entry
);
1520 __apicdebuginit(void) print_IO_APIC(int ioapic_idx
)
1523 union IO_APIC_reg_00 reg_00
;
1524 union IO_APIC_reg_01 reg_01
;
1525 union IO_APIC_reg_02 reg_02
;
1526 union IO_APIC_reg_03 reg_03
;
1527 unsigned long flags
;
1529 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
1530 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
1531 reg_01
.raw
= io_apic_read(ioapic_idx
, 1);
1532 if (reg_01
.bits
.version
>= 0x10)
1533 reg_02
.raw
= io_apic_read(ioapic_idx
, 2);
1534 if (reg_01
.bits
.version
>= 0x20)
1535 reg_03
.raw
= io_apic_read(ioapic_idx
, 3);
1536 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
1539 printk(KERN_DEBUG
"IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx
));
1540 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1541 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1542 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1543 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1545 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1546 printk(KERN_DEBUG
"....... : max redirection entries: %02X\n",
1547 reg_01
.bits
.entries
);
1549 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1550 printk(KERN_DEBUG
"....... : IO APIC version: %02X\n",
1551 reg_01
.bits
.version
);
1554 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1555 * but the value of reg_02 is read as the previous read register
1556 * value, so ignore it if reg_02 == reg_01.
1558 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1559 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1560 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1564 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1565 * or reg_03, but the value of reg_0[23] is read as the previous read
1566 * register value, so ignore it if reg_03 == reg_0[12].
1568 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1569 reg_03
.raw
!= reg_01
.raw
) {
1570 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1571 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1574 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1576 if (irq_remapping_enabled
) {
1577 printk(KERN_DEBUG
" NR Indx Fmt Mask Trig IRR"
1578 " Pol Stat Indx2 Zero Vect:\n");
1580 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1581 " Stat Dmod Deli Vect:\n");
1584 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1585 if (irq_remapping_enabled
) {
1586 struct IO_APIC_route_entry entry
;
1587 struct IR_IO_APIC_route_entry
*ir_entry
;
1589 entry
= ioapic_read_entry(ioapic_idx
, i
);
1590 ir_entry
= (struct IR_IO_APIC_route_entry
*) &entry
;
1591 printk(KERN_DEBUG
" %02x %04X ",
1595 printk("%1d %1d %1d %1d %1d "
1596 "%1d %1d %X %02X\n",
1602 ir_entry
->delivery_status
,
1608 struct IO_APIC_route_entry entry
;
1610 entry
= ioapic_read_entry(ioapic_idx
, i
);
1611 printk(KERN_DEBUG
" %02x %02X ",
1615 printk("%1d %1d %1d %1d %1d "
1621 entry
.delivery_status
,
1623 entry
.delivery_mode
,
1630 __apicdebuginit(void) print_IO_APICs(void)
1633 struct irq_cfg
*cfg
;
1635 struct irq_chip
*chip
;
1637 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1638 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++)
1639 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1640 mpc_ioapic_id(ioapic_idx
),
1641 ioapics
[ioapic_idx
].nr_registers
);
1644 * We are a bit conservative about what we expect. We have to
1645 * know about every hardware change ASAP.
1647 printk(KERN_INFO
"testing the IO APIC.......................\n");
1649 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++)
1650 print_IO_APIC(ioapic_idx
);
1652 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1653 for_each_active_irq(irq
) {
1654 struct irq_pin_list
*entry
;
1656 chip
= irq_get_chip(irq
);
1657 if (chip
!= &ioapic_chip
)
1660 cfg
= irq_get_chip_data(irq
);
1663 entry
= cfg
->irq_2_pin
;
1666 printk(KERN_DEBUG
"IRQ%d ", irq
);
1667 for_each_irq_pin(entry
, cfg
->irq_2_pin
)
1668 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1672 printk(KERN_INFO
".................................... done.\n");
1675 __apicdebuginit(void) print_APIC_field(int base
)
1681 for (i
= 0; i
< 8; i
++)
1682 printk(KERN_CONT
"%08x", apic_read(base
+ i
*0x10));
1684 printk(KERN_CONT
"\n");
1687 __apicdebuginit(void) print_local_APIC(void *dummy
)
1689 unsigned int i
, v
, ver
, maxlvt
;
1692 printk(KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1693 smp_processor_id(), hard_smp_processor_id());
1694 v
= apic_read(APIC_ID
);
1695 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1696 v
= apic_read(APIC_LVR
);
1697 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1698 ver
= GET_APIC_VERSION(v
);
1699 maxlvt
= lapic_get_maxlvt();
1701 v
= apic_read(APIC_TASKPRI
);
1702 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1704 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1705 if (!APIC_XAPIC(ver
)) {
1706 v
= apic_read(APIC_ARBPRI
);
1707 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1708 v
& APIC_ARBPRI_MASK
);
1710 v
= apic_read(APIC_PROCPRI
);
1711 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1715 * Remote read supported only in the 82489DX and local APIC for
1716 * Pentium processors.
1718 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1719 v
= apic_read(APIC_RRR
);
1720 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1723 v
= apic_read(APIC_LDR
);
1724 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1725 if (!x2apic_enabled()) {
1726 v
= apic_read(APIC_DFR
);
1727 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1729 v
= apic_read(APIC_SPIV
);
1730 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1732 printk(KERN_DEBUG
"... APIC ISR field:\n");
1733 print_APIC_field(APIC_ISR
);
1734 printk(KERN_DEBUG
"... APIC TMR field:\n");
1735 print_APIC_field(APIC_TMR
);
1736 printk(KERN_DEBUG
"... APIC IRR field:\n");
1737 print_APIC_field(APIC_IRR
);
1739 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1740 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1741 apic_write(APIC_ESR
, 0);
1743 v
= apic_read(APIC_ESR
);
1744 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1747 icr
= apic_icr_read();
1748 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1749 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1751 v
= apic_read(APIC_LVTT
);
1752 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1754 if (maxlvt
> 3) { /* PC is LVT#4. */
1755 v
= apic_read(APIC_LVTPC
);
1756 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1758 v
= apic_read(APIC_LVT0
);
1759 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1760 v
= apic_read(APIC_LVT1
);
1761 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1763 if (maxlvt
> 2) { /* ERR is LVT#3. */
1764 v
= apic_read(APIC_LVTERR
);
1765 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1768 v
= apic_read(APIC_TMICT
);
1769 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1770 v
= apic_read(APIC_TMCCT
);
1771 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1772 v
= apic_read(APIC_TDCR
);
1773 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1775 if (boot_cpu_has(X86_FEATURE_EXTAPIC
)) {
1776 v
= apic_read(APIC_EFEAT
);
1777 maxlvt
= (v
>> 16) & 0xff;
1778 printk(KERN_DEBUG
"... APIC EFEAT: %08x\n", v
);
1779 v
= apic_read(APIC_ECTRL
);
1780 printk(KERN_DEBUG
"... APIC ECTRL: %08x\n", v
);
1781 for (i
= 0; i
< maxlvt
; i
++) {
1782 v
= apic_read(APIC_EILVTn(i
));
1783 printk(KERN_DEBUG
"... APIC EILVT%d: %08x\n", i
, v
);
1789 __apicdebuginit(void) print_local_APICs(int maxcpu
)
1797 for_each_online_cpu(cpu
) {
1800 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1805 __apicdebuginit(void) print_PIC(void)
1808 unsigned long flags
;
1810 if (!legacy_pic
->nr_legacy_irqs
)
1813 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1815 raw_spin_lock_irqsave(&i8259A_lock
, flags
);
1817 v
= inb(0xa1) << 8 | inb(0x21);
1818 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1820 v
= inb(0xa0) << 8 | inb(0x20);
1821 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1825 v
= inb(0xa0) << 8 | inb(0x20);
1829 raw_spin_unlock_irqrestore(&i8259A_lock
, flags
);
1831 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1833 v
= inb(0x4d1) << 8 | inb(0x4d0);
1834 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1837 static int __initdata show_lapic
= 1;
1838 static __init
int setup_show_lapic(char *arg
)
1842 if (strcmp(arg
, "all") == 0) {
1843 show_lapic
= CONFIG_NR_CPUS
;
1845 get_option(&arg
, &num
);
1852 __setup("show_lapic=", setup_show_lapic
);
1854 __apicdebuginit(int) print_ICs(void)
1856 if (apic_verbosity
== APIC_QUIET
)
1861 /* don't print out if apic is not there */
1862 if (!cpu_has_apic
&& !apic_from_smp_config())
1865 print_local_APICs(show_lapic
);
1871 late_initcall(print_ICs
);
1874 /* Where if anywhere is the i8259 connect in external int mode */
1875 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1877 void __init
enable_IO_APIC(void)
1879 int i8259_apic
, i8259_pin
;
1882 if (!legacy_pic
->nr_legacy_irqs
)
1885 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1887 /* See if any of the pins is in ExtINT mode */
1888 for (pin
= 0; pin
< ioapics
[apic
].nr_registers
; pin
++) {
1889 struct IO_APIC_route_entry entry
;
1890 entry
= ioapic_read_entry(apic
, pin
);
1892 /* If the interrupt line is enabled and in ExtInt mode
1893 * I have found the pin where the i8259 is connected.
1895 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1896 ioapic_i8259
.apic
= apic
;
1897 ioapic_i8259
.pin
= pin
;
1903 /* Look to see what if the MP table has reported the ExtINT */
1904 /* If we could not find the appropriate pin by looking at the ioapic
1905 * the i8259 probably is not connected the ioapic but give the
1906 * mptable a chance anyway.
1908 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1909 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1910 /* Trust the MP table if nothing is setup in the hardware */
1911 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1912 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1913 ioapic_i8259
.pin
= i8259_pin
;
1914 ioapic_i8259
.apic
= i8259_apic
;
1916 /* Complain if the MP table and the hardware disagree */
1917 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1918 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1920 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1924 * Do not trust the IO-APIC being empty at bootup
1930 * Not an __init, needed by the reboot code
1932 void disable_IO_APIC(void)
1935 * Clear the IO-APIC before rebooting:
1939 if (!legacy_pic
->nr_legacy_irqs
)
1943 * If the i8259 is routed through an IOAPIC
1944 * Put that IOAPIC in virtual wire mode
1945 * so legacy interrupts can be delivered.
1947 * With interrupt-remapping, for now we will use virtual wire A mode,
1948 * as virtual wire B is little complex (need to configure both
1949 * IOAPIC RTE as well as interrupt-remapping table entry).
1950 * As this gets called during crash dump, keep this simple for now.
1952 if (ioapic_i8259
.pin
!= -1 && !irq_remapping_enabled
) {
1953 struct IO_APIC_route_entry entry
;
1955 memset(&entry
, 0, sizeof(entry
));
1956 entry
.mask
= 0; /* Enabled */
1957 entry
.trigger
= 0; /* Edge */
1959 entry
.polarity
= 0; /* High */
1960 entry
.delivery_status
= 0;
1961 entry
.dest_mode
= 0; /* Physical */
1962 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1964 entry
.dest
= read_apic_id();
1967 * Add it to the IO-APIC irq-routing table:
1969 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1973 * Use virtual wire A mode when interrupt remapping is enabled.
1975 if (cpu_has_apic
|| apic_from_smp_config())
1976 disconnect_bsp_APIC(!irq_remapping_enabled
&&
1977 ioapic_i8259
.pin
!= -1);
1980 #ifdef CONFIG_X86_32
1982 * function to set the IO-APIC physical IDs based on the
1983 * values stored in the MPC table.
1985 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1987 void __init
setup_ioapic_ids_from_mpc_nocheck(void)
1989 union IO_APIC_reg_00 reg_00
;
1990 physid_mask_t phys_id_present_map
;
1993 unsigned char old_id
;
1994 unsigned long flags
;
1997 * This is broken; anything with a real cpu count has to
1998 * circumvent this idiocy regardless.
2000 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &phys_id_present_map
);
2003 * Set the IOAPIC ID to the value stored in the MPC table.
2005 for (ioapic_idx
= 0; ioapic_idx
< nr_ioapics
; ioapic_idx
++) {
2006 /* Read the register 0 value */
2007 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2008 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
2009 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2011 old_id
= mpc_ioapic_id(ioapic_idx
);
2013 if (mpc_ioapic_id(ioapic_idx
) >= get_physical_broadcast()) {
2014 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2015 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
2016 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2018 ioapics
[ioapic_idx
].mp_config
.apicid
= reg_00
.bits
.ID
;
2022 * Sanity check, is the ID really free? Every APIC in a
2023 * system must have a unique ID or we get lots of nice
2024 * 'stuck on smp_invalidate_needed IPI wait' messages.
2026 if (apic
->check_apicid_used(&phys_id_present_map
,
2027 mpc_ioapic_id(ioapic_idx
))) {
2028 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2029 ioapic_idx
, mpc_ioapic_id(ioapic_idx
));
2030 for (i
= 0; i
< get_physical_broadcast(); i
++)
2031 if (!physid_isset(i
, phys_id_present_map
))
2033 if (i
>= get_physical_broadcast())
2034 panic("Max APIC ID exceeded!\n");
2035 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2037 physid_set(i
, phys_id_present_map
);
2038 ioapics
[ioapic_idx
].mp_config
.apicid
= i
;
2041 apic
->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx
),
2043 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2044 "phys_id_present_map\n",
2045 mpc_ioapic_id(ioapic_idx
));
2046 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2050 * We need to adjust the IRQ routing table
2051 * if the ID changed.
2053 if (old_id
!= mpc_ioapic_id(ioapic_idx
))
2054 for (i
= 0; i
< mp_irq_entries
; i
++)
2055 if (mp_irqs
[i
].dstapic
== old_id
)
2057 = mpc_ioapic_id(ioapic_idx
);
2060 * Update the ID register according to the right value
2061 * from the MPC table if they are different.
2063 if (mpc_ioapic_id(ioapic_idx
) == reg_00
.bits
.ID
)
2066 apic_printk(APIC_VERBOSE
, KERN_INFO
2067 "...changing IO-APIC physical APIC ID to %d ...",
2068 mpc_ioapic_id(ioapic_idx
));
2070 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
2071 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2072 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
2073 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2078 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2079 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
2080 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2081 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
))
2082 printk("could not set ID!\n");
2084 apic_printk(APIC_VERBOSE
, " ok.\n");
2088 void __init
setup_ioapic_ids_from_mpc(void)
2094 * Don't check I/O APIC IDs for xAPIC systems. They have
2095 * no meaning without the serial APIC bus.
2097 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2098 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2100 setup_ioapic_ids_from_mpc_nocheck();
2104 int no_timer_check __initdata
;
2106 static int __init
notimercheck(char *s
)
2111 __setup("no_timer_check", notimercheck
);
2114 * There is a nasty bug in some older SMP boards, their mptable lies
2115 * about the timer IRQ. We do the following to work around the situation:
2117 * - timer IRQ defaults to IO-APIC IRQ
2118 * - if this function detects that timer IRQs are defunct, then we fall
2119 * back to ISA timer IRQs
2121 static int __init
timer_irq_works(void)
2123 unsigned long t1
= jiffies
;
2124 unsigned long flags
;
2129 local_save_flags(flags
);
2131 /* Let ten ticks pass... */
2132 mdelay((10 * 1000) / HZ
);
2133 local_irq_restore(flags
);
2136 * Expect a few ticks at least, to be sure some possible
2137 * glue logic does not lock up after one or two first
2138 * ticks in a non-ExtINT mode. Also the local APIC
2139 * might have cached one ExtINT interrupt. Finally, at
2140 * least one tick may be lost due to delays.
2144 if (time_after(jiffies
, t1
+ 4))
2150 * In the SMP+IOAPIC case it might happen that there are an unspecified
2151 * number of pending IRQ events unhandled. These cases are very rare,
2152 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2153 * better to do it this way as thus we do not have to be aware of
2154 * 'pending' interrupts in the IRQ path, except at this point.
2157 * Edge triggered needs to resend any interrupt
2158 * that was delayed but this is now handled in the device
2163 * Starting up a edge-triggered IO-APIC interrupt is
2164 * nasty - we need to make sure that we get the edge.
2165 * If it is already asserted for some reason, we need
2166 * return 1 to indicate that is was pending.
2168 * This is not complete - we should be able to fake
2169 * an edge even if it isn't on the 8259A...
2172 static unsigned int startup_ioapic_irq(struct irq_data
*data
)
2174 int was_pending
= 0, irq
= data
->irq
;
2175 unsigned long flags
;
2177 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2178 if (irq
< legacy_pic
->nr_legacy_irqs
) {
2179 legacy_pic
->mask(irq
);
2180 if (legacy_pic
->irq_pending(irq
))
2183 __unmask_ioapic(data
->chip_data
);
2184 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2189 static int ioapic_retrigger_irq(struct irq_data
*data
)
2191 struct irq_cfg
*cfg
= data
->chip_data
;
2192 unsigned long flags
;
2194 raw_spin_lock_irqsave(&vector_lock
, flags
);
2195 apic
->send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2196 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
2202 * Level and edge triggered IO-APIC interrupts need different handling,
2203 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2204 * handled with the level-triggered descriptor, but that one has slightly
2205 * more overhead. Level-triggered interrupts cannot be handled with the
2206 * edge-triggered handler, without risking IRQ storms and other ugly
2211 void send_cleanup_vector(struct irq_cfg
*cfg
)
2213 cpumask_var_t cleanup_mask
;
2215 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
2217 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
2218 apic
->send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
2220 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
2221 apic
->send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
2222 free_cpumask_var(cleanup_mask
);
2224 cfg
->move_in_progress
= 0;
2227 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
2230 struct irq_pin_list
*entry
;
2231 u8 vector
= cfg
->vector
;
2233 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2239 * With interrupt-remapping, destination information comes
2240 * from interrupt-remapping table entry.
2242 if (!irq_remapped(cfg
))
2243 io_apic_write(apic
, 0x11 + pin
*2, dest
);
2244 reg
= io_apic_read(apic
, 0x10 + pin
*2);
2245 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
2247 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
2252 * Either sets data->affinity to a valid value, and returns
2253 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2254 * leaves data->affinity untouched.
2256 int __ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2257 unsigned int *dest_id
)
2259 struct irq_cfg
*cfg
= data
->chip_data
;
2260 unsigned int irq
= data
->irq
;
2263 if (!cpumask_intersects(mask
, cpu_online_mask
))
2266 err
= assign_irq_vector(irq
, cfg
, mask
);
2270 err
= apic
->cpu_mask_to_apicid_and(mask
, cfg
->domain
, dest_id
);
2272 if (assign_irq_vector(irq
, cfg
, data
->affinity
))
2273 pr_err("Failed to recover vector for irq %d\n", irq
);
2277 cpumask_copy(data
->affinity
, mask
);
2283 ioapic_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
2286 unsigned int dest
, irq
= data
->irq
;
2287 unsigned long flags
;
2290 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2291 ret
= __ioapic_set_affinity(data
, mask
, &dest
);
2293 /* Only the high 8 bits are valid. */
2294 dest
= SET_APIC_LOGICAL_ID(dest
);
2295 __target_IO_APIC_irq(irq
, dest
, data
->chip_data
);
2297 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2301 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2303 unsigned vector
, me
;
2309 me
= smp_processor_id();
2310 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2313 struct irq_desc
*desc
;
2314 struct irq_cfg
*cfg
;
2315 irq
= __this_cpu_read(vector_irq
[vector
]);
2320 desc
= irq_to_desc(irq
);
2325 raw_spin_lock(&desc
->lock
);
2328 * Check if the irq migration is in progress. If so, we
2329 * haven't received the cleanup request yet for this irq.
2331 if (cfg
->move_in_progress
)
2334 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2337 irr
= apic_read(APIC_IRR
+ (vector
/ 32 * 0x10));
2339 * Check if the vector that needs to be cleanedup is
2340 * registered at the cpu's IRR. If so, then this is not
2341 * the best time to clean it up. Lets clean it up in the
2342 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2345 if (irr
& (1 << (vector
% 32))) {
2346 apic
->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR
);
2349 __this_cpu_write(vector_irq
[vector
], -1);
2351 raw_spin_unlock(&desc
->lock
);
2357 static void __irq_complete_move(struct irq_cfg
*cfg
, unsigned vector
)
2361 if (likely(!cfg
->move_in_progress
))
2364 me
= smp_processor_id();
2366 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2367 send_cleanup_vector(cfg
);
2370 static void irq_complete_move(struct irq_cfg
*cfg
)
2372 __irq_complete_move(cfg
, ~get_irq_regs()->orig_ax
);
2375 void irq_force_complete_move(int irq
)
2377 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
2382 __irq_complete_move(cfg
, cfg
->vector
);
2385 static inline void irq_complete_move(struct irq_cfg
*cfg
) { }
2388 static void ack_apic_edge(struct irq_data
*data
)
2390 irq_complete_move(data
->chip_data
);
2395 atomic_t irq_mis_count
;
2397 #ifdef CONFIG_GENERIC_PENDING_IRQ
2398 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
2400 struct irq_pin_list
*entry
;
2401 unsigned long flags
;
2403 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2404 for_each_irq_pin(entry
, cfg
->irq_2_pin
) {
2409 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
2410 /* Is the remote IRR bit set? */
2411 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
2412 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2416 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2421 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
2423 /* If we are moving the irq we need to mask it */
2424 if (unlikely(irqd_is_setaffinity_pending(data
))) {
2431 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
2432 struct irq_cfg
*cfg
, bool masked
)
2434 if (unlikely(masked
)) {
2435 /* Only migrate the irq if the ack has been received.
2437 * On rare occasions the broadcast level triggered ack gets
2438 * delayed going to ioapics, and if we reprogram the
2439 * vector while Remote IRR is still set the irq will never
2442 * To prevent this scenario we read the Remote IRR bit
2443 * of the ioapic. This has two effects.
2444 * - On any sane system the read of the ioapic will
2445 * flush writes (and acks) going to the ioapic from
2447 * - We get to see if the ACK has actually been delivered.
2449 * Based on failed experiments of reprogramming the
2450 * ioapic entry from outside of irq context starting
2451 * with masking the ioapic entry and then polling until
2452 * Remote IRR was clear before reprogramming the
2453 * ioapic I don't trust the Remote IRR bit to be
2454 * completey accurate.
2456 * However there appears to be no other way to plug
2457 * this race, so if the Remote IRR bit is not
2458 * accurate and is causing problems then it is a hardware bug
2459 * and you can go talk to the chipset vendor about it.
2461 if (!io_apic_level_ack_pending(cfg
))
2462 irq_move_masked_irq(data
);
2467 static inline bool ioapic_irqd_mask(struct irq_data
*data
, struct irq_cfg
*cfg
)
2471 static inline void ioapic_irqd_unmask(struct irq_data
*data
,
2472 struct irq_cfg
*cfg
, bool masked
)
2477 static void ack_apic_level(struct irq_data
*data
)
2479 struct irq_cfg
*cfg
= data
->chip_data
;
2480 int i
, irq
= data
->irq
;
2484 irq_complete_move(cfg
);
2485 masked
= ioapic_irqd_mask(data
, cfg
);
2488 * It appears there is an erratum which affects at least version 0x11
2489 * of I/O APIC (that's the 82093AA and cores integrated into various
2490 * chipsets). Under certain conditions a level-triggered interrupt is
2491 * erroneously delivered as edge-triggered one but the respective IRR
2492 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2493 * message but it will never arrive and further interrupts are blocked
2494 * from the source. The exact reason is so far unknown, but the
2495 * phenomenon was observed when two consecutive interrupt requests
2496 * from a given source get delivered to the same CPU and the source is
2497 * temporarily disabled in between.
2499 * A workaround is to simulate an EOI message manually. We achieve it
2500 * by setting the trigger mode to edge and then to level when the edge
2501 * trigger mode gets detected in the TMR of a local APIC for a
2502 * level-triggered interrupt. We mask the source for the time of the
2503 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2504 * The idea is from Manfred Spraul. --macro
2506 * Also in the case when cpu goes offline, fixup_irqs() will forward
2507 * any unhandled interrupt on the offlined cpu to the new cpu
2508 * destination that is handling the corresponding interrupt. This
2509 * interrupt forwarding is done via IPI's. Hence, in this case also
2510 * level-triggered io-apic interrupt will be seen as an edge
2511 * interrupt in the IRR. And we can't rely on the cpu's EOI
2512 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2513 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2514 * supporting EOI register, we do an explicit EOI to clear the
2515 * remote IRR and on IO-APIC's which don't have an EOI register,
2516 * we use the above logic (mask+edge followed by unmask+level) from
2517 * Manfred Spraul to clear the remote IRR.
2520 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2523 * We must acknowledge the irq before we move it or the acknowledge will
2524 * not propagate properly.
2529 * Tail end of clearing remote IRR bit (either by delivering the EOI
2530 * message via io-apic EOI register write or simulating it using
2531 * mask+edge followed by unnask+level logic) manually when the
2532 * level triggered interrupt is seen as the edge triggered interrupt
2535 if (!(v
& (1 << (i
& 0x1f)))) {
2536 atomic_inc(&irq_mis_count
);
2538 eoi_ioapic_irq(irq
, cfg
);
2541 ioapic_irqd_unmask(data
, cfg
, masked
);
2544 #ifdef CONFIG_IRQ_REMAP
2545 static void ir_ack_apic_edge(struct irq_data
*data
)
2550 static void ir_ack_apic_level(struct irq_data
*data
)
2553 eoi_ioapic_irq(data
->irq
, data
->chip_data
);
2556 static void ir_print_prefix(struct irq_data
*data
, struct seq_file
*p
)
2558 seq_printf(p
, " IR-%s", data
->chip
->name
);
2561 static void irq_remap_modify_chip_defaults(struct irq_chip
*chip
)
2563 chip
->irq_print_chip
= ir_print_prefix
;
2564 chip
->irq_ack
= ir_ack_apic_edge
;
2565 chip
->irq_eoi
= ir_ack_apic_level
;
2568 chip
->irq_set_affinity
= set_remapped_irq_affinity
;
2571 #endif /* CONFIG_IRQ_REMAP */
2573 static struct irq_chip ioapic_chip __read_mostly
= {
2575 .irq_startup
= startup_ioapic_irq
,
2576 .irq_mask
= mask_ioapic_irq
,
2577 .irq_unmask
= unmask_ioapic_irq
,
2578 .irq_ack
= ack_apic_edge
,
2579 .irq_eoi
= ack_apic_level
,
2581 .irq_set_affinity
= ioapic_set_affinity
,
2583 .irq_retrigger
= ioapic_retrigger_irq
,
2586 static inline void init_IO_APIC_traps(void)
2588 struct irq_cfg
*cfg
;
2592 * NOTE! The local APIC isn't very good at handling
2593 * multiple interrupts at the same interrupt level.
2594 * As the interrupt level is determined by taking the
2595 * vector number and shifting that right by 4, we
2596 * want to spread these out a bit so that they don't
2597 * all fall in the same interrupt level.
2599 * Also, we've got to be careful not to trash gate
2600 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2602 for_each_active_irq(irq
) {
2603 cfg
= irq_get_chip_data(irq
);
2604 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2606 * Hmm.. We don't have an entry for this,
2607 * so default to an old-fashioned 8259
2608 * interrupt if we can..
2610 if (irq
< legacy_pic
->nr_legacy_irqs
)
2611 legacy_pic
->make_irq(irq
);
2613 /* Strange. Oh, well.. */
2614 irq_set_chip(irq
, &no_irq_chip
);
2620 * The local APIC irq-chip implementation:
2623 static void mask_lapic_irq(struct irq_data
*data
)
2627 v
= apic_read(APIC_LVT0
);
2628 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2631 static void unmask_lapic_irq(struct irq_data
*data
)
2635 v
= apic_read(APIC_LVT0
);
2636 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2639 static void ack_lapic_irq(struct irq_data
*data
)
2644 static struct irq_chip lapic_chip __read_mostly
= {
2645 .name
= "local-APIC",
2646 .irq_mask
= mask_lapic_irq
,
2647 .irq_unmask
= unmask_lapic_irq
,
2648 .irq_ack
= ack_lapic_irq
,
2651 static void lapic_register_intr(int irq
)
2653 irq_clear_status_flags(irq
, IRQ_LEVEL
);
2654 irq_set_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2659 * This looks a bit hackish but it's about the only one way of sending
2660 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2661 * not support the ExtINT mode, unfortunately. We need to send these
2662 * cycles as some i82489DX-based boards have glue logic that keeps the
2663 * 8259A interrupt line asserted until INTA. --macro
2665 static inline void __init
unlock_ExtINT_logic(void)
2668 struct IO_APIC_route_entry entry0
, entry1
;
2669 unsigned char save_control
, save_freq_select
;
2671 pin
= find_isa_irq_pin(8, mp_INT
);
2676 apic
= find_isa_irq_apic(8, mp_INT
);
2682 entry0
= ioapic_read_entry(apic
, pin
);
2683 clear_IO_APIC_pin(apic
, pin
);
2685 memset(&entry1
, 0, sizeof(entry1
));
2687 entry1
.dest_mode
= 0; /* physical delivery */
2688 entry1
.mask
= 0; /* unmask IRQ now */
2689 entry1
.dest
= hard_smp_processor_id();
2690 entry1
.delivery_mode
= dest_ExtINT
;
2691 entry1
.polarity
= entry0
.polarity
;
2695 ioapic_write_entry(apic
, pin
, entry1
);
2697 save_control
= CMOS_READ(RTC_CONTROL
);
2698 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2699 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2701 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2706 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2710 CMOS_WRITE(save_control
, RTC_CONTROL
);
2711 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2712 clear_IO_APIC_pin(apic
, pin
);
2714 ioapic_write_entry(apic
, pin
, entry0
);
2717 static int disable_timer_pin_1 __initdata
;
2718 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2719 static int __init
disable_timer_pin_setup(char *arg
)
2721 disable_timer_pin_1
= 1;
2724 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2726 int timer_through_8259 __initdata
;
2729 * This code may look a bit paranoid, but it's supposed to cooperate with
2730 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2731 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2732 * fanatically on his truly buggy board.
2734 * FIXME: really need to revamp this for all platforms.
2736 static inline void __init
check_timer(void)
2738 struct irq_cfg
*cfg
= irq_get_chip_data(0);
2739 int node
= cpu_to_node(0);
2740 int apic1
, pin1
, apic2
, pin2
;
2741 unsigned long flags
;
2744 local_irq_save(flags
);
2747 * get/set the timer IRQ vector:
2749 legacy_pic
->mask(0);
2750 assign_irq_vector(0, cfg
, apic
->target_cpus());
2753 * As IRQ0 is to be enabled in the 8259A, the virtual
2754 * wire has to be disabled in the local APIC. Also
2755 * timer interrupts need to be acknowledged manually in
2756 * the 8259A for the i82489DX when using the NMI
2757 * watchdog as that APIC treats NMIs as level-triggered.
2758 * The AEOI mode will finish them in the 8259A
2761 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2762 legacy_pic
->init(1);
2764 pin1
= find_isa_irq_pin(0, mp_INT
);
2765 apic1
= find_isa_irq_apic(0, mp_INT
);
2766 pin2
= ioapic_i8259
.pin
;
2767 apic2
= ioapic_i8259
.apic
;
2769 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2770 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2771 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2774 * Some BIOS writers are clueless and report the ExtINTA
2775 * I/O APIC input from the cascaded 8259A as the timer
2776 * interrupt input. So just in case, if only one pin
2777 * was found above, try it both directly and through the
2781 if (irq_remapping_enabled
)
2782 panic("BIOS bug: timer not connected to IO-APIC");
2786 } else if (pin2
== -1) {
2793 * Ok, does IRQ0 through the IOAPIC work?
2796 add_pin_to_irq_node(cfg
, node
, apic1
, pin1
);
2797 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2799 /* for edge trigger, setup_ioapic_irq already
2800 * leave it unmasked.
2801 * so only need to unmask if it is level-trigger
2802 * do we really have level trigger timer?
2805 idx
= find_irq_entry(apic1
, pin1
, mp_INT
);
2806 if (idx
!= -1 && irq_trigger(idx
))
2809 if (timer_irq_works()) {
2810 if (disable_timer_pin_1
> 0)
2811 clear_IO_APIC_pin(0, pin1
);
2814 if (irq_remapping_enabled
)
2815 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2816 local_irq_disable();
2817 clear_IO_APIC_pin(apic1
, pin1
);
2819 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2820 "8254 timer not connected to IO-APIC\n");
2822 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2823 "(IRQ0) through the 8259A ...\n");
2824 apic_printk(APIC_QUIET
, KERN_INFO
2825 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2827 * legacy devices should be connected to IO APIC #0
2829 replace_pin_at_irq_node(cfg
, node
, apic1
, pin1
, apic2
, pin2
);
2830 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2831 legacy_pic
->unmask(0);
2832 if (timer_irq_works()) {
2833 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2834 timer_through_8259
= 1;
2838 * Cleanup, just in case ...
2840 local_irq_disable();
2841 legacy_pic
->mask(0);
2842 clear_IO_APIC_pin(apic2
, pin2
);
2843 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2846 apic_printk(APIC_QUIET
, KERN_INFO
2847 "...trying to set up timer as Virtual Wire IRQ...\n");
2849 lapic_register_intr(0);
2850 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2851 legacy_pic
->unmask(0);
2853 if (timer_irq_works()) {
2854 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2857 local_irq_disable();
2858 legacy_pic
->mask(0);
2859 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
2860 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
2862 apic_printk(APIC_QUIET
, KERN_INFO
2863 "...trying to set up timer as ExtINT IRQ...\n");
2865 legacy_pic
->init(0);
2866 legacy_pic
->make_irq(0);
2867 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
2869 unlock_ExtINT_logic();
2871 if (timer_irq_works()) {
2872 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
2875 local_irq_disable();
2876 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
2877 if (x2apic_preenabled
)
2878 apic_printk(APIC_QUIET
, KERN_INFO
2879 "Perhaps problem with the pre-enabled x2apic mode\n"
2880 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2881 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2882 "report. Then try booting with the 'noapic' option.\n");
2884 local_irq_restore(flags
);
2888 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2889 * to devices. However there may be an I/O APIC pin available for
2890 * this interrupt regardless. The pin may be left unconnected, but
2891 * typically it will be reused as an ExtINT cascade interrupt for
2892 * the master 8259A. In the MPS case such a pin will normally be
2893 * reported as an ExtINT interrupt in the MP table. With ACPI
2894 * there is no provision for ExtINT interrupts, and in the absence
2895 * of an override it would be treated as an ordinary ISA I/O APIC
2896 * interrupt, that is edge-triggered and unmasked by default. We
2897 * used to do this, but it caused problems on some systems because
2898 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2899 * the same ExtINT cascade interrupt to drive the local APIC of the
2900 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2901 * the I/O APIC in all cases now. No actual device should request
2902 * it anyway. --macro
2904 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2906 void __init
setup_IO_APIC(void)
2910 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2912 io_apic_irqs
= legacy_pic
->nr_legacy_irqs
? ~PIC_IRQS
: ~0UL;
2914 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
2916 * Set up IO-APIC IRQ routing.
2918 x86_init
.mpparse
.setup_ioapic_ids();
2921 setup_IO_APIC_irqs();
2922 init_IO_APIC_traps();
2923 if (legacy_pic
->nr_legacy_irqs
)
2928 * Called after all the initialization is done. If we didn't find any
2929 * APIC bugs then we can allow the modify fast path
2932 static int __init
io_apic_bug_finalize(void)
2934 if (sis_apic_bug
== -1)
2939 late_initcall(io_apic_bug_finalize
);
2941 static void resume_ioapic_id(int ioapic_idx
)
2943 unsigned long flags
;
2944 union IO_APIC_reg_00 reg_00
;
2946 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
2947 reg_00
.raw
= io_apic_read(ioapic_idx
, 0);
2948 if (reg_00
.bits
.ID
!= mpc_ioapic_id(ioapic_idx
)) {
2949 reg_00
.bits
.ID
= mpc_ioapic_id(ioapic_idx
);
2950 io_apic_write(ioapic_idx
, 0, reg_00
.raw
);
2952 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
2955 static void ioapic_resume(void)
2959 for (ioapic_idx
= nr_ioapics
- 1; ioapic_idx
>= 0; ioapic_idx
--)
2960 resume_ioapic_id(ioapic_idx
);
2962 restore_ioapic_entries();
2965 static struct syscore_ops ioapic_syscore_ops
= {
2966 .suspend
= save_ioapic_entries
,
2967 .resume
= ioapic_resume
,
2970 static int __init
ioapic_init_ops(void)
2972 register_syscore_ops(&ioapic_syscore_ops
);
2977 device_initcall(ioapic_init_ops
);
2980 * Dynamic irq allocate and deallocation
2982 unsigned int create_irq_nr(unsigned int from
, int node
)
2984 struct irq_cfg
*cfg
;
2985 unsigned long flags
;
2986 unsigned int ret
= 0;
2989 if (from
< nr_irqs_gsi
)
2992 irq
= alloc_irq_from(from
, node
);
2995 cfg
= alloc_irq_cfg(irq
, node
);
2997 free_irq_at(irq
, NULL
);
3001 raw_spin_lock_irqsave(&vector_lock
, flags
);
3002 if (!__assign_irq_vector(irq
, cfg
, apic
->target_cpus()))
3004 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3007 irq_set_chip_data(irq
, cfg
);
3008 irq_clear_status_flags(irq
, IRQ_NOREQUEST
);
3010 free_irq_at(irq
, cfg
);
3015 int create_irq(void)
3017 int node
= cpu_to_node(0);
3018 unsigned int irq_want
;
3021 irq_want
= nr_irqs_gsi
;
3022 irq
= create_irq_nr(irq_want
, node
);
3030 void destroy_irq(unsigned int irq
)
3032 struct irq_cfg
*cfg
= irq_get_chip_data(irq
);
3033 unsigned long flags
;
3035 irq_set_status_flags(irq
, IRQ_NOREQUEST
|IRQ_NOPROBE
);
3037 if (irq_remapped(cfg
))
3038 free_remapped_irq(irq
);
3039 raw_spin_lock_irqsave(&vector_lock
, flags
);
3040 __clear_irq_vector(irq
, cfg
);
3041 raw_spin_unlock_irqrestore(&vector_lock
, flags
);
3042 free_irq_at(irq
, cfg
);
3046 * MSI message composition
3048 #ifdef CONFIG_PCI_MSI
3049 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
,
3050 struct msi_msg
*msg
, u8 hpet_id
)
3052 struct irq_cfg
*cfg
;
3060 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3064 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3065 apic
->target_cpus(), &dest
);
3069 if (irq_remapped(cfg
)) {
3070 compose_remapped_msi_msg(pdev
, irq
, dest
, msg
, hpet_id
);
3074 if (x2apic_enabled())
3075 msg
->address_hi
= MSI_ADDR_BASE_HI
|
3076 MSI_ADDR_EXT_DEST_ID(dest
);
3078 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3082 ((apic
->irq_dest_mode
== 0) ?
3083 MSI_ADDR_DEST_MODE_PHYSICAL
:
3084 MSI_ADDR_DEST_MODE_LOGICAL
) |
3085 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3086 MSI_ADDR_REDIRECTION_CPU
:
3087 MSI_ADDR_REDIRECTION_LOWPRI
) |
3088 MSI_ADDR_DEST_ID(dest
);
3091 MSI_DATA_TRIGGER_EDGE
|
3092 MSI_DATA_LEVEL_ASSERT
|
3093 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3094 MSI_DATA_DELIVERY_FIXED
:
3095 MSI_DATA_DELIVERY_LOWPRI
) |
3096 MSI_DATA_VECTOR(cfg
->vector
);
3103 msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3105 struct irq_cfg
*cfg
= data
->chip_data
;
3109 if (__ioapic_set_affinity(data
, mask
, &dest
))
3112 __get_cached_msi_msg(data
->msi_desc
, &msg
);
3114 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3115 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3116 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3117 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3119 __write_msi_msg(data
->msi_desc
, &msg
);
3123 #endif /* CONFIG_SMP */
3126 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3127 * which implement the MSI or MSI-X Capability Structure.
3129 static struct irq_chip msi_chip
= {
3131 .irq_unmask
= unmask_msi_irq
,
3132 .irq_mask
= mask_msi_irq
,
3133 .irq_ack
= ack_apic_edge
,
3135 .irq_set_affinity
= msi_set_affinity
,
3137 .irq_retrigger
= ioapic_retrigger_irq
,
3140 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3142 struct irq_chip
*chip
= &msi_chip
;
3146 ret
= msi_compose_msg(dev
, irq
, &msg
, -1);
3150 irq_set_msi_desc(irq
, msidesc
);
3151 write_msi_msg(irq
, &msg
);
3153 if (irq_remapped(irq_get_chip_data(irq
))) {
3154 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
3155 irq_remap_modify_chip_defaults(chip
);
3158 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3160 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3165 int native_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3167 int node
, ret
, sub_handle
, index
= 0;
3168 unsigned int irq
, irq_want
;
3169 struct msi_desc
*msidesc
;
3171 /* x86 doesn't support multiple MSI yet */
3172 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
3175 node
= dev_to_node(&dev
->dev
);
3176 irq_want
= nr_irqs_gsi
;
3178 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3179 irq
= create_irq_nr(irq_want
, node
);
3183 if (!irq_remapping_enabled
)
3188 * allocate the consecutive block of IRTE's
3191 index
= msi_alloc_remapped_irq(dev
, irq
, nvec
);
3197 ret
= msi_setup_remapped_irq(dev
, irq
, index
,
3203 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3215 void native_teardown_msi_irq(unsigned int irq
)
3220 #ifdef CONFIG_DMAR_TABLE
3223 dmar_msi_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
,
3226 struct irq_cfg
*cfg
= data
->chip_data
;
3227 unsigned int dest
, irq
= data
->irq
;
3230 if (__ioapic_set_affinity(data
, mask
, &dest
))
3233 dmar_msi_read(irq
, &msg
);
3235 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3236 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3237 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3238 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3239 msg
.address_hi
= MSI_ADDR_BASE_HI
| MSI_ADDR_EXT_DEST_ID(dest
);
3241 dmar_msi_write(irq
, &msg
);
3246 #endif /* CONFIG_SMP */
3248 static struct irq_chip dmar_msi_type
= {
3250 .irq_unmask
= dmar_msi_unmask
,
3251 .irq_mask
= dmar_msi_mask
,
3252 .irq_ack
= ack_apic_edge
,
3254 .irq_set_affinity
= dmar_msi_set_affinity
,
3256 .irq_retrigger
= ioapic_retrigger_irq
,
3259 int arch_setup_dmar_msi(unsigned int irq
)
3264 ret
= msi_compose_msg(NULL
, irq
, &msg
, -1);
3267 dmar_msi_write(irq
, &msg
);
3268 irq_set_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3274 #ifdef CONFIG_HPET_TIMER
3277 static int hpet_msi_set_affinity(struct irq_data
*data
,
3278 const struct cpumask
*mask
, bool force
)
3280 struct irq_cfg
*cfg
= data
->chip_data
;
3284 if (__ioapic_set_affinity(data
, mask
, &dest
))
3287 hpet_msi_read(data
->handler_data
, &msg
);
3289 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3290 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3291 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3292 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3294 hpet_msi_write(data
->handler_data
, &msg
);
3299 #endif /* CONFIG_SMP */
3301 static struct irq_chip hpet_msi_type
= {
3303 .irq_unmask
= hpet_msi_unmask
,
3304 .irq_mask
= hpet_msi_mask
,
3305 .irq_ack
= ack_apic_edge
,
3307 .irq_set_affinity
= hpet_msi_set_affinity
,
3309 .irq_retrigger
= ioapic_retrigger_irq
,
3312 int arch_setup_hpet_msi(unsigned int irq
, unsigned int id
)
3314 struct irq_chip
*chip
= &hpet_msi_type
;
3318 if (irq_remapping_enabled
) {
3319 if (!setup_hpet_msi_remapped(irq
, id
))
3323 ret
= msi_compose_msg(NULL
, irq
, &msg
, id
);
3327 hpet_msi_write(irq_get_handler_data(irq
), &msg
);
3328 irq_set_status_flags(irq
, IRQ_MOVE_PCNTXT
);
3329 if (irq_remapped(irq_get_chip_data(irq
)))
3330 irq_remap_modify_chip_defaults(chip
);
3332 irq_set_chip_and_handler_name(irq
, chip
, handle_edge_irq
, "edge");
3337 #endif /* CONFIG_PCI_MSI */
3339 * Hypertransport interrupt support
3341 #ifdef CONFIG_HT_IRQ
3345 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3347 struct ht_irq_msg msg
;
3348 fetch_ht_irq_msg(irq
, &msg
);
3350 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3351 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3353 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3354 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3356 write_ht_irq_msg(irq
, &msg
);
3360 ht_set_affinity(struct irq_data
*data
, const struct cpumask
*mask
, bool force
)
3362 struct irq_cfg
*cfg
= data
->chip_data
;
3365 if (__ioapic_set_affinity(data
, mask
, &dest
))
3368 target_ht_irq(data
->irq
, dest
, cfg
->vector
);
3374 static struct irq_chip ht_irq_chip
= {
3376 .irq_mask
= mask_ht_irq
,
3377 .irq_unmask
= unmask_ht_irq
,
3378 .irq_ack
= ack_apic_edge
,
3380 .irq_set_affinity
= ht_set_affinity
,
3382 .irq_retrigger
= ioapic_retrigger_irq
,
3385 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3387 struct irq_cfg
*cfg
;
3388 struct ht_irq_msg msg
;
3396 err
= assign_irq_vector(irq
, cfg
, apic
->target_cpus());
3400 err
= apic
->cpu_mask_to_apicid_and(cfg
->domain
,
3401 apic
->target_cpus(), &dest
);
3405 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3409 HT_IRQ_LOW_DEST_ID(dest
) |
3410 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3411 ((apic
->irq_dest_mode
== 0) ?
3412 HT_IRQ_LOW_DM_PHYSICAL
:
3413 HT_IRQ_LOW_DM_LOGICAL
) |
3414 HT_IRQ_LOW_RQEOI_EDGE
|
3415 ((apic
->irq_delivery_mode
!= dest_LowestPrio
) ?
3416 HT_IRQ_LOW_MT_FIXED
:
3417 HT_IRQ_LOW_MT_ARBITRATED
) |
3418 HT_IRQ_LOW_IRQ_MASKED
;
3420 write_ht_irq_msg(irq
, &msg
);
3422 irq_set_chip_and_handler_name(irq
, &ht_irq_chip
,
3423 handle_edge_irq
, "edge");
3425 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3429 #endif /* CONFIG_HT_IRQ */
3432 io_apic_setup_irq_pin(unsigned int irq
, int node
, struct io_apic_irq_attr
*attr
)
3434 struct irq_cfg
*cfg
= alloc_irq_and_cfg_at(irq
, node
);
3439 ret
= __add_pin_to_irq_node(cfg
, node
, attr
->ioapic
, attr
->ioapic_pin
);
3441 setup_ioapic_irq(irq
, cfg
, attr
);
3445 int io_apic_setup_irq_pin_once(unsigned int irq
, int node
,
3446 struct io_apic_irq_attr
*attr
)
3448 unsigned int ioapic_idx
= attr
->ioapic
, pin
= attr
->ioapic_pin
;
3451 /* Avoid redundant programming */
3452 if (test_bit(pin
, ioapics
[ioapic_idx
].pin_programmed
)) {
3453 pr_debug("Pin %d-%d already programmed\n",
3454 mpc_ioapic_id(ioapic_idx
), pin
);
3457 ret
= io_apic_setup_irq_pin(irq
, node
, attr
);
3459 set_bit(pin
, ioapics
[ioapic_idx
].pin_programmed
);
3463 static int __init
io_apic_get_redir_entries(int ioapic
)
3465 union IO_APIC_reg_01 reg_01
;
3466 unsigned long flags
;
3468 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3469 reg_01
.raw
= io_apic_read(ioapic
, 1);
3470 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3472 /* The register returns the maximum index redir index
3473 * supported, which is one less than the total number of redir
3476 return reg_01
.bits
.entries
+ 1;
3479 static void __init
probe_nr_irqs_gsi(void)
3483 nr
= gsi_top
+ NR_IRQS_LEGACY
;
3484 if (nr
> nr_irqs_gsi
)
3487 printk(KERN_DEBUG
"nr_irqs_gsi: %d\n", nr_irqs_gsi
);
3490 int get_nr_irqs_gsi(void)
3495 int __init
arch_probe_nr_irqs(void)
3499 if (nr_irqs
> (NR_VECTORS
* nr_cpu_ids
))
3500 nr_irqs
= NR_VECTORS
* nr_cpu_ids
;
3502 nr
= nr_irqs_gsi
+ 8 * nr_cpu_ids
;
3503 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3505 * for MSI and HT dyn irq
3507 nr
+= nr_irqs_gsi
* 16;
3512 return NR_IRQS_LEGACY
;
3515 int io_apic_set_pci_routing(struct device
*dev
, int irq
,
3516 struct io_apic_irq_attr
*irq_attr
)
3520 if (!IO_APIC_IRQ(irq
)) {
3521 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3526 node
= dev
? dev_to_node(dev
) : cpu_to_node(0);
3528 return io_apic_setup_irq_pin_once(irq
, node
, irq_attr
);
3531 #ifdef CONFIG_X86_32
3532 static int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3534 union IO_APIC_reg_00 reg_00
;
3535 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3537 unsigned long flags
;
3541 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3542 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3543 * supports up to 16 on one shared APIC bus.
3545 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3546 * advantage of new APIC bus architecture.
3549 if (physids_empty(apic_id_map
))
3550 apic
->ioapic_phys_id_map(&phys_cpu_present_map
, &apic_id_map
);
3552 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3553 reg_00
.raw
= io_apic_read(ioapic
, 0);
3554 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3556 if (apic_id
>= get_physical_broadcast()) {
3557 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3558 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3559 apic_id
= reg_00
.bits
.ID
;
3563 * Every APIC in a system must have a unique ID or we get lots of nice
3564 * 'stuck on smp_invalidate_needed IPI wait' messages.
3566 if (apic
->check_apicid_used(&apic_id_map
, apic_id
)) {
3568 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3569 if (!apic
->check_apicid_used(&apic_id_map
, i
))
3573 if (i
== get_physical_broadcast())
3574 panic("Max apic_id exceeded!\n");
3576 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3577 "trying %d\n", ioapic
, apic_id
, i
);
3582 apic
->apicid_to_cpu_present(apic_id
, &tmp
);
3583 physids_or(apic_id_map
, apic_id_map
, tmp
);
3585 if (reg_00
.bits
.ID
!= apic_id
) {
3586 reg_00
.bits
.ID
= apic_id
;
3588 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3589 io_apic_write(ioapic
, 0, reg_00
.raw
);
3590 reg_00
.raw
= io_apic_read(ioapic
, 0);
3591 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3594 if (reg_00
.bits
.ID
!= apic_id
) {
3595 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3600 apic_printk(APIC_VERBOSE
, KERN_INFO
3601 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3606 static u8 __init
io_apic_unique_id(u8 id
)
3608 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
3609 !APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
3610 return io_apic_get_unique_id(nr_ioapics
, id
);
3615 static u8 __init
io_apic_unique_id(u8 id
)
3618 DECLARE_BITMAP(used
, 256);
3620 bitmap_zero(used
, 256);
3621 for (i
= 0; i
< nr_ioapics
; i
++) {
3622 __set_bit(mpc_ioapic_id(i
), used
);
3624 if (!test_bit(id
, used
))
3626 return find_first_zero_bit(used
, 256);
3630 static int __init
io_apic_get_version(int ioapic
)
3632 union IO_APIC_reg_01 reg_01
;
3633 unsigned long flags
;
3635 raw_spin_lock_irqsave(&ioapic_lock
, flags
);
3636 reg_01
.raw
= io_apic_read(ioapic
, 1);
3637 raw_spin_unlock_irqrestore(&ioapic_lock
, flags
);
3639 return reg_01
.bits
.version
;
3642 int acpi_get_override_irq(u32 gsi
, int *trigger
, int *polarity
)
3644 int ioapic
, pin
, idx
;
3646 if (skip_ioapic_setup
)
3649 ioapic
= mp_find_ioapic(gsi
);
3653 pin
= mp_find_ioapic_pin(ioapic
, gsi
);
3657 idx
= find_irq_entry(ioapic
, pin
, mp_INT
);
3661 *trigger
= irq_trigger(idx
);
3662 *polarity
= irq_polarity(idx
);
3667 * This function currently is only a helper for the i386 smp boot process where
3668 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3669 * so mask in all cases should simply be apic->target_cpus()
3672 void __init
setup_ioapic_dest(void)
3674 int pin
, ioapic
, irq
, irq_entry
;
3675 const struct cpumask
*mask
;
3676 struct irq_data
*idata
;
3678 if (skip_ioapic_setup
== 1)
3681 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++)
3682 for (pin
= 0; pin
< ioapics
[ioapic
].nr_registers
; pin
++) {
3683 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
3684 if (irq_entry
== -1)
3686 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
3688 if ((ioapic
> 0) && (irq
> 16))
3691 idata
= irq_get_irq_data(irq
);
3694 * Honour affinities which have been set in early boot
3696 if (!irqd_can_balance(idata
) || irqd_affinity_was_set(idata
))
3697 mask
= idata
->affinity
;
3699 mask
= apic
->target_cpus();
3701 if (irq_remapping_enabled
)
3702 set_remapped_irq_affinity(idata
, mask
, false);
3704 ioapic_set_affinity(idata
, mask
, false);
3710 #define IOAPIC_RESOURCE_NAME_SIZE 11
3712 static struct resource
*ioapic_resources
;
3714 static struct resource
* __init
ioapic_setup_resources(int nr_ioapics
)
3717 struct resource
*res
;
3721 if (nr_ioapics
<= 0)
3724 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
3727 mem
= alloc_bootmem(n
);
3730 mem
+= sizeof(struct resource
) * nr_ioapics
;
3732 for (i
= 0; i
< nr_ioapics
; i
++) {
3734 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
3735 snprintf(mem
, IOAPIC_RESOURCE_NAME_SIZE
, "IOAPIC %u", i
);
3736 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
3739 ioapic_resources
= res
;
3744 void __init
native_io_apic_init_mappings(void)
3746 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
3747 struct resource
*ioapic_res
;
3750 ioapic_res
= ioapic_setup_resources(nr_ioapics
);
3751 for (i
= 0; i
< nr_ioapics
; i
++) {
3752 if (smp_found_config
) {
3753 ioapic_phys
= mpc_ioapic_addr(i
);
3754 #ifdef CONFIG_X86_32
3757 "WARNING: bogus zero IO-APIC "
3758 "address found in MPTABLE, "
3759 "disabling IO/APIC support!\n");
3760 smp_found_config
= 0;
3761 skip_ioapic_setup
= 1;
3762 goto fake_ioapic_page
;
3766 #ifdef CONFIG_X86_32
3769 ioapic_phys
= (unsigned long)alloc_bootmem_pages(PAGE_SIZE
);
3770 ioapic_phys
= __pa(ioapic_phys
);
3772 set_fixmap_nocache(idx
, ioapic_phys
);
3773 apic_printk(APIC_VERBOSE
, "mapped IOAPIC to %08lx (%08lx)\n",
3774 __fix_to_virt(idx
) + (ioapic_phys
& ~PAGE_MASK
),
3778 ioapic_res
->start
= ioapic_phys
;
3779 ioapic_res
->end
= ioapic_phys
+ IO_APIC_SLOT_SIZE
- 1;
3783 probe_nr_irqs_gsi();
3786 void __init
ioapic_insert_resources(void)
3789 struct resource
*r
= ioapic_resources
;
3794 "IO APIC resources couldn't be allocated.\n");
3798 for (i
= 0; i
< nr_ioapics
; i
++) {
3799 insert_resource(&iomem_resource
, r
);
3804 int mp_find_ioapic(u32 gsi
)
3808 if (nr_ioapics
== 0)
3811 /* Find the IOAPIC that manages this GSI. */
3812 for (i
= 0; i
< nr_ioapics
; i
++) {
3813 struct mp_ioapic_gsi
*gsi_cfg
= mp_ioapic_gsi_routing(i
);
3814 if ((gsi
>= gsi_cfg
->gsi_base
)
3815 && (gsi
<= gsi_cfg
->gsi_end
))
3819 printk(KERN_ERR
"ERROR: Unable to locate IOAPIC for GSI %d\n", gsi
);
3823 int mp_find_ioapic_pin(int ioapic
, u32 gsi
)
3825 struct mp_ioapic_gsi
*gsi_cfg
;
3827 if (WARN_ON(ioapic
== -1))
3830 gsi_cfg
= mp_ioapic_gsi_routing(ioapic
);
3831 if (WARN_ON(gsi
> gsi_cfg
->gsi_end
))
3834 return gsi
- gsi_cfg
->gsi_base
;
3837 static __init
int bad_ioapic(unsigned long address
)
3839 if (nr_ioapics
>= MAX_IO_APICS
) {
3840 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3841 MAX_IO_APICS
, nr_ioapics
);
3845 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3851 static __init
int bad_ioapic_register(int idx
)
3853 union IO_APIC_reg_00 reg_00
;
3854 union IO_APIC_reg_01 reg_01
;
3855 union IO_APIC_reg_02 reg_02
;
3857 reg_00
.raw
= io_apic_read(idx
, 0);
3858 reg_01
.raw
= io_apic_read(idx
, 1);
3859 reg_02
.raw
= io_apic_read(idx
, 2);
3861 if (reg_00
.raw
== -1 && reg_01
.raw
== -1 && reg_02
.raw
== -1) {
3862 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3863 mpc_ioapic_addr(idx
));
3870 void __init
mp_register_ioapic(int id
, u32 address
, u32 gsi_base
)
3874 struct mp_ioapic_gsi
*gsi_cfg
;
3876 if (bad_ioapic(address
))
3881 ioapics
[idx
].mp_config
.type
= MP_IOAPIC
;
3882 ioapics
[idx
].mp_config
.flags
= MPC_APIC_USABLE
;
3883 ioapics
[idx
].mp_config
.apicaddr
= address
;
3885 set_fixmap_nocache(FIX_IO_APIC_BASE_0
+ idx
, address
);
3887 if (bad_ioapic_register(idx
)) {
3888 clear_fixmap(FIX_IO_APIC_BASE_0
+ idx
);
3892 ioapics
[idx
].mp_config
.apicid
= io_apic_unique_id(id
);
3893 ioapics
[idx
].mp_config
.apicver
= io_apic_get_version(idx
);
3896 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3897 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3899 entries
= io_apic_get_redir_entries(idx
);
3900 gsi_cfg
= mp_ioapic_gsi_routing(idx
);
3901 gsi_cfg
->gsi_base
= gsi_base
;
3902 gsi_cfg
->gsi_end
= gsi_base
+ entries
- 1;
3905 * The number of IO-APIC IRQ registers (== #pins):
3907 ioapics
[idx
].nr_registers
= entries
;
3909 if (gsi_cfg
->gsi_end
>= gsi_top
)
3910 gsi_top
= gsi_cfg
->gsi_end
+ 1;
3912 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3913 idx
, mpc_ioapic_id(idx
),
3914 mpc_ioapic_ver(idx
), mpc_ioapic_addr(idx
),
3915 gsi_cfg
->gsi_base
, gsi_cfg
->gsi_end
);
3920 /* Enable IOAPIC early just for system timer */
3921 void __init
pre_init_apic_IRQ0(void)
3923 struct io_apic_irq_attr attr
= { 0, 0, 0, 0 };
3925 printk(KERN_INFO
"Early APIC setup for system timer0\n");
3927 physid_set_mask_of_physid(boot_cpu_physical_apicid
,
3928 &phys_cpu_present_map
);
3932 io_apic_setup_irq_pin(0, 0, &attr
);
3933 irq_set_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
,