Merge tag 'ep93xx-fixes-for-3.8' of git://github.com/RyanMallon/linux-ep93xx into...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / apic / apic_numachip.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Numascale NumaConnect-Specific APIC Code
7 *
8 * Copyright (C) 2011 Numascale AS. All rights reserved.
9 *
10 * Send feedback to <support@numascale.com>
11 *
12 */
13
14 #include <linux/errno.h>
15 #include <linux/threads.h>
16 #include <linux/cpumask.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/ctype.h>
21 #include <linux/init.h>
22 #include <linux/hardirq.h>
23 #include <linux/delay.h>
24
25 #include <asm/numachip/numachip.h>
26 #include <asm/numachip/numachip_csr.h>
27 #include <asm/smp.h>
28 #include <asm/apic.h>
29 #include <asm/ipi.h>
30 #include <asm/apic_flat_64.h>
31
32 static int numachip_system __read_mostly;
33
34 static const struct apic apic_numachip __read_mostly;
35
36 static unsigned int get_apic_id(unsigned long x)
37 {
38 unsigned long value;
39 unsigned int id;
40
41 rdmsrl(MSR_FAM10H_NODE_ID, value);
42 id = ((x >> 24) & 0xffU) | ((value << 2) & 0x3f00U);
43
44 return id;
45 }
46
47 static unsigned long set_apic_id(unsigned int id)
48 {
49 unsigned long x;
50
51 x = ((id & 0xffU) << 24);
52 return x;
53 }
54
55 static unsigned int read_xapic_id(void)
56 {
57 return get_apic_id(apic_read(APIC_ID));
58 }
59
60 static int numachip_apic_id_valid(int apicid)
61 {
62 /* Trust what bootloader passes in MADT */
63 return 1;
64 }
65
66 static int numachip_apic_id_registered(void)
67 {
68 return physid_isset(read_xapic_id(), phys_cpu_present_map);
69 }
70
71 static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
72 {
73 return initial_apic_id >> index_msb;
74 }
75
76 static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
77 {
78 union numachip_csr_g3_ext_irq_gen int_gen;
79
80 int_gen.s._destination_apic_id = phys_apicid;
81 int_gen.s._vector = 0;
82 int_gen.s._msgtype = APIC_DM_INIT >> 8;
83 int_gen.s._index = 0;
84
85 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
86
87 int_gen.s._msgtype = APIC_DM_STARTUP >> 8;
88 int_gen.s._vector = start_rip >> 12;
89
90 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
91
92 atomic_set(&init_deasserted, 1);
93 return 0;
94 }
95
96 static void numachip_send_IPI_one(int cpu, int vector)
97 {
98 union numachip_csr_g3_ext_irq_gen int_gen;
99 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
100
101 int_gen.s._destination_apic_id = apicid;
102 int_gen.s._vector = vector;
103 int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8;
104 int_gen.s._index = 0;
105
106 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
107 }
108
109 static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
110 {
111 unsigned int cpu;
112
113 for_each_cpu(cpu, mask)
114 numachip_send_IPI_one(cpu, vector);
115 }
116
117 static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
118 int vector)
119 {
120 unsigned int this_cpu = smp_processor_id();
121 unsigned int cpu;
122
123 for_each_cpu(cpu, mask) {
124 if (cpu != this_cpu)
125 numachip_send_IPI_one(cpu, vector);
126 }
127 }
128
129 static void numachip_send_IPI_allbutself(int vector)
130 {
131 unsigned int this_cpu = smp_processor_id();
132 unsigned int cpu;
133
134 for_each_online_cpu(cpu) {
135 if (cpu != this_cpu)
136 numachip_send_IPI_one(cpu, vector);
137 }
138 }
139
140 static void numachip_send_IPI_all(int vector)
141 {
142 numachip_send_IPI_mask(cpu_online_mask, vector);
143 }
144
145 static void numachip_send_IPI_self(int vector)
146 {
147 __default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
148 }
149
150 static int __init numachip_probe(void)
151 {
152 return apic == &apic_numachip;
153 }
154
155 static void __init map_csrs(void)
156 {
157 printk(KERN_INFO "NumaChip: Mapping local CSR space (%016llx - %016llx)\n",
158 NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_BASE + NUMACHIP_LCSR_SIZE - 1);
159 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
160
161 printk(KERN_INFO "NumaChip: Mapping global CSR space (%016llx - %016llx)\n",
162 NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_BASE + NUMACHIP_GCSR_SIZE - 1);
163 init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);
164 }
165
166 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
167 {
168
169 if (c->phys_proc_id != node) {
170 c->phys_proc_id = node;
171 per_cpu(cpu_llc_id, smp_processor_id()) = node;
172 }
173 }
174
175 static int __init numachip_system_init(void)
176 {
177 unsigned int val;
178
179 if (!numachip_system)
180 return 0;
181
182 x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
183 x86_init.pci.arch_init = pci_numachip_init;
184
185 map_csrs();
186
187 val = read_lcsr(CSR_G0_NODE_IDS);
188 printk(KERN_INFO "NumaChip: Local NodeID = %08x\n", val);
189
190 return 0;
191 }
192 early_initcall(numachip_system_init);
193
194 static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
195 {
196 if (!strncmp(oem_id, "NUMASC", 6)) {
197 numachip_system = 1;
198 return 1;
199 }
200
201 return 0;
202 }
203
204 static const struct apic apic_numachip __refconst = {
205
206 .name = "NumaConnect system",
207 .probe = numachip_probe,
208 .acpi_madt_oem_check = numachip_acpi_madt_oem_check,
209 .apic_id_valid = numachip_apic_id_valid,
210 .apic_id_registered = numachip_apic_id_registered,
211
212 .irq_delivery_mode = dest_Fixed,
213 .irq_dest_mode = 0, /* physical */
214
215 .target_cpus = online_target_cpus,
216 .disable_esr = 0,
217 .dest_logical = 0,
218 .check_apicid_used = NULL,
219 .check_apicid_present = NULL,
220
221 .vector_allocation_domain = default_vector_allocation_domain,
222 .init_apic_ldr = flat_init_apic_ldr,
223
224 .ioapic_phys_id_map = NULL,
225 .setup_apic_routing = NULL,
226 .multi_timer_check = NULL,
227 .cpu_present_to_apicid = default_cpu_present_to_apicid,
228 .apicid_to_cpu_present = NULL,
229 .setup_portio_remap = NULL,
230 .check_phys_apicid_present = default_check_phys_apicid_present,
231 .enable_apic_mode = NULL,
232 .phys_pkg_id = numachip_phys_pkg_id,
233 .mps_oem_check = NULL,
234
235 .get_apic_id = get_apic_id,
236 .set_apic_id = set_apic_id,
237 .apic_id_mask = 0xffU << 24,
238
239 .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and,
240
241 .send_IPI_mask = numachip_send_IPI_mask,
242 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
243 .send_IPI_allbutself = numachip_send_IPI_allbutself,
244 .send_IPI_all = numachip_send_IPI_all,
245 .send_IPI_self = numachip_send_IPI_self,
246
247 .wakeup_secondary_cpu = numachip_wakeup_secondary,
248 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
249 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
250 .wait_for_init_deassert = NULL,
251 .smp_callin_clear_local_apic = NULL,
252 .inquire_remote_apic = NULL, /* REMRD not supported */
253
254 .read = native_apic_mem_read,
255 .write = native_apic_mem_write,
256 .eoi_write = native_apic_mem_write,
257 .icr_read = native_apic_icr_read,
258 .icr_write = native_apic_icr_write,
259 .wait_icr_idle = native_apic_wait_icr_idle,
260 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
261 };
262 apic_driver(apic_numachip);
263