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x86/amd-iommu: Fix IOMMU-API initialization for iommu=pt
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / x86 / kernel / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitmap.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
30 #include <asm/gart.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
34
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36
37 #define EXIT_LOOP_COUNT 10000000
38
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44
45 /*
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
48 */
49 static struct protection_domain *pt_domain;
50
51 static struct iommu_ops amd_iommu_ops;
52
53 /*
54 * general struct to manage commands send to an IOMMU
55 */
56 struct iommu_cmd {
57 u32 data[4];
58 };
59
60 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
61 static void update_domain(struct protection_domain *domain);
62
63 /****************************************************************************
64 *
65 * Helper functions
66 *
67 ****************************************************************************/
68
69 static inline u16 get_device_id(struct device *dev)
70 {
71 struct pci_dev *pdev = to_pci_dev(dev);
72
73 return calc_devid(pdev->bus->number, pdev->devfn);
74 }
75
76 static struct iommu_dev_data *get_dev_data(struct device *dev)
77 {
78 return dev->archdata.iommu;
79 }
80
81 /*
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
84 */
85 static struct dma_ops_domain *find_protection_domain(u16 devid)
86 {
87 struct dma_ops_domain *entry, *ret = NULL;
88 unsigned long flags;
89 u16 alias = amd_iommu_alias_table[devid];
90
91 if (list_empty(&iommu_pd_list))
92 return NULL;
93
94 spin_lock_irqsave(&iommu_pd_list_lock, flags);
95
96 list_for_each_entry(entry, &iommu_pd_list, list) {
97 if (entry->target_dev == devid ||
98 entry->target_dev == alias) {
99 ret = entry;
100 break;
101 }
102 }
103
104 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
105
106 return ret;
107 }
108
109 /*
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
112 */
113 static bool check_device(struct device *dev)
114 {
115 u16 devid;
116
117 if (!dev || !dev->dma_mask)
118 return false;
119
120 /* No device or no PCI device */
121 if (!dev || dev->bus != &pci_bus_type)
122 return false;
123
124 devid = get_device_id(dev);
125
126 /* Out of our scope? */
127 if (devid > amd_iommu_last_bdf)
128 return false;
129
130 if (amd_iommu_rlookup_table[devid] == NULL)
131 return false;
132
133 return true;
134 }
135
136 static int iommu_init_device(struct device *dev)
137 {
138 struct iommu_dev_data *dev_data;
139 struct pci_dev *pdev;
140 u16 devid, alias;
141
142 if (dev->archdata.iommu)
143 return 0;
144
145 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
146 if (!dev_data)
147 return -ENOMEM;
148
149 dev_data->dev = dev;
150
151 devid = get_device_id(dev);
152 alias = amd_iommu_alias_table[devid];
153 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
154 if (pdev)
155 dev_data->alias = &pdev->dev;
156
157 atomic_set(&dev_data->bind, 0);
158
159 dev->archdata.iommu = dev_data;
160
161
162 return 0;
163 }
164
165 static void iommu_uninit_device(struct device *dev)
166 {
167 kfree(dev->archdata.iommu);
168 }
169
170 void __init amd_iommu_uninit_devices(void)
171 {
172 struct pci_dev *pdev = NULL;
173
174 for_each_pci_dev(pdev) {
175
176 if (!check_device(&pdev->dev))
177 continue;
178
179 iommu_uninit_device(&pdev->dev);
180 }
181 }
182
183 int __init amd_iommu_init_devices(void)
184 {
185 struct pci_dev *pdev = NULL;
186 int ret = 0;
187
188 for_each_pci_dev(pdev) {
189
190 if (!check_device(&pdev->dev))
191 continue;
192
193 ret = iommu_init_device(&pdev->dev);
194 if (ret)
195 goto out_free;
196 }
197
198 return 0;
199
200 out_free:
201
202 amd_iommu_uninit_devices();
203
204 return ret;
205 }
206 #ifdef CONFIG_AMD_IOMMU_STATS
207
208 /*
209 * Initialization code for statistics collection
210 */
211
212 DECLARE_STATS_COUNTER(compl_wait);
213 DECLARE_STATS_COUNTER(cnt_map_single);
214 DECLARE_STATS_COUNTER(cnt_unmap_single);
215 DECLARE_STATS_COUNTER(cnt_map_sg);
216 DECLARE_STATS_COUNTER(cnt_unmap_sg);
217 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
218 DECLARE_STATS_COUNTER(cnt_free_coherent);
219 DECLARE_STATS_COUNTER(cross_page);
220 DECLARE_STATS_COUNTER(domain_flush_single);
221 DECLARE_STATS_COUNTER(domain_flush_all);
222 DECLARE_STATS_COUNTER(alloced_io_mem);
223 DECLARE_STATS_COUNTER(total_map_requests);
224
225 static struct dentry *stats_dir;
226 static struct dentry *de_fflush;
227
228 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
229 {
230 if (stats_dir == NULL)
231 return;
232
233 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
234 &cnt->value);
235 }
236
237 static void amd_iommu_stats_init(void)
238 {
239 stats_dir = debugfs_create_dir("amd-iommu", NULL);
240 if (stats_dir == NULL)
241 return;
242
243 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
244 (u32 *)&amd_iommu_unmap_flush);
245
246 amd_iommu_stats_add(&compl_wait);
247 amd_iommu_stats_add(&cnt_map_single);
248 amd_iommu_stats_add(&cnt_unmap_single);
249 amd_iommu_stats_add(&cnt_map_sg);
250 amd_iommu_stats_add(&cnt_unmap_sg);
251 amd_iommu_stats_add(&cnt_alloc_coherent);
252 amd_iommu_stats_add(&cnt_free_coherent);
253 amd_iommu_stats_add(&cross_page);
254 amd_iommu_stats_add(&domain_flush_single);
255 amd_iommu_stats_add(&domain_flush_all);
256 amd_iommu_stats_add(&alloced_io_mem);
257 amd_iommu_stats_add(&total_map_requests);
258 }
259
260 #endif
261
262 /****************************************************************************
263 *
264 * Interrupt handling functions
265 *
266 ****************************************************************************/
267
268 static void dump_dte_entry(u16 devid)
269 {
270 int i;
271
272 for (i = 0; i < 8; ++i)
273 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
274 amd_iommu_dev_table[devid].data[i]);
275 }
276
277 static void dump_command(unsigned long phys_addr)
278 {
279 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
280 int i;
281
282 for (i = 0; i < 4; ++i)
283 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
284 }
285
286 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
287 {
288 u32 *event = __evt;
289 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
290 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
291 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
292 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
293 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
294
295 printk(KERN_ERR "AMD-Vi: Event logged [");
296
297 switch (type) {
298 case EVENT_TYPE_ILL_DEV:
299 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
300 "address=0x%016llx flags=0x%04x]\n",
301 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
302 address, flags);
303 dump_dte_entry(devid);
304 break;
305 case EVENT_TYPE_IO_FAULT:
306 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
307 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
308 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
309 domid, address, flags);
310 break;
311 case EVENT_TYPE_DEV_TAB_ERR:
312 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
313 "address=0x%016llx flags=0x%04x]\n",
314 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
315 address, flags);
316 break;
317 case EVENT_TYPE_PAGE_TAB_ERR:
318 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
319 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
320 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
321 domid, address, flags);
322 break;
323 case EVENT_TYPE_ILL_CMD:
324 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
325 iommu->reset_in_progress = true;
326 reset_iommu_command_buffer(iommu);
327 dump_command(address);
328 break;
329 case EVENT_TYPE_CMD_HARD_ERR:
330 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
331 "flags=0x%04x]\n", address, flags);
332 break;
333 case EVENT_TYPE_IOTLB_INV_TO:
334 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
335 "address=0x%016llx]\n",
336 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
337 address);
338 break;
339 case EVENT_TYPE_INV_DEV_REQ:
340 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
341 "address=0x%016llx flags=0x%04x]\n",
342 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
343 address, flags);
344 break;
345 default:
346 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
347 }
348 }
349
350 static void iommu_poll_events(struct amd_iommu *iommu)
351 {
352 u32 head, tail;
353 unsigned long flags;
354
355 spin_lock_irqsave(&iommu->lock, flags);
356
357 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
358 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
359
360 while (head != tail) {
361 iommu_print_event(iommu, iommu->evt_buf + head);
362 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
363 }
364
365 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
366
367 spin_unlock_irqrestore(&iommu->lock, flags);
368 }
369
370 irqreturn_t amd_iommu_int_handler(int irq, void *data)
371 {
372 struct amd_iommu *iommu;
373
374 for_each_iommu(iommu)
375 iommu_poll_events(iommu);
376
377 return IRQ_HANDLED;
378 }
379
380 /****************************************************************************
381 *
382 * IOMMU command queuing functions
383 *
384 ****************************************************************************/
385
386 /*
387 * Writes the command to the IOMMUs command buffer and informs the
388 * hardware about the new command. Must be called with iommu->lock held.
389 */
390 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
391 {
392 u32 tail, head;
393 u8 *target;
394
395 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
396 target = iommu->cmd_buf + tail;
397 memcpy_toio(target, cmd, sizeof(*cmd));
398 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
399 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
400 if (tail == head)
401 return -ENOMEM;
402 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
403
404 return 0;
405 }
406
407 /*
408 * General queuing function for commands. Takes iommu->lock and calls
409 * __iommu_queue_command().
410 */
411 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
412 {
413 unsigned long flags;
414 int ret;
415
416 spin_lock_irqsave(&iommu->lock, flags);
417 ret = __iommu_queue_command(iommu, cmd);
418 if (!ret)
419 iommu->need_sync = true;
420 spin_unlock_irqrestore(&iommu->lock, flags);
421
422 return ret;
423 }
424
425 /*
426 * This function waits until an IOMMU has completed a completion
427 * wait command
428 */
429 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
430 {
431 int ready = 0;
432 unsigned status = 0;
433 unsigned long i = 0;
434
435 INC_STATS_COUNTER(compl_wait);
436
437 while (!ready && (i < EXIT_LOOP_COUNT)) {
438 ++i;
439 /* wait for the bit to become one */
440 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
441 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
442 }
443
444 /* set bit back to zero */
445 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
446 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
447
448 if (unlikely(i == EXIT_LOOP_COUNT))
449 iommu->reset_in_progress = true;
450 }
451
452 /*
453 * This function queues a completion wait command into the command
454 * buffer of an IOMMU
455 */
456 static int __iommu_completion_wait(struct amd_iommu *iommu)
457 {
458 struct iommu_cmd cmd;
459
460 memset(&cmd, 0, sizeof(cmd));
461 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
462 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
463
464 return __iommu_queue_command(iommu, &cmd);
465 }
466
467 /*
468 * This function is called whenever we need to ensure that the IOMMU has
469 * completed execution of all commands we sent. It sends a
470 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
471 * us about that by writing a value to a physical address we pass with
472 * the command.
473 */
474 static int iommu_completion_wait(struct amd_iommu *iommu)
475 {
476 int ret = 0;
477 unsigned long flags;
478
479 spin_lock_irqsave(&iommu->lock, flags);
480
481 if (!iommu->need_sync)
482 goto out;
483
484 ret = __iommu_completion_wait(iommu);
485
486 iommu->need_sync = false;
487
488 if (ret)
489 goto out;
490
491 __iommu_wait_for_completion(iommu);
492
493 out:
494 spin_unlock_irqrestore(&iommu->lock, flags);
495
496 if (iommu->reset_in_progress)
497 reset_iommu_command_buffer(iommu);
498
499 return 0;
500 }
501
502 static void iommu_flush_complete(struct protection_domain *domain)
503 {
504 int i;
505
506 for (i = 0; i < amd_iommus_present; ++i) {
507 if (!domain->dev_iommu[i])
508 continue;
509
510 /*
511 * Devices of this domain are behind this IOMMU
512 * We need to wait for completion of all commands.
513 */
514 iommu_completion_wait(amd_iommus[i]);
515 }
516 }
517
518 /*
519 * Command send function for invalidating a device table entry
520 */
521 static int iommu_flush_device(struct device *dev)
522 {
523 struct amd_iommu *iommu;
524 struct iommu_cmd cmd;
525 u16 devid;
526
527 devid = get_device_id(dev);
528 iommu = amd_iommu_rlookup_table[devid];
529
530 /* Build command */
531 memset(&cmd, 0, sizeof(cmd));
532 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
533 cmd.data[0] = devid;
534
535 return iommu_queue_command(iommu, &cmd);
536 }
537
538 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
539 u16 domid, int pde, int s)
540 {
541 memset(cmd, 0, sizeof(*cmd));
542 address &= PAGE_MASK;
543 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
544 cmd->data[1] |= domid;
545 cmd->data[2] = lower_32_bits(address);
546 cmd->data[3] = upper_32_bits(address);
547 if (s) /* size bit - we flush more than one 4kb page */
548 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
549 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
550 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
551 }
552
553 /*
554 * Generic command send function for invalidaing TLB entries
555 */
556 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
557 u64 address, u16 domid, int pde, int s)
558 {
559 struct iommu_cmd cmd;
560 int ret;
561
562 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
563
564 ret = iommu_queue_command(iommu, &cmd);
565
566 return ret;
567 }
568
569 /*
570 * TLB invalidation function which is called from the mapping functions.
571 * It invalidates a single PTE if the range to flush is within a single
572 * page. Otherwise it flushes the whole TLB of the IOMMU.
573 */
574 static void __iommu_flush_pages(struct protection_domain *domain,
575 u64 address, size_t size, int pde)
576 {
577 int s = 0, i;
578 unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE);
579
580 address &= PAGE_MASK;
581
582 if (pages > 1) {
583 /*
584 * If we have to flush more than one page, flush all
585 * TLB entries for this domain
586 */
587 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
588 s = 1;
589 }
590
591
592 for (i = 0; i < amd_iommus_present; ++i) {
593 if (!domain->dev_iommu[i])
594 continue;
595
596 /*
597 * Devices of this domain are behind this IOMMU
598 * We need a TLB flush
599 */
600 iommu_queue_inv_iommu_pages(amd_iommus[i], address,
601 domain->id, pde, s);
602 }
603
604 return;
605 }
606
607 static void iommu_flush_pages(struct protection_domain *domain,
608 u64 address, size_t size)
609 {
610 __iommu_flush_pages(domain, address, size, 0);
611 }
612
613 /* Flush the whole IO/TLB for a given protection domain */
614 static void iommu_flush_tlb(struct protection_domain *domain)
615 {
616 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
617 }
618
619 /* Flush the whole IO/TLB for a given protection domain - including PDE */
620 static void iommu_flush_tlb_pde(struct protection_domain *domain)
621 {
622 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
623 }
624
625
626 /*
627 * This function flushes the DTEs for all devices in domain
628 */
629 static void iommu_flush_domain_devices(struct protection_domain *domain)
630 {
631 struct iommu_dev_data *dev_data;
632 unsigned long flags;
633
634 spin_lock_irqsave(&domain->lock, flags);
635
636 list_for_each_entry(dev_data, &domain->dev_list, list)
637 iommu_flush_device(dev_data->dev);
638
639 spin_unlock_irqrestore(&domain->lock, flags);
640 }
641
642 static void iommu_flush_all_domain_devices(void)
643 {
644 struct protection_domain *domain;
645 unsigned long flags;
646
647 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
648
649 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
650 iommu_flush_domain_devices(domain);
651 iommu_flush_complete(domain);
652 }
653
654 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
655 }
656
657 void amd_iommu_flush_all_devices(void)
658 {
659 iommu_flush_all_domain_devices();
660 }
661
662 /*
663 * This function uses heavy locking and may disable irqs for some time. But
664 * this is no issue because it is only called during resume.
665 */
666 void amd_iommu_flush_all_domains(void)
667 {
668 struct protection_domain *domain;
669 unsigned long flags;
670
671 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
672
673 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
674 spin_lock(&domain->lock);
675 iommu_flush_tlb_pde(domain);
676 iommu_flush_complete(domain);
677 spin_unlock(&domain->lock);
678 }
679
680 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
681 }
682
683 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
684 {
685 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
686
687 if (iommu->reset_in_progress)
688 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
689
690 amd_iommu_reset_cmd_buffer(iommu);
691 amd_iommu_flush_all_devices();
692 amd_iommu_flush_all_domains();
693
694 iommu->reset_in_progress = false;
695 }
696
697 /****************************************************************************
698 *
699 * The functions below are used the create the page table mappings for
700 * unity mapped regions.
701 *
702 ****************************************************************************/
703
704 /*
705 * This function is used to add another level to an IO page table. Adding
706 * another level increases the size of the address space by 9 bits to a size up
707 * to 64 bits.
708 */
709 static bool increase_address_space(struct protection_domain *domain,
710 gfp_t gfp)
711 {
712 u64 *pte;
713
714 if (domain->mode == PAGE_MODE_6_LEVEL)
715 /* address space already 64 bit large */
716 return false;
717
718 pte = (void *)get_zeroed_page(gfp);
719 if (!pte)
720 return false;
721
722 *pte = PM_LEVEL_PDE(domain->mode,
723 virt_to_phys(domain->pt_root));
724 domain->pt_root = pte;
725 domain->mode += 1;
726 domain->updated = true;
727
728 return true;
729 }
730
731 static u64 *alloc_pte(struct protection_domain *domain,
732 unsigned long address,
733 int end_lvl,
734 u64 **pte_page,
735 gfp_t gfp)
736 {
737 u64 *pte, *page;
738 int level;
739
740 while (address > PM_LEVEL_SIZE(domain->mode))
741 increase_address_space(domain, gfp);
742
743 level = domain->mode - 1;
744 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
745
746 while (level > end_lvl) {
747 if (!IOMMU_PTE_PRESENT(*pte)) {
748 page = (u64 *)get_zeroed_page(gfp);
749 if (!page)
750 return NULL;
751 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
752 }
753
754 level -= 1;
755
756 pte = IOMMU_PTE_PAGE(*pte);
757
758 if (pte_page && level == end_lvl)
759 *pte_page = pte;
760
761 pte = &pte[PM_LEVEL_INDEX(level, address)];
762 }
763
764 return pte;
765 }
766
767 /*
768 * This function checks if there is a PTE for a given dma address. If
769 * there is one, it returns the pointer to it.
770 */
771 static u64 *fetch_pte(struct protection_domain *domain,
772 unsigned long address, int map_size)
773 {
774 int level;
775 u64 *pte;
776
777 level = domain->mode - 1;
778 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
779
780 while (level > map_size) {
781 if (!IOMMU_PTE_PRESENT(*pte))
782 return NULL;
783
784 level -= 1;
785
786 pte = IOMMU_PTE_PAGE(*pte);
787 pte = &pte[PM_LEVEL_INDEX(level, address)];
788
789 if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
790 pte = NULL;
791 break;
792 }
793 }
794
795 return pte;
796 }
797
798 /*
799 * Generic mapping functions. It maps a physical address into a DMA
800 * address space. It allocates the page table pages if necessary.
801 * In the future it can be extended to a generic mapping function
802 * supporting all features of AMD IOMMU page tables like level skipping
803 * and full 64 bit address spaces.
804 */
805 static int iommu_map_page(struct protection_domain *dom,
806 unsigned long bus_addr,
807 unsigned long phys_addr,
808 int prot,
809 int map_size)
810 {
811 u64 __pte, *pte;
812
813 bus_addr = PAGE_ALIGN(bus_addr);
814 phys_addr = PAGE_ALIGN(phys_addr);
815
816 BUG_ON(!PM_ALIGNED(map_size, bus_addr));
817 BUG_ON(!PM_ALIGNED(map_size, phys_addr));
818
819 if (!(prot & IOMMU_PROT_MASK))
820 return -EINVAL;
821
822 pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
823
824 if (IOMMU_PTE_PRESENT(*pte))
825 return -EBUSY;
826
827 __pte = phys_addr | IOMMU_PTE_P;
828 if (prot & IOMMU_PROT_IR)
829 __pte |= IOMMU_PTE_IR;
830 if (prot & IOMMU_PROT_IW)
831 __pte |= IOMMU_PTE_IW;
832
833 *pte = __pte;
834
835 update_domain(dom);
836
837 return 0;
838 }
839
840 static void iommu_unmap_page(struct protection_domain *dom,
841 unsigned long bus_addr, int map_size)
842 {
843 u64 *pte = fetch_pte(dom, bus_addr, map_size);
844
845 if (pte)
846 *pte = 0;
847 }
848
849 /*
850 * This function checks if a specific unity mapping entry is needed for
851 * this specific IOMMU.
852 */
853 static int iommu_for_unity_map(struct amd_iommu *iommu,
854 struct unity_map_entry *entry)
855 {
856 u16 bdf, i;
857
858 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
859 bdf = amd_iommu_alias_table[i];
860 if (amd_iommu_rlookup_table[bdf] == iommu)
861 return 1;
862 }
863
864 return 0;
865 }
866
867 /*
868 * This function actually applies the mapping to the page table of the
869 * dma_ops domain.
870 */
871 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
872 struct unity_map_entry *e)
873 {
874 u64 addr;
875 int ret;
876
877 for (addr = e->address_start; addr < e->address_end;
878 addr += PAGE_SIZE) {
879 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
880 PM_MAP_4k);
881 if (ret)
882 return ret;
883 /*
884 * if unity mapping is in aperture range mark the page
885 * as allocated in the aperture
886 */
887 if (addr < dma_dom->aperture_size)
888 __set_bit(addr >> PAGE_SHIFT,
889 dma_dom->aperture[0]->bitmap);
890 }
891
892 return 0;
893 }
894
895 /*
896 * Init the unity mappings for a specific IOMMU in the system
897 *
898 * Basically iterates over all unity mapping entries and applies them to
899 * the default domain DMA of that IOMMU if necessary.
900 */
901 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
902 {
903 struct unity_map_entry *entry;
904 int ret;
905
906 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
907 if (!iommu_for_unity_map(iommu, entry))
908 continue;
909 ret = dma_ops_unity_map(iommu->default_dom, entry);
910 if (ret)
911 return ret;
912 }
913
914 return 0;
915 }
916
917 /*
918 * Inits the unity mappings required for a specific device
919 */
920 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
921 u16 devid)
922 {
923 struct unity_map_entry *e;
924 int ret;
925
926 list_for_each_entry(e, &amd_iommu_unity_map, list) {
927 if (!(devid >= e->devid_start && devid <= e->devid_end))
928 continue;
929 ret = dma_ops_unity_map(dma_dom, e);
930 if (ret)
931 return ret;
932 }
933
934 return 0;
935 }
936
937 /****************************************************************************
938 *
939 * The next functions belong to the address allocator for the dma_ops
940 * interface functions. They work like the allocators in the other IOMMU
941 * drivers. Its basically a bitmap which marks the allocated pages in
942 * the aperture. Maybe it could be enhanced in the future to a more
943 * efficient allocator.
944 *
945 ****************************************************************************/
946
947 /*
948 * The address allocator core functions.
949 *
950 * called with domain->lock held
951 */
952
953 /*
954 * Used to reserve address ranges in the aperture (e.g. for exclusion
955 * ranges.
956 */
957 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
958 unsigned long start_page,
959 unsigned int pages)
960 {
961 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
962
963 if (start_page + pages > last_page)
964 pages = last_page - start_page;
965
966 for (i = start_page; i < start_page + pages; ++i) {
967 int index = i / APERTURE_RANGE_PAGES;
968 int page = i % APERTURE_RANGE_PAGES;
969 __set_bit(page, dom->aperture[index]->bitmap);
970 }
971 }
972
973 /*
974 * This function is used to add a new aperture range to an existing
975 * aperture in case of dma_ops domain allocation or address allocation
976 * failure.
977 */
978 static int alloc_new_range(struct dma_ops_domain *dma_dom,
979 bool populate, gfp_t gfp)
980 {
981 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
982 struct amd_iommu *iommu;
983 unsigned long i;
984
985 #ifdef CONFIG_IOMMU_STRESS
986 populate = false;
987 #endif
988
989 if (index >= APERTURE_MAX_RANGES)
990 return -ENOMEM;
991
992 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
993 if (!dma_dom->aperture[index])
994 return -ENOMEM;
995
996 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
997 if (!dma_dom->aperture[index]->bitmap)
998 goto out_free;
999
1000 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1001
1002 if (populate) {
1003 unsigned long address = dma_dom->aperture_size;
1004 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1005 u64 *pte, *pte_page;
1006
1007 for (i = 0; i < num_ptes; ++i) {
1008 pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
1009 &pte_page, gfp);
1010 if (!pte)
1011 goto out_free;
1012
1013 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1014
1015 address += APERTURE_RANGE_SIZE / 64;
1016 }
1017 }
1018
1019 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1020
1021 /* Intialize the exclusion range if necessary */
1022 for_each_iommu(iommu) {
1023 if (iommu->exclusion_start &&
1024 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1025 && iommu->exclusion_start < dma_dom->aperture_size) {
1026 unsigned long startpage;
1027 int pages = iommu_num_pages(iommu->exclusion_start,
1028 iommu->exclusion_length,
1029 PAGE_SIZE);
1030 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1031 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1032 }
1033 }
1034
1035 /*
1036 * Check for areas already mapped as present in the new aperture
1037 * range and mark those pages as reserved in the allocator. Such
1038 * mappings may already exist as a result of requested unity
1039 * mappings for devices.
1040 */
1041 for (i = dma_dom->aperture[index]->offset;
1042 i < dma_dom->aperture_size;
1043 i += PAGE_SIZE) {
1044 u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
1045 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1046 continue;
1047
1048 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1049 }
1050
1051 update_domain(&dma_dom->domain);
1052
1053 return 0;
1054
1055 out_free:
1056 update_domain(&dma_dom->domain);
1057
1058 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1059
1060 kfree(dma_dom->aperture[index]);
1061 dma_dom->aperture[index] = NULL;
1062
1063 return -ENOMEM;
1064 }
1065
1066 static unsigned long dma_ops_area_alloc(struct device *dev,
1067 struct dma_ops_domain *dom,
1068 unsigned int pages,
1069 unsigned long align_mask,
1070 u64 dma_mask,
1071 unsigned long start)
1072 {
1073 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1074 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1075 int i = start >> APERTURE_RANGE_SHIFT;
1076 unsigned long boundary_size;
1077 unsigned long address = -1;
1078 unsigned long limit;
1079
1080 next_bit >>= PAGE_SHIFT;
1081
1082 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1083 PAGE_SIZE) >> PAGE_SHIFT;
1084
1085 for (;i < max_index; ++i) {
1086 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1087
1088 if (dom->aperture[i]->offset >= dma_mask)
1089 break;
1090
1091 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1092 dma_mask >> PAGE_SHIFT);
1093
1094 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1095 limit, next_bit, pages, 0,
1096 boundary_size, align_mask);
1097 if (address != -1) {
1098 address = dom->aperture[i]->offset +
1099 (address << PAGE_SHIFT);
1100 dom->next_address = address + (pages << PAGE_SHIFT);
1101 break;
1102 }
1103
1104 next_bit = 0;
1105 }
1106
1107 return address;
1108 }
1109
1110 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1111 struct dma_ops_domain *dom,
1112 unsigned int pages,
1113 unsigned long align_mask,
1114 u64 dma_mask)
1115 {
1116 unsigned long address;
1117
1118 #ifdef CONFIG_IOMMU_STRESS
1119 dom->next_address = 0;
1120 dom->need_flush = true;
1121 #endif
1122
1123 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1124 dma_mask, dom->next_address);
1125
1126 if (address == -1) {
1127 dom->next_address = 0;
1128 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1129 dma_mask, 0);
1130 dom->need_flush = true;
1131 }
1132
1133 if (unlikely(address == -1))
1134 address = DMA_ERROR_CODE;
1135
1136 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1137
1138 return address;
1139 }
1140
1141 /*
1142 * The address free function.
1143 *
1144 * called with domain->lock held
1145 */
1146 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1147 unsigned long address,
1148 unsigned int pages)
1149 {
1150 unsigned i = address >> APERTURE_RANGE_SHIFT;
1151 struct aperture_range *range = dom->aperture[i];
1152
1153 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1154
1155 #ifdef CONFIG_IOMMU_STRESS
1156 if (i < 4)
1157 return;
1158 #endif
1159
1160 if (address >= dom->next_address)
1161 dom->need_flush = true;
1162
1163 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1164
1165 bitmap_clear(range->bitmap, address, pages);
1166
1167 }
1168
1169 /****************************************************************************
1170 *
1171 * The next functions belong to the domain allocation. A domain is
1172 * allocated for every IOMMU as the default domain. If device isolation
1173 * is enabled, every device get its own domain. The most important thing
1174 * about domains is the page table mapping the DMA address space they
1175 * contain.
1176 *
1177 ****************************************************************************/
1178
1179 /*
1180 * This function adds a protection domain to the global protection domain list
1181 */
1182 static void add_domain_to_list(struct protection_domain *domain)
1183 {
1184 unsigned long flags;
1185
1186 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1187 list_add(&domain->list, &amd_iommu_pd_list);
1188 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1189 }
1190
1191 /*
1192 * This function removes a protection domain to the global
1193 * protection domain list
1194 */
1195 static void del_domain_from_list(struct protection_domain *domain)
1196 {
1197 unsigned long flags;
1198
1199 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1200 list_del(&domain->list);
1201 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1202 }
1203
1204 static u16 domain_id_alloc(void)
1205 {
1206 unsigned long flags;
1207 int id;
1208
1209 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1210 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1211 BUG_ON(id == 0);
1212 if (id > 0 && id < MAX_DOMAIN_ID)
1213 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1214 else
1215 id = 0;
1216 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1217
1218 return id;
1219 }
1220
1221 static void domain_id_free(int id)
1222 {
1223 unsigned long flags;
1224
1225 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1226 if (id > 0 && id < MAX_DOMAIN_ID)
1227 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1228 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1229 }
1230
1231 static void free_pagetable(struct protection_domain *domain)
1232 {
1233 int i, j;
1234 u64 *p1, *p2, *p3;
1235
1236 p1 = domain->pt_root;
1237
1238 if (!p1)
1239 return;
1240
1241 for (i = 0; i < 512; ++i) {
1242 if (!IOMMU_PTE_PRESENT(p1[i]))
1243 continue;
1244
1245 p2 = IOMMU_PTE_PAGE(p1[i]);
1246 for (j = 0; j < 512; ++j) {
1247 if (!IOMMU_PTE_PRESENT(p2[j]))
1248 continue;
1249 p3 = IOMMU_PTE_PAGE(p2[j]);
1250 free_page((unsigned long)p3);
1251 }
1252
1253 free_page((unsigned long)p2);
1254 }
1255
1256 free_page((unsigned long)p1);
1257
1258 domain->pt_root = NULL;
1259 }
1260
1261 /*
1262 * Free a domain, only used if something went wrong in the
1263 * allocation path and we need to free an already allocated page table
1264 */
1265 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1266 {
1267 int i;
1268
1269 if (!dom)
1270 return;
1271
1272 del_domain_from_list(&dom->domain);
1273
1274 free_pagetable(&dom->domain);
1275
1276 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1277 if (!dom->aperture[i])
1278 continue;
1279 free_page((unsigned long)dom->aperture[i]->bitmap);
1280 kfree(dom->aperture[i]);
1281 }
1282
1283 kfree(dom);
1284 }
1285
1286 /*
1287 * Allocates a new protection domain usable for the dma_ops functions.
1288 * It also intializes the page table and the address allocator data
1289 * structures required for the dma_ops interface
1290 */
1291 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1292 {
1293 struct dma_ops_domain *dma_dom;
1294
1295 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1296 if (!dma_dom)
1297 return NULL;
1298
1299 spin_lock_init(&dma_dom->domain.lock);
1300
1301 dma_dom->domain.id = domain_id_alloc();
1302 if (dma_dom->domain.id == 0)
1303 goto free_dma_dom;
1304 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1305 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1306 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1307 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1308 dma_dom->domain.priv = dma_dom;
1309 if (!dma_dom->domain.pt_root)
1310 goto free_dma_dom;
1311
1312 dma_dom->need_flush = false;
1313 dma_dom->target_dev = 0xffff;
1314
1315 add_domain_to_list(&dma_dom->domain);
1316
1317 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1318 goto free_dma_dom;
1319
1320 /*
1321 * mark the first page as allocated so we never return 0 as
1322 * a valid dma-address. So we can use 0 as error value
1323 */
1324 dma_dom->aperture[0]->bitmap[0] = 1;
1325 dma_dom->next_address = 0;
1326
1327
1328 return dma_dom;
1329
1330 free_dma_dom:
1331 dma_ops_domain_free(dma_dom);
1332
1333 return NULL;
1334 }
1335
1336 /*
1337 * little helper function to check whether a given protection domain is a
1338 * dma_ops domain
1339 */
1340 static bool dma_ops_domain(struct protection_domain *domain)
1341 {
1342 return domain->flags & PD_DMA_OPS_MASK;
1343 }
1344
1345 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1346 {
1347 u64 pte_root = virt_to_phys(domain->pt_root);
1348
1349 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1350 << DEV_ENTRY_MODE_SHIFT;
1351 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1352
1353 amd_iommu_dev_table[devid].data[2] = domain->id;
1354 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1355 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1356 }
1357
1358 static void clear_dte_entry(u16 devid)
1359 {
1360 /* remove entry from the device table seen by the hardware */
1361 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1362 amd_iommu_dev_table[devid].data[1] = 0;
1363 amd_iommu_dev_table[devid].data[2] = 0;
1364
1365 amd_iommu_apply_erratum_63(devid);
1366 }
1367
1368 static void do_attach(struct device *dev, struct protection_domain *domain)
1369 {
1370 struct iommu_dev_data *dev_data;
1371 struct amd_iommu *iommu;
1372 u16 devid;
1373
1374 devid = get_device_id(dev);
1375 iommu = amd_iommu_rlookup_table[devid];
1376 dev_data = get_dev_data(dev);
1377
1378 /* Update data structures */
1379 dev_data->domain = domain;
1380 list_add(&dev_data->list, &domain->dev_list);
1381 set_dte_entry(devid, domain);
1382
1383 /* Do reference counting */
1384 domain->dev_iommu[iommu->index] += 1;
1385 domain->dev_cnt += 1;
1386
1387 /* Flush the DTE entry */
1388 iommu_flush_device(dev);
1389 }
1390
1391 static void do_detach(struct device *dev)
1392 {
1393 struct iommu_dev_data *dev_data;
1394 struct amd_iommu *iommu;
1395 u16 devid;
1396
1397 devid = get_device_id(dev);
1398 iommu = amd_iommu_rlookup_table[devid];
1399 dev_data = get_dev_data(dev);
1400
1401 /* decrease reference counters */
1402 dev_data->domain->dev_iommu[iommu->index] -= 1;
1403 dev_data->domain->dev_cnt -= 1;
1404
1405 /* Update data structures */
1406 dev_data->domain = NULL;
1407 list_del(&dev_data->list);
1408 clear_dte_entry(devid);
1409
1410 /* Flush the DTE entry */
1411 iommu_flush_device(dev);
1412 }
1413
1414 /*
1415 * If a device is not yet associated with a domain, this function does
1416 * assigns it visible for the hardware
1417 */
1418 static int __attach_device(struct device *dev,
1419 struct protection_domain *domain)
1420 {
1421 struct iommu_dev_data *dev_data, *alias_data;
1422
1423 dev_data = get_dev_data(dev);
1424 alias_data = get_dev_data(dev_data->alias);
1425
1426 if (!alias_data)
1427 return -EINVAL;
1428
1429 /* lock domain */
1430 spin_lock(&domain->lock);
1431
1432 /* Some sanity checks */
1433 if (alias_data->domain != NULL &&
1434 alias_data->domain != domain)
1435 return -EBUSY;
1436
1437 if (dev_data->domain != NULL &&
1438 dev_data->domain != domain)
1439 return -EBUSY;
1440
1441 /* Do real assignment */
1442 if (dev_data->alias != dev) {
1443 alias_data = get_dev_data(dev_data->alias);
1444 if (alias_data->domain == NULL)
1445 do_attach(dev_data->alias, domain);
1446
1447 atomic_inc(&alias_data->bind);
1448 }
1449
1450 if (dev_data->domain == NULL)
1451 do_attach(dev, domain);
1452
1453 atomic_inc(&dev_data->bind);
1454
1455 /* ready */
1456 spin_unlock(&domain->lock);
1457
1458 return 0;
1459 }
1460
1461 /*
1462 * If a device is not yet associated with a domain, this function does
1463 * assigns it visible for the hardware
1464 */
1465 static int attach_device(struct device *dev,
1466 struct protection_domain *domain)
1467 {
1468 unsigned long flags;
1469 int ret;
1470
1471 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1472 ret = __attach_device(dev, domain);
1473 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1474
1475 /*
1476 * We might boot into a crash-kernel here. The crashed kernel
1477 * left the caches in the IOMMU dirty. So we have to flush
1478 * here to evict all dirty stuff.
1479 */
1480 iommu_flush_tlb_pde(domain);
1481
1482 return ret;
1483 }
1484
1485 /*
1486 * Removes a device from a protection domain (unlocked)
1487 */
1488 static void __detach_device(struct device *dev)
1489 {
1490 struct iommu_dev_data *dev_data = get_dev_data(dev);
1491 struct iommu_dev_data *alias_data;
1492 struct protection_domain *domain;
1493 unsigned long flags;
1494
1495 BUG_ON(!dev_data->domain);
1496
1497 domain = dev_data->domain;
1498
1499 spin_lock_irqsave(&domain->lock, flags);
1500
1501 if (dev_data->alias != dev) {
1502 alias_data = get_dev_data(dev_data->alias);
1503 if (atomic_dec_and_test(&alias_data->bind))
1504 do_detach(dev_data->alias);
1505 }
1506
1507 if (atomic_dec_and_test(&dev_data->bind))
1508 do_detach(dev);
1509
1510 spin_unlock_irqrestore(&domain->lock, flags);
1511
1512 /*
1513 * If we run in passthrough mode the device must be assigned to the
1514 * passthrough domain if it is detached from any other domain
1515 */
1516 if (iommu_pass_through && dev_data->domain == NULL)
1517 __attach_device(dev, pt_domain);
1518 }
1519
1520 /*
1521 * Removes a device from a protection domain (with devtable_lock held)
1522 */
1523 static void detach_device(struct device *dev)
1524 {
1525 unsigned long flags;
1526
1527 /* lock device table */
1528 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1529 __detach_device(dev);
1530 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1531 }
1532
1533 /*
1534 * Find out the protection domain structure for a given PCI device. This
1535 * will give us the pointer to the page table root for example.
1536 */
1537 static struct protection_domain *domain_for_device(struct device *dev)
1538 {
1539 struct protection_domain *dom;
1540 struct iommu_dev_data *dev_data, *alias_data;
1541 unsigned long flags;
1542 u16 devid, alias;
1543
1544 devid = get_device_id(dev);
1545 alias = amd_iommu_alias_table[devid];
1546 dev_data = get_dev_data(dev);
1547 alias_data = get_dev_data(dev_data->alias);
1548 if (!alias_data)
1549 return NULL;
1550
1551 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1552 dom = dev_data->domain;
1553 if (dom == NULL &&
1554 alias_data->domain != NULL) {
1555 __attach_device(dev, alias_data->domain);
1556 dom = alias_data->domain;
1557 }
1558
1559 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1560
1561 return dom;
1562 }
1563
1564 static int device_change_notifier(struct notifier_block *nb,
1565 unsigned long action, void *data)
1566 {
1567 struct device *dev = data;
1568 u16 devid;
1569 struct protection_domain *domain;
1570 struct dma_ops_domain *dma_domain;
1571 struct amd_iommu *iommu;
1572 unsigned long flags;
1573
1574 if (!check_device(dev))
1575 return 0;
1576
1577 devid = get_device_id(dev);
1578 iommu = amd_iommu_rlookup_table[devid];
1579
1580 switch (action) {
1581 case BUS_NOTIFY_UNBOUND_DRIVER:
1582
1583 domain = domain_for_device(dev);
1584
1585 if (!domain)
1586 goto out;
1587 if (iommu_pass_through)
1588 break;
1589 detach_device(dev);
1590 break;
1591 case BUS_NOTIFY_ADD_DEVICE:
1592
1593 iommu_init_device(dev);
1594
1595 domain = domain_for_device(dev);
1596
1597 /* allocate a protection domain if a device is added */
1598 dma_domain = find_protection_domain(devid);
1599 if (dma_domain)
1600 goto out;
1601 dma_domain = dma_ops_domain_alloc();
1602 if (!dma_domain)
1603 goto out;
1604 dma_domain->target_dev = devid;
1605
1606 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1607 list_add_tail(&dma_domain->list, &iommu_pd_list);
1608 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1609
1610 break;
1611 case BUS_NOTIFY_DEL_DEVICE:
1612
1613 iommu_uninit_device(dev);
1614
1615 default:
1616 goto out;
1617 }
1618
1619 iommu_flush_device(dev);
1620 iommu_completion_wait(iommu);
1621
1622 out:
1623 return 0;
1624 }
1625
1626 static struct notifier_block device_nb = {
1627 .notifier_call = device_change_notifier,
1628 };
1629
1630 void amd_iommu_init_notifier(void)
1631 {
1632 bus_register_notifier(&pci_bus_type, &device_nb);
1633 }
1634
1635 /*****************************************************************************
1636 *
1637 * The next functions belong to the dma_ops mapping/unmapping code.
1638 *
1639 *****************************************************************************/
1640
1641 /*
1642 * In the dma_ops path we only have the struct device. This function
1643 * finds the corresponding IOMMU, the protection domain and the
1644 * requestor id for a given device.
1645 * If the device is not yet associated with a domain this is also done
1646 * in this function.
1647 */
1648 static struct protection_domain *get_domain(struct device *dev)
1649 {
1650 struct protection_domain *domain;
1651 struct dma_ops_domain *dma_dom;
1652 u16 devid = get_device_id(dev);
1653
1654 if (!check_device(dev))
1655 return ERR_PTR(-EINVAL);
1656
1657 domain = domain_for_device(dev);
1658 if (domain != NULL && !dma_ops_domain(domain))
1659 return ERR_PTR(-EBUSY);
1660
1661 if (domain != NULL)
1662 return domain;
1663
1664 /* Device not bount yet - bind it */
1665 dma_dom = find_protection_domain(devid);
1666 if (!dma_dom)
1667 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1668 attach_device(dev, &dma_dom->domain);
1669 DUMP_printk("Using protection domain %d for device %s\n",
1670 dma_dom->domain.id, dev_name(dev));
1671
1672 return &dma_dom->domain;
1673 }
1674
1675 static void update_device_table(struct protection_domain *domain)
1676 {
1677 struct iommu_dev_data *dev_data;
1678
1679 list_for_each_entry(dev_data, &domain->dev_list, list) {
1680 u16 devid = get_device_id(dev_data->dev);
1681 set_dte_entry(devid, domain);
1682 }
1683 }
1684
1685 static void update_domain(struct protection_domain *domain)
1686 {
1687 if (!domain->updated)
1688 return;
1689
1690 update_device_table(domain);
1691 iommu_flush_domain_devices(domain);
1692 iommu_flush_tlb_pde(domain);
1693
1694 domain->updated = false;
1695 }
1696
1697 /*
1698 * This function fetches the PTE for a given address in the aperture
1699 */
1700 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1701 unsigned long address)
1702 {
1703 struct aperture_range *aperture;
1704 u64 *pte, *pte_page;
1705
1706 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1707 if (!aperture)
1708 return NULL;
1709
1710 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1711 if (!pte) {
1712 pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
1713 GFP_ATOMIC);
1714 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1715 } else
1716 pte += PM_LEVEL_INDEX(0, address);
1717
1718 update_domain(&dom->domain);
1719
1720 return pte;
1721 }
1722
1723 /*
1724 * This is the generic map function. It maps one 4kb page at paddr to
1725 * the given address in the DMA address space for the domain.
1726 */
1727 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1728 unsigned long address,
1729 phys_addr_t paddr,
1730 int direction)
1731 {
1732 u64 *pte, __pte;
1733
1734 WARN_ON(address > dom->aperture_size);
1735
1736 paddr &= PAGE_MASK;
1737
1738 pte = dma_ops_get_pte(dom, address);
1739 if (!pte)
1740 return DMA_ERROR_CODE;
1741
1742 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1743
1744 if (direction == DMA_TO_DEVICE)
1745 __pte |= IOMMU_PTE_IR;
1746 else if (direction == DMA_FROM_DEVICE)
1747 __pte |= IOMMU_PTE_IW;
1748 else if (direction == DMA_BIDIRECTIONAL)
1749 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1750
1751 WARN_ON(*pte);
1752
1753 *pte = __pte;
1754
1755 return (dma_addr_t)address;
1756 }
1757
1758 /*
1759 * The generic unmapping function for on page in the DMA address space.
1760 */
1761 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1762 unsigned long address)
1763 {
1764 struct aperture_range *aperture;
1765 u64 *pte;
1766
1767 if (address >= dom->aperture_size)
1768 return;
1769
1770 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1771 if (!aperture)
1772 return;
1773
1774 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1775 if (!pte)
1776 return;
1777
1778 pte += PM_LEVEL_INDEX(0, address);
1779
1780 WARN_ON(!*pte);
1781
1782 *pte = 0ULL;
1783 }
1784
1785 /*
1786 * This function contains common code for mapping of a physically
1787 * contiguous memory region into DMA address space. It is used by all
1788 * mapping functions provided with this IOMMU driver.
1789 * Must be called with the domain lock held.
1790 */
1791 static dma_addr_t __map_single(struct device *dev,
1792 struct dma_ops_domain *dma_dom,
1793 phys_addr_t paddr,
1794 size_t size,
1795 int dir,
1796 bool align,
1797 u64 dma_mask)
1798 {
1799 dma_addr_t offset = paddr & ~PAGE_MASK;
1800 dma_addr_t address, start, ret;
1801 unsigned int pages;
1802 unsigned long align_mask = 0;
1803 int i;
1804
1805 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1806 paddr &= PAGE_MASK;
1807
1808 INC_STATS_COUNTER(total_map_requests);
1809
1810 if (pages > 1)
1811 INC_STATS_COUNTER(cross_page);
1812
1813 if (align)
1814 align_mask = (1UL << get_order(size)) - 1;
1815
1816 retry:
1817 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1818 dma_mask);
1819 if (unlikely(address == DMA_ERROR_CODE)) {
1820 /*
1821 * setting next_address here will let the address
1822 * allocator only scan the new allocated range in the
1823 * first run. This is a small optimization.
1824 */
1825 dma_dom->next_address = dma_dom->aperture_size;
1826
1827 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1828 goto out;
1829
1830 /*
1831 * aperture was successfully enlarged by 128 MB, try
1832 * allocation again
1833 */
1834 goto retry;
1835 }
1836
1837 start = address;
1838 for (i = 0; i < pages; ++i) {
1839 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1840 if (ret == DMA_ERROR_CODE)
1841 goto out_unmap;
1842
1843 paddr += PAGE_SIZE;
1844 start += PAGE_SIZE;
1845 }
1846 address += offset;
1847
1848 ADD_STATS_COUNTER(alloced_io_mem, size);
1849
1850 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1851 iommu_flush_tlb(&dma_dom->domain);
1852 dma_dom->need_flush = false;
1853 } else if (unlikely(amd_iommu_np_cache))
1854 iommu_flush_pages(&dma_dom->domain, address, size);
1855
1856 out:
1857 return address;
1858
1859 out_unmap:
1860
1861 for (--i; i >= 0; --i) {
1862 start -= PAGE_SIZE;
1863 dma_ops_domain_unmap(dma_dom, start);
1864 }
1865
1866 dma_ops_free_addresses(dma_dom, address, pages);
1867
1868 return DMA_ERROR_CODE;
1869 }
1870
1871 /*
1872 * Does the reverse of the __map_single function. Must be called with
1873 * the domain lock held too
1874 */
1875 static void __unmap_single(struct dma_ops_domain *dma_dom,
1876 dma_addr_t dma_addr,
1877 size_t size,
1878 int dir)
1879 {
1880 dma_addr_t i, start;
1881 unsigned int pages;
1882
1883 if ((dma_addr == DMA_ERROR_CODE) ||
1884 (dma_addr + size > dma_dom->aperture_size))
1885 return;
1886
1887 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1888 dma_addr &= PAGE_MASK;
1889 start = dma_addr;
1890
1891 for (i = 0; i < pages; ++i) {
1892 dma_ops_domain_unmap(dma_dom, start);
1893 start += PAGE_SIZE;
1894 }
1895
1896 SUB_STATS_COUNTER(alloced_io_mem, size);
1897
1898 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1899
1900 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1901 iommu_flush_pages(&dma_dom->domain, dma_addr, size);
1902 dma_dom->need_flush = false;
1903 }
1904 }
1905
1906 /*
1907 * The exported map_single function for dma_ops.
1908 */
1909 static dma_addr_t map_page(struct device *dev, struct page *page,
1910 unsigned long offset, size_t size,
1911 enum dma_data_direction dir,
1912 struct dma_attrs *attrs)
1913 {
1914 unsigned long flags;
1915 struct protection_domain *domain;
1916 dma_addr_t addr;
1917 u64 dma_mask;
1918 phys_addr_t paddr = page_to_phys(page) + offset;
1919
1920 INC_STATS_COUNTER(cnt_map_single);
1921
1922 domain = get_domain(dev);
1923 if (PTR_ERR(domain) == -EINVAL)
1924 return (dma_addr_t)paddr;
1925 else if (IS_ERR(domain))
1926 return DMA_ERROR_CODE;
1927
1928 dma_mask = *dev->dma_mask;
1929
1930 spin_lock_irqsave(&domain->lock, flags);
1931
1932 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
1933 dma_mask);
1934 if (addr == DMA_ERROR_CODE)
1935 goto out;
1936
1937 iommu_flush_complete(domain);
1938
1939 out:
1940 spin_unlock_irqrestore(&domain->lock, flags);
1941
1942 return addr;
1943 }
1944
1945 /*
1946 * The exported unmap_single function for dma_ops.
1947 */
1948 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1949 enum dma_data_direction dir, struct dma_attrs *attrs)
1950 {
1951 unsigned long flags;
1952 struct protection_domain *domain;
1953
1954 INC_STATS_COUNTER(cnt_unmap_single);
1955
1956 domain = get_domain(dev);
1957 if (IS_ERR(domain))
1958 return;
1959
1960 spin_lock_irqsave(&domain->lock, flags);
1961
1962 __unmap_single(domain->priv, dma_addr, size, dir);
1963
1964 iommu_flush_complete(domain);
1965
1966 spin_unlock_irqrestore(&domain->lock, flags);
1967 }
1968
1969 /*
1970 * This is a special map_sg function which is used if we should map a
1971 * device which is not handled by an AMD IOMMU in the system.
1972 */
1973 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1974 int nelems, int dir)
1975 {
1976 struct scatterlist *s;
1977 int i;
1978
1979 for_each_sg(sglist, s, nelems, i) {
1980 s->dma_address = (dma_addr_t)sg_phys(s);
1981 s->dma_length = s->length;
1982 }
1983
1984 return nelems;
1985 }
1986
1987 /*
1988 * The exported map_sg function for dma_ops (handles scatter-gather
1989 * lists).
1990 */
1991 static int map_sg(struct device *dev, struct scatterlist *sglist,
1992 int nelems, enum dma_data_direction dir,
1993 struct dma_attrs *attrs)
1994 {
1995 unsigned long flags;
1996 struct protection_domain *domain;
1997 int i;
1998 struct scatterlist *s;
1999 phys_addr_t paddr;
2000 int mapped_elems = 0;
2001 u64 dma_mask;
2002
2003 INC_STATS_COUNTER(cnt_map_sg);
2004
2005 domain = get_domain(dev);
2006 if (PTR_ERR(domain) == -EINVAL)
2007 return map_sg_no_iommu(dev, sglist, nelems, dir);
2008 else if (IS_ERR(domain))
2009 return 0;
2010
2011 dma_mask = *dev->dma_mask;
2012
2013 spin_lock_irqsave(&domain->lock, flags);
2014
2015 for_each_sg(sglist, s, nelems, i) {
2016 paddr = sg_phys(s);
2017
2018 s->dma_address = __map_single(dev, domain->priv,
2019 paddr, s->length, dir, false,
2020 dma_mask);
2021
2022 if (s->dma_address) {
2023 s->dma_length = s->length;
2024 mapped_elems++;
2025 } else
2026 goto unmap;
2027 }
2028
2029 iommu_flush_complete(domain);
2030
2031 out:
2032 spin_unlock_irqrestore(&domain->lock, flags);
2033
2034 return mapped_elems;
2035 unmap:
2036 for_each_sg(sglist, s, mapped_elems, i) {
2037 if (s->dma_address)
2038 __unmap_single(domain->priv, s->dma_address,
2039 s->dma_length, dir);
2040 s->dma_address = s->dma_length = 0;
2041 }
2042
2043 mapped_elems = 0;
2044
2045 goto out;
2046 }
2047
2048 /*
2049 * The exported map_sg function for dma_ops (handles scatter-gather
2050 * lists).
2051 */
2052 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2053 int nelems, enum dma_data_direction dir,
2054 struct dma_attrs *attrs)
2055 {
2056 unsigned long flags;
2057 struct protection_domain *domain;
2058 struct scatterlist *s;
2059 int i;
2060
2061 INC_STATS_COUNTER(cnt_unmap_sg);
2062
2063 domain = get_domain(dev);
2064 if (IS_ERR(domain))
2065 return;
2066
2067 spin_lock_irqsave(&domain->lock, flags);
2068
2069 for_each_sg(sglist, s, nelems, i) {
2070 __unmap_single(domain->priv, s->dma_address,
2071 s->dma_length, dir);
2072 s->dma_address = s->dma_length = 0;
2073 }
2074
2075 iommu_flush_complete(domain);
2076
2077 spin_unlock_irqrestore(&domain->lock, flags);
2078 }
2079
2080 /*
2081 * The exported alloc_coherent function for dma_ops.
2082 */
2083 static void *alloc_coherent(struct device *dev, size_t size,
2084 dma_addr_t *dma_addr, gfp_t flag)
2085 {
2086 unsigned long flags;
2087 void *virt_addr;
2088 struct protection_domain *domain;
2089 phys_addr_t paddr;
2090 u64 dma_mask = dev->coherent_dma_mask;
2091
2092 INC_STATS_COUNTER(cnt_alloc_coherent);
2093
2094 domain = get_domain(dev);
2095 if (PTR_ERR(domain) == -EINVAL) {
2096 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2097 *dma_addr = __pa(virt_addr);
2098 return virt_addr;
2099 } else if (IS_ERR(domain))
2100 return NULL;
2101
2102 dma_mask = dev->coherent_dma_mask;
2103 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2104 flag |= __GFP_ZERO;
2105
2106 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2107 if (!virt_addr)
2108 return NULL;
2109
2110 paddr = virt_to_phys(virt_addr);
2111
2112 if (!dma_mask)
2113 dma_mask = *dev->dma_mask;
2114
2115 spin_lock_irqsave(&domain->lock, flags);
2116
2117 *dma_addr = __map_single(dev, domain->priv, paddr,
2118 size, DMA_BIDIRECTIONAL, true, dma_mask);
2119
2120 if (*dma_addr == DMA_ERROR_CODE) {
2121 spin_unlock_irqrestore(&domain->lock, flags);
2122 goto out_free;
2123 }
2124
2125 iommu_flush_complete(domain);
2126
2127 spin_unlock_irqrestore(&domain->lock, flags);
2128
2129 return virt_addr;
2130
2131 out_free:
2132
2133 free_pages((unsigned long)virt_addr, get_order(size));
2134
2135 return NULL;
2136 }
2137
2138 /*
2139 * The exported free_coherent function for dma_ops.
2140 */
2141 static void free_coherent(struct device *dev, size_t size,
2142 void *virt_addr, dma_addr_t dma_addr)
2143 {
2144 unsigned long flags;
2145 struct protection_domain *domain;
2146
2147 INC_STATS_COUNTER(cnt_free_coherent);
2148
2149 domain = get_domain(dev);
2150 if (IS_ERR(domain))
2151 goto free_mem;
2152
2153 spin_lock_irqsave(&domain->lock, flags);
2154
2155 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2156
2157 iommu_flush_complete(domain);
2158
2159 spin_unlock_irqrestore(&domain->lock, flags);
2160
2161 free_mem:
2162 free_pages((unsigned long)virt_addr, get_order(size));
2163 }
2164
2165 /*
2166 * This function is called by the DMA layer to find out if we can handle a
2167 * particular device. It is part of the dma_ops.
2168 */
2169 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2170 {
2171 return check_device(dev);
2172 }
2173
2174 /*
2175 * The function for pre-allocating protection domains.
2176 *
2177 * If the driver core informs the DMA layer if a driver grabs a device
2178 * we don't need to preallocate the protection domains anymore.
2179 * For now we have to.
2180 */
2181 static void prealloc_protection_domains(void)
2182 {
2183 struct pci_dev *dev = NULL;
2184 struct dma_ops_domain *dma_dom;
2185 u16 devid;
2186
2187 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2188
2189 /* Do we handle this device? */
2190 if (!check_device(&dev->dev))
2191 continue;
2192
2193 /* Is there already any domain for it? */
2194 if (domain_for_device(&dev->dev))
2195 continue;
2196
2197 devid = get_device_id(&dev->dev);
2198
2199 dma_dom = dma_ops_domain_alloc();
2200 if (!dma_dom)
2201 continue;
2202 init_unity_mappings_for_device(dma_dom, devid);
2203 dma_dom->target_dev = devid;
2204
2205 attach_device(&dev->dev, &dma_dom->domain);
2206
2207 list_add_tail(&dma_dom->list, &iommu_pd_list);
2208 }
2209 }
2210
2211 static struct dma_map_ops amd_iommu_dma_ops = {
2212 .alloc_coherent = alloc_coherent,
2213 .free_coherent = free_coherent,
2214 .map_page = map_page,
2215 .unmap_page = unmap_page,
2216 .map_sg = map_sg,
2217 .unmap_sg = unmap_sg,
2218 .dma_supported = amd_iommu_dma_supported,
2219 };
2220
2221 /*
2222 * The function which clues the AMD IOMMU driver into dma_ops.
2223 */
2224
2225 void __init amd_iommu_init_api(void)
2226 {
2227 register_iommu(&amd_iommu_ops);
2228 }
2229
2230 int __init amd_iommu_init_dma_ops(void)
2231 {
2232 struct amd_iommu *iommu;
2233 int ret;
2234
2235 /*
2236 * first allocate a default protection domain for every IOMMU we
2237 * found in the system. Devices not assigned to any other
2238 * protection domain will be assigned to the default one.
2239 */
2240 for_each_iommu(iommu) {
2241 iommu->default_dom = dma_ops_domain_alloc();
2242 if (iommu->default_dom == NULL)
2243 return -ENOMEM;
2244 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2245 ret = iommu_init_unity_mappings(iommu);
2246 if (ret)
2247 goto free_domains;
2248 }
2249
2250 /*
2251 * Pre-allocate the protection domains for each device.
2252 */
2253 prealloc_protection_domains();
2254
2255 iommu_detected = 1;
2256 swiotlb = 0;
2257 #ifdef CONFIG_GART_IOMMU
2258 gart_iommu_aperture_disabled = 1;
2259 gart_iommu_aperture = 0;
2260 #endif
2261
2262 /* Make the driver finally visible to the drivers */
2263 dma_ops = &amd_iommu_dma_ops;
2264
2265 amd_iommu_stats_init();
2266
2267 return 0;
2268
2269 free_domains:
2270
2271 for_each_iommu(iommu) {
2272 if (iommu->default_dom)
2273 dma_ops_domain_free(iommu->default_dom);
2274 }
2275
2276 return ret;
2277 }
2278
2279 /*****************************************************************************
2280 *
2281 * The following functions belong to the exported interface of AMD IOMMU
2282 *
2283 * This interface allows access to lower level functions of the IOMMU
2284 * like protection domain handling and assignement of devices to domains
2285 * which is not possible with the dma_ops interface.
2286 *
2287 *****************************************************************************/
2288
2289 static void cleanup_domain(struct protection_domain *domain)
2290 {
2291 struct iommu_dev_data *dev_data, *next;
2292 unsigned long flags;
2293
2294 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2295
2296 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2297 struct device *dev = dev_data->dev;
2298
2299 do_detach(dev);
2300 atomic_set(&dev_data->bind, 0);
2301 }
2302
2303 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2304 }
2305
2306 static void protection_domain_free(struct protection_domain *domain)
2307 {
2308 if (!domain)
2309 return;
2310
2311 del_domain_from_list(domain);
2312
2313 if (domain->id)
2314 domain_id_free(domain->id);
2315
2316 kfree(domain);
2317 }
2318
2319 static struct protection_domain *protection_domain_alloc(void)
2320 {
2321 struct protection_domain *domain;
2322
2323 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2324 if (!domain)
2325 return NULL;
2326
2327 spin_lock_init(&domain->lock);
2328 domain->id = domain_id_alloc();
2329 if (!domain->id)
2330 goto out_err;
2331 INIT_LIST_HEAD(&domain->dev_list);
2332
2333 add_domain_to_list(domain);
2334
2335 return domain;
2336
2337 out_err:
2338 kfree(domain);
2339
2340 return NULL;
2341 }
2342
2343 static int amd_iommu_domain_init(struct iommu_domain *dom)
2344 {
2345 struct protection_domain *domain;
2346
2347 domain = protection_domain_alloc();
2348 if (!domain)
2349 goto out_free;
2350
2351 domain->mode = PAGE_MODE_3_LEVEL;
2352 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2353 if (!domain->pt_root)
2354 goto out_free;
2355
2356 dom->priv = domain;
2357
2358 return 0;
2359
2360 out_free:
2361 protection_domain_free(domain);
2362
2363 return -ENOMEM;
2364 }
2365
2366 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2367 {
2368 struct protection_domain *domain = dom->priv;
2369
2370 if (!domain)
2371 return;
2372
2373 if (domain->dev_cnt > 0)
2374 cleanup_domain(domain);
2375
2376 BUG_ON(domain->dev_cnt != 0);
2377
2378 free_pagetable(domain);
2379
2380 domain_id_free(domain->id);
2381
2382 kfree(domain);
2383
2384 dom->priv = NULL;
2385 }
2386
2387 static void amd_iommu_detach_device(struct iommu_domain *dom,
2388 struct device *dev)
2389 {
2390 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2391 struct amd_iommu *iommu;
2392 u16 devid;
2393
2394 if (!check_device(dev))
2395 return;
2396
2397 devid = get_device_id(dev);
2398
2399 if (dev_data->domain != NULL)
2400 detach_device(dev);
2401
2402 iommu = amd_iommu_rlookup_table[devid];
2403 if (!iommu)
2404 return;
2405
2406 iommu_flush_device(dev);
2407 iommu_completion_wait(iommu);
2408 }
2409
2410 static int amd_iommu_attach_device(struct iommu_domain *dom,
2411 struct device *dev)
2412 {
2413 struct protection_domain *domain = dom->priv;
2414 struct iommu_dev_data *dev_data;
2415 struct amd_iommu *iommu;
2416 int ret;
2417 u16 devid;
2418
2419 if (!check_device(dev))
2420 return -EINVAL;
2421
2422 dev_data = dev->archdata.iommu;
2423
2424 devid = get_device_id(dev);
2425
2426 iommu = amd_iommu_rlookup_table[devid];
2427 if (!iommu)
2428 return -EINVAL;
2429
2430 if (dev_data->domain)
2431 detach_device(dev);
2432
2433 ret = attach_device(dev, domain);
2434
2435 iommu_completion_wait(iommu);
2436
2437 return ret;
2438 }
2439
2440 static int amd_iommu_map_range(struct iommu_domain *dom,
2441 unsigned long iova, phys_addr_t paddr,
2442 size_t size, int iommu_prot)
2443 {
2444 struct protection_domain *domain = dom->priv;
2445 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2446 int prot = 0;
2447 int ret;
2448
2449 if (iommu_prot & IOMMU_READ)
2450 prot |= IOMMU_PROT_IR;
2451 if (iommu_prot & IOMMU_WRITE)
2452 prot |= IOMMU_PROT_IW;
2453
2454 iova &= PAGE_MASK;
2455 paddr &= PAGE_MASK;
2456
2457 for (i = 0; i < npages; ++i) {
2458 ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
2459 if (ret)
2460 return ret;
2461
2462 iova += PAGE_SIZE;
2463 paddr += PAGE_SIZE;
2464 }
2465
2466 return 0;
2467 }
2468
2469 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2470 unsigned long iova, size_t size)
2471 {
2472
2473 struct protection_domain *domain = dom->priv;
2474 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2475
2476 iova &= PAGE_MASK;
2477
2478 for (i = 0; i < npages; ++i) {
2479 iommu_unmap_page(domain, iova, PM_MAP_4k);
2480 iova += PAGE_SIZE;
2481 }
2482
2483 iommu_flush_tlb_pde(domain);
2484 }
2485
2486 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2487 unsigned long iova)
2488 {
2489 struct protection_domain *domain = dom->priv;
2490 unsigned long offset = iova & ~PAGE_MASK;
2491 phys_addr_t paddr;
2492 u64 *pte;
2493
2494 pte = fetch_pte(domain, iova, PM_MAP_4k);
2495
2496 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2497 return 0;
2498
2499 paddr = *pte & IOMMU_PAGE_MASK;
2500 paddr |= offset;
2501
2502 return paddr;
2503 }
2504
2505 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2506 unsigned long cap)
2507 {
2508 return 0;
2509 }
2510
2511 static struct iommu_ops amd_iommu_ops = {
2512 .domain_init = amd_iommu_domain_init,
2513 .domain_destroy = amd_iommu_domain_destroy,
2514 .attach_dev = amd_iommu_attach_device,
2515 .detach_dev = amd_iommu_detach_device,
2516 .map = amd_iommu_map_range,
2517 .unmap = amd_iommu_unmap_range,
2518 .iova_to_phys = amd_iommu_iova_to_phys,
2519 .domain_has_cap = amd_iommu_domain_has_cap,
2520 };
2521
2522 /*****************************************************************************
2523 *
2524 * The next functions do a basic initialization of IOMMU for pass through
2525 * mode
2526 *
2527 * In passthrough mode the IOMMU is initialized and enabled but not used for
2528 * DMA-API translation.
2529 *
2530 *****************************************************************************/
2531
2532 int __init amd_iommu_init_passthrough(void)
2533 {
2534 struct amd_iommu *iommu;
2535 struct pci_dev *dev = NULL;
2536 u16 devid;
2537
2538 /* allocate passthrough domain */
2539 pt_domain = protection_domain_alloc();
2540 if (!pt_domain)
2541 return -ENOMEM;
2542
2543 pt_domain->mode |= PAGE_MODE_NONE;
2544
2545 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2546
2547 if (!check_device(&dev->dev))
2548 continue;
2549
2550 devid = get_device_id(&dev->dev);
2551
2552 iommu = amd_iommu_rlookup_table[devid];
2553 if (!iommu)
2554 continue;
2555
2556 attach_device(&dev->dev, pt_domain);
2557 }
2558
2559 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
2560
2561 return 0;
2562 }
kernel source for telekom puls (alcatel/mediatek)