arch/x86/include/asm/system.h

   1 #ifndef _ASM_X86_SYSTEM_H
   2 #define _ASM_X86_SYSTEM_H
   3
   4 #include <asm/asm.h>
   5 #include <asm/segment.h>
   6 #include <asm/cpufeature.h>
   7 #include <asm/cmpxchg.h>
   8 #include <asm/nops.h>
   9
  10 #include <linux/kernel.h>
  11 #include <linux/irqflags.h>
  12
  13 /* entries in ARCH_DLINFO: */
  14 #ifdef CONFIG_IA32_EMULATION
  15 # define AT_VECTOR_SIZE_ARCH 2
  16 #else
  17 # define AT_VECTOR_SIZE_ARCH 1
  18 #endif
  19
  20 struct task_struct; /* one of the stranger aspects of C forward declarations */
  21 struct task_struct *__switch_to(struct task_struct *prev,
  22                                 struct task_struct *next);
  23
  24 #ifdef CONFIG_X86_32
  25
  26 /*
  27  * Saving eflags is important. It switches not only IOPL between tasks,
  28  * it also protects other tasks from NT leaking through sysenter etc.
  29  */
  30 #define switch_to(prev, next, last)                                     \
  31 do {                                                                    \
  32         /*                                                              \
  33          * Context-switching clobbers all registers, so we clobber      \
  34          * them explicitly, via unused output variables.                \
  35          * (EAX and EBP is not listed because EBP is saved/restored     \
  36          * explicitly for wchan access and EAX is the return value of   \
  37          * __switch_to())                                               \
  38          */                                                             \
  39         unsigned long ebx, ecx, edx, esi, edi;                          \
  40                                                                         \
  41         asm volatile("pushfl\n\t"               /* save    flags */     \
  42                      "pushl %%ebp\n\t"          /* save    EBP   */     \
  43                      "movl %%esp,%[prev_sp]\n\t"        /* save    ESP   */ \
  44                      "movl %[next_sp],%%esp\n\t"        /* restore ESP   */ \
  45                      "movl $1f,%[prev_ip]\n\t"  /* save    EIP   */     \
  46                      "pushl %[next_ip]\n\t"     /* restore EIP   */     \
  47                      "jmp __switch_to\n"        /* regparm call  */     \
  48                      "1:\t"                                             \
  49                      "popl %%ebp\n\t"           /* restore EBP   */     \
  50                      "popfl\n"                  /* restore flags */     \
  51                                                                         \
  52                      /* output parameters */                            \
  53                      : [prev_sp] "=m" (prev->thread.sp),                \
  54                        [prev_ip] "=m" (prev->thread.ip),                \
  55                        "=a" (last),                                     \
  56                                                                         \
  57                        /* clobbered output registers: */                \
  58                        "=b" (ebx), "=c" (ecx), "=d" (edx),              \
  59                        "=S" (esi), "=D" (edi)                           \
  60                                                                         \
  61                        /* input parameters: */                          \
  62                      : [next_sp]  "m" (next->thread.sp),                \
  63                        [next_ip]  "m" (next->thread.ip),                \
  64                                                                         \
  65                        /* regparm parameters for __switch_to(): */      \
  66                        [prev]     "a" (prev),                           \
  67                        [next]     "d" (next)                            \
  68                                                                         \
  69                      : /* reloaded segment registers */                 \
  70                         "memory");                                      \
  71 } while (0)
  72
  73 /*
  74  * disable hlt during certain critical i/o operations
  75  */
  76 #define HAVE_DISABLE_HLT
  77 #else
  78 #define __SAVE(reg, offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  79 #define __RESTORE(reg, offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  80
  81 /* frame pointer must be last for get_wchan */
  82 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  83 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
  84
  85 #define __EXTRA_CLOBBER  \
  86         , "rcx", "rbx", "rdx", "r8", "r9", "r10", "r11", \
  87           "r12", "r13", "r14", "r15"
  88
  89 /* Save restore flags to clear handle leaking NT */
  90 #define switch_to(prev, next, last) \
  91         asm volatile(SAVE_CONTEXT                                                   \
  92              "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
  93              "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
  94              "call __switch_to\n\t"                                       \
  95              ".globl thread_return\n"                                     \
  96              "thread_return:\n\t"                                         \
  97              "movq "__percpu_arg([current_task])",%%rsi\n\t"              \
  98              "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
  99              LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
 100              "movq %%rax,%%rdi\n\t"                                       \
 101              "jc   ret_from_fork\n\t"                                     \
 102              RESTORE_CONTEXT                                              \
 103              : "=a" (last)                                                \
 104              : [next] "S" (next), [prev] "D" (prev),                      \
 105                [threadrsp] "i" (offsetof(struct task_struct, thread.sp)), \
 106                [ti_flags] "i" (offsetof(struct thread_info, flags)),      \
 107                [tif_fork] "i" (TIF_FORK),                                 \
 108                [thread_info] "i" (offsetof(struct task_struct, stack)),   \
 109                [current_task] "m" (per_cpu_var(current_task))             \
 110              : "memory", "cc" __EXTRA_CLOBBER)
 111 #endif
 112
 113 #ifdef __KERNEL__
 114 #define _set_base(addr, base) do { unsigned long __pr; \
 115 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 116         "rorl $16,%%edx\n\t" \
 117         "movb %%dl,%2\n\t" \
 118         "movb %%dh,%3" \
 119         :"=&d" (__pr) \
 120         :"m" (*((addr)+2)), \
 121          "m" (*((addr)+4)), \
 122          "m" (*((addr)+7)), \
 123          "0" (base) \
 124         ); } while (0)
 125
 126 #define _set_limit(addr, limit) do { unsigned long __lr; \
 127 __asm__ __volatile__ ("movw %%dx,%1\n\t" \
 128         "rorl $16,%%edx\n\t" \
 129         "movb %2,%%dh\n\t" \
 130         "andb $0xf0,%%dh\n\t" \
 131         "orb %%dh,%%dl\n\t" \
 132         "movb %%dl,%2" \
 133         :"=&d" (__lr) \
 134         :"m" (*(addr)), \
 135          "m" (*((addr)+6)), \
 136          "0" (limit) \
 137         ); } while (0)
 138
 139 #define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
 140 #define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
 141
 142 extern void native_load_gs_index(unsigned);
 143
 144 /*
 145  * Load a segment. Fall back on loading the zero
 146  * segment if something goes wrong..
 147  */
 148 #define loadsegment(seg, value)                 \
 149         asm volatile("\n"                       \
 150                      "1:\t"                     \
 151                      "movl %k0,%%" #seg "\n"    \
 152                      "2:\n"                     \
 153                      ".section .fixup,\"ax\"\n" \
 154                      "3:\t"                     \
 155                      "movl %k1, %%" #seg "\n\t" \
 156                      "jmp 2b\n"                 \
 157                      ".previous\n"              \
 158                      _ASM_EXTABLE(1b,3b)        \
 159                      : :"r" (value), "r" (0) : "memory")
 160
 161
 162 /*
 163  * Save a segment register away
 164  */
 165 #define savesegment(seg, value)                         \
 166         asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
 167
 168 static inline unsigned long get_limit(unsigned long segment)
 169 {
 170         unsigned long __limit;
 171         asm("lsll %1,%0" : "=r" (__limit) : "r" (segment));
 172         return __limit + 1;
 173 }
 174
 175 static inline void native_clts(void)
 176 {
 177         asm volatile("clts");
 178 }
 179
 180 /*
 181  * Volatile isn't enough to prevent the compiler from reordering the
 182  * read/write functions for the control registers and messing everything up.
 183  * A memory clobber would solve the problem, but would prevent reordering of
 184  * all loads stores around it, which can hurt performance. Solution is to
 185  * use a variable and mimic reads and writes to it to enforce serialization
 186  */
 187 static unsigned long __force_order;
 188
 189 static inline unsigned long native_read_cr0(void)
 190 {
 191         unsigned long val;
 192         asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
 193         return val;
 194 }
 195
 196 static inline void native_write_cr0(unsigned long val)
 197 {
 198         asm volatile("mov %0,%%cr0": : "r" (val), "m" (__force_order));
 199 }
 200
 201 static inline unsigned long native_read_cr2(void)
 202 {
 203         unsigned long val;
 204         asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
 205         return val;
 206 }
 207
 208 static inline void native_write_cr2(unsigned long val)
 209 {
 210         asm volatile("mov %0,%%cr2": : "r" (val), "m" (__force_order));
 211 }
 212
 213 static inline unsigned long native_read_cr3(void)
 214 {
 215         unsigned long val;
 216         asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
 217         return val;
 218 }
 219
 220 static inline void native_write_cr3(unsigned long val)
 221 {
 222         asm volatile("mov %0,%%cr3": : "r" (val), "m" (__force_order));
 223 }
 224
 225 static inline unsigned long native_read_cr4(void)
 226 {
 227         unsigned long val;
 228         asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
 229         return val;
 230 }
 231
 232 static inline unsigned long native_read_cr4_safe(void)
 233 {
 234         unsigned long val;
 235         /* This could fault if %cr4 does not exist. In x86_64, a cr4 always
 236          * exists, so it will never fail. */
 237 #ifdef CONFIG_X86_32
 238         asm volatile("1: mov %%cr4, %0\n"
 239                      "2:\n"
 240                      _ASM_EXTABLE(1b, 2b)
 241                      : "=r" (val), "=m" (__force_order) : "0" (0));
 242 #else
 243         val = native_read_cr4();
 244 #endif
 245         return val;
 246 }
 247
 248 static inline void native_write_cr4(unsigned long val)
 249 {
 250         asm volatile("mov %0,%%cr4": : "r" (val), "m" (__force_order));
 251 }
 252
 253 #ifdef CONFIG_X86_64
 254 static inline unsigned long native_read_cr8(void)
 255 {
 256         unsigned long cr8;
 257         asm volatile("movq %%cr8,%0" : "=r" (cr8));
 258         return cr8;
 259 }
 260
 261 static inline void native_write_cr8(unsigned long val)
 262 {
 263         asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
 264 }
 265 #endif
 266
 267 static inline void native_wbinvd(void)
 268 {
 269         asm volatile("wbinvd": : :"memory");
 270 }
 271
 272 #ifdef CONFIG_PARAVIRT
 273 #include <asm/paravirt.h>
 274 #else
 275 #define read_cr0()      (native_read_cr0())
 276 #define write_cr0(x)    (native_write_cr0(x))
 277 #define read_cr2()      (native_read_cr2())
 278 #define write_cr2(x)    (native_write_cr2(x))
 279 #define read_cr3()      (native_read_cr3())
 280 #define write_cr3(x)    (native_write_cr3(x))
 281 #define read_cr4()      (native_read_cr4())
 282 #define read_cr4_safe() (native_read_cr4_safe())
 283 #define write_cr4(x)    (native_write_cr4(x))
 284 #define wbinvd()        (native_wbinvd())
 285 #ifdef CONFIG_X86_64
 286 #define read_cr8()      (native_read_cr8())
 287 #define write_cr8(x)    (native_write_cr8(x))
 288 #define load_gs_index   native_load_gs_index
 289 #endif
 290
 291 /* Clear the 'TS' bit */
 292 #define clts()          (native_clts())
 293
 294 #endif/* CONFIG_PARAVIRT */
 295
 296 #define stts() write_cr0(read_cr0() | X86_CR0_TS)
 297
 298 #endif /* __KERNEL__ */
 299
 300 static inline void clflush(volatile void *__p)
 301 {
 302         asm volatile("clflush %0" : "+m" (*(volatile char __force *)__p));
 303 }
 304
 305 #define nop() asm volatile ("nop")
 306
 307 void disable_hlt(void);
 308 void enable_hlt(void);
 309
 310 void cpu_idle_wait(void);
 311
 312 extern unsigned long arch_align_stack(unsigned long sp);
 313 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 314
 315 void default_idle(void);
 316
 317 void stop_this_cpu(void *dummy);
 318
 319 /*
 320  * Force strict CPU ordering.
 321  * And yes, this is required on UP too when we're talking
 322  * to devices.
 323  */
 324 #ifdef CONFIG_X86_32
 325 /*
 326  * Some non-Intel clones support out of order store. wmb() ceases to be a
 327  * nop for these.
 328  */
 329 #define mb() alternative("lock; addl $0,0(%%esp)", "mfence", X86_FEATURE_XMM2)
 330 #define rmb() alternative("lock; addl $0,0(%%esp)", "lfence", X86_FEATURE_XMM2)
 331 #define wmb() alternative("lock; addl $0,0(%%esp)", "sfence", X86_FEATURE_XMM)
 332 #else
 333 #define mb()    asm volatile("mfence":::"memory")
 334 #define rmb()   asm volatile("lfence":::"memory")
 335 #define wmb()   asm volatile("sfence" ::: "memory")
 336 #endif
 337
 338 /**
 339  * read_barrier_depends - Flush all pending reads that subsequents reads
 340  * depend on.
 341  *
 342  * No data-dependent reads from memory-like regions are ever reordered
 343  * over this barrier.  All reads preceding this primitive are guaranteed
 344  * to access memory (but not necessarily other CPUs' caches) before any
 345  * reads following this primitive that depend on the data return by
 346  * any of the preceding reads.  This primitive is much lighter weight than
 347  * rmb() on most CPUs, and is never heavier weight than is
 348  * rmb().
 349  *
 350  * These ordering constraints are respected by both the local CPU
 351  * and the compiler.
 352  *
 353  * Ordering is not guaranteed by anything other than these primitives,
 354  * not even by data dependencies.  See the documentation for
 355  * memory_barrier() for examples and URLs to more information.
 356  *
 357  * For example, the following code would force ordering (the initial
 358  * value of "a" is zero, "b" is one, and "p" is "&a"):
 359  *
 360  * <programlisting>
 361  *      CPU 0                           CPU 1
 362  *
 363  *      b = 2;
 364  *      memory_barrier();
 365  *      p = &b;                         q = p;
 366  *                                      read_barrier_depends();
 367  *                                      d = *q;
 368  * </programlisting>
 369  *
 370  * because the read of "*q" depends on the read of "p" and these
 371  * two reads are separated by a read_barrier_depends().  However,
 372  * the following code, with the same initial values for "a" and "b":
 373  *
 374  * <programlisting>
 375  *      CPU 0                           CPU 1
 376  *
 377  *      a = 2;
 378  *      memory_barrier();
 379  *      b = 3;                          y = b;
 380  *                                      read_barrier_depends();
 381  *                                      x = a;
 382  * </programlisting>
 383  *
 384  * does not enforce ordering, since there is no data dependency between
 385  * the read of "a" and the read of "b".  Therefore, on some CPUs, such
 386  * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
 387  * in cases like this where there are no data dependencies.
 388  **/
 389
 390 #define read_barrier_depends()  do { } while (0)
 391
 392 #ifdef CONFIG_SMP
 393 #define smp_mb()        mb()
 394 #ifdef CONFIG_X86_PPRO_FENCE
 395 # define smp_rmb()      rmb()
 396 #else
 397 # define smp_rmb()      barrier()
 398 #endif
 399 #ifdef CONFIG_X86_OOSTORE
 400 # define smp_wmb()      wmb()
 401 #else
 402 # define smp_wmb()      barrier()
 403 #endif
 404 #define smp_read_barrier_depends()      read_barrier_depends()
 405 #define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
 406 #else
 407 #define smp_mb()        barrier()
 408 #define smp_rmb()       barrier()
 409 #define smp_wmb()       barrier()
 410 #define smp_read_barrier_depends()      do { } while (0)
 411 #define set_mb(var, value) do { var = value; barrier(); } while (0)
 412 #endif
 413
 414 /*
 415  * Stop RDTSC speculation. This is needed when you need to use RDTSC
 416  * (or get_cycles or vread that possibly accesses the TSC) in a defined
 417  * code region.
 418  *
 419  * (Could use an alternative three way for this if there was one.)
 420  */
 421 static inline void rdtsc_barrier(void)
 422 {
 423         alternative(ASM_NOP3, "mfence", X86_FEATURE_MFENCE_RDTSC);
 424         alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
 425 }
 426
 427 #endif /* _ASM_X86_SYSTEM_H */