4 * Copyright (C) 2007 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
16 #include <linux/sh_dma.h>
17 #include <linux/sh_timer.h>
19 #include <asm/mmzone.h>
21 #include <cpu/dma-register.h>
23 static struct plat_sci_port scif0_platform_data
= {
24 .mapbase
= 0xffea0000,
25 .flags
= UPF_BOOT_AUTOCONF
,
26 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_CKE1
,
27 .scbrr_algo_id
= SCBRR_ALGO_1
,
29 .irqs
= { 40, 40, 40, 40 },
32 static struct platform_device scif0_device
= {
36 .platform_data
= &scif0_platform_data
,
40 static struct plat_sci_port scif1_platform_data
= {
41 .mapbase
= 0xffeb0000,
42 .flags
= UPF_BOOT_AUTOCONF
,
43 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_CKE1
,
44 .scbrr_algo_id
= SCBRR_ALGO_1
,
46 .irqs
= { 44, 44, 44, 44 },
49 static struct platform_device scif1_device
= {
53 .platform_data
= &scif1_platform_data
,
57 static struct plat_sci_port scif2_platform_data
= {
58 .mapbase
= 0xffec0000,
59 .flags
= UPF_BOOT_AUTOCONF
,
60 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_CKE1
,
61 .scbrr_algo_id
= SCBRR_ALGO_1
,
63 .irqs
= { 60, 60, 60, 60 },
66 static struct platform_device scif2_device
= {
70 .platform_data
= &scif2_platform_data
,
74 static struct plat_sci_port scif3_platform_data
= {
75 .mapbase
= 0xffed0000,
76 .flags
= UPF_BOOT_AUTOCONF
,
77 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_CKE1
,
78 .scbrr_algo_id
= SCBRR_ALGO_1
,
80 .irqs
= { 61, 61, 61, 61 },
83 static struct platform_device scif3_device
= {
87 .platform_data
= &scif3_platform_data
,
91 static struct plat_sci_port scif4_platform_data
= {
92 .mapbase
= 0xffee0000,
93 .flags
= UPF_BOOT_AUTOCONF
,
94 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_CKE1
,
95 .scbrr_algo_id
= SCBRR_ALGO_1
,
97 .irqs
= { 62, 62, 62, 62 },
100 static struct platform_device scif4_device
= {
104 .platform_data
= &scif4_platform_data
,
108 static struct plat_sci_port scif5_platform_data
= {
109 .mapbase
= 0xffef0000,
110 .flags
= UPF_BOOT_AUTOCONF
,
111 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_CKE1
,
112 .scbrr_algo_id
= SCBRR_ALGO_1
,
114 .irqs
= { 63, 63, 63, 63 },
117 static struct platform_device scif5_device
= {
121 .platform_data
= &scif5_platform_data
,
125 static struct sh_timer_config tmu0_platform_data
= {
126 .channel_offset
= 0x04,
128 .clockevent_rating
= 200,
131 static struct resource tmu0_resources
[] = {
135 .flags
= IORESOURCE_MEM
,
139 .flags
= IORESOURCE_IRQ
,
143 static struct platform_device tmu0_device
= {
147 .platform_data
= &tmu0_platform_data
,
149 .resource
= tmu0_resources
,
150 .num_resources
= ARRAY_SIZE(tmu0_resources
),
153 static struct sh_timer_config tmu1_platform_data
= {
154 .channel_offset
= 0x10,
156 .clocksource_rating
= 200,
159 static struct resource tmu1_resources
[] = {
163 .flags
= IORESOURCE_MEM
,
167 .flags
= IORESOURCE_IRQ
,
171 static struct platform_device tmu1_device
= {
175 .platform_data
= &tmu1_platform_data
,
177 .resource
= tmu1_resources
,
178 .num_resources
= ARRAY_SIZE(tmu1_resources
),
181 static struct sh_timer_config tmu2_platform_data
= {
182 .channel_offset
= 0x1c,
186 static struct resource tmu2_resources
[] = {
190 .flags
= IORESOURCE_MEM
,
194 .flags
= IORESOURCE_IRQ
,
198 static struct platform_device tmu2_device
= {
202 .platform_data
= &tmu2_platform_data
,
204 .resource
= tmu2_resources
,
205 .num_resources
= ARRAY_SIZE(tmu2_resources
),
208 static struct sh_timer_config tmu3_platform_data
= {
209 .channel_offset
= 0x04,
213 static struct resource tmu3_resources
[] = {
217 .flags
= IORESOURCE_MEM
,
221 .flags
= IORESOURCE_IRQ
,
225 static struct platform_device tmu3_device
= {
229 .platform_data
= &tmu3_platform_data
,
231 .resource
= tmu3_resources
,
232 .num_resources
= ARRAY_SIZE(tmu3_resources
),
235 static struct sh_timer_config tmu4_platform_data
= {
236 .channel_offset
= 0x10,
240 static struct resource tmu4_resources
[] = {
244 .flags
= IORESOURCE_MEM
,
248 .flags
= IORESOURCE_IRQ
,
252 static struct platform_device tmu4_device
= {
256 .platform_data
= &tmu4_platform_data
,
258 .resource
= tmu4_resources
,
259 .num_resources
= ARRAY_SIZE(tmu4_resources
),
262 static struct sh_timer_config tmu5_platform_data
= {
263 .channel_offset
= 0x1c,
267 static struct resource tmu5_resources
[] = {
271 .flags
= IORESOURCE_MEM
,
275 .flags
= IORESOURCE_IRQ
,
279 static struct platform_device tmu5_device
= {
283 .platform_data
= &tmu5_platform_data
,
285 .resource
= tmu5_resources
,
286 .num_resources
= ARRAY_SIZE(tmu5_resources
),
290 static const struct sh_dmae_channel sh7785_dmae0_channels
[] = {
318 static const struct sh_dmae_channel sh7785_dmae1_channels
[] = {
334 static const unsigned int ts_shift
[] = TS_SHIFT
;
336 static struct sh_dmae_pdata dma0_platform_data
= {
337 .channel
= sh7785_dmae0_channels
,
338 .channel_num
= ARRAY_SIZE(sh7785_dmae0_channels
),
339 .ts_low_shift
= CHCR_TS_LOW_SHIFT
,
340 .ts_low_mask
= CHCR_TS_LOW_MASK
,
341 .ts_high_shift
= CHCR_TS_HIGH_SHIFT
,
342 .ts_high_mask
= CHCR_TS_HIGH_MASK
,
343 .ts_shift
= ts_shift
,
344 .ts_shift_num
= ARRAY_SIZE(ts_shift
),
345 .dmaor_init
= DMAOR_INIT
,
348 static struct sh_dmae_pdata dma1_platform_data
= {
349 .channel
= sh7785_dmae1_channels
,
350 .channel_num
= ARRAY_SIZE(sh7785_dmae1_channels
),
351 .ts_low_shift
= CHCR_TS_LOW_SHIFT
,
352 .ts_low_mask
= CHCR_TS_LOW_MASK
,
353 .ts_high_shift
= CHCR_TS_HIGH_SHIFT
,
354 .ts_high_mask
= CHCR_TS_HIGH_MASK
,
355 .ts_shift
= ts_shift
,
356 .ts_shift_num
= ARRAY_SIZE(ts_shift
),
357 .dmaor_init
= DMAOR_INIT
,
360 static struct resource sh7785_dmae0_resources
[] = {
362 /* Channel registers and DMAOR */
365 .flags
= IORESOURCE_MEM
,
371 .flags
= IORESOURCE_MEM
,
374 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
377 .flags
= IORESOURCE_IRQ
| IORESOURCE_IRQ_SHAREABLE
,
381 static struct resource sh7785_dmae1_resources
[] = {
383 /* Channel registers and DMAOR */
386 .flags
= IORESOURCE_MEM
,
388 /* DMAC1 has no DMARS */
390 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
393 .flags
= IORESOURCE_IRQ
| IORESOURCE_IRQ_SHAREABLE
,
397 static struct platform_device dma0_device
= {
398 .name
= "sh-dma-engine",
400 .resource
= sh7785_dmae0_resources
,
401 .num_resources
= ARRAY_SIZE(sh7785_dmae0_resources
),
403 .platform_data
= &dma0_platform_data
,
407 static struct platform_device dma1_device
= {
408 .name
= "sh-dma-engine",
410 .resource
= sh7785_dmae1_resources
,
411 .num_resources
= ARRAY_SIZE(sh7785_dmae1_resources
),
413 .platform_data
= &dma1_platform_data
,
417 static struct platform_device
*sh7785_devices
[] __initdata
= {
434 static int __init
sh7785_devices_setup(void)
436 return platform_add_devices(sh7785_devices
,
437 ARRAY_SIZE(sh7785_devices
));
439 arch_initcall(sh7785_devices_setup
);
441 static struct platform_device
*sh7785_early_devices
[] __initdata
= {
456 void __init
plat_early_device_setup(void)
458 early_platform_add_devices(sh7785_early_devices
,
459 ARRAY_SIZE(sh7785_early_devices
));
465 /* interrupt sources */
467 IRL0_LLLL
, IRL0_LLLH
, IRL0_LLHL
, IRL0_LLHH
,
468 IRL0_LHLL
, IRL0_LHLH
, IRL0_LHHL
, IRL0_LHHH
,
469 IRL0_HLLL
, IRL0_HLLH
, IRL0_HLHL
, IRL0_HLHH
,
470 IRL0_HHLL
, IRL0_HHLH
, IRL0_HHHL
,
472 IRL4_LLLL
, IRL4_LLLH
, IRL4_LLHL
, IRL4_LLHH
,
473 IRL4_LHLL
, IRL4_LHLH
, IRL4_LHHL
, IRL4_LHHH
,
474 IRL4_HLLL
, IRL4_HLLH
, IRL4_HLHL
, IRL4_HLHH
,
475 IRL4_HHLL
, IRL4_HHLH
, IRL4_HHHL
,
477 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
478 WDT
, TMU0
, TMU1
, TMU2
, TMU2_TICPI
,
479 HUDI
, DMAC0
, SCIF0
, SCIF1
, DMAC1
, HSPI
,
480 SCIF2
, SCIF3
, SCIF4
, SCIF5
,
481 PCISERR
, PCIINTA
, PCIINTB
, PCIINTC
, PCIINTD
, PCIC5
,
482 SIOF
, MMCIF
, DU
, GDTA
,
488 /* interrupt groups */
493 static struct intc_vect vectors
[] __initdata
= {
494 INTC_VECT(WDT
, 0x560),
495 INTC_VECT(TMU0
, 0x580), INTC_VECT(TMU1
, 0x5a0),
496 INTC_VECT(TMU2
, 0x5c0), INTC_VECT(TMU2_TICPI
, 0x5e0),
497 INTC_VECT(HUDI
, 0x600),
498 INTC_VECT(DMAC0
, 0x620), INTC_VECT(DMAC0
, 0x640),
499 INTC_VECT(DMAC0
, 0x660), INTC_VECT(DMAC0
, 0x680),
500 INTC_VECT(DMAC0
, 0x6a0), INTC_VECT(DMAC0
, 0x6c0),
501 INTC_VECT(DMAC0
, 0x6e0),
502 INTC_VECT(SCIF0
, 0x700), INTC_VECT(SCIF0
, 0x720),
503 INTC_VECT(SCIF0
, 0x740), INTC_VECT(SCIF0
, 0x760),
504 INTC_VECT(SCIF1
, 0x780), INTC_VECT(SCIF1
, 0x7a0),
505 INTC_VECT(SCIF1
, 0x7c0), INTC_VECT(SCIF1
, 0x7e0),
506 INTC_VECT(DMAC1
, 0x880), INTC_VECT(DMAC1
, 0x8a0),
507 INTC_VECT(DMAC1
, 0x8c0), INTC_VECT(DMAC1
, 0x8e0),
508 INTC_VECT(DMAC1
, 0x900), INTC_VECT(DMAC1
, 0x920),
509 INTC_VECT(DMAC1
, 0x940),
510 INTC_VECT(HSPI
, 0x960),
511 INTC_VECT(SCIF2
, 0x980), INTC_VECT(SCIF3
, 0x9a0),
512 INTC_VECT(SCIF4
, 0x9c0), INTC_VECT(SCIF5
, 0x9e0),
513 INTC_VECT(PCISERR
, 0xa00), INTC_VECT(PCIINTA
, 0xa20),
514 INTC_VECT(PCIINTB
, 0xa40), INTC_VECT(PCIINTC
, 0xa60),
515 INTC_VECT(PCIINTD
, 0xa80), INTC_VECT(PCIC5
, 0xaa0),
516 INTC_VECT(PCIC5
, 0xac0), INTC_VECT(PCIC5
, 0xae0),
517 INTC_VECT(PCIC5
, 0xb00), INTC_VECT(PCIC5
, 0xb20),
518 INTC_VECT(SIOF
, 0xc00),
519 INTC_VECT(MMCIF
, 0xd00), INTC_VECT(MMCIF
, 0xd20),
520 INTC_VECT(MMCIF
, 0xd40), INTC_VECT(MMCIF
, 0xd60),
521 INTC_VECT(DU
, 0xd80),
522 INTC_VECT(GDTA
, 0xda0), INTC_VECT(GDTA
, 0xdc0),
523 INTC_VECT(GDTA
, 0xde0),
524 INTC_VECT(TMU3
, 0xe00), INTC_VECT(TMU4
, 0xe20),
525 INTC_VECT(TMU5
, 0xe40),
526 INTC_VECT(SSI0
, 0xe80), INTC_VECT(SSI1
, 0xea0),
527 INTC_VECT(HAC0
, 0xec0), INTC_VECT(HAC1
, 0xee0),
528 INTC_VECT(FLCTL
, 0xf00), INTC_VECT(FLCTL
, 0xf20),
529 INTC_VECT(FLCTL
, 0xf40), INTC_VECT(FLCTL
, 0xf60),
530 INTC_VECT(GPIO
, 0xf80), INTC_VECT(GPIO
, 0xfa0),
531 INTC_VECT(GPIO
, 0xfc0), INTC_VECT(GPIO
, 0xfe0),
534 static struct intc_group groups
[] __initdata
= {
535 INTC_GROUP(TMU012
, TMU0
, TMU1
, TMU2
, TMU2_TICPI
),
536 INTC_GROUP(TMU345
, TMU3
, TMU4
, TMU5
),
539 static struct intc_mask_reg mask_registers
[] __initdata
= {
540 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
541 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
543 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
544 { IRL0_LLLL
, IRL0_LLLH
, IRL0_LLHL
, IRL0_LLHH
,
545 IRL0_LHLL
, IRL0_LHLH
, IRL0_LHHL
, IRL0_LHHH
,
546 IRL0_HLLL
, IRL0_HLLH
, IRL0_HLHL
, IRL0_HLHH
,
547 IRL0_HHLL
, IRL0_HHLH
, IRL0_HHHL
, 0,
548 IRL4_LLLL
, IRL4_LLLH
, IRL4_LLHL
, IRL4_LLHH
,
549 IRL4_LHLL
, IRL4_LHLH
, IRL4_LHHL
, IRL4_LHHH
,
550 IRL4_HLLL
, IRL4_HLLH
, IRL4_HLHL
, IRL4_HLHH
,
551 IRL4_HHLL
, IRL4_HHLH
, IRL4_HHHL
, 0, } },
553 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
554 { 0, 0, 0, GDTA
, DU
, SSI0
, SSI1
, GPIO
,
555 FLCTL
, MMCIF
, HSPI
, SIOF
, PCIC5
, PCIINTD
, PCIINTC
, PCIINTB
,
556 PCIINTA
, PCISERR
, HAC1
, HAC0
, DMAC1
, DMAC0
, HUDI
, WDT
,
557 SCIF5
, SCIF4
, SCIF3
, SCIF2
, SCIF1
, SCIF0
, TMU345
, TMU012
} },
560 static struct intc_prio_reg prio_registers
[] __initdata
= {
561 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
,
562 IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
563 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0
, TMU1
,
564 TMU2
, TMU2_TICPI
} },
565 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3
, TMU4
, TMU5
, } },
566 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0
, SCIF1
,
568 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4
, SCIF5
, WDT
, } },
569 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI
, DMAC0
, DMAC1
, } },
570 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0
, HAC1
,
571 PCISERR
, PCIINTA
} },
572 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB
, PCIINTC
,
574 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF
, HSPI
, MMCIF
, } },
575 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL
, GPIO
, SSI0
, SSI1
, } },
576 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU
, GDTA
, } },
579 static DECLARE_INTC_DESC(intc_desc
, "sh7785", vectors
, groups
,
580 mask_registers
, prio_registers
, NULL
);
582 /* Support for external interrupt pins in IRQ mode */
584 static struct intc_vect vectors_irq0123
[] __initdata
= {
585 INTC_VECT(IRQ0
, 0x240), INTC_VECT(IRQ1
, 0x280),
586 INTC_VECT(IRQ2
, 0x2c0), INTC_VECT(IRQ3
, 0x300),
589 static struct intc_vect vectors_irq4567
[] __initdata
= {
590 INTC_VECT(IRQ4
, 0x340), INTC_VECT(IRQ5
, 0x380),
591 INTC_VECT(IRQ6
, 0x3c0), INTC_VECT(IRQ7
, 0x200),
594 static struct intc_sense_reg sense_registers
[] __initdata
= {
595 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
,
596 IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
599 static struct intc_mask_reg ack_registers
[] __initdata
= {
600 { 0xffd00024, 0, 32, /* INTREQ */
601 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
604 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123
, "sh7785-irq0123",
605 vectors_irq0123
, NULL
, mask_registers
,
606 prio_registers
, sense_registers
, ack_registers
);
608 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567
, "sh7785-irq4567",
609 vectors_irq4567
, NULL
, mask_registers
,
610 prio_registers
, sense_registers
, ack_registers
);
612 /* External interrupt pins in IRL mode */
614 static struct intc_vect vectors_irl0123
[] __initdata
= {
615 INTC_VECT(IRL0_LLLL
, 0x200), INTC_VECT(IRL0_LLLH
, 0x220),
616 INTC_VECT(IRL0_LLHL
, 0x240), INTC_VECT(IRL0_LLHH
, 0x260),
617 INTC_VECT(IRL0_LHLL
, 0x280), INTC_VECT(IRL0_LHLH
, 0x2a0),
618 INTC_VECT(IRL0_LHHL
, 0x2c0), INTC_VECT(IRL0_LHHH
, 0x2e0),
619 INTC_VECT(IRL0_HLLL
, 0x300), INTC_VECT(IRL0_HLLH
, 0x320),
620 INTC_VECT(IRL0_HLHL
, 0x340), INTC_VECT(IRL0_HLHH
, 0x360),
621 INTC_VECT(IRL0_HHLL
, 0x380), INTC_VECT(IRL0_HHLH
, 0x3a0),
622 INTC_VECT(IRL0_HHHL
, 0x3c0),
625 static struct intc_vect vectors_irl4567
[] __initdata
= {
626 INTC_VECT(IRL4_LLLL
, 0xb00), INTC_VECT(IRL4_LLLH
, 0xb20),
627 INTC_VECT(IRL4_LLHL
, 0xb40), INTC_VECT(IRL4_LLHH
, 0xb60),
628 INTC_VECT(IRL4_LHLL
, 0xb80), INTC_VECT(IRL4_LHLH
, 0xba0),
629 INTC_VECT(IRL4_LHHL
, 0xbc0), INTC_VECT(IRL4_LHHH
, 0xbe0),
630 INTC_VECT(IRL4_HLLL
, 0xc00), INTC_VECT(IRL4_HLLH
, 0xc20),
631 INTC_VECT(IRL4_HLHL
, 0xc40), INTC_VECT(IRL4_HLHH
, 0xc60),
632 INTC_VECT(IRL4_HHLL
, 0xc80), INTC_VECT(IRL4_HHLH
, 0xca0),
633 INTC_VECT(IRL4_HHHL
, 0xcc0),
636 static DECLARE_INTC_DESC(intc_desc_irl0123
, "sh7785-irl0123", vectors_irl0123
,
637 NULL
, mask_registers
, NULL
, NULL
);
639 static DECLARE_INTC_DESC(intc_desc_irl4567
, "sh7785-irl4567", vectors_irl4567
,
640 NULL
, mask_registers
, NULL
, NULL
);
642 #define INTC_ICR0 0xffd00000
643 #define INTC_INTMSK0 0xffd00044
644 #define INTC_INTMSK1 0xffd00048
645 #define INTC_INTMSK2 0xffd40080
646 #define INTC_INTMSKCLR1 0xffd00068
647 #define INTC_INTMSKCLR2 0xffd40084
649 void __init
plat_irq_setup(void)
651 /* disable IRQ3-0 + IRQ7-4 */
652 __raw_writel(0xff000000, INTC_INTMSK0
);
654 /* disable IRL3-0 + IRL7-4 */
655 __raw_writel(0xc0000000, INTC_INTMSK1
);
656 __raw_writel(0xfffefffe, INTC_INTMSK2
);
658 /* select IRL mode for IRL3-0 + IRL7-4 */
659 __raw_writel(__raw_readl(INTC_ICR0
) & ~0x00c00000, INTC_ICR0
);
661 /* disable holding function, ie enable "SH-4 Mode" */
662 __raw_writel(__raw_readl(INTC_ICR0
) | 0x00200000, INTC_ICR0
);
664 register_intc_controller(&intc_desc
);
667 void __init
plat_irq_setup_pins(int mode
)
670 case IRQ_MODE_IRQ7654
:
671 /* select IRQ mode for IRL7-4 */
672 __raw_writel(__raw_readl(INTC_ICR0
) | 0x00400000, INTC_ICR0
);
673 register_intc_controller(&intc_desc_irq4567
);
675 case IRQ_MODE_IRQ3210
:
676 /* select IRQ mode for IRL3-0 */
677 __raw_writel(__raw_readl(INTC_ICR0
) | 0x00800000, INTC_ICR0
);
678 register_intc_controller(&intc_desc_irq0123
);
680 case IRQ_MODE_IRL7654
:
681 /* enable IRL7-4 but don't provide any masking */
682 __raw_writel(0x40000000, INTC_INTMSKCLR1
);
683 __raw_writel(0x0000fffe, INTC_INTMSKCLR2
);
685 case IRQ_MODE_IRL3210
:
686 /* enable IRL0-3 but don't provide any masking */
687 __raw_writel(0x80000000, INTC_INTMSKCLR1
);
688 __raw_writel(0xfffe0000, INTC_INTMSKCLR2
);
690 case IRQ_MODE_IRL7654_MASK
:
691 /* enable IRL7-4 and mask using cpu intc controller */
692 __raw_writel(0x40000000, INTC_INTMSKCLR1
);
693 register_intc_controller(&intc_desc_irl4567
);
695 case IRQ_MODE_IRL3210_MASK
:
696 /* enable IRL0-3 and mask using cpu intc controller */
697 __raw_writel(0x80000000, INTC_INTMSKCLR1
);
698 register_intc_controller(&intc_desc_irl0123
);
705 void __init
plat_mem_setup(void)
707 /* Register the URAM space as Node 1 */
708 setup_bootmem_node(1, 0xe55f0000, 0xe5610000);