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Merge branch 'for-linus' of git://git.kernel.dk/linux-block
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / s390 / include / asm / pgtable.h
1 /*
2 * S390 version
3 * Copyright IBM Corp. 1999, 2000
4 * Author(s): Hartmut Penner (hp@de.ibm.com)
5 * Ulrich Weigand (weigand@de.ibm.com)
6 * Martin Schwidefsky (schwidefsky@de.ibm.com)
7 *
8 * Derived from "include/asm-i386/pgtable.h"
9 */
10
11 #ifndef _ASM_S390_PGTABLE_H
12 #define _ASM_S390_PGTABLE_H
13
14 /*
15 * The Linux memory management assumes a three-level page table setup. For
16 * s390 31 bit we "fold" the mid level into the top-level page table, so
17 * that we physically have the same two-level page table as the s390 mmu
18 * expects in 31 bit mode. For s390 64 bit we use three of the five levels
19 * the hardware provides (region first and region second tables are not
20 * used).
21 *
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
24 * into the pgd entry)
25 *
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
28 */
29 #ifndef __ASSEMBLY__
30 #include <linux/sched.h>
31 #include <linux/mm_types.h>
32 #include <linux/page-flags.h>
33 #include <asm/bug.h>
34 #include <asm/page.h>
35
36 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
37 extern void paging_init(void);
38 extern void vmem_map_init(void);
39
40 /*
41 * The S390 doesn't have any external MMU info: the kernel page
42 * tables contain all the necessary information.
43 */
44 #define update_mmu_cache(vma, address, ptep) do { } while (0)
45 #define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
46
47 /*
48 * ZERO_PAGE is a global shared page that is always zero; used
49 * for zero-mapped memory areas etc..
50 */
51
52 extern unsigned long empty_zero_page;
53 extern unsigned long zero_page_mask;
54
55 #define ZERO_PAGE(vaddr) \
56 (virt_to_page((void *)(empty_zero_page + \
57 (((unsigned long)(vaddr)) &zero_page_mask))))
58 #define __HAVE_COLOR_ZERO_PAGE
59
60 /* TODO: s390 cannot support io_remap_pfn_range... */
61 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
62 remap_pfn_range(vma, vaddr, pfn, size, prot)
63
64 #endif /* !__ASSEMBLY__ */
65
66 /*
67 * PMD_SHIFT determines the size of the area a second-level page
68 * table can map
69 * PGDIR_SHIFT determines what a third-level page table entry can map
70 */
71 #ifndef CONFIG_64BIT
72 # define PMD_SHIFT 20
73 # define PUD_SHIFT 20
74 # define PGDIR_SHIFT 20
75 #else /* CONFIG_64BIT */
76 # define PMD_SHIFT 20
77 # define PUD_SHIFT 31
78 # define PGDIR_SHIFT 42
79 #endif /* CONFIG_64BIT */
80
81 #define PMD_SIZE (1UL << PMD_SHIFT)
82 #define PMD_MASK (~(PMD_SIZE-1))
83 #define PUD_SIZE (1UL << PUD_SHIFT)
84 #define PUD_MASK (~(PUD_SIZE-1))
85 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
86 #define PGDIR_MASK (~(PGDIR_SIZE-1))
87
88 /*
89 * entries per page directory level: the S390 is two-level, so
90 * we don't really have any PMD directory physically.
91 * for S390 segment-table entries are combined to one PGD
92 * that leads to 1024 pte per pgd
93 */
94 #define PTRS_PER_PTE 256
95 #ifndef CONFIG_64BIT
96 #define PTRS_PER_PMD 1
97 #define PTRS_PER_PUD 1
98 #else /* CONFIG_64BIT */
99 #define PTRS_PER_PMD 2048
100 #define PTRS_PER_PUD 2048
101 #endif /* CONFIG_64BIT */
102 #define PTRS_PER_PGD 2048
103
104 #define FIRST_USER_ADDRESS 0
105
106 #define pte_ERROR(e) \
107 printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
108 #define pmd_ERROR(e) \
109 printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
110 #define pud_ERROR(e) \
111 printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
112 #define pgd_ERROR(e) \
113 printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
114
115 #ifndef __ASSEMBLY__
116 /*
117 * The vmalloc and module area will always be on the topmost area of the kernel
118 * mapping. We reserve 96MB (31bit) / 128GB (64bit) for vmalloc and modules.
119 * On 64 bit kernels we have a 2GB area at the top of the vmalloc area where
120 * modules will reside. That makes sure that inter module branches always
121 * happen without trampolines and in addition the placement within a 2GB frame
122 * is branch prediction unit friendly.
123 */
124 extern unsigned long VMALLOC_START;
125 extern unsigned long VMALLOC_END;
126 extern struct page *vmemmap;
127
128 #define VMEM_MAX_PHYS ((unsigned long) vmemmap)
129
130 #ifdef CONFIG_64BIT
131 extern unsigned long MODULES_VADDR;
132 extern unsigned long MODULES_END;
133 #define MODULES_VADDR MODULES_VADDR
134 #define MODULES_END MODULES_END
135 #define MODULES_LEN (1UL << 31)
136 #endif
137
138 /*
139 * A 31 bit pagetable entry of S390 has following format:
140 * | PFRA | | OS |
141 * 0 0IP0
142 * 00000000001111111111222222222233
143 * 01234567890123456789012345678901
144 *
145 * I Page-Invalid Bit: Page is not available for address-translation
146 * P Page-Protection Bit: Store access not possible for page
147 *
148 * A 31 bit segmenttable entry of S390 has following format:
149 * | P-table origin | |PTL
150 * 0 IC
151 * 00000000001111111111222222222233
152 * 01234567890123456789012345678901
153 *
154 * I Segment-Invalid Bit: Segment is not available for address-translation
155 * C Common-Segment Bit: Segment is not private (PoP 3-30)
156 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
157 *
158 * The 31 bit segmenttable origin of S390 has following format:
159 *
160 * |S-table origin | | STL |
161 * X **GPS
162 * 00000000001111111111222222222233
163 * 01234567890123456789012345678901
164 *
165 * X Space-Switch event:
166 * G Segment-Invalid Bit: *
167 * P Private-Space Bit: Segment is not private (PoP 3-30)
168 * S Storage-Alteration:
169 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
170 *
171 * A 64 bit pagetable entry of S390 has following format:
172 * | PFRA |0IPC| OS |
173 * 0000000000111111111122222222223333333333444444444455555555556666
174 * 0123456789012345678901234567890123456789012345678901234567890123
175 *
176 * I Page-Invalid Bit: Page is not available for address-translation
177 * P Page-Protection Bit: Store access not possible for page
178 * C Change-bit override: HW is not required to set change bit
179 *
180 * A 64 bit segmenttable entry of S390 has following format:
181 * | P-table origin | TT
182 * 0000000000111111111122222222223333333333444444444455555555556666
183 * 0123456789012345678901234567890123456789012345678901234567890123
184 *
185 * I Segment-Invalid Bit: Segment is not available for address-translation
186 * C Common-Segment Bit: Segment is not private (PoP 3-30)
187 * P Page-Protection Bit: Store access not possible for page
188 * TT Type 00
189 *
190 * A 64 bit region table entry of S390 has following format:
191 * | S-table origin | TF TTTL
192 * 0000000000111111111122222222223333333333444444444455555555556666
193 * 0123456789012345678901234567890123456789012345678901234567890123
194 *
195 * I Segment-Invalid Bit: Segment is not available for address-translation
196 * TT Type 01
197 * TF
198 * TL Table length
199 *
200 * The 64 bit regiontable origin of S390 has following format:
201 * | region table origon | DTTL
202 * 0000000000111111111122222222223333333333444444444455555555556666
203 * 0123456789012345678901234567890123456789012345678901234567890123
204 *
205 * X Space-Switch event:
206 * G Segment-Invalid Bit:
207 * P Private-Space Bit:
208 * S Storage-Alteration:
209 * R Real space
210 * TL Table-Length:
211 *
212 * A storage key has the following format:
213 * | ACC |F|R|C|0|
214 * 0 3 4 5 6 7
215 * ACC: access key
216 * F : fetch protection bit
217 * R : referenced bit
218 * C : changed bit
219 */
220
221 /* Hardware bits in the page table entry */
222 #define _PAGE_CO 0x100 /* HW Change-bit override */
223 #define _PAGE_RO 0x200 /* HW read-only bit */
224 #define _PAGE_INVALID 0x400 /* HW invalid bit */
225
226 /* Software bits in the page table entry */
227 #define _PAGE_SWT 0x001 /* SW pte type bit t */
228 #define _PAGE_SWX 0x002 /* SW pte type bit x */
229 #define _PAGE_SWC 0x004 /* SW pte changed bit */
230 #define _PAGE_SWR 0x008 /* SW pte referenced bit */
231 #define _PAGE_SWW 0x010 /* SW pte write bit */
232 #define _PAGE_SPECIAL 0x020 /* SW associated with special page */
233 #define __HAVE_ARCH_PTE_SPECIAL
234
235 /* Set of bits not changed in pte_modify */
236 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_CO | \
237 _PAGE_SWC | _PAGE_SWR)
238
239 /* Six different types of pages. */
240 #define _PAGE_TYPE_EMPTY 0x400
241 #define _PAGE_TYPE_NONE 0x401
242 #define _PAGE_TYPE_SWAP 0x403
243 #define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */
244 #define _PAGE_TYPE_RO 0x200
245 #define _PAGE_TYPE_RW 0x000
246
247 /*
248 * Only four types for huge pages, using the invalid bit and protection bit
249 * of a segment table entry.
250 */
251 #define _HPAGE_TYPE_EMPTY 0x020 /* _SEGMENT_ENTRY_INV */
252 #define _HPAGE_TYPE_NONE 0x220
253 #define _HPAGE_TYPE_RO 0x200 /* _SEGMENT_ENTRY_RO */
254 #define _HPAGE_TYPE_RW 0x000
255
256 /*
257 * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
258 * pte_none and pte_file to find out the pte type WITHOUT holding the page
259 * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
260 * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
261 * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
262 * This change is done while holding the lock, but the intermediate step
263 * of a previously valid pte with the hw invalid bit set can be observed by
264 * handle_pte_fault. That makes it necessary that all valid pte types with
265 * the hw invalid bit set must be distinguishable from the four pte types
266 * empty, none, swap and file.
267 *
268 * irxt ipte irxt
269 * _PAGE_TYPE_EMPTY 1000 -> 1000
270 * _PAGE_TYPE_NONE 1001 -> 1001
271 * _PAGE_TYPE_SWAP 1011 -> 1011
272 * _PAGE_TYPE_FILE 11?1 -> 11?1
273 * _PAGE_TYPE_RO 0100 -> 1100
274 * _PAGE_TYPE_RW 0000 -> 1000
275 *
276 * pte_none is true for bits combinations 1000, 1010, 1100, 1110
277 * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
278 * pte_file is true for bits combinations 1101, 1111
279 * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
280 */
281
282 #ifndef CONFIG_64BIT
283
284 /* Bits in the segment table address-space-control-element */
285 #define _ASCE_SPACE_SWITCH 0x80000000UL /* space switch event */
286 #define _ASCE_ORIGIN_MASK 0x7ffff000UL /* segment table origin */
287 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
288 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
289 #define _ASCE_TABLE_LENGTH 0x7f /* 128 x 64 entries = 8k */
290
291 /* Bits in the segment table entry */
292 #define _SEGMENT_ENTRY_ORIGIN 0x7fffffc0UL /* page table origin */
293 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
294 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
295 #define _SEGMENT_ENTRY_COMMON 0x10 /* common segment bit */
296 #define _SEGMENT_ENTRY_PTL 0x0f /* page table length */
297
298 #define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PTL)
299 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
300
301 /* Page status table bits for virtualization */
302 #define RCP_ACC_BITS 0xf0000000UL
303 #define RCP_FP_BIT 0x08000000UL
304 #define RCP_PCL_BIT 0x00800000UL
305 #define RCP_HR_BIT 0x00400000UL
306 #define RCP_HC_BIT 0x00200000UL
307 #define RCP_GR_BIT 0x00040000UL
308 #define RCP_GC_BIT 0x00020000UL
309 #define RCP_IN_BIT 0x00002000UL /* IPTE notify bit */
310
311 /* User dirty / referenced bit for KVM's migration feature */
312 #define KVM_UR_BIT 0x00008000UL
313 #define KVM_UC_BIT 0x00004000UL
314
315 #else /* CONFIG_64BIT */
316
317 /* Bits in the segment/region table address-space-control-element */
318 #define _ASCE_ORIGIN ~0xfffUL/* segment table origin */
319 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
320 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
321 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
322 #define _ASCE_REAL_SPACE 0x20 /* real space control */
323 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
324 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
325 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
326 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
327 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
328 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
329
330 /* Bits in the region table entry */
331 #define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
332 #define _REGION_ENTRY_RO 0x200 /* region protection bit */
333 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
334 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
335 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
336 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
337 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
338 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
339
340 #define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
341 #define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
342 #define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
343 #define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
344 #define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
345 #define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)
346
347 #define _REGION3_ENTRY_LARGE 0x400 /* RTTE-format control, large page */
348 #define _REGION3_ENTRY_RO 0x200 /* page protection bit */
349 #define _REGION3_ENTRY_CO 0x100 /* change-recording override */
350
351 /* Bits in the segment table entry */
352 #define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
353 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* segment table origin */
354 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
355 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
356
357 #define _SEGMENT_ENTRY (0)
358 #define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INV)
359
360 #define _SEGMENT_ENTRY_LARGE 0x400 /* STE-format control, large page */
361 #define _SEGMENT_ENTRY_CO 0x100 /* change-recording override */
362 #define _SEGMENT_ENTRY_SPLIT_BIT 0 /* THP splitting bit number */
363 #define _SEGMENT_ENTRY_SPLIT (1UL << _SEGMENT_ENTRY_SPLIT_BIT)
364
365 /* Set of bits not changed in pmd_modify */
366 #define _SEGMENT_CHG_MASK (_SEGMENT_ENTRY_ORIGIN | _SEGMENT_ENTRY_LARGE \
367 | _SEGMENT_ENTRY_SPLIT | _SEGMENT_ENTRY_CO)
368
369 /* Page status table bits for virtualization */
370 #define RCP_ACC_BITS 0xf000000000000000UL
371 #define RCP_FP_BIT 0x0800000000000000UL
372 #define RCP_PCL_BIT 0x0080000000000000UL
373 #define RCP_HR_BIT 0x0040000000000000UL
374 #define RCP_HC_BIT 0x0020000000000000UL
375 #define RCP_GR_BIT 0x0004000000000000UL
376 #define RCP_GC_BIT 0x0002000000000000UL
377 #define RCP_IN_BIT 0x0000200000000000UL /* IPTE notify bit */
378
379 /* User dirty / referenced bit for KVM's migration feature */
380 #define KVM_UR_BIT 0x0000800000000000UL
381 #define KVM_UC_BIT 0x0000400000000000UL
382
383 #endif /* CONFIG_64BIT */
384
385 /*
386 * A user page table pointer has the space-switch-event bit, the
387 * private-space-control bit and the storage-alteration-event-control
388 * bit set. A kernel page table pointer doesn't need them.
389 */
390 #define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
391 _ASCE_ALT_EVENT)
392
393 /*
394 * Page protection definitions.
395 */
396 #define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
397 #define PAGE_RO __pgprot(_PAGE_TYPE_RO)
398 #define PAGE_RW __pgprot(_PAGE_TYPE_RO | _PAGE_SWW)
399 #define PAGE_RWC __pgprot(_PAGE_TYPE_RW | _PAGE_SWW | _PAGE_SWC)
400
401 #define PAGE_KERNEL PAGE_RWC
402 #define PAGE_SHARED PAGE_KERNEL
403 #define PAGE_COPY PAGE_RO
404
405 /*
406 * On s390 the page table entry has an invalid bit and a read-only bit.
407 * Read permission implies execute permission and write permission
408 * implies read permission.
409 */
410 /*xwr*/
411 #define __P000 PAGE_NONE
412 #define __P001 PAGE_RO
413 #define __P010 PAGE_RO
414 #define __P011 PAGE_RO
415 #define __P100 PAGE_RO
416 #define __P101 PAGE_RO
417 #define __P110 PAGE_RO
418 #define __P111 PAGE_RO
419
420 #define __S000 PAGE_NONE
421 #define __S001 PAGE_RO
422 #define __S010 PAGE_RW
423 #define __S011 PAGE_RW
424 #define __S100 PAGE_RO
425 #define __S101 PAGE_RO
426 #define __S110 PAGE_RW
427 #define __S111 PAGE_RW
428
429 /*
430 * Segment entry (large page) protection definitions.
431 */
432 #define SEGMENT_NONE __pgprot(_HPAGE_TYPE_NONE)
433 #define SEGMENT_RO __pgprot(_HPAGE_TYPE_RO)
434 #define SEGMENT_RW __pgprot(_HPAGE_TYPE_RW)
435
436 static inline int mm_exclusive(struct mm_struct *mm)
437 {
438 return likely(mm == current->active_mm &&
439 atomic_read(&mm->context.attach_count) <= 1);
440 }
441
442 static inline int mm_has_pgste(struct mm_struct *mm)
443 {
444 #ifdef CONFIG_PGSTE
445 if (unlikely(mm->context.has_pgste))
446 return 1;
447 #endif
448 return 0;
449 }
450 /*
451 * pgd/pmd/pte query functions
452 */
453 #ifndef CONFIG_64BIT
454
455 static inline int pgd_present(pgd_t pgd) { return 1; }
456 static inline int pgd_none(pgd_t pgd) { return 0; }
457 static inline int pgd_bad(pgd_t pgd) { return 0; }
458
459 static inline int pud_present(pud_t pud) { return 1; }
460 static inline int pud_none(pud_t pud) { return 0; }
461 static inline int pud_large(pud_t pud) { return 0; }
462 static inline int pud_bad(pud_t pud) { return 0; }
463
464 #else /* CONFIG_64BIT */
465
466 static inline int pgd_present(pgd_t pgd)
467 {
468 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
469 return 1;
470 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
471 }
472
473 static inline int pgd_none(pgd_t pgd)
474 {
475 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2)
476 return 0;
477 return (pgd_val(pgd) & _REGION_ENTRY_INV) != 0UL;
478 }
479
480 static inline int pgd_bad(pgd_t pgd)
481 {
482 /*
483 * With dynamic page table levels the pgd can be a region table
484 * entry or a segment table entry. Check for the bit that are
485 * invalid for either table entry.
486 */
487 unsigned long mask =
488 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
489 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
490 return (pgd_val(pgd) & mask) != 0;
491 }
492
493 static inline int pud_present(pud_t pud)
494 {
495 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
496 return 1;
497 return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
498 }
499
500 static inline int pud_none(pud_t pud)
501 {
502 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3)
503 return 0;
504 return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL;
505 }
506
507 static inline int pud_large(pud_t pud)
508 {
509 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
510 return 0;
511 return !!(pud_val(pud) & _REGION3_ENTRY_LARGE);
512 }
513
514 static inline int pud_bad(pud_t pud)
515 {
516 /*
517 * With dynamic page table levels the pud can be a region table
518 * entry or a segment table entry. Check for the bit that are
519 * invalid for either table entry.
520 */
521 unsigned long mask =
522 ~_SEGMENT_ENTRY_ORIGIN & ~_REGION_ENTRY_INV &
523 ~_REGION_ENTRY_TYPE_MASK & ~_REGION_ENTRY_LENGTH;
524 return (pud_val(pud) & mask) != 0;
525 }
526
527 #endif /* CONFIG_64BIT */
528
529 static inline int pmd_present(pmd_t pmd)
530 {
531 unsigned long mask = _SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO;
532 return (pmd_val(pmd) & mask) == _HPAGE_TYPE_NONE ||
533 !(pmd_val(pmd) & _SEGMENT_ENTRY_INV);
534 }
535
536 static inline int pmd_none(pmd_t pmd)
537 {
538 return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) &&
539 !(pmd_val(pmd) & _SEGMENT_ENTRY_RO);
540 }
541
542 static inline int pmd_large(pmd_t pmd)
543 {
544 #ifdef CONFIG_64BIT
545 return !!(pmd_val(pmd) & _SEGMENT_ENTRY_LARGE);
546 #else
547 return 0;
548 #endif
549 }
550
551 static inline int pmd_bad(pmd_t pmd)
552 {
553 unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV;
554 return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
555 }
556
557 #define __HAVE_ARCH_PMDP_SPLITTING_FLUSH
558 extern void pmdp_splitting_flush(struct vm_area_struct *vma,
559 unsigned long addr, pmd_t *pmdp);
560
561 #define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
562 extern int pmdp_set_access_flags(struct vm_area_struct *vma,
563 unsigned long address, pmd_t *pmdp,
564 pmd_t entry, int dirty);
565
566 #define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
567 extern int pmdp_clear_flush_young(struct vm_area_struct *vma,
568 unsigned long address, pmd_t *pmdp);
569
570 #define __HAVE_ARCH_PMD_WRITE
571 static inline int pmd_write(pmd_t pmd)
572 {
573 return (pmd_val(pmd) & _SEGMENT_ENTRY_RO) == 0;
574 }
575
576 static inline int pmd_young(pmd_t pmd)
577 {
578 return 0;
579 }
580
581 static inline int pte_none(pte_t pte)
582 {
583 return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
584 }
585
586 static inline int pte_present(pte_t pte)
587 {
588 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
589 return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
590 (!(pte_val(pte) & _PAGE_INVALID) &&
591 !(pte_val(pte) & _PAGE_SWT));
592 }
593
594 static inline int pte_file(pte_t pte)
595 {
596 unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
597 return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
598 }
599
600 static inline int pte_special(pte_t pte)
601 {
602 return (pte_val(pte) & _PAGE_SPECIAL);
603 }
604
605 #define __HAVE_ARCH_PTE_SAME
606 static inline int pte_same(pte_t a, pte_t b)
607 {
608 return pte_val(a) == pte_val(b);
609 }
610
611 static inline pgste_t pgste_get_lock(pte_t *ptep)
612 {
613 unsigned long new = 0;
614 #ifdef CONFIG_PGSTE
615 unsigned long old;
616
617 preempt_disable();
618 asm(
619 " lg %0,%2\n"
620 "0: lgr %1,%0\n"
621 " nihh %0,0xff7f\n" /* clear RCP_PCL_BIT in old */
622 " oihh %1,0x0080\n" /* set RCP_PCL_BIT in new */
623 " csg %0,%1,%2\n"
624 " jl 0b\n"
625 : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
626 : "Q" (ptep[PTRS_PER_PTE]) : "cc");
627 #endif
628 return __pgste(new);
629 }
630
631 static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
632 {
633 #ifdef CONFIG_PGSTE
634 asm(
635 " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */
636 " stg %1,%0\n"
637 : "=Q" (ptep[PTRS_PER_PTE])
638 : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc");
639 preempt_enable();
640 #endif
641 }
642
643 static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
644 {
645 #ifdef CONFIG_PGSTE
646 unsigned long address, bits;
647 unsigned char skey;
648
649 if (pte_val(*ptep) & _PAGE_INVALID)
650 return pgste;
651 address = pte_val(*ptep) & PAGE_MASK;
652 skey = page_get_storage_key(address);
653 bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
654 /* Clear page changed & referenced bit in the storage key */
655 if (bits & _PAGE_CHANGED)
656 page_set_storage_key(address, skey ^ bits, 0);
657 else if (bits)
658 page_reset_referenced(address);
659 /* Transfer page changed & referenced bit to guest bits in pgste */
660 pgste_val(pgste) |= bits << 48; /* RCP_GR_BIT & RCP_GC_BIT */
661 /* Get host changed & referenced bits from pgste */
662 bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52;
663 /* Transfer page changed & referenced bit to kvm user bits */
664 pgste_val(pgste) |= bits << 45; /* KVM_UR_BIT & KVM_UC_BIT */
665 /* Clear relevant host bits in pgste. */
666 pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT);
667 pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT);
668 /* Copy page access key and fetch protection bit to pgste */
669 pgste_val(pgste) |=
670 (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
671 /* Transfer referenced bit to pte */
672 pte_val(*ptep) |= (bits & _PAGE_REFERENCED) << 1;
673 #endif
674 return pgste;
675
676 }
677
678 static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
679 {
680 #ifdef CONFIG_PGSTE
681 int young;
682
683 if (pte_val(*ptep) & _PAGE_INVALID)
684 return pgste;
685 /* Get referenced bit from storage key */
686 young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK);
687 if (young)
688 pgste_val(pgste) |= RCP_GR_BIT;
689 /* Get host referenced bit from pgste */
690 if (pgste_val(pgste) & RCP_HR_BIT) {
691 pgste_val(pgste) &= ~RCP_HR_BIT;
692 young = 1;
693 }
694 /* Transfer referenced bit to kvm user bits and pte */
695 if (young) {
696 pgste_val(pgste) |= KVM_UR_BIT;
697 pte_val(*ptep) |= _PAGE_SWR;
698 }
699 #endif
700 return pgste;
701 }
702
703 static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry)
704 {
705 #ifdef CONFIG_PGSTE
706 unsigned long address;
707 unsigned long okey, nkey;
708
709 if (pte_val(entry) & _PAGE_INVALID)
710 return;
711 address = pte_val(entry) & PAGE_MASK;
712 okey = nkey = page_get_storage_key(address);
713 nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT);
714 /* Set page access key and fetch protection bit from pgste */
715 nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
716 if (okey != nkey)
717 page_set_storage_key(address, nkey, 0);
718 #endif
719 }
720
721 static inline void pgste_set_pte(pte_t *ptep, pte_t entry)
722 {
723 if (!MACHINE_HAS_ESOP && (pte_val(entry) & _PAGE_SWW)) {
724 /*
725 * Without enhanced suppression-on-protection force
726 * the dirty bit on for all writable ptes.
727 */
728 pte_val(entry) |= _PAGE_SWC;
729 pte_val(entry) &= ~_PAGE_RO;
730 }
731 *ptep = entry;
732 }
733
734 /**
735 * struct gmap_struct - guest address space
736 * @mm: pointer to the parent mm_struct
737 * @table: pointer to the page directory
738 * @asce: address space control element for gmap page table
739 * @crst_list: list of all crst tables used in the guest address space
740 */
741 struct gmap {
742 struct list_head list;
743 struct mm_struct *mm;
744 unsigned long *table;
745 unsigned long asce;
746 struct list_head crst_list;
747 };
748
749 /**
750 * struct gmap_rmap - reverse mapping for segment table entries
751 * @gmap: pointer to the gmap_struct
752 * @entry: pointer to a segment table entry
753 * @vmaddr: virtual address in the guest address space
754 */
755 struct gmap_rmap {
756 struct list_head list;
757 struct gmap *gmap;
758 unsigned long *entry;
759 unsigned long vmaddr;
760 };
761
762 /**
763 * struct gmap_pgtable - gmap information attached to a page table
764 * @vmaddr: address of the 1MB segment in the process virtual memory
765 * @mapper: list of segment table entries mapping a page table
766 */
767 struct gmap_pgtable {
768 unsigned long vmaddr;
769 struct list_head mapper;
770 };
771
772 /**
773 * struct gmap_notifier - notify function block for page invalidation
774 * @notifier_call: address of callback function
775 */
776 struct gmap_notifier {
777 struct list_head list;
778 void (*notifier_call)(struct gmap *gmap, unsigned long address);
779 };
780
781 struct gmap *gmap_alloc(struct mm_struct *mm);
782 void gmap_free(struct gmap *gmap);
783 void gmap_enable(struct gmap *gmap);
784 void gmap_disable(struct gmap *gmap);
785 int gmap_map_segment(struct gmap *gmap, unsigned long from,
786 unsigned long to, unsigned long len);
787 int gmap_unmap_segment(struct gmap *gmap, unsigned long to, unsigned long len);
788 unsigned long __gmap_translate(unsigned long address, struct gmap *);
789 unsigned long gmap_translate(unsigned long address, struct gmap *);
790 unsigned long __gmap_fault(unsigned long address, struct gmap *);
791 unsigned long gmap_fault(unsigned long address, struct gmap *);
792 void gmap_discard(unsigned long from, unsigned long to, struct gmap *);
793
794 void gmap_register_ipte_notifier(struct gmap_notifier *);
795 void gmap_unregister_ipte_notifier(struct gmap_notifier *);
796 int gmap_ipte_notify(struct gmap *, unsigned long start, unsigned long len);
797 void gmap_do_ipte_notify(struct mm_struct *, unsigned long addr, pte_t *);
798
799 static inline pgste_t pgste_ipte_notify(struct mm_struct *mm,
800 unsigned long addr,
801 pte_t *ptep, pgste_t pgste)
802 {
803 #ifdef CONFIG_PGSTE
804 if (pgste_val(pgste) & RCP_IN_BIT) {
805 pgste_val(pgste) &= ~RCP_IN_BIT;
806 gmap_do_ipte_notify(mm, addr, ptep);
807 }
808 #endif
809 return pgste;
810 }
811
812 /*
813 * Certain architectures need to do special things when PTEs
814 * within a page table are directly modified. Thus, the following
815 * hook is made available.
816 */
817 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
818 pte_t *ptep, pte_t entry)
819 {
820 pgste_t pgste;
821
822 if (mm_has_pgste(mm)) {
823 pgste = pgste_get_lock(ptep);
824 pgste_set_key(ptep, pgste, entry);
825 pgste_set_pte(ptep, entry);
826 pgste_set_unlock(ptep, pgste);
827 } else {
828 if (!(pte_val(entry) & _PAGE_INVALID) && MACHINE_HAS_EDAT1)
829 pte_val(entry) |= _PAGE_CO;
830 *ptep = entry;
831 }
832 }
833
834 /*
835 * query functions pte_write/pte_dirty/pte_young only work if
836 * pte_present() is true. Undefined behaviour if not..
837 */
838 static inline int pte_write(pte_t pte)
839 {
840 return (pte_val(pte) & _PAGE_SWW) != 0;
841 }
842
843 static inline int pte_dirty(pte_t pte)
844 {
845 return (pte_val(pte) & _PAGE_SWC) != 0;
846 }
847
848 static inline int pte_young(pte_t pte)
849 {
850 #ifdef CONFIG_PGSTE
851 if (pte_val(pte) & _PAGE_SWR)
852 return 1;
853 #endif
854 return 0;
855 }
856
857 /*
858 * pgd/pmd/pte modification functions
859 */
860
861 static inline void pgd_clear(pgd_t *pgd)
862 {
863 #ifdef CONFIG_64BIT
864 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
865 pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
866 #endif
867 }
868
869 static inline void pud_clear(pud_t *pud)
870 {
871 #ifdef CONFIG_64BIT
872 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
873 pud_val(*pud) = _REGION3_ENTRY_EMPTY;
874 #endif
875 }
876
877 static inline void pmd_clear(pmd_t *pmdp)
878 {
879 pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
880 }
881
882 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
883 {
884 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
885 }
886
887 /*
888 * The following pte modification functions only work if
889 * pte_present() is true. Undefined behaviour if not..
890 */
891 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
892 {
893 pte_val(pte) &= _PAGE_CHG_MASK;
894 pte_val(pte) |= pgprot_val(newprot);
895 if ((pte_val(pte) & _PAGE_SWC) && (pte_val(pte) & _PAGE_SWW))
896 pte_val(pte) &= ~_PAGE_RO;
897 return pte;
898 }
899
900 static inline pte_t pte_wrprotect(pte_t pte)
901 {
902 pte_val(pte) &= ~_PAGE_SWW;
903 /* Do not clobber _PAGE_TYPE_NONE pages! */
904 if (!(pte_val(pte) & _PAGE_INVALID))
905 pte_val(pte) |= _PAGE_RO;
906 return pte;
907 }
908
909 static inline pte_t pte_mkwrite(pte_t pte)
910 {
911 pte_val(pte) |= _PAGE_SWW;
912 if (pte_val(pte) & _PAGE_SWC)
913 pte_val(pte) &= ~_PAGE_RO;
914 return pte;
915 }
916
917 static inline pte_t pte_mkclean(pte_t pte)
918 {
919 pte_val(pte) &= ~_PAGE_SWC;
920 /* Do not clobber _PAGE_TYPE_NONE pages! */
921 if (!(pte_val(pte) & _PAGE_INVALID))
922 pte_val(pte) |= _PAGE_RO;
923 return pte;
924 }
925
926 static inline pte_t pte_mkdirty(pte_t pte)
927 {
928 pte_val(pte) |= _PAGE_SWC;
929 if (pte_val(pte) & _PAGE_SWW)
930 pte_val(pte) &= ~_PAGE_RO;
931 return pte;
932 }
933
934 static inline pte_t pte_mkold(pte_t pte)
935 {
936 #ifdef CONFIG_PGSTE
937 pte_val(pte) &= ~_PAGE_SWR;
938 #endif
939 return pte;
940 }
941
942 static inline pte_t pte_mkyoung(pte_t pte)
943 {
944 return pte;
945 }
946
947 static inline pte_t pte_mkspecial(pte_t pte)
948 {
949 pte_val(pte) |= _PAGE_SPECIAL;
950 return pte;
951 }
952
953 #ifdef CONFIG_HUGETLB_PAGE
954 static inline pte_t pte_mkhuge(pte_t pte)
955 {
956 pte_val(pte) |= (_SEGMENT_ENTRY_LARGE | _SEGMENT_ENTRY_CO);
957 return pte;
958 }
959 #endif
960
961 /*
962 * Get (and clear) the user dirty bit for a pte.
963 */
964 static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
965 pte_t *ptep)
966 {
967 pgste_t pgste;
968 int dirty = 0;
969
970 if (mm_has_pgste(mm)) {
971 pgste = pgste_get_lock(ptep);
972 pgste = pgste_update_all(ptep, pgste);
973 dirty = !!(pgste_val(pgste) & KVM_UC_BIT);
974 pgste_val(pgste) &= ~KVM_UC_BIT;
975 pgste_set_unlock(ptep, pgste);
976 return dirty;
977 }
978 return dirty;
979 }
980
981 /*
982 * Get (and clear) the user referenced bit for a pte.
983 */
984 static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
985 pte_t *ptep)
986 {
987 pgste_t pgste;
988 int young = 0;
989
990 if (mm_has_pgste(mm)) {
991 pgste = pgste_get_lock(ptep);
992 pgste = pgste_update_young(ptep, pgste);
993 young = !!(pgste_val(pgste) & KVM_UR_BIT);
994 pgste_val(pgste) &= ~KVM_UR_BIT;
995 pgste_set_unlock(ptep, pgste);
996 }
997 return young;
998 }
999
1000 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1001 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
1002 unsigned long addr, pte_t *ptep)
1003 {
1004 pgste_t pgste;
1005 pte_t pte;
1006
1007 if (mm_has_pgste(vma->vm_mm)) {
1008 pgste = pgste_get_lock(ptep);
1009 pgste = pgste_update_young(ptep, pgste);
1010 pte = *ptep;
1011 *ptep = pte_mkold(pte);
1012 pgste_set_unlock(ptep, pgste);
1013 return pte_young(pte);
1014 }
1015 return 0;
1016 }
1017
1018 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1019 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
1020 unsigned long address, pte_t *ptep)
1021 {
1022 /* No need to flush TLB
1023 * On s390 reference bits are in storage key and never in TLB
1024 * With virtualization we handle the reference bit, without we
1025 * we can simply return */
1026 return ptep_test_and_clear_young(vma, address, ptep);
1027 }
1028
1029 static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
1030 {
1031 if (!(pte_val(*ptep) & _PAGE_INVALID)) {
1032 #ifndef CONFIG_64BIT
1033 /* pto must point to the start of the segment table */
1034 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
1035 #else
1036 /* ipte in zarch mode can do the math */
1037 pte_t *pto = ptep;
1038 #endif
1039 asm volatile(
1040 " ipte %2,%3"
1041 : "=m" (*ptep) : "m" (*ptep),
1042 "a" (pto), "a" (address));
1043 }
1044 }
1045
1046 /*
1047 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
1048 * both clear the TLB for the unmapped pte. The reason is that
1049 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
1050 * to modify an active pte. The sequence is
1051 * 1) ptep_get_and_clear
1052 * 2) set_pte_at
1053 * 3) flush_tlb_range
1054 * On s390 the tlb needs to get flushed with the modification of the pte
1055 * if the pte is active. The only way how this can be implemented is to
1056 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1057 * is a nop.
1058 */
1059 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
1060 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
1061 unsigned long address, pte_t *ptep)
1062 {
1063 pgste_t pgste;
1064 pte_t pte;
1065
1066 mm->context.flush_mm = 1;
1067 if (mm_has_pgste(mm)) {
1068 pgste = pgste_get_lock(ptep);
1069 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1070 }
1071
1072 pte = *ptep;
1073 if (!mm_exclusive(mm))
1074 __ptep_ipte(address, ptep);
1075 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1076
1077 if (mm_has_pgste(mm)) {
1078 pgste = pgste_update_all(&pte, pgste);
1079 pgste_set_unlock(ptep, pgste);
1080 }
1081 return pte;
1082 }
1083
1084 #define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1085 static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
1086 unsigned long address,
1087 pte_t *ptep)
1088 {
1089 pgste_t pgste;
1090 pte_t pte;
1091
1092 mm->context.flush_mm = 1;
1093 if (mm_has_pgste(mm)) {
1094 pgste = pgste_get_lock(ptep);
1095 pgste_ipte_notify(mm, address, ptep, pgste);
1096 }
1097
1098 pte = *ptep;
1099 if (!mm_exclusive(mm))
1100 __ptep_ipte(address, ptep);
1101
1102 if (mm_has_pgste(mm))
1103 pgste = pgste_update_all(&pte, pgste);
1104 return pte;
1105 }
1106
1107 static inline void ptep_modify_prot_commit(struct mm_struct *mm,
1108 unsigned long address,
1109 pte_t *ptep, pte_t pte)
1110 {
1111 pgste_t pgste;
1112
1113 if (mm_has_pgste(mm)) {
1114 pgste = *(pgste_t *)(ptep + PTRS_PER_PTE);
1115 pgste_set_key(ptep, pgste, pte);
1116 pgste_set_pte(ptep, pte);
1117 pgste_set_unlock(ptep, pgste);
1118 } else
1119 *ptep = pte;
1120 }
1121
1122 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH
1123 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1124 unsigned long address, pte_t *ptep)
1125 {
1126 pgste_t pgste;
1127 pte_t pte;
1128
1129 if (mm_has_pgste(vma->vm_mm)) {
1130 pgste = pgste_get_lock(ptep);
1131 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
1132 }
1133
1134 pte = *ptep;
1135 __ptep_ipte(address, ptep);
1136 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1137
1138 if (mm_has_pgste(vma->vm_mm)) {
1139 pgste = pgste_update_all(&pte, pgste);
1140 pgste_set_unlock(ptep, pgste);
1141 }
1142 return pte;
1143 }
1144
1145 /*
1146 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1147 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1148 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1149 * cannot be accessed while the batched unmap is running. In this case
1150 * full==1 and a simple pte_clear is enough. See tlb.h.
1151 */
1152 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1153 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
1154 unsigned long address,
1155 pte_t *ptep, int full)
1156 {
1157 pgste_t pgste;
1158 pte_t pte;
1159
1160 if (mm_has_pgste(mm)) {
1161 pgste = pgste_get_lock(ptep);
1162 if (!full)
1163 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1164 }
1165
1166 pte = *ptep;
1167 if (!full)
1168 __ptep_ipte(address, ptep);
1169 pte_val(*ptep) = _PAGE_TYPE_EMPTY;
1170
1171 if (mm_has_pgste(mm)) {
1172 pgste = pgste_update_all(&pte, pgste);
1173 pgste_set_unlock(ptep, pgste);
1174 }
1175 return pte;
1176 }
1177
1178 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
1179 static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
1180 unsigned long address, pte_t *ptep)
1181 {
1182 pgste_t pgste;
1183 pte_t pte = *ptep;
1184
1185 if (pte_write(pte)) {
1186 mm->context.flush_mm = 1;
1187 if (mm_has_pgste(mm)) {
1188 pgste = pgste_get_lock(ptep);
1189 pgste = pgste_ipte_notify(mm, address, ptep, pgste);
1190 }
1191
1192 if (!mm_exclusive(mm))
1193 __ptep_ipte(address, ptep);
1194 pte = pte_wrprotect(pte);
1195
1196 if (mm_has_pgste(mm)) {
1197 pgste_set_pte(ptep, pte);
1198 pgste_set_unlock(ptep, pgste);
1199 } else
1200 *ptep = pte;
1201 }
1202 return pte;
1203 }
1204
1205 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
1206 static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1207 unsigned long address, pte_t *ptep,
1208 pte_t entry, int dirty)
1209 {
1210 pgste_t pgste;
1211
1212 if (pte_same(*ptep, entry))
1213 return 0;
1214 if (mm_has_pgste(vma->vm_mm)) {
1215 pgste = pgste_get_lock(ptep);
1216 pgste = pgste_ipte_notify(vma->vm_mm, address, ptep, pgste);
1217 }
1218
1219 __ptep_ipte(address, ptep);
1220
1221 if (mm_has_pgste(vma->vm_mm)) {
1222 pgste_set_pte(ptep, entry);
1223 pgste_set_unlock(ptep, pgste);
1224 } else
1225 *ptep = entry;
1226 return 1;
1227 }
1228
1229 /*
1230 * Conversion functions: convert a page and protection to a page entry,
1231 * and a page entry and page directory to the page they refer to.
1232 */
1233 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1234 {
1235 pte_t __pte;
1236 pte_val(__pte) = physpage + pgprot_val(pgprot);
1237 return __pte;
1238 }
1239
1240 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
1241 {
1242 unsigned long physpage = page_to_phys(page);
1243 pte_t __pte = mk_pte_phys(physpage, pgprot);
1244
1245 if ((pte_val(__pte) & _PAGE_SWW) && PageDirty(page)) {
1246 pte_val(__pte) |= _PAGE_SWC;
1247 pte_val(__pte) &= ~_PAGE_RO;
1248 }
1249 return __pte;
1250 }
1251
1252 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1253 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1254 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1255 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
1256
1257 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
1258 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
1259
1260 #ifndef CONFIG_64BIT
1261
1262 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1263 #define pud_deref(pmd) ({ BUG(); 0UL; })
1264 #define pgd_deref(pmd) ({ BUG(); 0UL; })
1265
1266 #define pud_offset(pgd, address) ((pud_t *) pgd)
1267 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
1268
1269 #else /* CONFIG_64BIT */
1270
1271 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
1272 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
1273 #define pgd_deref(pgd) (pgd_val(pgd) & _REGION_ENTRY_ORIGIN)
1274
1275 static inline pud_t *pud_offset(pgd_t *pgd, unsigned long address)
1276 {
1277 pud_t *pud = (pud_t *) pgd;
1278 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1279 pud = (pud_t *) pgd_deref(*pgd);
1280 return pud + pud_index(address);
1281 }
1282
1283 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
1284 {
1285 pmd_t *pmd = (pmd_t *) pud;
1286 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1287 pmd = (pmd_t *) pud_deref(*pud);
1288 return pmd + pmd_index(address);
1289 }
1290
1291 #endif /* CONFIG_64BIT */
1292
1293 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
1294 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1295 #define pte_page(x) pfn_to_page(pte_pfn(x))
1296
1297 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
1298
1299 /* Find an entry in the lowest level page table.. */
1300 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
1301 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
1302 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
1303 #define pte_unmap(pte) do { } while (0)
1304
1305 static inline void __pmd_idte(unsigned long address, pmd_t *pmdp)
1306 {
1307 unsigned long sto = (unsigned long) pmdp -
1308 pmd_index(address) * sizeof(pmd_t);
1309
1310 if (!(pmd_val(*pmdp) & _SEGMENT_ENTRY_INV)) {
1311 asm volatile(
1312 " .insn rrf,0xb98e0000,%2,%3,0,0"
1313 : "=m" (*pmdp)
1314 : "m" (*pmdp), "a" (sto),
1315 "a" ((address & HPAGE_MASK))
1316 : "cc"
1317 );
1318 }
1319 }
1320
1321 #if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
1322 static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1323 {
1324 /*
1325 * pgprot is PAGE_NONE, PAGE_RO, or PAGE_RW (see __Pxxx / __Sxxx)
1326 * Convert to segment table entry format.
1327 */
1328 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1329 return pgprot_val(SEGMENT_NONE);
1330 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO))
1331 return pgprot_val(SEGMENT_RO);
1332 return pgprot_val(SEGMENT_RW);
1333 }
1334
1335 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1336 {
1337 pmd_val(pmd) &= _SEGMENT_CHG_MASK;
1338 pmd_val(pmd) |= massage_pgprot_pmd(newprot);
1339 return pmd;
1340 }
1341
1342 static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1343 {
1344 pmd_t __pmd;
1345 pmd_val(__pmd) = physpage + massage_pgprot_pmd(pgprot);
1346 return __pmd;
1347 }
1348
1349 static inline pmd_t pmd_mkwrite(pmd_t pmd)
1350 {
1351 /* Do not clobber _HPAGE_TYPE_NONE pages! */
1352 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_INV))
1353 pmd_val(pmd) &= ~_SEGMENT_ENTRY_RO;
1354 return pmd;
1355 }
1356 #endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
1357
1358 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
1359
1360 #define __HAVE_ARCH_PGTABLE_DEPOSIT
1361 extern void pgtable_trans_huge_deposit(struct mm_struct *mm, pgtable_t pgtable);
1362
1363 #define __HAVE_ARCH_PGTABLE_WITHDRAW
1364 extern pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm);
1365
1366 static inline int pmd_trans_splitting(pmd_t pmd)
1367 {
1368 return pmd_val(pmd) & _SEGMENT_ENTRY_SPLIT;
1369 }
1370
1371 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1372 pmd_t *pmdp, pmd_t entry)
1373 {
1374 if (!(pmd_val(entry) & _SEGMENT_ENTRY_INV) && MACHINE_HAS_EDAT1)
1375 pmd_val(entry) |= _SEGMENT_ENTRY_CO;
1376 *pmdp = entry;
1377 }
1378
1379 static inline pmd_t pmd_mkhuge(pmd_t pmd)
1380 {
1381 pmd_val(pmd) |= _SEGMENT_ENTRY_LARGE;
1382 return pmd;
1383 }
1384
1385 static inline pmd_t pmd_wrprotect(pmd_t pmd)
1386 {
1387 pmd_val(pmd) |= _SEGMENT_ENTRY_RO;
1388 return pmd;
1389 }
1390
1391 static inline pmd_t pmd_mkdirty(pmd_t pmd)
1392 {
1393 /* No dirty bit in the segment table entry. */
1394 return pmd;
1395 }
1396
1397 static inline pmd_t pmd_mkold(pmd_t pmd)
1398 {
1399 /* No referenced bit in the segment table entry. */
1400 return pmd;
1401 }
1402
1403 static inline pmd_t pmd_mkyoung(pmd_t pmd)
1404 {
1405 /* No referenced bit in the segment table entry. */
1406 return pmd;
1407 }
1408
1409 #define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1410 static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1411 unsigned long address, pmd_t *pmdp)
1412 {
1413 unsigned long pmd_addr = pmd_val(*pmdp) & HPAGE_MASK;
1414 long tmp, rc;
1415 int counter;
1416
1417 rc = 0;
1418 if (MACHINE_HAS_RRBM) {
1419 counter = PTRS_PER_PTE >> 6;
1420 asm volatile(
1421 "0: .insn rre,0xb9ae0000,%0,%3\n" /* rrbm */
1422 " ogr %1,%0\n"
1423 " la %3,0(%4,%3)\n"
1424 " brct %2,0b\n"
1425 : "=&d" (tmp), "+&d" (rc), "+d" (counter),
1426 "+a" (pmd_addr)
1427 : "a" (64 * 4096UL) : "cc");
1428 rc = !!rc;
1429 } else {
1430 counter = PTRS_PER_PTE;
1431 asm volatile(
1432 "0: rrbe 0,%2\n"
1433 " la %2,0(%3,%2)\n"
1434 " brc 12,1f\n"
1435 " lhi %0,1\n"
1436 "1: brct %1,0b\n"
1437 : "+d" (rc), "+d" (counter), "+a" (pmd_addr)
1438 : "a" (4096UL) : "cc");
1439 }
1440 return rc;
1441 }
1442
1443 #define __HAVE_ARCH_PMDP_GET_AND_CLEAR
1444 static inline pmd_t pmdp_get_and_clear(struct mm_struct *mm,
1445 unsigned long address, pmd_t *pmdp)
1446 {
1447 pmd_t pmd = *pmdp;
1448
1449 __pmd_idte(address, pmdp);
1450 pmd_clear(pmdp);
1451 return pmd;
1452 }
1453
1454 #define __HAVE_ARCH_PMDP_CLEAR_FLUSH
1455 static inline pmd_t pmdp_clear_flush(struct vm_area_struct *vma,
1456 unsigned long address, pmd_t *pmdp)
1457 {
1458 return pmdp_get_and_clear(vma->vm_mm, address, pmdp);
1459 }
1460
1461 #define __HAVE_ARCH_PMDP_INVALIDATE
1462 static inline void pmdp_invalidate(struct vm_area_struct *vma,
1463 unsigned long address, pmd_t *pmdp)
1464 {
1465 __pmd_idte(address, pmdp);
1466 }
1467
1468 #define __HAVE_ARCH_PMDP_SET_WRPROTECT
1469 static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1470 unsigned long address, pmd_t *pmdp)
1471 {
1472 pmd_t pmd = *pmdp;
1473
1474 if (pmd_write(pmd)) {
1475 __pmd_idte(address, pmdp);
1476 set_pmd_at(mm, address, pmdp, pmd_wrprotect(pmd));
1477 }
1478 }
1479
1480 #define pfn_pmd(pfn, pgprot) mk_pmd_phys(__pa((pfn) << PAGE_SHIFT), (pgprot))
1481 #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot))
1482
1483 static inline int pmd_trans_huge(pmd_t pmd)
1484 {
1485 return pmd_val(pmd) & _SEGMENT_ENTRY_LARGE;
1486 }
1487
1488 static inline int has_transparent_hugepage(void)
1489 {
1490 return MACHINE_HAS_HPAGE ? 1 : 0;
1491 }
1492
1493 static inline unsigned long pmd_pfn(pmd_t pmd)
1494 {
1495 return pmd_val(pmd) >> PAGE_SHIFT;
1496 }
1497 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1498
1499 /*
1500 * 31 bit swap entry format:
1501 * A page-table entry has some bits we have to treat in a special way.
1502 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
1503 * exception will occur instead of a page translation exception. The
1504 * specifiation exception has the bad habit not to store necessary
1505 * information in the lowcore.
1506 * Bit 21 and bit 22 are the page invalid bit and the page protection
1507 * bit. We set both to indicate a swapped page.
1508 * Bit 30 and 31 are used to distinguish the different page types. For
1509 * a swapped page these bits need to be zero.
1510 * This leaves the bits 1-19 and bits 24-29 to store type and offset.
1511 * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
1512 * plus 24 for the offset.
1513 * 0| offset |0110|o|type |00|
1514 * 0 0000000001111111111 2222 2 22222 33
1515 * 0 1234567890123456789 0123 4 56789 01
1516 *
1517 * 64 bit swap entry format:
1518 * A page-table entry has some bits we have to treat in a special way.
1519 * Bits 52 and bit 55 have to be zero, otherwise an specification
1520 * exception will occur instead of a page translation exception. The
1521 * specifiation exception has the bad habit not to store necessary
1522 * information in the lowcore.
1523 * Bit 53 and bit 54 are the page invalid bit and the page protection
1524 * bit. We set both to indicate a swapped page.
1525 * Bit 62 and 63 are used to distinguish the different page types. For
1526 * a swapped page these bits need to be zero.
1527 * This leaves the bits 0-51 and bits 56-61 to store type and offset.
1528 * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
1529 * plus 56 for the offset.
1530 * | offset |0110|o|type |00|
1531 * 0000000000111111111122222222223333333333444444444455 5555 5 55566 66
1532 * 0123456789012345678901234567890123456789012345678901 2345 6 78901 23
1533 */
1534 #ifndef CONFIG_64BIT
1535 #define __SWP_OFFSET_MASK (~0UL >> 12)
1536 #else
1537 #define __SWP_OFFSET_MASK (~0UL >> 11)
1538 #endif
1539 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1540 {
1541 pte_t pte;
1542 offset &= __SWP_OFFSET_MASK;
1543 pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
1544 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
1545 return pte;
1546 }
1547
1548 #define __swp_type(entry) (((entry).val >> 2) & 0x1f)
1549 #define __swp_offset(entry) (((entry).val >> 11) | (((entry).val >> 7) & 1))
1550 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
1551
1552 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1553 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1554
1555 #ifndef CONFIG_64BIT
1556 # define PTE_FILE_MAX_BITS 26
1557 #else /* CONFIG_64BIT */
1558 # define PTE_FILE_MAX_BITS 59
1559 #endif /* CONFIG_64BIT */
1560
1561 #define pte_to_pgoff(__pte) \
1562 ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
1563
1564 #define pgoff_to_pte(__off) \
1565 ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
1566 | _PAGE_TYPE_FILE })
1567
1568 #endif /* !__ASSEMBLY__ */
1569
1570 #define kern_addr_valid(addr) (1)
1571
1572 extern int vmem_add_mapping(unsigned long start, unsigned long size);
1573 extern int vmem_remove_mapping(unsigned long start, unsigned long size);
1574 extern int s390_enable_sie(void);
1575
1576 /*
1577 * No page table caches to initialise
1578 */
1579 static inline void pgtable_cache_init(void) { }
1580 static inline void check_pgt_cache(void) { }
1581
1582 #include <asm-generic/pgtable.h>
1583
1584 #endif /* _S390_PAGE_H */
kernel source for telekom puls (alcatel/mediatek)