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Linux-2.6.12-rc2
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / ppc64 / xmon / ppc-opc.c
1 /* ppc-opc.c -- PowerPC opcode list
2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Written by Ian Lance Taylor, Cygnus Support
5
6 This file is part of GDB, GAS, and the GNU binutils.
7
8 GDB, GAS, and the GNU binutils are free software; you can redistribute
9 them and/or modify them under the terms of the GNU General Public
10 License as published by the Free Software Foundation; either version
11 2, or (at your option) any later version.
12
13 GDB, GAS, and the GNU binutils are distributed in the hope that they
14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
16 the GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this file; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
23 #include "nonstdio.h"
24 #include "ppc.h"
25
26 #define ATTRIBUTE_UNUSED
27 #define _(x) x
28
29 /* This file holds the PowerPC opcode table. The opcode table
30 includes almost all of the extended instruction mnemonics. This
31 permits the disassembler to use them, and simplifies the assembler
32 logic, at the cost of increasing the table size. The table is
33 strictly constant data, so the compiler should be able to put it in
34 the .text section.
35
36 This file also holds the operand table. All knowledge about
37 inserting operands into instructions and vice-versa is kept in this
38 file. */
39 \f
40 /* Local insertion and extraction functions. */
41
42 static unsigned long insert_bat (unsigned long, long, int, const char **);
43 static long extract_bat (unsigned long, int, int *);
44 static unsigned long insert_bba (unsigned long, long, int, const char **);
45 static long extract_bba (unsigned long, int, int *);
46 static unsigned long insert_bd (unsigned long, long, int, const char **);
47 static long extract_bd (unsigned long, int, int *);
48 static unsigned long insert_bdm (unsigned long, long, int, const char **);
49 static long extract_bdm (unsigned long, int, int *);
50 static unsigned long insert_bdp (unsigned long, long, int, const char **);
51 static long extract_bdp (unsigned long, int, int *);
52 static unsigned long insert_bo (unsigned long, long, int, const char **);
53 static long extract_bo (unsigned long, int, int *);
54 static unsigned long insert_boe (unsigned long, long, int, const char **);
55 static long extract_boe (unsigned long, int, int *);
56 static unsigned long insert_dq (unsigned long, long, int, const char **);
57 static long extract_dq (unsigned long, int, int *);
58 static unsigned long insert_ds (unsigned long, long, int, const char **);
59 static long extract_ds (unsigned long, int, int *);
60 static unsigned long insert_de (unsigned long, long, int, const char **);
61 static long extract_de (unsigned long, int, int *);
62 static unsigned long insert_des (unsigned long, long, int, const char **);
63 static long extract_des (unsigned long, int, int *);
64 static unsigned long insert_fxm (unsigned long, long, int, const char **);
65 static long extract_fxm (unsigned long, int, int *);
66 static unsigned long insert_li (unsigned long, long, int, const char **);
67 static long extract_li (unsigned long, int, int *);
68 static unsigned long insert_mbe (unsigned long, long, int, const char **);
69 static long extract_mbe (unsigned long, int, int *);
70 static unsigned long insert_mb6 (unsigned long, long, int, const char **);
71 static long extract_mb6 (unsigned long, int, int *);
72 static unsigned long insert_nb (unsigned long, long, int, const char **);
73 static long extract_nb (unsigned long, int, int *);
74 static unsigned long insert_nsi (unsigned long, long, int, const char **);
75 static long extract_nsi (unsigned long, int, int *);
76 static unsigned long insert_ral (unsigned long, long, int, const char **);
77 static unsigned long insert_ram (unsigned long, long, int, const char **);
78 static unsigned long insert_raq (unsigned long, long, int, const char **);
79 static unsigned long insert_ras (unsigned long, long, int, const char **);
80 static unsigned long insert_rbs (unsigned long, long, int, const char **);
81 static long extract_rbs (unsigned long, int, int *);
82 static unsigned long insert_rsq (unsigned long, long, int, const char **);
83 static unsigned long insert_rtq (unsigned long, long, int, const char **);
84 static unsigned long insert_sh6 (unsigned long, long, int, const char **);
85 static long extract_sh6 (unsigned long, int, int *);
86 static unsigned long insert_spr (unsigned long, long, int, const char **);
87 static long extract_spr (unsigned long, int, int *);
88 static unsigned long insert_tbr (unsigned long, long, int, const char **);
89 static long extract_tbr (unsigned long, int, int *);
90 static unsigned long insert_ev2 (unsigned long, long, int, const char **);
91 static long extract_ev2 (unsigned long, int, int *);
92 static unsigned long insert_ev4 (unsigned long, long, int, const char **);
93 static long extract_ev4 (unsigned long, int, int *);
94 static unsigned long insert_ev8 (unsigned long, long, int, const char **);
95 static long extract_ev8 (unsigned long, int, int *);
96 \f
97 /* The operands table.
98
99 The fields are bits, shift, insert, extract, flags.
100
101 We used to put parens around the various additions, like the one
102 for BA just below. However, that caused trouble with feeble
103 compilers with a limit on depth of a parenthesized expression, like
104 (reportedly) the compiler in Microsoft Developer Studio 5. So we
105 omit the parens, since the macros are never used in a context where
106 the addition will be ambiguous. */
107
108 const struct powerpc_operand powerpc_operands[] =
109 {
110 /* The zero index is used to indicate the end of the list of
111 operands. */
112 #define UNUSED 0
113 { 0, 0, 0, 0, 0 },
114
115 /* The BA field in an XL form instruction. */
116 #define BA UNUSED + 1
117 #define BA_MASK (0x1f << 16)
118 { 5, 16, 0, 0, PPC_OPERAND_CR },
119
120 /* The BA field in an XL form instruction when it must be the same
121 as the BT field in the same instruction. */
122 #define BAT BA + 1
123 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },
124
125 /* The BB field in an XL form instruction. */
126 #define BB BAT + 1
127 #define BB_MASK (0x1f << 11)
128 { 5, 11, 0, 0, PPC_OPERAND_CR },
129
130 /* The BB field in an XL form instruction when it must be the same
131 as the BA field in the same instruction. */
132 #define BBA BB + 1
133 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },
134
135 /* The BD field in a B form instruction. The lower two bits are
136 forced to zero. */
137 #define BD BBA + 1
138 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
139
140 /* The BD field in a B form instruction when absolute addressing is
141 used. */
142 #define BDA BD + 1
143 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
144
145 /* The BD field in a B form instruction when the - modifier is used.
146 This sets the y bit of the BO field appropriately. */
147 #define BDM BDA + 1
148 { 16, 0, insert_bdm, extract_bdm,
149 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
150
151 /* The BD field in a B form instruction when the - modifier is used
152 and absolute address is used. */
153 #define BDMA BDM + 1
154 { 16, 0, insert_bdm, extract_bdm,
155 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
156
157 /* The BD field in a B form instruction when the + modifier is used.
158 This sets the y bit of the BO field appropriately. */
159 #define BDP BDMA + 1
160 { 16, 0, insert_bdp, extract_bdp,
161 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
162
163 /* The BD field in a B form instruction when the + modifier is used
164 and absolute addressing is used. */
165 #define BDPA BDP + 1
166 { 16, 0, insert_bdp, extract_bdp,
167 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
168
169 /* The BF field in an X or XL form instruction. */
170 #define BF BDPA + 1
171 { 3, 23, 0, 0, PPC_OPERAND_CR },
172
173 /* An optional BF field. This is used for comparison instructions,
174 in which an omitted BF field is taken as zero. */
175 #define OBF BF + 1
176 { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
177
178 /* The BFA field in an X or XL form instruction. */
179 #define BFA OBF + 1
180 { 3, 18, 0, 0, PPC_OPERAND_CR },
181
182 /* The BI field in a B form or XL form instruction. */
183 #define BI BFA + 1
184 #define BI_MASK (0x1f << 16)
185 { 5, 16, 0, 0, PPC_OPERAND_CR },
186
187 /* The BO field in a B form instruction. Certain values are
188 illegal. */
189 #define BO BI + 1
190 #define BO_MASK (0x1f << 21)
191 { 5, 21, insert_bo, extract_bo, 0 },
192
193 /* The BO field in a B form instruction when the + or - modifier is
194 used. This is like the BO field, but it must be even. */
195 #define BOE BO + 1
196 { 5, 21, insert_boe, extract_boe, 0 },
197
198 /* The BT field in an X or XL form instruction. */
199 #define BT BOE + 1
200 { 5, 21, 0, 0, PPC_OPERAND_CR },
201
202 /* The condition register number portion of the BI field in a B form
203 or XL form instruction. This is used for the extended
204 conditional branch mnemonics, which set the lower two bits of the
205 BI field. This field is optional. */
206 #define CR BT + 1
207 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
208
209 /* The CRB field in an X form instruction. */
210 #define CRB CR + 1
211 { 5, 6, 0, 0, 0 },
212
213 /* The CRFD field in an X form instruction. */
214 #define CRFD CRB + 1
215 { 3, 23, 0, 0, PPC_OPERAND_CR },
216
217 /* The CRFS field in an X form instruction. */
218 #define CRFS CRFD + 1
219 { 3, 0, 0, 0, PPC_OPERAND_CR },
220
221 /* The CT field in an X form instruction. */
222 #define CT CRFS + 1
223 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
224
225 /* The D field in a D form instruction. This is a displacement off
226 a register, and implies that the next operand is a register in
227 parentheses. */
228 #define D CT + 1
229 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
230
231 /* The DE field in a DE form instruction. This is like D, but is 12
232 bits only. */
233 #define DE D + 1
234 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS },
235
236 /* The DES field in a DES form instruction. This is like DS, but is 14
237 bits only (12 stored.) */
238 #define DES DE + 1
239 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
240
241 /* The DQ field in a DQ form instruction. This is like D, but the
242 lower four bits are forced to zero. */
243 #define DQ DES + 1
244 { 16, 0, insert_dq, extract_dq,
245 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },
246
247 /* The DS field in a DS form instruction. This is like D, but the
248 lower two bits are forced to zero. */
249 #define DS DQ + 1
250 { 16, 0, insert_ds, extract_ds,
251 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },
252
253 /* The E field in a wrteei instruction. */
254 #define E DS + 1
255 { 1, 15, 0, 0, 0 },
256
257 /* The FL1 field in a POWER SC form instruction. */
258 #define FL1 E + 1
259 { 4, 12, 0, 0, 0 },
260
261 /* The FL2 field in a POWER SC form instruction. */
262 #define FL2 FL1 + 1
263 { 3, 2, 0, 0, 0 },
264
265 /* The FLM field in an XFL form instruction. */
266 #define FLM FL2 + 1
267 { 8, 17, 0, 0, 0 },
268
269 /* The FRA field in an X or A form instruction. */
270 #define FRA FLM + 1
271 #define FRA_MASK (0x1f << 16)
272 { 5, 16, 0, 0, PPC_OPERAND_FPR },
273
274 /* The FRB field in an X or A form instruction. */
275 #define FRB FRA + 1
276 #define FRB_MASK (0x1f << 11)
277 { 5, 11, 0, 0, PPC_OPERAND_FPR },
278
279 /* The FRC field in an A form instruction. */
280 #define FRC FRB + 1
281 #define FRC_MASK (0x1f << 6)
282 { 5, 6, 0, 0, PPC_OPERAND_FPR },
283
284 /* The FRS field in an X form instruction or the FRT field in a D, X
285 or A form instruction. */
286 #define FRS FRC + 1
287 #define FRT FRS
288 { 5, 21, 0, 0, PPC_OPERAND_FPR },
289
290 /* The FXM field in an XFX instruction. */
291 #define FXM FRS + 1
292 #define FXM_MASK (0xff << 12)
293 { 8, 12, insert_fxm, extract_fxm, 0 },
294
295 /* Power4 version for mfcr. */
296 #define FXM4 FXM + 1
297 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },
298
299 /* The L field in a D or X form instruction. */
300 #define L FXM4 + 1
301 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
302
303 /* The LEV field in a POWER SC form instruction. */
304 #define LEV L + 1
305 { 7, 5, 0, 0, 0 },
306
307 /* The LI field in an I form instruction. The lower two bits are
308 forced to zero. */
309 #define LI LEV + 1
310 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },
311
312 /* The LI field in an I form instruction when used as an absolute
313 address. */
314 #define LIA LI + 1
315 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },
316
317 /* The LS field in an X (sync) form instruction. */
318 #define LS LIA + 1
319 { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
320
321 /* The MB field in an M form instruction. */
322 #define MB LS + 1
323 #define MB_MASK (0x1f << 6)
324 { 5, 6, 0, 0, 0 },
325
326 /* The ME field in an M form instruction. */
327 #define ME MB + 1
328 #define ME_MASK (0x1f << 1)
329 { 5, 1, 0, 0, 0 },
330
331 /* The MB and ME fields in an M form instruction expressed a single
332 operand which is a bitmask indicating which bits to select. This
333 is a two operand form using PPC_OPERAND_NEXT. See the
334 description in opcode/ppc.h for what this means. */
335 #define MBE ME + 1
336 { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
337 { 32, 0, insert_mbe, extract_mbe, 0 },
338
339 /* The MB or ME field in an MD or MDS form instruction. The high
340 bit is wrapped to the low end. */
341 #define MB6 MBE + 2
342 #define ME6 MB6
343 #define MB6_MASK (0x3f << 5)
344 { 6, 5, insert_mb6, extract_mb6, 0 },
345
346 /* The MO field in an mbar instruction. */
347 #define MO MB6 + 1
348 { 5, 21, 0, 0, 0 },
349
350 /* The NB field in an X form instruction. The value 32 is stored as
351 0. */
352 #define NB MO + 1
353 { 6, 11, insert_nb, extract_nb, 0 },
354
355 /* The NSI field in a D form instruction. This is the same as the
356 SI field, only negated. */
357 #define NSI NB + 1
358 { 16, 0, insert_nsi, extract_nsi,
359 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },
360
361 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */
362 #define RA NSI + 1
363 #define RA_MASK (0x1f << 16)
364 { 5, 16, 0, 0, PPC_OPERAND_GPR },
365
366 /* The RA field in the DQ form lq instruction, which has special
367 value restrictions. */
368 #define RAQ RA + 1
369 { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
370
371 /* The RA field in a D or X form instruction which is an updating
372 load, which means that the RA field may not be zero and may not
373 equal the RT field. */
374 #define RAL RAQ + 1
375 { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
376
377 /* The RA field in an lmw instruction, which has special value
378 restrictions. */
379 #define RAM RAL + 1
380 { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
381
382 /* The RA field in a D or X form instruction which is an updating
383 store or an updating floating point load, which means that the RA
384 field may not be zero. */
385 #define RAS RAM + 1
386 { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
387
388 /* The RB field in an X, XO, M, or MDS form instruction. */
389 #define RB RAS + 1
390 #define RB_MASK (0x1f << 11)
391 { 5, 11, 0, 0, PPC_OPERAND_GPR },
392
393 /* The RB field in an X form instruction when it must be the same as
394 the RS field in the instruction. This is used for extended
395 mnemonics like mr. */
396 #define RBS RB + 1
397 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },
398
399 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
400 instruction or the RT field in a D, DS, X, XFX or XO form
401 instruction. */
402 #define RS RBS + 1
403 #define RT RS
404 #define RT_MASK (0x1f << 21)
405 { 5, 21, 0, 0, PPC_OPERAND_GPR },
406
407 /* The RS field of the DS form stq instruction, which has special
408 value restrictions. */
409 #define RSQ RS + 1
410 { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
411
412 /* The RT field of the DQ form lq instruction, which has special
413 value restrictions. */
414 #define RTQ RSQ + 1
415 { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
416
417 /* The SH field in an X or M form instruction. */
418 #define SH RTQ + 1
419 #define SH_MASK (0x1f << 11)
420 { 5, 11, 0, 0, 0 },
421
422 /* The SH field in an MD form instruction. This is split. */
423 #define SH6 SH + 1
424 #define SH6_MASK ((0x1f << 11) | (1 << 1))
425 { 6, 1, insert_sh6, extract_sh6, 0 },
426
427 /* The SI field in a D form instruction. */
428 #define SI SH6 + 1
429 { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
430
431 /* The SI field in a D form instruction when we accept a wide range
432 of positive values. */
433 #define SISIGNOPT SI + 1
434 { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
435
436 /* The SPR field in an XFX form instruction. This is flipped--the
437 lower 5 bits are stored in the upper 5 and vice- versa. */
438 #define SPR SISIGNOPT + 1
439 #define PMR SPR
440 #define SPR_MASK (0x3ff << 11)
441 { 10, 11, insert_spr, extract_spr, 0 },
442
443 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */
444 #define SPRBAT SPR + 1
445 #define SPRBAT_MASK (0x3 << 17)
446 { 2, 17, 0, 0, 0 },
447
448 /* The SPRG register number in an XFX form m[ft]sprg instruction. */
449 #define SPRG SPRBAT + 1
450 #define SPRG_MASK (0x3 << 16)
451 { 2, 16, 0, 0, 0 },
452
453 /* The SR field in an X form instruction. */
454 #define SR SPRG + 1
455 { 4, 16, 0, 0, 0 },
456
457 /* The STRM field in an X AltiVec form instruction. */
458 #define STRM SR + 1
459 #define STRM_MASK (0x3 << 21)
460 { 2, 21, 0, 0, 0 },
461
462 /* The SV field in a POWER SC form instruction. */
463 #define SV STRM + 1
464 { 14, 2, 0, 0, 0 },
465
466 /* The TBR field in an XFX form instruction. This is like the SPR
467 field, but it is optional. */
468 #define TBR SV + 1
469 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },
470
471 /* The TO field in a D or X form instruction. */
472 #define TO TBR + 1
473 #define TO_MASK (0x1f << 21)
474 { 5, 21, 0, 0, 0 },
475
476 /* The U field in an X form instruction. */
477 #define U TO + 1
478 { 4, 12, 0, 0, 0 },
479
480 /* The UI field in a D form instruction. */
481 #define UI U + 1
482 { 16, 0, 0, 0, 0 },
483
484 /* The VA field in a VA, VX or VXR form instruction. */
485 #define VA UI + 1
486 #define VA_MASK (0x1f << 16)
487 { 5, 16, 0, 0, PPC_OPERAND_VR },
488
489 /* The VB field in a VA, VX or VXR form instruction. */
490 #define VB VA + 1
491 #define VB_MASK (0x1f << 11)
492 { 5, 11, 0, 0, PPC_OPERAND_VR },
493
494 /* The VC field in a VA form instruction. */
495 #define VC VB + 1
496 #define VC_MASK (0x1f << 6)
497 { 5, 6, 0, 0, PPC_OPERAND_VR },
498
499 /* The VD or VS field in a VA, VX, VXR or X form instruction. */
500 #define VD VC + 1
501 #define VS VD
502 #define VD_MASK (0x1f << 21)
503 { 5, 21, 0, 0, PPC_OPERAND_VR },
504
505 /* The SIMM field in a VX form instruction. */
506 #define SIMM VD + 1
507 { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
508
509 /* The UIMM field in a VX form instruction. */
510 #define UIMM SIMM + 1
511 { 5, 16, 0, 0, 0 },
512
513 /* The SHB field in a VA form instruction. */
514 #define SHB UIMM + 1
515 { 4, 6, 0, 0, 0 },
516
517 /* The other UIMM field in a EVX form instruction. */
518 #define EVUIMM SHB + 1
519 { 5, 11, 0, 0, 0 },
520
521 /* The other UIMM field in a half word EVX form instruction. */
522 #define EVUIMM_2 EVUIMM + 1
523 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
524
525 /* The other UIMM field in a word EVX form instruction. */
526 #define EVUIMM_4 EVUIMM_2 + 1
527 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
528
529 /* The other UIMM field in a double EVX form instruction. */
530 #define EVUIMM_8 EVUIMM_4 + 1
531 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
532
533 /* The WS field. */
534 #define WS EVUIMM_8 + 1
535 #define WS_MASK (0x7 << 11)
536 { 3, 11, 0, 0, 0 },
537
538 /* The L field in an mtmsrd instruction */
539 #define MTMSRD_L WS + 1
540 { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
541
542 };
543
544 /* The functions used to insert and extract complicated operands. */
545
546 /* The BA field in an XL form instruction when it must be the same as
547 the BT field in the same instruction. This operand is marked FAKE.
548 The insertion function just copies the BT field into the BA field,
549 and the extraction function just checks that the fields are the
550 same. */
551
552 /*ARGSUSED*/
553 static unsigned long
554 insert_bat (unsigned long insn,
555 long value ATTRIBUTE_UNUSED,
556 int dialect ATTRIBUTE_UNUSED,
557 const char **errmsg ATTRIBUTE_UNUSED)
558 {
559 return insn | (((insn >> 21) & 0x1f) << 16);
560 }
561
562 static long
563 extract_bat (unsigned long insn,
564 int dialect ATTRIBUTE_UNUSED,
565 int *invalid)
566 {
567 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
568 *invalid = 1;
569 return 0;
570 }
571
572 /* The BB field in an XL form instruction when it must be the same as
573 the BA field in the same instruction. This operand is marked FAKE.
574 The insertion function just copies the BA field into the BB field,
575 and the extraction function just checks that the fields are the
576 same. */
577
578 /*ARGSUSED*/
579 static unsigned long
580 insert_bba (unsigned long insn,
581 long value ATTRIBUTE_UNUSED,
582 int dialect ATTRIBUTE_UNUSED,
583 const char **errmsg ATTRIBUTE_UNUSED)
584 {
585 return insn | (((insn >> 16) & 0x1f) << 11);
586 }
587
588 static long
589 extract_bba (unsigned long insn,
590 int dialect ATTRIBUTE_UNUSED,
591 int *invalid)
592 {
593 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
594 *invalid = 1;
595 return 0;
596 }
597
598 /* The BD field in a B form instruction. The lower two bits are
599 forced to zero. */
600
601 /*ARGSUSED*/
602 static unsigned long
603 insert_bd (unsigned long insn,
604 long value,
605 int dialect ATTRIBUTE_UNUSED,
606 const char **errmsg ATTRIBUTE_UNUSED)
607 {
608 return insn | (value & 0xfffc);
609 }
610
611 /*ARGSUSED*/
612 static long
613 extract_bd (unsigned long insn,
614 int dialect ATTRIBUTE_UNUSED,
615 int *invalid ATTRIBUTE_UNUSED)
616 {
617 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
618 }
619
620 /* The BD field in a B form instruction when the - modifier is used.
621 This modifier means that the branch is not expected to be taken.
622 For chips built to versions of the architecture prior to version 2
623 (ie. not Power4 compatible), we set the y bit of the BO field to 1
624 if the offset is negative. When extracting, we require that the y
625 bit be 1 and that the offset be positive, since if the y bit is 0
626 we just want to print the normal form of the instruction.
627 Power4 compatible targets use two bits, "a", and "t", instead of
628 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable,
629 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001
630 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
631 for branch on CTR. We only handle the taken/not-taken hint here. */
632
633 /*ARGSUSED*/
634 static unsigned long
635 insert_bdm (unsigned long insn,
636 long value,
637 int dialect,
638 const char **errmsg ATTRIBUTE_UNUSED)
639 {
640 if ((dialect & PPC_OPCODE_POWER4) == 0)
641 {
642 if ((value & 0x8000) != 0)
643 insn |= 1 << 21;
644 }
645 else
646 {
647 if ((insn & (0x14 << 21)) == (0x04 << 21))
648 insn |= 0x02 << 21;
649 else if ((insn & (0x14 << 21)) == (0x10 << 21))
650 insn |= 0x08 << 21;
651 }
652 return insn | (value & 0xfffc);
653 }
654
655 static long
656 extract_bdm (unsigned long insn,
657 int dialect,
658 int *invalid)
659 {
660 if ((dialect & PPC_OPCODE_POWER4) == 0)
661 {
662 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
663 *invalid = 1;
664 }
665 else
666 {
667 if ((insn & (0x17 << 21)) != (0x06 << 21)
668 && (insn & (0x1d << 21)) != (0x18 << 21))
669 *invalid = 1;
670 }
671
672 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
673 }
674
675 /* The BD field in a B form instruction when the + modifier is used.
676 This is like BDM, above, except that the branch is expected to be
677 taken. */
678
679 /*ARGSUSED*/
680 static unsigned long
681 insert_bdp (unsigned long insn,
682 long value,
683 int dialect,
684 const char **errmsg ATTRIBUTE_UNUSED)
685 {
686 if ((dialect & PPC_OPCODE_POWER4) == 0)
687 {
688 if ((value & 0x8000) == 0)
689 insn |= 1 << 21;
690 }
691 else
692 {
693 if ((insn & (0x14 << 21)) == (0x04 << 21))
694 insn |= 0x03 << 21;
695 else if ((insn & (0x14 << 21)) == (0x10 << 21))
696 insn |= 0x09 << 21;
697 }
698 return insn | (value & 0xfffc);
699 }
700
701 static long
702 extract_bdp (unsigned long insn,
703 int dialect,
704 int *invalid)
705 {
706 if ((dialect & PPC_OPCODE_POWER4) == 0)
707 {
708 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
709 *invalid = 1;
710 }
711 else
712 {
713 if ((insn & (0x17 << 21)) != (0x07 << 21)
714 && (insn & (0x1d << 21)) != (0x19 << 21))
715 *invalid = 1;
716 }
717
718 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
719 }
720
721 /* Check for legal values of a BO field. */
722
723 static int
724 valid_bo (long value, int dialect)
725 {
726 if ((dialect & PPC_OPCODE_POWER4) == 0)
727 {
728 /* Certain encodings have bits that are required to be zero.
729 These are (z must be zero, y may be anything):
730 001zy
731 011zy
732 1z00y
733 1z01y
734 1z1zz
735 */
736 switch (value & 0x14)
737 {
738 default:
739 case 0:
740 return 1;
741 case 0x4:
742 return (value & 0x2) == 0;
743 case 0x10:
744 return (value & 0x8) == 0;
745 case 0x14:
746 return value == 0x14;
747 }
748 }
749 else
750 {
751 /* Certain encodings have bits that are required to be zero.
752 These are (z must be zero, a & t may be anything):
753 0000z
754 0001z
755 0100z
756 0101z
757 001at
758 011at
759 1a00t
760 1a01t
761 1z1zz
762 */
763 if ((value & 0x14) == 0)
764 return (value & 0x1) == 0;
765 else if ((value & 0x14) == 0x14)
766 return value == 0x14;
767 else
768 return 1;
769 }
770 }
771
772 /* The BO field in a B form instruction. Warn about attempts to set
773 the field to an illegal value. */
774
775 static unsigned long
776 insert_bo (unsigned long insn,
777 long value,
778 int dialect,
779 const char **errmsg)
780 {
781 if (!valid_bo (value, dialect))
782 *errmsg = _("invalid conditional option");
783 return insn | ((value & 0x1f) << 21);
784 }
785
786 static long
787 extract_bo (unsigned long insn,
788 int dialect,
789 int *invalid)
790 {
791 long value;
792
793 value = (insn >> 21) & 0x1f;
794 if (!valid_bo (value, dialect))
795 *invalid = 1;
796 return value;
797 }
798
799 /* The BO field in a B form instruction when the + or - modifier is
800 used. This is like the BO field, but it must be even. When
801 extracting it, we force it to be even. */
802
803 static unsigned long
804 insert_boe (unsigned long insn,
805 long value,
806 int dialect,
807 const char **errmsg)
808 {
809 if (!valid_bo (value, dialect))
810 *errmsg = _("invalid conditional option");
811 else if ((value & 1) != 0)
812 *errmsg = _("attempt to set y bit when using + or - modifier");
813
814 return insn | ((value & 0x1f) << 21);
815 }
816
817 static long
818 extract_boe (unsigned long insn,
819 int dialect,
820 int *invalid)
821 {
822 long value;
823
824 value = (insn >> 21) & 0x1f;
825 if (!valid_bo (value, dialect))
826 *invalid = 1;
827 return value & 0x1e;
828 }
829
830 /* The DQ field in a DQ form instruction. This is like D, but the
831 lower four bits are forced to zero. */
832
833 /*ARGSUSED*/
834 static unsigned long
835 insert_dq (unsigned long insn,
836 long value,
837 int dialect ATTRIBUTE_UNUSED,
838 const char **errmsg)
839 {
840 if ((value & 0xf) != 0)
841 *errmsg = _("offset not a multiple of 16");
842 return insn | (value & 0xfff0);
843 }
844
845 /*ARGSUSED*/
846 static long
847 extract_dq (unsigned long insn,
848 int dialect ATTRIBUTE_UNUSED,
849 int *invalid ATTRIBUTE_UNUSED)
850 {
851 return ((insn & 0xfff0) ^ 0x8000) - 0x8000;
852 }
853
854 static unsigned long
855 insert_ev2 (unsigned long insn,
856 long value,
857 int dialect ATTRIBUTE_UNUSED,
858 const char **errmsg)
859 {
860 if ((value & 1) != 0)
861 *errmsg = _("offset not a multiple of 2");
862 if ((value > 62) != 0)
863 *errmsg = _("offset greater than 62");
864 return insn | ((value & 0x3e) << 10);
865 }
866
867 static long
868 extract_ev2 (unsigned long insn,
869 int dialect ATTRIBUTE_UNUSED,
870 int *invalid ATTRIBUTE_UNUSED)
871 {
872 return (insn >> 10) & 0x3e;
873 }
874
875 static unsigned long
876 insert_ev4 (unsigned long insn,
877 long value,
878 int dialect ATTRIBUTE_UNUSED,
879 const char **errmsg)
880 {
881 if ((value & 3) != 0)
882 *errmsg = _("offset not a multiple of 4");
883 if ((value > 124) != 0)
884 *errmsg = _("offset greater than 124");
885 return insn | ((value & 0x7c) << 9);
886 }
887
888 static long
889 extract_ev4 (unsigned long insn,
890 int dialect ATTRIBUTE_UNUSED,
891 int *invalid ATTRIBUTE_UNUSED)
892 {
893 return (insn >> 9) & 0x7c;
894 }
895
896 static unsigned long
897 insert_ev8 (unsigned long insn,
898 long value,
899 int dialect ATTRIBUTE_UNUSED,
900 const char **errmsg)
901 {
902 if ((value & 7) != 0)
903 *errmsg = _("offset not a multiple of 8");
904 if ((value > 248) != 0)
905 *errmsg = _("offset greater than 248");
906 return insn | ((value & 0xf8) << 8);
907 }
908
909 static long
910 extract_ev8 (unsigned long insn,
911 int dialect ATTRIBUTE_UNUSED,
912 int *invalid ATTRIBUTE_UNUSED)
913 {
914 return (insn >> 8) & 0xf8;
915 }
916
917 /* The DS field in a DS form instruction. This is like D, but the
918 lower two bits are forced to zero. */
919
920 /*ARGSUSED*/
921 static unsigned long
922 insert_ds (unsigned long insn,
923 long value,
924 int dialect ATTRIBUTE_UNUSED,
925 const char **errmsg)
926 {
927 if ((value & 3) != 0)
928 *errmsg = _("offset not a multiple of 4");
929 return insn | (value & 0xfffc);
930 }
931
932 /*ARGSUSED*/
933 static long
934 extract_ds (unsigned long insn,
935 int dialect ATTRIBUTE_UNUSED,
936 int *invalid ATTRIBUTE_UNUSED)
937 {
938 return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
939 }
940
941 /* The DE field in a DE form instruction. */
942
943 /*ARGSUSED*/
944 static unsigned long
945 insert_de (unsigned long insn,
946 long value,
947 int dialect ATTRIBUTE_UNUSED,
948 const char **errmsg)
949 {
950 if (value > 2047 || value < -2048)
951 *errmsg = _("offset not between -2048 and 2047");
952 return insn | ((value << 4) & 0xfff0);
953 }
954
955 /*ARGSUSED*/
956 static long
957 extract_de (unsigned long insn,
958 int dialect ATTRIBUTE_UNUSED,
959 int *invalid ATTRIBUTE_UNUSED)
960 {
961 return (insn & 0xfff0) >> 4;
962 }
963
964 /* The DES field in a DES form instruction. */
965
966 /*ARGSUSED*/
967 static unsigned long
968 insert_des (unsigned long insn,
969 long value,
970 int dialect ATTRIBUTE_UNUSED,
971 const char **errmsg)
972 {
973 if (value > 8191 || value < -8192)
974 *errmsg = _("offset not between -8192 and 8191");
975 else if ((value & 3) != 0)
976 *errmsg = _("offset not a multiple of 4");
977 return insn | ((value << 2) & 0xfff0);
978 }
979
980 /*ARGSUSED*/
981 static long
982 extract_des (unsigned long insn,
983 int dialect ATTRIBUTE_UNUSED,
984 int *invalid ATTRIBUTE_UNUSED)
985 {
986 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000;
987 }
988
989 /* FXM mask in mfcr and mtcrf instructions. */
990
991 static unsigned long
992 insert_fxm (unsigned long insn,
993 long value,
994 int dialect,
995 const char **errmsg)
996 {
997 /* If the optional field on mfcr is missing that means we want to use
998 the old form of the instruction that moves the whole cr. In that
999 case we'll have VALUE zero. There doesn't seem to be a way to
1000 distinguish this from the case where someone writes mfcr %r3,0. */
1001 if (value == 0)
1002 ;
1003
1004 /* If only one bit of the FXM field is set, we can use the new form
1005 of the instruction, which is faster. Unlike the Power4 branch hint
1006 encoding, this is not backward compatible. */
1007 else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
1008 insn |= 1 << 20;
1009
1010 /* Any other value on mfcr is an error. */
1011 else if ((insn & (0x3ff << 1)) == 19 << 1)
1012 {
1013 *errmsg = _("ignoring invalid mfcr mask");
1014 value = 0;
1015 }
1016
1017 return insn | ((value & 0xff) << 12);
1018 }
1019
1020 static long
1021 extract_fxm (unsigned long insn,
1022 int dialect,
1023 int *invalid)
1024 {
1025 long mask = (insn >> 12) & 0xff;
1026
1027 /* Is this a Power4 insn? */
1028 if ((insn & (1 << 20)) != 0)
1029 {
1030 if ((dialect & PPC_OPCODE_POWER4) == 0)
1031 *invalid = 1;
1032 else
1033 {
1034 /* Exactly one bit of MASK should be set. */
1035 if (mask == 0 || (mask & -mask) != mask)
1036 *invalid = 1;
1037 }
1038 }
1039
1040 /* Check that non-power4 form of mfcr has a zero MASK. */
1041 else if ((insn & (0x3ff << 1)) == 19 << 1)
1042 {
1043 if (mask != 0)
1044 *invalid = 1;
1045 }
1046
1047 return mask;
1048 }
1049
1050 /* The LI field in an I form instruction. The lower two bits are
1051 forced to zero. */
1052
1053 /*ARGSUSED*/
1054 static unsigned long
1055 insert_li (unsigned long insn,
1056 long value,
1057 int dialect ATTRIBUTE_UNUSED,
1058 const char **errmsg)
1059 {
1060 if ((value & 3) != 0)
1061 *errmsg = _("ignoring least significant bits in branch offset");
1062 return insn | (value & 0x3fffffc);
1063 }
1064
1065 /*ARGSUSED*/
1066 static long
1067 extract_li (unsigned long insn,
1068 int dialect ATTRIBUTE_UNUSED,
1069 int *invalid ATTRIBUTE_UNUSED)
1070 {
1071 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000;
1072 }
1073
1074 /* The MB and ME fields in an M form instruction expressed as a single
1075 operand which is itself a bitmask. The extraction function always
1076 marks it as invalid, since we never want to recognize an
1077 instruction which uses a field of this type. */
1078
1079 static unsigned long
1080 insert_mbe (unsigned long insn,
1081 long value,
1082 int dialect ATTRIBUTE_UNUSED,
1083 const char **errmsg)
1084 {
1085 unsigned long uval, mask;
1086 int mb, me, mx, count, last;
1087
1088 uval = value;
1089
1090 if (uval == 0)
1091 {
1092 *errmsg = _("illegal bitmask");
1093 return insn;
1094 }
1095
1096 mb = 0;
1097 me = 32;
1098 if ((uval & 1) != 0)
1099 last = 1;
1100 else
1101 last = 0;
1102 count = 0;
1103
1104 /* mb: location of last 0->1 transition */
1105 /* me: location of last 1->0 transition */
1106 /* count: # transitions */
1107
1108 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
1109 {
1110 if ((uval & mask) && !last)
1111 {
1112 ++count;
1113 mb = mx;
1114 last = 1;
1115 }
1116 else if (!(uval & mask) && last)
1117 {
1118 ++count;
1119 me = mx;
1120 last = 0;
1121 }
1122 }
1123 if (me == 0)
1124 me = 32;
1125
1126 if (count != 2 && (count != 0 || ! last))
1127 *errmsg = _("illegal bitmask");
1128
1129 return insn | (mb << 6) | ((me - 1) << 1);
1130 }
1131
1132 static long
1133 extract_mbe (unsigned long insn,
1134 int dialect ATTRIBUTE_UNUSED,
1135 int *invalid)
1136 {
1137 long ret;
1138 int mb, me;
1139 int i;
1140
1141 *invalid = 1;
1142
1143 mb = (insn >> 6) & 0x1f;
1144 me = (insn >> 1) & 0x1f;
1145 if (mb < me + 1)
1146 {
1147 ret = 0;
1148 for (i = mb; i <= me; i++)
1149 ret |= 1L << (31 - i);
1150 }
1151 else if (mb == me + 1)
1152 ret = ~0;
1153 else /* (mb > me + 1) */
1154 {
1155 ret = ~0;
1156 for (i = me + 1; i < mb; i++)
1157 ret &= ~(1L << (31 - i));
1158 }
1159 return ret;
1160 }
1161
1162 /* The MB or ME field in an MD or MDS form instruction. The high bit
1163 is wrapped to the low end. */
1164
1165 /*ARGSUSED*/
1166 static unsigned long
1167 insert_mb6 (unsigned long insn,
1168 long value,
1169 int dialect ATTRIBUTE_UNUSED,
1170 const char **errmsg ATTRIBUTE_UNUSED)
1171 {
1172 return insn | ((value & 0x1f) << 6) | (value & 0x20);
1173 }
1174
1175 /*ARGSUSED*/
1176 static long
1177 extract_mb6 (unsigned long insn,
1178 int dialect ATTRIBUTE_UNUSED,
1179 int *invalid ATTRIBUTE_UNUSED)
1180 {
1181 return ((insn >> 6) & 0x1f) | (insn & 0x20);
1182 }
1183
1184 /* The NB field in an X form instruction. The value 32 is stored as
1185 0. */
1186
1187 static unsigned long
1188 insert_nb (unsigned long insn,
1189 long value,
1190 int dialect ATTRIBUTE_UNUSED,
1191 const char **errmsg)
1192 {
1193 if (value < 0 || value > 32)
1194 *errmsg = _("value out of range");
1195 if (value == 32)
1196 value = 0;
1197 return insn | ((value & 0x1f) << 11);
1198 }
1199
1200 /*ARGSUSED*/
1201 static long
1202 extract_nb (unsigned long insn,
1203 int dialect ATTRIBUTE_UNUSED,
1204 int *invalid ATTRIBUTE_UNUSED)
1205 {
1206 long ret;
1207
1208 ret = (insn >> 11) & 0x1f;
1209 if (ret == 0)
1210 ret = 32;
1211 return ret;
1212 }
1213
1214 /* The NSI field in a D form instruction. This is the same as the SI
1215 field, only negated. The extraction function always marks it as
1216 invalid, since we never want to recognize an instruction which uses
1217 a field of this type. */
1218
1219 /*ARGSUSED*/
1220 static unsigned long
1221 insert_nsi (unsigned long insn,
1222 long value,
1223 int dialect ATTRIBUTE_UNUSED,
1224 const char **errmsg ATTRIBUTE_UNUSED)
1225 {
1226 return insn | (-value & 0xffff);
1227 }
1228
1229 static long
1230 extract_nsi (unsigned long insn,
1231 int dialect ATTRIBUTE_UNUSED,
1232 int *invalid)
1233 {
1234 *invalid = 1;
1235 return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
1236 }
1237
1238 /* The RA field in a D or X form instruction which is an updating
1239 load, which means that the RA field may not be zero and may not
1240 equal the RT field. */
1241
1242 static unsigned long
1243 insert_ral (unsigned long insn,
1244 long value,
1245 int dialect ATTRIBUTE_UNUSED,
1246 const char **errmsg)
1247 {
1248 if (value == 0
1249 || (unsigned long) value == ((insn >> 21) & 0x1f))
1250 *errmsg = "invalid register operand when updating";
1251 return insn | ((value & 0x1f) << 16);
1252 }
1253
1254 /* The RA field in an lmw instruction, which has special value
1255 restrictions. */
1256
1257 static unsigned long
1258 insert_ram (unsigned long insn,
1259 long value,
1260 int dialect ATTRIBUTE_UNUSED,
1261 const char **errmsg)
1262 {
1263 if ((unsigned long) value >= ((insn >> 21) & 0x1f))
1264 *errmsg = _("index register in load range");
1265 return insn | ((value & 0x1f) << 16);
1266 }
1267
1268 /* The RA field in the DQ form lq instruction, which has special
1269 value restrictions. */
1270
1271 /*ARGSUSED*/
1272 static unsigned long
1273 insert_raq (unsigned long insn,
1274 long value,
1275 int dialect ATTRIBUTE_UNUSED,
1276 const char **errmsg)
1277 {
1278 long rtvalue = (insn & RT_MASK) >> 21;
1279
1280 if (value == rtvalue)
1281 *errmsg = _("source and target register operands must be different");
1282 return insn | ((value & 0x1f) << 16);
1283 }
1284
1285 /* The RA field in a D or X form instruction which is an updating
1286 store or an updating floating point load, which means that the RA
1287 field may not be zero. */
1288
1289 static unsigned long
1290 insert_ras (unsigned long insn,
1291 long value,
1292 int dialect ATTRIBUTE_UNUSED,
1293 const char **errmsg)
1294 {
1295 if (value == 0)
1296 *errmsg = _("invalid register operand when updating");
1297 return insn | ((value & 0x1f) << 16);
1298 }
1299
1300 /* The RB field in an X form instruction when it must be the same as
1301 the RS field in the instruction. This is used for extended
1302 mnemonics like mr. This operand is marked FAKE. The insertion
1303 function just copies the BT field into the BA field, and the
1304 extraction function just checks that the fields are the same. */
1305
1306 /*ARGSUSED*/
1307 static unsigned long
1308 insert_rbs (unsigned long insn,
1309 long value ATTRIBUTE_UNUSED,
1310 int dialect ATTRIBUTE_UNUSED,
1311 const char **errmsg ATTRIBUTE_UNUSED)
1312 {
1313 return insn | (((insn >> 21) & 0x1f) << 11);
1314 }
1315
1316 static long
1317 extract_rbs (unsigned long insn,
1318 int dialect ATTRIBUTE_UNUSED,
1319 int *invalid)
1320 {
1321 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
1322 *invalid = 1;
1323 return 0;
1324 }
1325
1326 /* The RT field of the DQ form lq instruction, which has special
1327 value restrictions. */
1328
1329 /*ARGSUSED*/
1330 static unsigned long
1331 insert_rtq (unsigned long insn,
1332 long value,
1333 int dialect ATTRIBUTE_UNUSED,
1334 const char **errmsg)
1335 {
1336 if ((value & 1) != 0)
1337 *errmsg = _("target register operand must be even");
1338 return insn | ((value & 0x1f) << 21);
1339 }
1340
1341 /* The RS field of the DS form stq instruction, which has special
1342 value restrictions. */
1343
1344 /*ARGSUSED*/
1345 static unsigned long
1346 insert_rsq (unsigned long insn,
1347 long value ATTRIBUTE_UNUSED,
1348 int dialect ATTRIBUTE_UNUSED,
1349 const char **errmsg)
1350 {
1351 if ((value & 1) != 0)
1352 *errmsg = _("source register operand must be even");
1353 return insn | ((value & 0x1f) << 21);
1354 }
1355
1356 /* The SH field in an MD form instruction. This is split. */
1357
1358 /*ARGSUSED*/
1359 static unsigned long
1360 insert_sh6 (unsigned long insn,
1361 long value,
1362 int dialect ATTRIBUTE_UNUSED,
1363 const char **errmsg ATTRIBUTE_UNUSED)
1364 {
1365 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
1366 }
1367
1368 /*ARGSUSED*/
1369 static long
1370 extract_sh6 (unsigned long insn,
1371 int dialect ATTRIBUTE_UNUSED,
1372 int *invalid ATTRIBUTE_UNUSED)
1373 {
1374 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
1375 }
1376
1377 /* The SPR field in an XFX form instruction. This is flipped--the
1378 lower 5 bits are stored in the upper 5 and vice- versa. */
1379
1380 static unsigned long
1381 insert_spr (unsigned long insn,
1382 long value,
1383 int dialect ATTRIBUTE_UNUSED,
1384 const char **errmsg ATTRIBUTE_UNUSED)
1385 {
1386 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1387 }
1388
1389 static long
1390 extract_spr (unsigned long insn,
1391 int dialect ATTRIBUTE_UNUSED,
1392 int *invalid ATTRIBUTE_UNUSED)
1393 {
1394 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1395 }
1396
1397 /* The TBR field in an XFX instruction. This is just like SPR, but it
1398 is optional. When TBR is omitted, it must be inserted as 268 (the
1399 magic number of the TB register). These functions treat 0
1400 (indicating an omitted optional operand) as 268. This means that
1401 ``mftb 4,0'' is not handled correctly. This does not matter very
1402 much, since the architecture manual does not define mftb as
1403 accepting any values other than 268 or 269. */
1404
1405 #define TB (268)
1406
1407 static unsigned long
1408 insert_tbr (unsigned long insn,
1409 long value,
1410 int dialect ATTRIBUTE_UNUSED,
1411 const char **errmsg ATTRIBUTE_UNUSED)
1412 {
1413 if (value == 0)
1414 value = TB;
1415 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
1416 }
1417
1418 static long
1419 extract_tbr (unsigned long insn,
1420 int dialect ATTRIBUTE_UNUSED,
1421 int *invalid ATTRIBUTE_UNUSED)
1422 {
1423 long ret;
1424
1425 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
1426 if (ret == TB)
1427 ret = 0;
1428 return ret;
1429 }
1430 \f
1431 /* Macros used to form opcodes. */
1432
1433 /* The main opcode. */
1434 #define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
1435 #define OP_MASK OP (0x3f)
1436
1437 /* The main opcode combined with a trap code in the TO field of a D
1438 form instruction. Used for extended mnemonics for the trap
1439 instructions. */
1440 #define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
1441 #define OPTO_MASK (OP_MASK | TO_MASK)
1442
1443 /* The main opcode combined with a comparison size bit in the L field
1444 of a D form or X form instruction. Used for extended mnemonics for
1445 the comparison instructions. */
1446 #define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
1447 #define OPL_MASK OPL (0x3f,1)
1448
1449 /* An A form instruction. */
1450 #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
1451 #define A_MASK A (0x3f, 0x1f, 1)
1452
1453 /* An A_MASK with the FRB field fixed. */
1454 #define AFRB_MASK (A_MASK | FRB_MASK)
1455
1456 /* An A_MASK with the FRC field fixed. */
1457 #define AFRC_MASK (A_MASK | FRC_MASK)
1458
1459 /* An A_MASK with the FRA and FRC fields fixed. */
1460 #define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)
1461
1462 /* A B form instruction. */
1463 #define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
1464 #define B_MASK B (0x3f, 1, 1)
1465
1466 /* A B form instruction setting the BO field. */
1467 #define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1468 #define BBO_MASK BBO (0x3f, 0x1f, 1, 1)
1469
1470 /* A BBO_MASK with the y bit of the BO field removed. This permits
1471 matching a conditional branch regardless of the setting of the y
1472 bit. Similarly for the 'at' bits used for power4 branch hints. */
1473 #define Y_MASK (((unsigned long) 1) << 21)
1474 #define AT1_MASK (((unsigned long) 3) << 21)
1475 #define AT2_MASK (((unsigned long) 9) << 21)
1476 #define BBOY_MASK (BBO_MASK &~ Y_MASK)
1477 #define BBOAT_MASK (BBO_MASK &~ AT1_MASK)
1478
1479 /* A B form instruction setting the BO field and the condition bits of
1480 the BI field. */
1481 #define BBOCB(op, bo, cb, aa, lk) \
1482 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
1483 #define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)
1484
1485 /* A BBOCB_MASK with the y bit of the BO field removed. */
1486 #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
1487 #define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
1488 #define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)
1489
1490 /* A BBOYCB_MASK in which the BI field is fixed. */
1491 #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
1492 #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)
1493
1494 /* An Context form instruction. */
1495 #define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7))
1496 #define CTX_MASK CTX(0x3f, 0x7)
1497
1498 /* An User Context form instruction. */
1499 #define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1500 #define UCTX_MASK UCTX(0x3f, 0x1f)
1501
1502 /* The main opcode mask with the RA field clear. */
1503 #define DRA_MASK (OP_MASK | RA_MASK)
1504
1505 /* A DS form instruction. */
1506 #define DSO(op, xop) (OP (op) | ((xop) & 0x3))
1507 #define DS_MASK DSO (0x3f, 3)
1508
1509 /* A DE form instruction. */
1510 #define DEO(op, xop) (OP (op) | ((xop) & 0xf))
1511 #define DE_MASK DEO (0x3e, 0xf)
1512
1513 /* An EVSEL form instruction. */
1514 #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
1515 #define EVSEL_MASK EVSEL(0x3f, 0xff)
1516
1517 /* An M form instruction. */
1518 #define M(op, rc) (OP (op) | ((rc) & 1))
1519 #define M_MASK M (0x3f, 1)
1520
1521 /* An M form instruction with the ME field specified. */
1522 #define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))
1523
1524 /* An M_MASK with the MB and ME fields fixed. */
1525 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
1526
1527 /* An M_MASK with the SH and ME fields fixed. */
1528 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
1529
1530 /* An MD form instruction. */
1531 #define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
1532 #define MD_MASK MD (0x3f, 0x7, 1)
1533
1534 /* An MD_MASK with the MB field fixed. */
1535 #define MDMB_MASK (MD_MASK | MB6_MASK)
1536
1537 /* An MD_MASK with the SH field fixed. */
1538 #define MDSH_MASK (MD_MASK | SH6_MASK)
1539
1540 /* An MDS form instruction. */
1541 #define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
1542 #define MDS_MASK MDS (0x3f, 0xf, 1)
1543
1544 /* An MDS_MASK with the MB field fixed. */
1545 #define MDSMB_MASK (MDS_MASK | MB6_MASK)
1546
1547 /* An SC form instruction. */
1548 #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
1549 #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
1550
1551 /* An VX form instruction. */
1552 #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
1553
1554 /* The mask for an VX form instruction. */
1555 #define VX_MASK VX(0x3f, 0x7ff)
1556
1557 /* An VA form instruction. */
1558 #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
1559
1560 /* The mask for an VA form instruction. */
1561 #define VXA_MASK VXA(0x3f, 0x3f)
1562
1563 /* An VXR form instruction. */
1564 #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
1565
1566 /* The mask for a VXR form instruction. */
1567 #define VXR_MASK VXR(0x3f, 0x3ff, 1)
1568
1569 /* An X form instruction. */
1570 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1571
1572 /* An X form instruction with the RC bit specified. */
1573 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
1574
1575 /* The mask for an X form instruction. */
1576 #define X_MASK XRC (0x3f, 0x3ff, 1)
1577
1578 /* An X_MASK with the RA field fixed. */
1579 #define XRA_MASK (X_MASK | RA_MASK)
1580
1581 /* An X_MASK with the RB field fixed. */
1582 #define XRB_MASK (X_MASK | RB_MASK)
1583
1584 /* An X_MASK with the RT field fixed. */
1585 #define XRT_MASK (X_MASK | RT_MASK)
1586
1587 /* An X_MASK with the RA and RB fields fixed. */
1588 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
1589
1590 /* An XRARB_MASK, but with the L bit clear. */
1591 #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
1592
1593 /* An X_MASK with the RT and RA fields fixed. */
1594 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
1595
1596 /* An XRTRA_MASK, but with L bit clear. */
1597 #define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
1598
1599 /* An X form comparison instruction. */
1600 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
1601
1602 /* The mask for an X form comparison instruction. */
1603 #define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))
1604
1605 /* The mask for an X form comparison instruction with the L field
1606 fixed. */
1607 #define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))
1608
1609 /* An X form trap instruction with the TO field specified. */
1610 #define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
1611 #define XTO_MASK (X_MASK | TO_MASK)
1612
1613 /* An X form tlb instruction with the SH field specified. */
1614 #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
1615 #define XTLB_MASK (X_MASK | SH_MASK)
1616
1617 /* An X form sync instruction. */
1618 #define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))
1619
1620 /* An X form sync instruction with everything filled in except the LS field. */
1621 #define XSYNC_MASK (0xff9fffff)
1622
1623 /* An X form AltiVec dss instruction. */
1624 #define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
1625 #define XDSS_MASK XDSS(0x3f, 0x3ff, 1)
1626
1627 /* An XFL form instruction. */
1628 #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
1629 #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
1630
1631 /* An X form isel instruction. */
1632 #define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
1633 #define XISEL_MASK XISEL(0x3f, 0x1f)
1634
1635 /* An XL form instruction with the LK field set to 0. */
1636 #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
1637
1638 /* An XL form instruction which uses the LK field. */
1639 #define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))
1640
1641 /* The mask for an XL form instruction. */
1642 #define XL_MASK XLLK (0x3f, 0x3ff, 1)
1643
1644 /* An XL form instruction which explicitly sets the BO field. */
1645 #define XLO(op, bo, xop, lk) \
1646 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
1647 #define XLO_MASK (XL_MASK | BO_MASK)
1648
1649 /* An XL form instruction which explicitly sets the y bit of the BO
1650 field. */
1651 #define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
1652 #define XLYLK_MASK (XL_MASK | Y_MASK)
1653
1654 /* An XL form instruction which sets the BO field and the condition
1655 bits of the BI field. */
1656 #define XLOCB(op, bo, cb, xop, lk) \
1657 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
1658 #define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)
1659
1660 /* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */
1661 #define XLBB_MASK (XL_MASK | BB_MASK)
1662 #define XLYBB_MASK (XLYLK_MASK | BB_MASK)
1663 #define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)
1664
1665 /* An XL_MASK with the BO and BB fields fixed. */
1666 #define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)
1667
1668 /* An XL_MASK with the BO, BI and BB fields fixed. */
1669 #define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)
1670
1671 /* An XO form instruction. */
1672 #define XO(op, xop, oe, rc) \
1673 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
1674 #define XO_MASK XO (0x3f, 0x1ff, 1, 1)
1675
1676 /* An XO_MASK with the RB field fixed. */
1677 #define XORB_MASK (XO_MASK | RB_MASK)
1678
1679 /* An XS form instruction. */
1680 #define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
1681 #define XS_MASK XS (0x3f, 0x1ff, 1)
1682
1683 /* A mask for the FXM version of an XFX form instruction. */
1684 #define XFXFXM_MASK (X_MASK | (1 << 11))
1685
1686 /* An XFX form instruction with the FXM field filled in. */
1687 #define XFXM(op, xop, fxm) \
1688 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12))
1689
1690 /* An XFX form instruction with the SPR field filled in. */
1691 #define XSPR(op, xop, spr) \
1692 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
1693 #define XSPR_MASK (X_MASK | SPR_MASK)
1694
1695 /* An XFX form instruction with the SPR field filled in except for the
1696 SPRBAT field. */
1697 #define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)
1698
1699 /* An XFX form instruction with the SPR field filled in except for the
1700 SPRG field. */
1701 #define XSPRG_MASK (XSPR_MASK &~ SPRG_MASK)
1702
1703 /* An X form instruction with everything filled in except the E field. */
1704 #define XE_MASK (0xffff7fff)
1705
1706 /* An X form user context instruction. */
1707 #define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f))
1708 #define XUC_MASK XUC(0x3f, 0x1f)
1709
1710 /* The BO encodings used in extended conditional branch mnemonics. */
1711 #define BODNZF (0x0)
1712 #define BODNZFP (0x1)
1713 #define BODZF (0x2)
1714 #define BODZFP (0x3)
1715 #define BODNZT (0x8)
1716 #define BODNZTP (0x9)
1717 #define BODZT (0xa)
1718 #define BODZTP (0xb)
1719
1720 #define BOF (0x4)
1721 #define BOFP (0x5)
1722 #define BOFM4 (0x6)
1723 #define BOFP4 (0x7)
1724 #define BOT (0xc)
1725 #define BOTP (0xd)
1726 #define BOTM4 (0xe)
1727 #define BOTP4 (0xf)
1728
1729 #define BODNZ (0x10)
1730 #define BODNZP (0x11)
1731 #define BODZ (0x12)
1732 #define BODZP (0x13)
1733 #define BODNZM4 (0x18)
1734 #define BODNZP4 (0x19)
1735 #define BODZM4 (0x1a)
1736 #define BODZP4 (0x1b)
1737
1738 #define BOU (0x14)
1739
1740 /* The BI condition bit encodings used in extended conditional branch
1741 mnemonics. */
1742 #define CBLT (0)
1743 #define CBGT (1)
1744 #define CBEQ (2)
1745 #define CBSO (3)
1746
1747 /* The TO encodings used in extended trap mnemonics. */
1748 #define TOLGT (0x1)
1749 #define TOLLT (0x2)
1750 #define TOEQ (0x4)
1751 #define TOLGE (0x5)
1752 #define TOLNL (0x5)
1753 #define TOLLE (0x6)
1754 #define TOLNG (0x6)
1755 #define TOGT (0x8)
1756 #define TOGE (0xc)
1757 #define TONL (0xc)
1758 #define TOLT (0x10)
1759 #define TOLE (0x14)
1760 #define TONG (0x14)
1761 #define TONE (0x18)
1762 #define TOU (0x1f)
1763 \f
1764 /* Smaller names for the flags so each entry in the opcodes table will
1765 fit on a single line. */
1766 #undef PPC
1767 #define PPC PPC_OPCODE_PPC
1768 #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1769 #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
1770 #define POWER4 PPC_OPCODE_POWER4
1771 #define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
1772 #define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
1773 #define PPC403 PPC_OPCODE_403
1774 #define PPC405 PPC403
1775 #define PPC440 PPC_OPCODE_440
1776 #define PPC750 PPC
1777 #define PPC860 PPC
1778 #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
1779 #define POWER PPC_OPCODE_POWER
1780 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1781 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
1782 #define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
1783 #define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
1784 #define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
1785 #define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
1786 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
1787 #define MFDEC1 PPC_OPCODE_POWER
1788 #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
1789 #define BOOKE PPC_OPCODE_BOOKE
1790 #define BOOKE64 PPC_OPCODE_BOOKE64
1791 #define CLASSIC PPC_OPCODE_CLASSIC
1792 #define PPCSPE PPC_OPCODE_SPE
1793 #define PPCISEL PPC_OPCODE_ISEL
1794 #define PPCEFS PPC_OPCODE_EFS
1795 #define PPCBRLK PPC_OPCODE_BRLOCK
1796 #define PPCPMR PPC_OPCODE_PMR
1797 #define PPCCHLK PPC_OPCODE_CACHELCK
1798 #define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
1799 #define PPCRFMCI PPC_OPCODE_RFMCI
1800 \f
1801 /* The opcode table.
1802
1803 The format of the opcode table is:
1804
1805 NAME OPCODE MASK FLAGS { OPERANDS }
1806
1807 NAME is the name of the instruction.
1808 OPCODE is the instruction opcode.
1809 MASK is the opcode mask; this is used to tell the disassembler
1810 which bits in the actual opcode must match OPCODE.
1811 FLAGS are flags indicated what processors support the instruction.
1812 OPERANDS is the list of operands.
1813
1814 The disassembler reads the table in order and prints the first
1815 instruction which matches, so this table is sorted to put more
1816 specific instructions before more general instructions. It is also
1817 sorted by major opcode. */
1818
1819 const struct powerpc_opcode powerpc_opcodes[] = {
1820 { "attn", X(0,256), X_MASK, POWER4, { 0 } },
1821 { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } },
1822 { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } },
1823 { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } },
1824 { "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } },
1825 { "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } },
1826 { "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } },
1827 { "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } },
1828 { "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } },
1829 { "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } },
1830 { "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } },
1831 { "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } },
1832 { "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } },
1833 { "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } },
1834 { "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } },
1835 { "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } },
1836
1837 { "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } },
1838 { "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } },
1839 { "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } },
1840 { "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } },
1841 { "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } },
1842 { "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } },
1843 { "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } },
1844 { "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } },
1845 { "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } },
1846 { "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } },
1847 { "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } },
1848 { "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } },
1849 { "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } },
1850 { "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } },
1851 { "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } },
1852 { "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } },
1853 { "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } },
1854 { "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } },
1855 { "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } },
1856 { "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } },
1857 { "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } },
1858 { "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } },
1859 { "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } },
1860 { "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } },
1861 { "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } },
1862 { "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } },
1863 { "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } },
1864 { "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } },
1865 { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } },
1866 { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } },
1867
1868 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1869 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1870 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1871 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1872 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1873 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1874 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1875 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1876 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1877 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1878 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1879 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1880 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1881 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1882 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1883 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1884 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1885 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1886 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1887 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1888 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1889 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1890 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1891 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1892 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1893 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1894 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1895 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1896 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1897 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1898 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1899 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1900 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1901 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1902 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1903 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1904 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1905 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1906 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1907 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1908 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1909 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1910 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1911 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1912 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1913 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1914 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1915 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1916 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1917 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1918 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1919 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1920 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1921 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1922 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1923 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1924 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1925 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1926 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1927 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
1928 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1929 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1930 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1931 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1932 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1933 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1934 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1935 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1936 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1937 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1938 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1939 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1940 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1941 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1942 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1943 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1944 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1945 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1946 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1947 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1948 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1949 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1950 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1951 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1952 { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } },
1953 { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } },
1954 { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } },
1955 { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } },
1956 { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } },
1957 { "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } },
1958 { "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } },
1959 { "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } },
1960 { "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } },
1961 { "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } },
1962 { "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } },
1963 { "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } },
1964 { "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } },
1965 { "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } },
1966 { "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } },
1967 { "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } },
1968 { "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } },
1969 { "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } },
1970 { "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } },
1971 { "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } },
1972 { "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } },
1973 { "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1974 { "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } },
1975 { "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1976 { "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1977 { "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1978 { "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1979 { "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1980 { "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1981 { "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1982 { "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1983 { "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1984 { "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1985 { "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1986 { "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1987 { "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1988 { "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1989 { "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1990 { "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1991 { "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1992 { "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1993 { "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1994 { "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1995 { "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1996 { "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1997 { "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
1998 { "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
1999 { "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } },
2000 { "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } },
2001 { "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2002 { "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2003 { "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } },
2004 { "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } },
2005 { "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2006 { "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } },
2007 { "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } },
2008 { "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } },
2009 { "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } },
2010 { "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } },
2011 { "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } },
2012 { "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } },
2013 { "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2014 { "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2015 { "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } },
2016 { "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } },
2017 { "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } },
2018 { "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } },
2019 { "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } },
2020 { "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } },
2021 { "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } },
2022 { "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2023 { "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } },
2024 { "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } },
2025 { "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } },
2026 { "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } },
2027 { "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } },
2028 { "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } },
2029 { "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2030 { "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2031 { "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2032 { "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2033 { "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2034 { "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2035 { "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } },
2036 { "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } },
2037 { "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } },
2038 { "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } },
2039 { "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } },
2040 { "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } },
2041 { "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } },
2042 { "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } },
2043 { "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } },
2044 { "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } },
2045 { "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } },
2046 { "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2047 { "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } },
2048 { "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } },
2049 { "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } },
2050 { "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } },
2051 { "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } },
2052 { "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } },
2053 { "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } },
2054 { "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } },
2055 { "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } },
2056 { "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } },
2057 { "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } },
2058 { "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } },
2059 { "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } },
2060 { "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } },
2061 { "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } },
2062 { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } },
2063 { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } },
2064 { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } },
2065 { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } },
2066 { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } },
2067 { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } },
2068 { "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } },
2069 { "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } },
2070 { "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } },
2071 { "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } },
2072 { "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2073 { "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2074 { "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } },
2075 { "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } },
2076 { "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } },
2077 { "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } },
2078 { "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } },
2079 { "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } },
2080 { "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } },
2081 { "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } },
2082 { "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } },
2083 { "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } },
2084 { "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } },
2085 { "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } },
2086 { "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } },
2087 { "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } },
2088 { "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } },
2089 { "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } },
2090 { "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } },
2091 { "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } },
2092 { "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } },
2093 { "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } },
2094 { "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } },
2095 { "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } },
2096 { "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } },
2097 { "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } },
2098 { "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } },
2099 { "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } },
2100 { "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } },
2101 { "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } },
2102 { "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } },
2103 { "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } },
2104 { "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } },
2105 { "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } },
2106 { "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } },
2107 { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } },
2108 { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } },
2109
2110 { "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } },
2111 { "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2112 { "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } },
2113 { "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } },
2114 { "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } },
2115 { "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } },
2116 { "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } },
2117 { "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } },
2118 { "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } },
2119 { "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } },
2120 { "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } },
2121 { "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } },
2122 { "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } },
2123
2124 { "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } },
2125
2126 { "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } },
2127 { "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } },
2128 { "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } },
2129 { "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } },
2130 { "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } },
2131 { "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } },
2132 { "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } },
2133 { "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } },
2134 { "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } },
2135 { "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } },
2136
2137 { "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } },
2138 { "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2139 { "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } },
2140 { "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2141 { "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } },
2142 { "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } },
2143 { "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2144 { "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } },
2145 { "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } },
2146 { "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } },
2147 { "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } },
2148 { "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } },
2149 { "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } },
2150 { "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } },
2151
2152 { "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2153 { "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2154 { "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2155 { "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2156 { "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2157 { "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } },
2158
2159 { "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2160 { "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } },
2161 { "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2162 { "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } },
2163 { "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2164 { "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } },
2165 { "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2166 { "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } },
2167 { "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2168 { "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } },
2169 { "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2170 { "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } },
2171 { "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2172 { "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } },
2173 { "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2174 { "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } },
2175 { "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2176 { "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } },
2177 { "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2178 { "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } },
2179 { "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } },
2180 { "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } },
2181
2182 { "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2183 { "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } },
2184 { "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2185 { "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } },
2186 { "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } },
2187 { "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } },
2188 { "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2189 { "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } },
2190 { "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2191 { "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } },
2192 { "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2193 { "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } },
2194 { "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } },
2195 { "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } },
2196
2197 { "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } },
2198 { "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } },
2199 { "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } },
2200 { "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } },
2201 { "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } },
2202 { "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } },
2203 { "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } },
2204 { "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2205 { "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2206 { "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2207 { "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2208 { "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2209 { "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } },
2210 { "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } },
2211 { "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } },
2212 { "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } },
2213 { "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } },
2214 { "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } },
2215 { "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } },
2216 { "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } },
2217 { "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } },
2218 { "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } },
2219 { "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } },
2220
2221 { "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } },
2222 { "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } },
2223 { "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } },
2224 { "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } },
2225 { "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } },
2226 { "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } },
2227 { "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } },
2228 { "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2229 { "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2230 { "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2231 { "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2232 { "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2233 { "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } },
2234 { "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } },
2235 { "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } },
2236 { "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } },
2237 { "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } },
2238 { "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } },
2239 { "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } },
2240 { "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } },
2241 { "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } },
2242 { "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } },
2243 { "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } },
2244
2245 { "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } },
2246 { "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } },
2247 { "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } },
2248 { "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } },
2249 { "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } },
2250 { "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } },
2251 { "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } },
2252 { "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } },
2253 { "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } },
2254 { "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } },
2255 { "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } },
2256 { "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } },
2257 { "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } },
2258 { "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } },
2259 { "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } },
2260 { "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } },
2261
2262 { "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } },
2263 { "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } },
2264 { "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } },
2265 { "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } },
2266 { "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } },
2267 { "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } },
2268 { "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } },
2269 { "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } },
2270 { "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } },
2271 { "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } },
2272 { "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } },
2273 { "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } },
2274
2275 { "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } },
2276 { "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } },
2277 { "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } },
2278 { "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } },
2279 { "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } },
2280 { "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } },
2281 { "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } },
2282 { "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } },
2283 { "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } },
2284 { "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } },
2285 { "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } },
2286 { "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } },
2287
2288 { "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } },
2289 { "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } },
2290 { "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } },
2291 { "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } },
2292 { "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } },
2293 { "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } },
2294
2295 { "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } },
2296 { "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } },
2297 { "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } },
2298 { "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } },
2299 { "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } },
2300 { "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } },
2301
2302 { "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } },
2303 { "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } },
2304 { "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } },
2305 { "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } },
2306 { "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } },
2307 { "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } },
2308 { "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } },
2309 { "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } },
2310
2311 { "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } },
2312 { "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } },
2313
2314 { "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } },
2315 { "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } },
2316 { "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } },
2317 { "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } },
2318
2319 { "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } },
2320 { "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } },
2321 { "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } },
2322 { "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } },
2323
2324 { "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } },
2325 { "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } },
2326 { "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } },
2327 { "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } },
2328 { "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } },
2329 { "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } },
2330 { "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } },
2331 { "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } },
2332
2333 { "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } },
2334 { "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } },
2335 { "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } },
2336 { "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } },
2337
2338 { "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } },
2339 { "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } },
2340 { "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } },
2341 { "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } },
2342
2343 { "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } },
2344 { "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } },
2345 { "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } },
2346 { "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } },
2347
2348 { "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } },
2349 { "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } },
2350 { "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } },
2351 { "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } },
2352
2353 { "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } },
2354
2355 { "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } },
2356 { "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } },
2357
2358 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2359 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2360
2361 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2362 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2363
2364 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2365
2366 { "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } },
2367 { "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } },
2368 { "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } },
2369 { "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } },
2370
2371 { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
2372 { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
2373 { "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
2374 { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
2375
2376 { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
2377 { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
2378 { "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
2379 { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
2380
2381 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2382 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2383 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2384
2385 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2386 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2387 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2388
2389 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2390 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2391 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } },
2392 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } },
2393 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } },
2394 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } },
2395
2396 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2397 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2398 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } },
2399 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
2400 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
2401
2402 { "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2403 { "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2404 { "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
2405 { "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
2406 { "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2407 { "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2408 { "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
2409 { "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
2410 { "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2411 { "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2412 { "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
2413 { "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
2414 { "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2415 { "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2416 { "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
2417 { "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
2418 { "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
2419 { "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
2420 { "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
2421 { "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
2422 { "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
2423 { "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
2424 { "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
2425 { "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
2426 { "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
2427 { "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
2428 { "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
2429 { "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
2430 { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2431 { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2432 { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2433 { "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2434 { "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2435 { "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2436 { "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2437 { "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2438 { "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2439 { "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2440 { "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2441 { "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2442 { "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2443 { "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2444 { "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2445 { "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2446 { "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2447 { "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2448 { "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2449 { "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2450 { "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2451 { "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2452 { "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2453 { "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2454 { "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2455 { "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2456 { "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2457 { "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2458 { "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2459 { "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2460 { "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2461 { "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2462 { "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2463 { "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2464 { "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2465 { "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2466 { "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2467 { "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2468 { "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2469 { "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2470 { "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2471 { "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2472 { "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2473 { "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2474 { "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2475 { "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2476 { "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2477 { "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2478 { "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2479 { "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2480 { "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2481 { "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2482 { "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2483 { "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2484 { "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2485 { "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2486 { "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2487 { "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2488 { "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2489 { "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2490 { "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2491 { "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2492 { "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2493 { "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2494 { "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2495 { "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2496 { "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2497 { "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2498 { "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2499 { "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2500 { "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2501 { "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2502 { "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2503 { "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2504 { "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2505 { "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2506 { "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2507 { "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2508 { "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2509 { "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2510 { "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2511 { "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2512 { "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2513 { "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2514 { "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2515 { "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2516 { "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2517 { "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2518 { "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2519 { "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2520 { "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2521 { "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2522 { "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2523 { "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2524 { "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2525 { "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2526 { "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2527 { "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2528 { "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } },
2529 { "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2530 { "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2531 { "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } },
2532 { "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2533 { "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2534 { "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2535 { "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2536 { "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2537 { "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2538 { "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2539 { "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2540 { "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } },
2541 { "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2542 { "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2543 { "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } },
2544 { "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2545 { "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2546 { "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2547 { "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2548 { "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2549 { "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2550 { "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2551 { "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2552 { "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } },
2553 { "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2554 { "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2555 { "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } },
2556 { "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2557 { "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2558 { "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } },
2559 { "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2560 { "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2561 { "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } },
2562 { "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2563 { "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2564 { "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } },
2565 { "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } },
2566 { "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } },
2567 { "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } },
2568 { "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2569 { "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2570 { "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2571 { "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } },
2572 { "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } },
2573 { "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } },
2574 { "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2575 { "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2576 { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2577 { "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2578 { "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2579 { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2580 { "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2581 { "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2582 { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2583 { "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2584 { "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2585 { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2586 { "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2587 { "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2588 { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2589 { "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2590 { "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2591 { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2592 { "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2593 { "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2594 { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2595 { "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2596 { "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2597 { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2598 { "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2599 { "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2600 { "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2601 { "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2602 { "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2603 { "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2604 { "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2605 { "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2606 { "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2607 { "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2608 { "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2609 { "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2610 { "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2611 { "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2612 { "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2613 { "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2614 { "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } },
2615 { "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } },
2616 { "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } },
2617 { "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } },
2618 { "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } },
2619 { "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } },
2620 { "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } },
2621 { "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } },
2622 { "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2623 { "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2624 { "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } },
2625 { "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } },
2626 { "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } },
2627 { "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } },
2628 { "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } },
2629 { "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } },
2630 { "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2631 { "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2632 { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2633 { "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2634 { "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2635 { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2636 { "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2637 { "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2638 { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2639 { "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2640 { "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2641 { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2642 { "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } },
2643 { "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } },
2644 { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } },
2645 { "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } },
2646 { "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } },
2647 { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } },
2648 { "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2649 { "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2650 { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } },
2651 { "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } },
2652 { "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } },
2653 { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } },
2654 { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } },
2655 { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } },
2656 { "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } },
2657 { "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } },
2658 { "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } },
2659 { "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } },
2660 { "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2661 { "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2662 { "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } },
2663 { "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } },
2664 { "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
2665 { "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
2666
2667 { "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
2668 { "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
2669 { "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
2670 { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
2671 { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
2672
2673 { "b", B(18,0,0), B_MASK, COM, { LI } },
2674 { "bl", B(18,0,1), B_MASK, COM, { LI } },
2675 { "ba", B(18,1,0), B_MASK, COM, { LIA } },
2676 { "bla", B(18,1,1), B_MASK, COM, { LIA } },
2677
2678 { "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
2679
2680 { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2681 { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
2682 { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2683 { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } },
2684 { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2685 { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2686 { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2687 { "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2688 { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2689 { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2690 { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2691 { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2692 { "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2693 { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2694 { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
2695 { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2696 { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2697 { "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2698 { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } },
2699 { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
2700 { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2701 { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2702 { "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } },
2703 { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } },
2704 { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2705 { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2706 { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2707 { "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2708 { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2709 { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2710 { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2711 { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2712 { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2713 { "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2714 { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2715 { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2716 { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2717 { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2718 { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2719 { "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2720 { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2721 { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2722 { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2723 { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2724 { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2725 { "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2726 { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2727 { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2728 { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2729 { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2730 { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2731 { "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2732 { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2733 { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2734 { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2735 { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2736 { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2737 { "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2738 { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2739 { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2740 { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2741 { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2742 { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2743 { "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2744 { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2745 { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2746 { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2747 { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2748 { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2749 { "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2750 { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2751 { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2752 { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2753 { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2754 { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2755 { "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2756 { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2757 { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2758 { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2759 { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2760 { "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2761 { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2762 { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2763 { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2764 { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2765 { "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2766 { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2767 { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2768 { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2769 { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2770 { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2771 { "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2772 { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2773 { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2774 { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2775 { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2776 { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2777 { "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2778 { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2779 { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2780 { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2781 { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2782 { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2783 { "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2784 { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2785 { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2786 { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2787 { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2788 { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2789 { "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2790 { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2791 { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2792 { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2793 { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2794 { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2795 { "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2796 { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2797 { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2798 { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2799 { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2800 { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2801 { "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2802 { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2803 { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2804 { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2805 { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2806 { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2807 { "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2808 { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2809 { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2810 { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2811 { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2812 { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2813 { "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2814 { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2815 { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2816 { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2817 { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2818 { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2819 { "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2820 { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2821 { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2822 { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2823 { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2824 { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2825 { "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2826 { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2827 { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
2828 { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2829 { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2830 { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2831 { "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2832 { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2833 { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
2834 { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2835 { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2836 { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2837 { "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2838 { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
2839 { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2840 { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2841 { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2842 { "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2843 { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
2844 { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2845 { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2846 { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2847 { "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2848 { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2849 { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2850 { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2851 { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2852 { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2853 { "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2854 { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2855 { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2856 { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2857 { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2858 { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } },
2859 { "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2860 { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } },
2861 { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } },
2862 { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2863 { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2864 { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } },
2865 { "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2866 { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } },
2867 { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } },
2868 { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2869 { "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2870 { "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2871 { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2872 { "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2873 { "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2874 { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2875 { "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2876 { "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2877 { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2878 { "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2879 { "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2880 { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2881 { "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2882 { "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2883 { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2884 { "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2885 { "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2886 { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } },
2887 { "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2888 { "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } },
2889 { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } },
2890 { "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2891 { "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } },
2892 { "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } },
2893 { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } },
2894 { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2895 { "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2896 { "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
2897 { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
2898 { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } },
2899 { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } },
2900 { "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } },
2901 { "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } },
2902
2903 { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } },
2904
2905 { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
2906 { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
2907 { "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
2908
2909 { "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
2910 { "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } },
2911
2912 { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } },
2913
2914 { "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } },
2915
2916 { "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } },
2917 { "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } },
2918
2919 { "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2920 { "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } },
2921
2922 { "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } },
2923
2924 { "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
2925
2926 { "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
2927 { "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
2928
2929 { "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } },
2930
2931 { "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } },
2932 { "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } },
2933
2934 { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } },
2935 { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } },
2936 { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2937 { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2938 { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2939 { "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2940 { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2941 { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2942 { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2943 { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2944 { "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2945 { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2946 { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2947 { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2948 { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2949 { "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2950 { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2951 { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2952 { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2953 { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2954 { "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2955 { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2956 { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2957 { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2958 { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2959 { "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2960 { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2961 { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2962 { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2963 { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2964 { "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2965 { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2966 { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2967 { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2968 { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2969 { "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2970 { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2971 { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2972 { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2973 { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2974 { "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2975 { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2976 { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2977 { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2978 { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2979 { "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2980 { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2981 { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2982 { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2983 { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2984 { "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2985 { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2986 { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2987 { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2988 { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2989 { "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2990 { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2991 { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
2992 { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2993 { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2994 { "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
2995 { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
2996 { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
2997 { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
2998 { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
2999 { "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3000 { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3001 { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3002 { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3003 { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3004 { "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3005 { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3006 { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3007 { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3008 { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3009 { "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3010 { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3011 { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3012 { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3013 { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3014 { "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3015 { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3016 { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3017 { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3018 { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3019 { "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3020 { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3021 { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3022 { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3023 { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3024 { "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3025 { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3026 { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3027 { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3028 { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3029 { "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3030 { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3031 { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3032 { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3033 { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3034 { "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3035 { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3036 { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3037 { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3038 { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3039 { "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3040 { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3041 { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3042 { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3043 { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3044 { "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3045 { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3046 { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } },
3047 { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3048 { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3049 { "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
3050 { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } },
3051 { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } },
3052 { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3053 { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3054 { "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
3055 { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } },
3056 { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3057 { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3058 { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3059 { "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3060 { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3061 { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3062 { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3063 { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3064 { "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3065 { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3066 { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } },
3067 { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3068 { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } },
3069 { "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } },
3070 { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } },
3071 { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } },
3072 { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3073 { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } },
3074 { "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } },
3075 { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } },
3076 { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } },
3077 { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3078 { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } },
3079 { "bcctrl", XLLK(19,528,1), XLYBB_MASK, PPCCOM, { BO, BI } },
3080 { "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3081 { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } },
3082 { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } },
3083 { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } },
3084 { "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } },
3085 { "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } },
3086
3087 { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3088 { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3089
3090 { "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3091 { "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3092
3093 { "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } },
3094 { "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3095 { "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3096 { "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3097 { "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } },
3098 { "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } },
3099 { "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } },
3100 { "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } },
3101
3102 { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3103 { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } },
3104
3105 { "be", B(22,0,0), B_MASK, BOOKE64, { LI } },
3106 { "bel", B(22,0,1), B_MASK, BOOKE64, { LI } },
3107 { "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } },
3108 { "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } },
3109
3110 { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3111 { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3112 { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3113 { "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } },
3114 { "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } },
3115 { "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } },
3116
3117 { "nop", OP(24), 0xffffffff, PPCCOM, { 0 } },
3118 { "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } },
3119 { "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } },
3120
3121 { "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } },
3122 { "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } },
3123
3124 { "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } },
3125 { "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } },
3126
3127 { "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } },
3128 { "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } },
3129
3130 { "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } },
3131 { "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } },
3132
3133 { "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } },
3134 { "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } },
3135
3136 { "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3137 { "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3138 { "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3139 { "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } },
3140 { "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } },
3141 { "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3142
3143 { "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3144 { "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } },
3145
3146 { "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3147 { "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3148
3149 { "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3150 { "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } },
3151
3152 { "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } },
3153 { "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3154 { "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } },
3155 { "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } },
3156
3157 { "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3158 { "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } },
3159
3160 { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3161 { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3162 { "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
3163 { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3164
3165 { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
3166 { "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } },
3167 { "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } },
3168 { "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } },
3169 { "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } },
3170 { "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } },
3171 { "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } },
3172 { "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } },
3173 { "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } },
3174 { "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } },
3175 { "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } },
3176 { "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } },
3177 { "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } },
3178 { "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } },
3179 { "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } },
3180 { "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } },
3181 { "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } },
3182 { "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } },
3183 { "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } },
3184 { "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } },
3185 { "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } },
3186 { "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } },
3187 { "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } },
3188 { "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } },
3189 { "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } },
3190 { "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } },
3191 { "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } },
3192 { "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } },
3193 { "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } },
3194 { "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } },
3195 { "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } },
3196
3197 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3198 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3199 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3200 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3201 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3202 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3203 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3204 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3205 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3206 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3207 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3208 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3209
3210 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3211 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3212
3213 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3214 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3215 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3216 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3217 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3218 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3219 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3220 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3221
3222 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3223 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3224
3225 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3226 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3227 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3228 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3229
3230 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } },
3231 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3232
3233 { "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } },
3234
3235 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } },
3236
3237 { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } },
3238 { "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } },
3239
3240 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } },
3241 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3242
3243 { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } },
3244 { "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } },
3245 { "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } },
3246 { "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } },
3247
3248 { "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } },
3249 { "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } },
3250 { "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } },
3251 { "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } },
3252
3253 { "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } },
3254 { "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } },
3255
3256 { "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } },
3257 { "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } },
3258
3259 { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } },
3260 { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } },
3261
3262 { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } },
3263
3264 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } },
3265
3266 { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
3267 { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
3268 { "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
3269 { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
3270
3271 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3272 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3273 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3274 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3275 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3276 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3277 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3278 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3279
3280 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3281
3282 { "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } },
3283
3284 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3285 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3286
3287 { "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } },
3288
3289 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3290
3291 { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } },
3292 { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } },
3293
3294 { "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } },
3295 { "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } },
3296
3297 { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } },
3298 { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } },
3299 { "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } },
3300 { "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } },
3301 { "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } },
3302 { "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } },
3303 { "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } },
3304 { "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } },
3305 { "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } },
3306 { "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } },
3307 { "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } },
3308 { "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } },
3309 { "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } },
3310 { "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } },
3311 { "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } },
3312
3313 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3314 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3315
3316 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3317 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3318
3319 { "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3320 { "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } },
3321
3322 { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } },
3323
3324 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3325
3326 { "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } },
3327
3328 { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } },
3329
3330 { "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } },
3331
3332 { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } },
3333
3334 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } },
3335
3336 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3337 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3338 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3339 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3340
3341 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3342 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3343 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3344 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3345
3346 { "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } },
3347
3348 { "clf", X(31,118), XTO_MASK, POWER, { RA, RB } },
3349
3350 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3351
3352 { "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
3353 { "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
3354 { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
3355 { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } },
3356
3357 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } },
3358
3359 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3360
3361 { "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } },
3362
3363 { "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }},
3364
3365 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3366 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3367 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3368 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3369 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3370 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3371 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3372 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3373
3374 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3375 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3376 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3377 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3378 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3379 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3380 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3381 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3382
3383 { "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }},
3384
3385 { "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }},
3386 { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } },
3387
3388 { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } },
3389
3390 { "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } },
3391
3392 { "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } },
3393
3394 { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } },
3395 { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } },
3396
3397 { "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } },
3398
3399 { "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } },
3400
3401 { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } },
3402 { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } },
3403
3404 { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } },
3405 { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } },
3406
3407 { "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } },
3408
3409 { "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }},
3410 { "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }},
3411
3412 { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } },
3413
3414 { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } },
3415
3416 { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } },
3417 { "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } },
3418
3419 { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } },
3420 { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } },
3421
3422 { "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } },
3423
3424 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3425 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3426 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3427 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3428 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3429 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3430 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3431 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3432
3433 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3434 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3435 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3436 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3437 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3438 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3439 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3440 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3441
3442 { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } },
3443
3444 { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } },
3445
3446 { "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } },
3447
3448 { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } },
3449 { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } },
3450
3451 { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } },
3452 { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } },
3453
3454 { "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } },
3455
3456 { "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }},
3457
3458 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3459 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3460 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3461 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3462 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3463 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3464 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3465 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3466
3467 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3468 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3469 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3470 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3471
3472 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3473 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3474 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3475 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3476 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3477 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3478 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3479 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3480
3481 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3482 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3483 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3484 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3485 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3486 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3487 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3488 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3489
3490 { "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }},
3491 { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } },
3492 { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } },
3493
3494 { "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } },
3495
3496 { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } },
3497
3498 { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } },
3499 { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } },
3500
3501 { "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } },
3502
3503 { "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } },
3504
3505 { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } },
3506
3507 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3508 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3509 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3510 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3511
3512 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3513 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3514 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3515 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3516 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3517 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3518 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3519 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3520
3521 { "tlbiel", X(31,274), XRTRA_MASK, POWER4, { RB } },
3522
3523 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3524
3525 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3526 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3527
3528 { "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } },
3529
3530 { "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } },
3531
3532 { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } },
3533 { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } },
3534
3535 { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } },
3536
3537 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } },
3538
3539 { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } },
3540 { "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } },
3541
3542 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3543
3544 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3545
3546 { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } },
3547 { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } },
3548
3549 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3550
3551 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3552 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3553 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3554 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3555 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3556 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3557 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3558 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3559 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3560 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3561 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3562 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3563 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3564 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3565 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3566 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3567 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3568 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3569 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3570 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3571 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3572 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3573 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3574 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3575 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3576 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3577 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3578 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3579 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3580 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3581 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3582 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3583 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3584 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3585 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3586
3587 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3588 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3589 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3590 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3591
3592 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3593
3594 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3595 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3596 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3597 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3598 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3599 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3600 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3601 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3602 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3603 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3604 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3605 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3606 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3607 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3608 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3609 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3610 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3611 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3612 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3613 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3614 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3615 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3616 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3617 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3618 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3619 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3620 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3621 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3622 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3623 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3624 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3625 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3626 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3627 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3628 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3629 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3630 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3631 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3632 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3633 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3634 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3635 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3636 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } },
3637 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
3638 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
3639 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
3640 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3641 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3642 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3643 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3644 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3645 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3646 { "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
3647 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3648 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3649 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3650 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3651 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3652 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3653 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3654 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3655 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3656 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3657 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3658 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3659 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3660 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3661 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3662 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3663 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3664 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3665 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3666 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3667 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3668 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3669 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3670 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3671 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3672 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3673 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3674 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3675 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3676 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3677 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3678 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3679 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3680 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3681 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3682 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3683 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3684 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3685 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3686 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3687 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3688 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3689 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3690 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3691 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3692 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3693 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3694 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3695 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3696 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3697 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3698 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3699 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3700 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3701 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3702 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3703 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3704 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3705 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3706 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3707 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3708 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3709 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3710 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3711 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3712 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3713 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3714 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3715 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3716 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3717 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3718 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3719 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3720 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3721 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3722 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3723 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3724 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3725 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3726 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3727 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3728 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3729 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3730 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3731 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3732 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3733 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3734 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3735 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3736 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3737 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3738 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3739 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3740 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3741 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3742 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3743 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3744 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3745 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3746 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3747 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3748 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3749 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3750 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3751 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3752 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3753 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3754 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3755 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3756 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3757 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3758 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3759 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3760 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3761 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3762 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3763 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3764 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3765 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3766 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3767 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3768 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3769 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3770 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3771 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3772 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3773 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3774 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3775 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3776
3777 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } },
3778
3779 { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3780 { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3781
3782 { "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } },
3783
3784 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } },
3785
3786 { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3787 { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } },
3788
3789 { "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } },
3790
3791 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3792 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3793 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3794 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3795
3796 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3797 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3798 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3799 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3800
3801 { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } },
3802
3803 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3804
3805 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3806
3807 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3808
3809 { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } },
3810
3811 { "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }},
3812
3813 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3814 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3815
3816 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3817 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3818
3819 { "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }},
3820
3821 { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } },
3822
3823 { "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } },
3824
3825 { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } },
3826
3827 { "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } },
3828
3829 { "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } },
3830
3831 { "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } },
3832
3833 { "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } },
3834 { "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } },
3835
3836 { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } },
3837 { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } },
3838
3839 { "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } },
3840
3841 { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } },
3842
3843 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
3844
3845 { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } },
3846
3847 { "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } },
3848
3849 { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } },
3850 { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } },
3851 { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } },
3852 { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } },
3853
3854 { "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } },
3855 { "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } },
3856 { "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } },
3857 { "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } },
3858 { "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } },
3859 { "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } },
3860 { "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } },
3861 { "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } },
3862 { "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } },
3863 { "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } },
3864 { "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } },
3865 { "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } },
3866 { "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } },
3867 { "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } },
3868 { "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } },
3869 { "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } },
3870 { "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } },
3871 { "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } },
3872 { "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } },
3873 { "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } },
3874 { "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } },
3875 { "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } },
3876 { "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } },
3877 { "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } },
3878 { "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } },
3879 { "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } },
3880 { "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } },
3881 { "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } },
3882 { "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } },
3883 { "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } },
3884 { "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } },
3885 { "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } },
3886 { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } },
3887 { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } },
3888 { "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } },
3889
3890 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3891 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3892
3893 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3894 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3895 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3896 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3897
3898 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
3899 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
3900
3901 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
3902 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
3903 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
3904 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
3905
3906 { "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } },
3907 { "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } },
3908 { "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } },
3909 { "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } },
3910 { "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } },
3911 { "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } },
3912 { "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } },
3913 { "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } },
3914 { "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } },
3915 { "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } },
3916 { "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } },
3917 { "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } },
3918 { "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } },
3919 { "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } },
3920 { "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } },
3921 { "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } },
3922 { "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } },
3923 { "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } },
3924 { "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } },
3925 { "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } },
3926 { "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } },
3927 { "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } },
3928 { "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } },
3929 { "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } },
3930 { "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } },
3931 { "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } },
3932 { "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } },
3933 { "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } },
3934 { "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } },
3935 { "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } },
3936 { "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } },
3937 { "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } },
3938 { "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } },
3939 { "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } },
3940 { "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } },
3941 { "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } },
3942 { "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } },
3943 { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } },
3944 { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } },
3945 { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } },
3946 { "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } },
3947 { "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } },
3948 { "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } },
3949 { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } },
3950 { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } },
3951 { "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } },
3952 { "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } },
3953 { "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } },
3954 { "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } },
3955 { "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } },
3956 { "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } },
3957 { "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } },
3958 { "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } },
3959 { "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } },
3960 { "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } },
3961 { "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } },
3962 { "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } },
3963 { "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } },
3964 { "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } },
3965 { "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } },
3966 { "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } },
3967 { "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } },
3968 { "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } },
3969 { "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } },
3970 { "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } },
3971 { "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } },
3972 { "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } },
3973 { "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } },
3974 { "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } },
3975 { "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } },
3976 { "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } },
3977 { "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } },
3978 { "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } },
3979 { "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } },
3980 { "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } },
3981 { "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } },
3982 { "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } },
3983 { "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } },
3984 { "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } },
3985 { "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } },
3986 { "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } },
3987 { "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } },
3988 { "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } },
3989 { "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } },
3990 { "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } },
3991 { "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } },
3992 { "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } },
3993 { "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } },
3994 { "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } },
3995 { "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } },
3996 { "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } },
3997 { "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } },
3998 { "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } },
3999 { "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } },
4000 { "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } },
4001 { "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } },
4002 { "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } },
4003 { "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } },
4004 { "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } },
4005 { "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } },
4006 { "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } },
4007 { "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4008 { "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4009 { "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4010 { "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } },
4011 { "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } },
4012 { "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } },
4013 { "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } },
4014 { "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } },
4015 { "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } },
4016 { "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } },
4017 { "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } },
4018 { "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } },
4019 { "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } },
4020 { "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } },
4021 { "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } },
4022 { "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } },
4023 { "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } },
4024 { "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } },
4025 { "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } },
4026 { "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } },
4027 { "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } },
4028 { "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } },
4029 { "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } },
4030 { "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } },
4031 { "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } },
4032 { "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } },
4033 { "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } },
4034 { "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } },
4035 { "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } },
4036 { "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } },
4037 { "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } },
4038 { "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } },
4039 { "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } },
4040 { "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } },
4041 { "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } },
4042 { "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } },
4043 { "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } },
4044 { "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } },
4045 { "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } },
4046 { "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } },
4047 { "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } },
4048 { "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } },
4049 { "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } },
4050 { "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } },
4051 { "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } },
4052 { "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } },
4053 { "mtspr", X(31,467), X_MASK, COM, { SPR, RS } },
4054
4055 { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } },
4056
4057 { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } },
4058 { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } },
4059
4060 { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } },
4061
4062 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4063
4064 { "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }},
4065
4066 { "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }},
4067
4068 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4069 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4070 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4071 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4072 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4073 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4074
4075 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4076 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4077 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4078 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4079
4080 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4081 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4082
4083 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4084 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4085 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4086 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4087
4088 { "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }},
4089
4090 { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } },
4091
4092 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4093
4094 { "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } },
4095
4096 { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } },
4097
4098 { "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }},
4099 { "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } },
4100
4101 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4102
4103 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } },
4104 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4105
4106 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } },
4107 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4108
4109 { "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } },
4110
4111 { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } },
4112 { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } },
4113 { "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } },
4114 { "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } },
4115
4116 { "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } },
4117 { "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } },
4118
4119 { "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } },
4120 { "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } },
4121
4122 { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } },
4123 { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } },
4124
4125 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } },
4126
4127 { "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } },
4128
4129 { "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }},
4130 { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } },
4131
4132 { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } },
4133
4134 { "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } },
4135
4136 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4137
4138 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
4139 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
4140
4141 { "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
4142 { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
4143 { "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
4144 { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
4145 { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } },
4146
4147 { "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } },
4148
4149 { "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } },
4150
4151 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4152
4153 { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } },
4154
4155 { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } },
4156
4157 { "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } },
4158
4159 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4160
4161 { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } },
4162 { "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } },
4163
4164 { "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } },
4165 { "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } },
4166
4167 { "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } },
4168
4169 { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } },
4170 { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } },
4171
4172 { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } },
4173 { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } },
4174
4175 { "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } },
4176
4177 { "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } },
4178
4179 { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } },
4180
4181 { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } },
4182 { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } },
4183
4184 { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } },
4185
4186 { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } },
4187 { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } },
4188
4189 { "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } },
4190
4191 { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } },
4192 { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } },
4193
4194 { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } },
4195 { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } },
4196
4197 { "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } },
4198
4199 { "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } },
4200
4201 { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } },
4202
4203 { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } },
4204 { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } },
4205
4206 { "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } },
4207
4208 { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } },
4209
4210 { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } },
4211 { "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } },
4212
4213 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } },
4214
4215 { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } },
4216 { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } },
4217 { "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } },
4218 { "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } },
4219
4220 { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } },
4221 { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } },
4222
4223 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } },
4224
4225 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } },
4226 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } },
4227
4228 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4229
4230 { "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } },
4231 { "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } },
4232
4233 { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } },
4234 { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } },
4235 { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } },
4236 { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } },
4237
4238 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4239
4240 { "mbar", X(31,854), X_MASK, BOOKE, { MO } },
4241 { "eieio", X(31,854), 0xffffffff, PPC, { 0 } },
4242
4243 { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } },
4244 { "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } },
4245 { "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } },
4246 { "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } },
4247 { "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } },
4248 { "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } },
4249
4250 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4251
4252 { "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } },
4253
4254 { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } },
4255 { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } },
4256
4257 { "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } },
4258 { "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } },
4259
4260 { "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } },
4261 { "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } },
4262 { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } },
4263 { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } },
4264
4265 { "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } },
4266
4267 { "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } },
4268
4269 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4270 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4271 { "tlbre", X(31,946), X_MASK, BOOKE, { 0 } },
4272 { "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } },
4273
4274 { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } },
4275 { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } },
4276
4277 { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} },
4278 { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} },
4279
4280 { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } },
4281
4282 { "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } },
4283
4284 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4285 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4286 { "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } },
4287 { "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } },
4288 { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } },
4289
4290 { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } },
4291
4292 { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } },
4293
4294 { "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } },
4295 { "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } },
4296
4297 { "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } },
4298
4299 { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } },
4300 { "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } },
4301
4302 { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } },
4303
4304 { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4305 { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } },
4306
4307 { "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } },
4308
4309 { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } },
4310 { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } },
4311 { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } },
4312 { "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } },
4313 { "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } },
4314 { "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } },
4315 { "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } },
4316 { "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } },
4317 { "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } },
4318 { "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } },
4319 { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
4320 { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
4321
4322 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } },
4323 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } },
4324
4325 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4326 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } },
4327
4328 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA } },
4329
4330 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4331
4332 { "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } },
4333 { "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } },
4334
4335 { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } },
4336 { "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } },
4337
4338 { "stb", OP(38), OP_MASK, COM, { RS, D, RA } },
4339
4340 { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } },
4341
4342 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA } },
4343
4344 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4345
4346 { "lha", OP(42), OP_MASK, COM, { RT, D, RA } },
4347
4348 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4349
4350 { "sth", OP(44), OP_MASK, COM, { RS, D, RA } },
4351
4352 { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } },
4353
4354 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4355 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } },
4356
4357 { "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } },
4358 { "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } },
4359
4360 { "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } },
4361
4362 { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } },
4363
4364 { "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } },
4365
4366 { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } },
4367
4368 { "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } },
4369
4370 { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } },
4371
4372 { "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } },
4373
4374 { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } },
4375
4376 { "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } },
4377
4378 { "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } },
4379
4380 { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } },
4381
4382 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } },
4383 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4384 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } },
4385 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4386 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } },
4387 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4388 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } },
4389 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4390 { "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } },
4391 { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } },
4392 { "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } },
4393 { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } },
4394 { "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } },
4395 { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } },
4396
4397 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } },
4398
4399 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4400
4401 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } },
4402
4403 { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4404 { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4405
4406 { "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4407 { "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4408
4409 { "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4410 { "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } },
4411
4412 { "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4413 { "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4414
4415 { "fres", A(59,24,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4416 { "fres.", A(59,24,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4417
4418 { "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4419 { "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
4420
4421 { "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4422 { "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4423
4424 { "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4425 { "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4426
4427 { "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4428 { "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4429
4430 { "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4431 { "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4432
4433 { "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } },
4434
4435 { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } },
4436
4437 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } },
4438 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } },
4439 { "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } },
4440 { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4441 { "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } },
4442 { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } },
4443 { "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } },
4444 { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } },
4445 { "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } },
4446 { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4447 { "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } },
4448 { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } },
4449
4450 { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } },
4451
4452 { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } },
4453
4454 { "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA } },
4455
4456 { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4457
4458 { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } },
4459 { "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } },
4460
4461 { "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4462 { "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } },
4463 { "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4464 { "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } },
4465
4466 { "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } },
4467 { "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } },
4468 { "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } },
4469 { "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } },
4470
4471 { "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4472 { "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4473 { "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4474 { "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4475
4476 { "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4477 { "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4478 { "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4479 { "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4480
4481 { "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4482 { "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4483 { "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } },
4484 { "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } },
4485
4486 { "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4487 { "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } },
4488
4489 { "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4490 { "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
4491
4492 { "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4493 { "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4494 { "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
4495 { "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
4496
4497 { "frsqrte", A(63,26,0), AFRAFRC_MASK, PPC, { FRT, FRB } },
4498 { "frsqrte.",A(63,26,1), AFRAFRC_MASK, PPC, { FRT, FRB } },
4499
4500 { "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4501 { "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4502 { "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4503 { "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4504
4505 { "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4506 { "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4507 { "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4508 { "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4509
4510 { "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4511 { "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4512 { "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4513 { "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4514
4515 { "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4516 { "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4517 { "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } },
4518 { "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } },
4519
4520 { "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } },
4521
4522 { "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } },
4523 { "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } },
4524
4525 { "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } },
4526 { "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } },
4527
4528 { "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
4529
4530 { "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } },
4531 { "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } },
4532
4533 { "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } },
4534 { "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } },
4535
4536 { "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4537 { "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
4538
4539 { "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
4540 { "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
4541
4542 { "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } },
4543 { "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } },
4544
4545 { "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } },
4546 { "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } },
4547
4548 { "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
4549 { "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
4550
4551 { "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } },
4552 { "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } },
4553
4554 { "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } },
4555 { "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } },
4556
4557 { "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } },
4558 { "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } },
4559
4560 };
4561
4562 const int powerpc_num_opcodes =
4563 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]);
4564 \f
4565 /* The macro table. This is only used by the assembler. */
4566
4567 /* The expressions of the form (-x ! 31) & (x | 31) have the value 0
4568 when x=0; 32-x when x is between 1 and 31; are negative if x is
4569 negative; and are 32 or more otherwise. This is what you want
4570 when, for instance, you are emulating a right shift by a
4571 rotate-left-and-mask, because the underlying instructions support
4572 shifts of size 0 but not shifts of size 32. By comparison, when
4573 extracting x bits from some word you want to use just 32-x, because
4574 the underlying instructions don't support extracting 0 bits but do
4575 support extracting the whole word (32 bits in this case). */
4576
4577 const struct powerpc_macro powerpc_macros[] = {
4578 { "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" },
4579 { "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" },
4580 { "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" },
4581 { "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" },
4582 { "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" },
4583 { "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" },
4584 { "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" },
4585 { "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" },
4586 { "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" },
4587 { "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" },
4588 { "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" },
4589 { "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" },
4590 { "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" },
4591 { "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" },
4592 { "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" },
4593 { "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" },
4594
4595 { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" },
4596 { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" },
4597 { "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4598 { "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" },
4599 { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" },
4600 { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"},
4601 { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" },
4602 { "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"},
4603 { "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4604 { "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" },
4605 { "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" },
4606 { "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" },
4607 { "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" },
4608 { "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" },
4609 { "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4610 { "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4611 { "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4612 { "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" },
4613 { "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" },
4614 { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" },
4615 { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" },
4616 { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" },
4617 };
4618
4619 const int powerpc_num_macros =
4620 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]);
kernel source for telekom puls (alcatel/mediatek)