arch/ppc/syslib/hawk_common.c

   1 /*
   2  * arch/ppc/syslib/hawk_common.c
   3  *
   4  * Common Motorola PowerPlus Platform--really Falcon/Raven or HAWK.
   5  *
   6  * Author: Mark A. Greer
   7  *         mgreer@mvista.com
   8  *
   9  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/pci.h>
  17
  18 #include <asm/byteorder.h>
  19 #include <asm/io.h>
  20 #include <asm/irq.h>
  21 #include <asm/pci.h>
  22 #include <asm/pci-bridge.h>
  23 #include <asm/open_pic.h>
  24 #include <asm/hawk.h>
  25
  26 /*
  27  * The Falcon/Raven and HAWK has 4 sets of registers:
  28  *   1) PPC Registers which define the mappings from PPC bus to PCI bus,
  29  *      etc.
  30  *   2) PCI Registers which define the mappings from PCI bus to PPC bus and the
  31  *      MPIC base address.
  32  *   3) MPIC registers.
  33  *   4) System Memory Controller (SMC) registers.
  34  */
  35
  36 /*
  37  * Initialize the Motorola MCG Raven or HAWK host bridge.
  38  *
  39  * This means setting up the PPC bus to PCI memory and I/O space mappings,
  40  * setting the PCI memory space address of the MPIC (mapped straight
  41  * through), and ioremap'ing the mpic registers.
  42  * This routine will set the PCI_CONFIG_ADDR or PCI_CONFIG_DATA
  43  * addresses based on the PCI I/O address that is passed in.
  44  * 'OpenPIC_Addr' will be set correctly by this routine.
  45  */
  46 int __init
  47 hawk_init(struct pci_controller *hose,
  48              uint ppc_reg_base,
  49              ulong processor_pci_mem_start,
  50              ulong processor_pci_mem_end,
  51              ulong processor_pci_io_start,
  52              ulong processor_pci_io_end,
  53              ulong processor_mpic_base)
  54 {
  55         uint            addr, offset;
  56
  57         /*
  58          * Some sanity checks...
  59          */
  60         if (((processor_pci_mem_start&0xffff0000) != processor_pci_mem_start) ||
  61             ((processor_pci_io_start &0xffff0000) != processor_pci_io_start)) {
  62                 printk("hawk_init: %s\n",
  63                         "PPC to PCI mappings must start on 64 KB boundaries");
  64                 return -1;
  65         }
  66
  67         if (((processor_pci_mem_end  &0x0000ffff) != 0x0000ffff) ||
  68             ((processor_pci_io_end   &0x0000ffff) != 0x0000ffff)) {
  69                 printk("hawk_init: PPC to PCI mappings %s\n",
  70                         "must end just before a 64 KB boundaries");
  71                 return -1;
  72         }
  73
  74         if (((processor_pci_mem_end - processor_pci_mem_start) !=
  75              (hose->mem_space.end - hose->mem_space.start)) ||
  76             ((processor_pci_io_end - processor_pci_io_start) !=
  77              (hose->io_space.end - hose->io_space.start))) {
  78                 printk("hawk_init: %s\n",
  79                         "PPC and PCI memory or I/O space sizes don't match");
  80                 return -1;
  81         }
  82
  83         if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) {
  84                 printk("hawk_init: %s\n",
  85                         "MPIC address must start on 256 MB boundary");
  86                 return -1;
  87         }
  88
  89         if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) {
  90                 printk("hawk_init: %s\n",
  91                         "pci_dram_offset must be multiple of 64 KB");
  92                 return -1;
  93         }
  94
  95         /*
  96          * Disable previous PPC->PCI mappings.
  97          */
  98         out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), 0x00000000);
  99         out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), 0x00000000);
 100         out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF2_OFF), 0x00000000);
 101         out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), 0x00000000);
 102
 103         /*
 104          * Program the XSADD/XSOFF registers to set up the PCI Mem & I/O
 105          * space mappings.  These are the mappings going from the processor to
 106          * the PCI bus.
 107          *
 108          * Note: Don't need to 'AND' start/end addresses with 0xffff0000
 109          *       because sanity check above ensures that they are properly
 110          *       aligned.
 111          */
 112
 113         /* Set up PPC->PCI Mem mapping */
 114         addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
 115         offset = (hose->mem_space.start - processor_pci_mem_start) | 0xd2;
 116         out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD0_OFF), addr);
 117         out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF0_OFF), offset);
 118
 119         /* Set up PPC->MPIC mapping on the bridge */
 120         addr = processor_mpic_base |
 121                 (((processor_mpic_base + HAWK_MPIC_SIZE) >> 16) - 1);
 122         /* No write posting for this PCI Mem space */
 123         offset = (hose->mem_space.start - processor_pci_mem_start) | 0xc2;
 124
 125         out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD1_OFF), addr);
 126         out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF1_OFF), offset);
 127
 128         /* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
 129         addr = processor_pci_io_start | (processor_pci_io_end >> 16);
 130         offset = (hose->io_space.start - processor_pci_io_start) | 0xc0;
 131         out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSADD3_OFF), addr);
 132         out_be32((uint *)(ppc_reg_base + HAWK_PPC_XSOFF3_OFF), offset);
 133
 134         hose->io_base_virt = (void *)ioremap(processor_pci_io_start,
 135                         (processor_pci_io_end - processor_pci_io_start + 1));
 136
 137         /*
 138          * Set up the indirect method of accessing PCI config space.
 139          * The PCI config addr/data pair based on start addr of PCI I/O space.
 140          */
 141         setup_indirect_pci(hose,
 142                            processor_pci_io_start + HAWK_PCI_CONFIG_ADDR_OFF,
 143                            processor_pci_io_start + HAWK_PCI_CONFIG_DATA_OFF);
 144
 145         /*
 146          * Disable previous PCI->PPC mappings.
 147          */
 148
 149         /* XXXX Put in mappings from PCI bus to processor bus XXXX */
 150
 151         /*
 152          * Disable MPIC response to PCI I/O space (BAR 0).
 153          * Make MPIC respond to PCI Mem space at specified address.
 154          * (BAR 1).
 155          */
 156         early_write_config_dword(hose,
 157                                  0,
 158                                  PCI_DEVFN(0,0),
 159                                  PCI_BASE_ADDRESS_0,
 160                                  0x00000000 | 0x1);
 161
 162         early_write_config_dword(hose,
 163                                  0,
 164                                  PCI_DEVFN(0,0),
 165                                  PCI_BASE_ADDRESS_1,
 166                                  (processor_mpic_base -
 167                                  processor_pci_mem_start +
 168                                  hose->mem_space.start) | 0x0);
 169
 170         /* Map MPIC into vitual memory */
 171         OpenPIC_Addr = ioremap(processor_mpic_base, HAWK_MPIC_SIZE);
 172
 173         return 0;
 174 }
 175
 176 /*
 177  * Find the amount of RAM present.
 178  * This assumes that PPCBug has initialized the memory controller (SMC)
 179  * on the Falcon/HAWK correctly (i.e., it does no sanity checking).
 180  * It also assumes that the memory base registers are set to configure the
 181  * memory as contigous starting with "RAM A BASE", "RAM B BASE", etc.
 182  * however, RAM base registers can be skipped (e.g. A, B, C are set,
 183  * D is skipped but E is set is okay).
 184  */
 185 #define MB      (1024*1024)
 186
 187 static uint reg_offset_table[] __initdata = {
 188         HAWK_SMC_RAM_A_SIZE_REG_OFF,
 189         HAWK_SMC_RAM_B_SIZE_REG_OFF,
 190         HAWK_SMC_RAM_C_SIZE_REG_OFF,
 191         HAWK_SMC_RAM_D_SIZE_REG_OFF,
 192         HAWK_SMC_RAM_E_SIZE_REG_OFF,
 193         HAWK_SMC_RAM_F_SIZE_REG_OFF,
 194         HAWK_SMC_RAM_G_SIZE_REG_OFF,
 195         HAWK_SMC_RAM_H_SIZE_REG_OFF
 196 };
 197
 198 static uint falcon_size_table[] __initdata = {
 199            0 * MB, /* 0 ==>    0 MB */
 200           16 * MB, /* 1 ==>   16 MB */
 201           32 * MB, /* 2 ==>   32 MB */
 202           64 * MB, /* 3 ==>   64 MB */
 203          128 * MB, /* 4 ==>  128 MB */
 204          256 * MB, /* 5 ==>  256 MB */
 205         1024 * MB, /* 6 ==> 1024 MB (1 GB) */
 206 };
 207
 208 static uint hawk_size_table[] __initdata = {
 209           0 * MB, /* 0 ==>    0 MB */
 210          32 * MB, /* 1 ==>   32 MB */
 211          64 * MB, /* 2 ==>   64 MB */
 212          64 * MB, /* 3 ==>   64 MB */
 213         128 * MB, /* 4 ==>  128 MB */
 214         128 * MB, /* 5 ==>  128 MB */
 215         128 * MB, /* 6 ==>  128 MB */
 216         256 * MB, /* 7 ==>  256 MB */
 217         256 * MB, /* 8 ==>  256 MB */
 218         512 * MB, /* 9 ==>  512 MB */
 219 };
 220
 221 /*
 222  * *** WARNING: You MUST have a BAT set up to map in the SMC regs ***
 223  *
 224  * Read the memory controller's registers to determine the amount of system
 225  * memory.  Assumes that the memory controller registers are already mapped
 226  * into virtual memory--too early to use ioremap().
 227  */
 228 unsigned long __init
 229 hawk_get_mem_size(uint smc_base)
 230 {
 231         unsigned long   total;
 232         int             i, size_table_entries, reg_limit;
 233         uint            vend_dev_id;
 234         uint            *size_table;
 235         u_char          val;
 236
 237
 238         vend_dev_id = in_be32((uint *)smc_base + PCI_VENDOR_ID);
 239
 240         if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) {
 241                 printk("hawk_get_mem_size: %s (0x%x)\n",
 242                         "Not a Motorola Memory Controller", vend_dev_id);
 243                 return 0;
 244         }
 245
 246         vend_dev_id &= 0x0000ffff;
 247
 248         if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_FALCON) {
 249                 size_table = falcon_size_table;
 250                 size_table_entries = sizeof(falcon_size_table) /
 251                                      sizeof(falcon_size_table[0]);
 252
 253                 reg_limit = FALCON_SMC_REG_COUNT;
 254         }
 255         else if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HAWK) {
 256                 size_table = hawk_size_table;
 257                 size_table_entries = sizeof(hawk_size_table) /
 258                                      sizeof(hawk_size_table[0]);
 259                 reg_limit = HAWK_SMC_REG_COUNT;
 260         }
 261         else {
 262                 printk("hawk_get_mem_size: %s (0x%x)\n",
 263                         "Not a Falcon or HAWK", vend_dev_id);
 264                 return 0;
 265         }
 266
 267         total = 0;
 268
 269         /* Check every reg because PPCBug may skip some */
 270         for (i=0; i<reg_limit; i++) {
 271                 val = in_8((u_char *)(smc_base + reg_offset_table[i]));
 272
 273                 if (val & 0x80) {       /* If enabled */
 274                         val &= 0x0f;
 275
 276                         /* Don't go past end of size_table */
 277                         if (val < size_table_entries) {
 278                                 total += size_table[val];
 279                         }
 280                         else {  /* Register not set correctly */
 281                                 break;
 282                         }
 283                 }
 284         }
 285
 286         return total;
 287 }
 288
 289 int __init
 290 hawk_mpic_init(unsigned int pci_mem_offset)
 291 {
 292         unsigned short  devid;
 293         unsigned int    pci_membase;
 294
 295         /* Check the first PCI device to see if it is a Raven or Hawk. */
 296         early_read_config_word(0, 0, 0, PCI_DEVICE_ID, &devid);
 297
 298         switch (devid) {
 299         case PCI_DEVICE_ID_MOTOROLA_RAVEN:
 300         case PCI_DEVICE_ID_MOTOROLA_HAWK:
 301                 break;
 302         default:
 303                 OpenPIC_Addr = NULL;
 304                 return 1;
 305         }
 306
 307         /* Read the memory base register. */
 308         early_read_config_dword(0, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
 309
 310         if (pci_membase == 0) {
 311                 OpenPIC_Addr = NULL;
 312                 return 1;
 313         }
 314
 315         /* Map the MPIC registers to virtual memory. */
 316         OpenPIC_Addr = ioremap(pci_membase + pci_mem_offset, 0x22000);
 317
 318         return 0;
 319 }