arch/ppc/platforms/83xx/mpc834x_sys.c

   1 /*
   2  * arch/ppc/platforms/83xx/mpc834x_sys.c
   3  *
   4  * MPC834x SYS board specific routines
   5  *
   6  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
   7  *
   8  * Copyright 2005 Freescale Semiconductor Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/stddef.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/reboot.h>
  22 #include <linux/pci.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/major.h>
  25 #include <linux/console.h>
  26 #include <linux/delay.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/serial.h>
  30 #include <linux/tty.h>  /* for linux/serial_core.h */
  31 #include <linux/serial_core.h>
  32 #include <linux/initrd.h>
  33 #include <linux/module.h>
  34 #include <linux/fsl_devices.h>
  35
  36 #include <asm/system.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/page.h>
  39 #include <asm/atomic.h>
  40 #include <asm/time.h>
  41 #include <asm/io.h>
  42 #include <asm/machdep.h>
  43 #include <asm/ipic.h>
  44 #include <asm/bootinfo.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/mpc83xx.h>
  47 #include <asm/irq.h>
  48 #include <asm/kgdb.h>
  49 #include <asm/ppc_sys.h>
  50 #include <mm/mmu_decl.h>
  51
  52 #include <syslib/ppc83xx_setup.h>
  53
  54 static const char *GFAR_PHY_0 = "phy0:0";
  55 static const char *GFAR_PHY_1 = "phy0:1";
  56
  57 #ifndef CONFIG_PCI
  58 unsigned long isa_io_base = 0;
  59 unsigned long isa_mem_base = 0;
  60 #endif
  61
  62 extern unsigned long total_memory;      /* in mm/init */
  63
  64 unsigned char __res[sizeof (bd_t)];
  65
  66 #ifdef CONFIG_PCI
  67 int
  68 mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  69 {
  70         static char pci_irq_table[][4] =
  71             /*
  72              *      PCI IDSEL/INTPIN->INTLINE
  73              *       A      B      C      D
  74              */
  75         {
  76                 {PIRQA, PIRQB,  PIRQC,  PIRQD}, /* idsel 0x11 */
  77                 {PIRQC, PIRQD,  PIRQA,  PIRQB}, /* idsel 0x12 */
  78                 {PIRQD, PIRQA,  PIRQB,  PIRQC}  /* idsel 0x13 */
  79         };
  80
  81         const long min_idsel = 0x11, max_idsel = 0x13, irqs_per_slot = 4;
  82         return PCI_IRQ_TABLE_LOOKUP;
  83 }
  84
  85 int
  86 mpc83xx_exclude_device(u_char bus, u_char devfn)
  87 {
  88         return PCIBIOS_SUCCESSFUL;
  89 }
  90 #endif /* CONFIG_PCI */
  91
  92 /* ************************************************************************
  93  *
  94  * Setup the architecture
  95  *
  96  */
  97 static void __init
  98 mpc834x_sys_setup_arch(void)
  99 {
 100         bd_t *binfo = (bd_t *) __res;
 101         unsigned int freq;
 102         struct gianfar_platform_data *pdata;
 103         struct gianfar_mdio_data *mdata;
 104
 105         /* get the core frequency */
 106         freq = binfo->bi_intfreq;
 107
 108         /* Set loops_per_jiffy to a half-way reasonable value,
 109            for use until calibrate_delay gets called. */
 110         loops_per_jiffy = freq / HZ;
 111
 112 #ifdef CONFIG_PCI
 113         /* setup PCI host bridges */
 114         mpc83xx_setup_hose();
 115 #endif
 116         mpc83xx_early_serial_map();
 117
 118         /* setup the board related info for the MDIO bus */
 119         mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC83xx_MDIO);
 120
 121         mdata->irq[0] = MPC83xx_IRQ_EXT1;
 122         mdata->irq[1] = MPC83xx_IRQ_EXT2;
 123         mdata->irq[2] = -1;
 124         mdata->irq[31] = -1;
 125         mdata->paddr += binfo->bi_immr_base;
 126
 127         /* setup the board related information for the enet controllers */
 128         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC1);
 129         if (pdata) {
 130                 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 131                 pdata->bus_id = GFAR_PHY_0;
 132                 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
 133         }
 134
 135         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC83xx_TSEC2);
 136         if (pdata) {
 137                 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 138                 pdata->bus_id = GFAR_PHY_1;
 139                 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
 140         }
 141
 142 #ifdef CONFIG_BLK_DEV_INITRD
 143         if (initrd_start)
 144                 ROOT_DEV = Root_RAM0;
 145         else
 146 #endif
 147 #ifdef  CONFIG_ROOT_NFS
 148                 ROOT_DEV = Root_NFS;
 149 #else
 150                 ROOT_DEV = Root_HDA1;
 151 #endif
 152 }
 153
 154 static void __init
 155 mpc834x_sys_map_io(void)
 156 {
 157         /* we steal the lowest ioremap addr for virt space */
 158         io_block_mapping(VIRT_IMMRBAR, immrbar, 1024*1024, _PAGE_IO);
 159 }
 160
 161 int
 162 mpc834x_sys_show_cpuinfo(struct seq_file *m)
 163 {
 164         uint pvid, svid, phid1;
 165         bd_t *binfo = (bd_t *) __res;
 166         unsigned int freq;
 167
 168         /* get the core frequency */
 169         freq = binfo->bi_intfreq;
 170
 171         pvid = mfspr(SPRN_PVR);
 172         svid = mfspr(SPRN_SVR);
 173
 174         seq_printf(m, "Vendor\t\t: Freescale Inc.\n");
 175         seq_printf(m, "Machine\t\t: mpc%s sys\n", cur_ppc_sys_spec->ppc_sys_name);
 176         seq_printf(m, "core clock\t: %d MHz\n"
 177                         "bus  clock\t: %d MHz\n",
 178                         (int)(binfo->bi_intfreq / 1000000),
 179                         (int)(binfo->bi_busfreq / 1000000));
 180         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 181         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 182
 183         /* Display cpu Pll setting */
 184         phid1 = mfspr(SPRN_HID1);
 185         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 186
 187         /* Display the amount of memory */
 188         seq_printf(m, "Memory\t\t: %d MB\n", (int)(binfo->bi_memsize / (1024 * 1024)));
 189
 190         return 0;
 191 }
 192
 193
 194 void __init
 195 mpc834x_sys_init_IRQ(void)
 196 {
 197         bd_t *binfo = (bd_t *) __res;
 198
 199         u8 senses[8] = {
 200                 0,                      /* EXT 0 */
 201                 IRQ_SENSE_LEVEL,        /* EXT 1 */
 202                 IRQ_SENSE_LEVEL,        /* EXT 2 */
 203                 0,                      /* EXT 3 */
 204 #ifdef CONFIG_PCI
 205                 IRQ_SENSE_LEVEL,        /* EXT 4 */
 206                 IRQ_SENSE_LEVEL,        /* EXT 5 */
 207                 IRQ_SENSE_LEVEL,        /* EXT 6 */
 208                 IRQ_SENSE_LEVEL,        /* EXT 7 */
 209 #else
 210                 0,                      /* EXT 4 */
 211                 0,                      /* EXT 5 */
 212                 0,                      /* EXT 6 */
 213                 0,                      /* EXT 7 */
 214 #endif
 215         };
 216
 217         ipic_init(binfo->bi_immr_base + 0x00700, 0, MPC83xx_IPIC_IRQ_OFFSET, senses, 8);
 218
 219         /* Initialize the default interrupt mapping priorities,
 220          * in case the boot rom changed something on us.
 221          */
 222         ipic_set_default_priority();
 223 }
 224
 225 #if defined(CONFIG_I2C_MPC) && defined(CONFIG_SENSORS_DS1374)
 226 extern ulong    ds1374_get_rtc_time(void);
 227 extern int      ds1374_set_rtc_time(ulong);
 228
 229 static int __init
 230 mpc834x_rtc_hookup(void)
 231 {
 232         struct timespec tv;
 233
 234         ppc_md.get_rtc_time = ds1374_get_rtc_time;
 235         ppc_md.set_rtc_time = ds1374_set_rtc_time;
 236
 237         tv.tv_nsec = 0;
 238         tv.tv_sec = (ppc_md.get_rtc_time)();
 239         do_settimeofday(&tv);
 240
 241         return 0;
 242 }
 243 late_initcall(mpc834x_rtc_hookup);
 244 #endif
 245 static __inline__ void
 246 mpc834x_sys_set_bat(void)
 247 {
 248         /* we steal the lowest ioremap addr for virt space */
 249         mb();
 250         mtspr(SPRN_DBAT1U, VIRT_IMMRBAR | 0x1e);
 251         mtspr(SPRN_DBAT1L, immrbar | 0x2a);
 252         mb();
 253 }
 254
 255 void __init
 256 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 257               unsigned long r6, unsigned long r7)
 258 {
 259         bd_t *binfo = (bd_t *) __res;
 260
 261         /* parse_bootinfo must always be called first */
 262         parse_bootinfo(find_bootinfo());
 263
 264         /*
 265          * If we were passed in a board information, copy it into the
 266          * residual data area.
 267          */
 268         if (r3) {
 269                 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
 270                        sizeof (bd_t));
 271         }
 272
 273 #if defined(CONFIG_BLK_DEV_INITRD)
 274         /*
 275          * If the init RAM disk has been configured in, and there's a valid
 276          * starting address for it, set it up.
 277          */
 278         if (r4) {
 279                 initrd_start = r4 + KERNELBASE;
 280                 initrd_end = r5 + KERNELBASE;
 281         }
 282 #endif /* CONFIG_BLK_DEV_INITRD */
 283
 284         /* Copy the kernel command line arguments to a safe place. */
 285         if (r6) {
 286                 *(char *) (r7 + KERNELBASE) = 0;
 287                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 288         }
 289
 290         immrbar = binfo->bi_immr_base;
 291
 292         mpc834x_sys_set_bat();
 293
 294 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
 295         {
 296                 struct uart_port p;
 297
 298                 memset(&p, 0, sizeof (p));
 299                 p.iotype = SERIAL_IO_MEM;
 300                 p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4500);
 301                 p.uartclk = binfo->bi_busfreq;
 302
 303                 gen550_init(0, &p);
 304
 305                 memset(&p, 0, sizeof (p));
 306                 p.iotype = SERIAL_IO_MEM;
 307                 p.membase = (unsigned char __iomem *)(VIRT_IMMRBAR + 0x4600);
 308                 p.uartclk = binfo->bi_busfreq;
 309
 310                 gen550_init(1, &p);
 311         }
 312 #endif
 313
 314         identify_ppc_sys_by_id(mfspr(SPRN_SVR));
 315
 316         /* setup the PowerPC module struct */
 317         ppc_md.setup_arch = mpc834x_sys_setup_arch;
 318         ppc_md.show_cpuinfo = mpc834x_sys_show_cpuinfo;
 319
 320         ppc_md.init_IRQ = mpc834x_sys_init_IRQ;
 321         ppc_md.get_irq = ipic_get_irq;
 322
 323         ppc_md.restart = mpc83xx_restart;
 324         ppc_md.power_off = mpc83xx_power_off;
 325         ppc_md.halt = mpc83xx_halt;
 326
 327         ppc_md.find_end_of_memory = mpc83xx_find_end_of_memory;
 328         ppc_md.setup_io_mappings  = mpc834x_sys_map_io;
 329
 330         ppc_md.time_init = mpc83xx_time_init;
 331         ppc_md.set_rtc_time = NULL;
 332         ppc_md.get_rtc_time = NULL;
 333         ppc_md.calibrate_decr = mpc83xx_calibrate_decr;
 334
 335         ppc_md.early_serial_map = mpc83xx_early_serial_map;
 336 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
 337         ppc_md.progress = gen550_progress;
 338 #endif  /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
 339
 340         if (ppc_md.progress)
 341                 ppc_md.progress("mpc834x_sys_init(): exit", 0);
 342
 343         return;
 344 }