1 #ifndef __POWERNV_PCI_H
2 #define __POWERNV_PCI_H
12 /* Precise PHB model for error management */
14 PNV_PHB_MODEL_UNKNOWN
,
20 #define PNV_PCI_DIAG_BUF_SIZE 4096
21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
25 /* Data associated with a PE, including IOMMU tracking etc.. */
31 /* A PE can be associated with a single device or an
32 * entire bus (& children). In the former case, pdev
33 * is populated, in the later case, pbus is.
38 /* Effective RID (device RID for a device PE and base bus
39 * RID with devfn 0 for a bus PE)
44 unsigned int pe_number
;
46 /* "Weight" assigned to the PE for the sake of DMA resource
49 unsigned int dma_weight
;
51 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
54 struct iommu_table tce32_table
;
56 /* XXX TODO: Add support for additional 64-bit iommus */
58 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
59 * and -1 if not supported. (It's actually identical to the
64 /* Link in list of PE#s */
65 struct list_head dma_link
;
66 struct list_head list
;
70 struct pci_controller
*hose
;
71 enum pnv_phb_type type
;
72 enum pnv_phb_model model
;
79 unsigned int msi_base
;
80 unsigned int msi32_support
;
81 struct msi_bitmap msi_bmp
;
83 int (*msi_setup
)(struct pnv_phb
*phb
, struct pci_dev
*dev
,
84 unsigned int hwirq
, unsigned int virq
,
85 unsigned int is_64
, struct msi_msg
*msg
);
86 void (*dma_dev_setup
)(struct pnv_phb
*phb
, struct pci_dev
*pdev
);
87 void (*fixup_phb
)(struct pci_controller
*hose
);
88 u32 (*bdfn_to_pe
)(struct pnv_phb
*phb
, struct pci_bus
*bus
, u32 devfn
);
92 struct iommu_table iommu_table
;
96 /* Global bridge info */
97 unsigned int total_pe
;
98 unsigned int m32_size
;
99 unsigned int m32_segsize
;
100 unsigned int m32_pci_base
;
101 unsigned int io_size
;
102 unsigned int io_segsize
;
103 unsigned int io_pci_base
;
105 /* PE allocation bitmap */
106 unsigned long *pe_alloc
;
108 /* M32 & IO segment maps */
109 unsigned int *m32_segmap
;
110 unsigned int *io_segmap
;
111 struct pnv_ioda_pe
*pe_array
;
115 struct irq_chip irq_chip
;
117 /* Sorted list of used PE's based
118 * on the sequence of creation
120 struct list_head pe_list
;
122 /* Reverse map of PEs, will have to extend if
123 * we are to support more than 256 PEs, indexed
126 unsigned char pe_rmap
[0x10000];
128 /* 32-bit TCE tables allocation */
129 unsigned long tce32_count
;
131 /* Total "weight" for the sake of DMA resources
134 unsigned int dma_weight
;
135 unsigned int dma_pe_count
;
137 /* Sorted list of used PE's, sorted at
138 * boot for resource allocation purposes
140 struct list_head pe_dma_list
;
144 /* PHB status structure */
146 unsigned char blob
[PNV_PCI_DIAG_BUF_SIZE
];
147 struct OpalIoP7IOCPhbErrorData p7ioc
;
151 extern struct pci_ops pnv_pci_ops
;
153 extern void pnv_pci_setup_iommu_table(struct iommu_table
*tbl
,
154 void *tce_mem
, u64 tce_size
,
156 extern void pnv_pci_init_p5ioc2_hub(struct device_node
*np
);
157 extern void pnv_pci_init_ioda_hub(struct device_node
*np
);
158 extern void pnv_pci_init_ioda2_phb(struct device_node
*np
);
159 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table
*tbl
,
160 u64
*startp
, u64
*endp
);
161 #endif /* __POWERNV_PCI_H */