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Merge branches 'sh/serial-rework' and 'sh/oprofile'
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kvm / emulate.c
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
14 *
15 * Copyright IBM Corp. 2007
16 *
17 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
18 */
19
20 #include <linux/jiffies.h>
21 #include <linux/timer.h>
22 #include <linux/types.h>
23 #include <linux/string.h>
24 #include <linux/kvm_host.h>
25
26 #include <asm/dcr.h>
27 #include <asm/dcr-regs.h>
28 #include <asm/time.h>
29 #include <asm/byteorder.h>
30 #include <asm/kvm_ppc.h>
31
32 #include "44x_tlb.h"
33
34 /* Instruction decoding */
35 static inline unsigned int get_op(u32 inst)
36 {
37 return inst >> 26;
38 }
39
40 static inline unsigned int get_xop(u32 inst)
41 {
42 return (inst >> 1) & 0x3ff;
43 }
44
45 static inline unsigned int get_sprn(u32 inst)
46 {
47 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
48 }
49
50 static inline unsigned int get_dcrn(u32 inst)
51 {
52 return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
53 }
54
55 static inline unsigned int get_rt(u32 inst)
56 {
57 return (inst >> 21) & 0x1f;
58 }
59
60 static inline unsigned int get_rs(u32 inst)
61 {
62 return (inst >> 21) & 0x1f;
63 }
64
65 static inline unsigned int get_ra(u32 inst)
66 {
67 return (inst >> 16) & 0x1f;
68 }
69
70 static inline unsigned int get_rb(u32 inst)
71 {
72 return (inst >> 11) & 0x1f;
73 }
74
75 static inline unsigned int get_rc(u32 inst)
76 {
77 return inst & 0x1;
78 }
79
80 static inline unsigned int get_ws(u32 inst)
81 {
82 return (inst >> 11) & 0x1f;
83 }
84
85 static inline unsigned int get_d(u32 inst)
86 {
87 return inst & 0xffff;
88 }
89
90 static int tlbe_is_host_safe(const struct kvm_vcpu *vcpu,
91 const struct tlbe *tlbe)
92 {
93 gpa_t gpa;
94
95 if (!get_tlb_v(tlbe))
96 return 0;
97
98 /* Does it match current guest AS? */
99 /* XXX what about IS != DS? */
100 if (get_tlb_ts(tlbe) != !!(vcpu->arch.msr & MSR_IS))
101 return 0;
102
103 gpa = get_tlb_raddr(tlbe);
104 if (!gfn_to_memslot(vcpu->kvm, gpa >> PAGE_SHIFT))
105 /* Mapping is not for RAM. */
106 return 0;
107
108 return 1;
109 }
110
111 static int kvmppc_emul_tlbwe(struct kvm_vcpu *vcpu, u32 inst)
112 {
113 u64 eaddr;
114 u64 raddr;
115 u64 asid;
116 u32 flags;
117 struct tlbe *tlbe;
118 unsigned int ra;
119 unsigned int rs;
120 unsigned int ws;
121 unsigned int index;
122
123 ra = get_ra(inst);
124 rs = get_rs(inst);
125 ws = get_ws(inst);
126
127 index = vcpu->arch.gpr[ra];
128 if (index > PPC44x_TLB_SIZE) {
129 printk("%s: index %d\n", __func__, index);
130 kvmppc_dump_vcpu(vcpu);
131 return EMULATE_FAIL;
132 }
133
134 tlbe = &vcpu->arch.guest_tlb[index];
135
136 /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
137 if (tlbe->word0 & PPC44x_TLB_VALID) {
138 eaddr = get_tlb_eaddr(tlbe);
139 asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
140 kvmppc_mmu_invalidate(vcpu, eaddr, get_tlb_end(tlbe), asid);
141 }
142
143 switch (ws) {
144 case PPC44x_TLB_PAGEID:
145 tlbe->tid = vcpu->arch.mmucr & 0xff;
146 tlbe->word0 = vcpu->arch.gpr[rs];
147 break;
148
149 case PPC44x_TLB_XLAT:
150 tlbe->word1 = vcpu->arch.gpr[rs];
151 break;
152
153 case PPC44x_TLB_ATTRIB:
154 tlbe->word2 = vcpu->arch.gpr[rs];
155 break;
156
157 default:
158 return EMULATE_FAIL;
159 }
160
161 if (tlbe_is_host_safe(vcpu, tlbe)) {
162 eaddr = get_tlb_eaddr(tlbe);
163 raddr = get_tlb_raddr(tlbe);
164 asid = (tlbe->word0 & PPC44x_TLB_TS) | tlbe->tid;
165 flags = tlbe->word2 & 0xffff;
166
167 /* Create a 4KB mapping on the host. If the guest wanted a
168 * large page, only the first 4KB is mapped here and the rest
169 * are mapped on the fly. */
170 kvmppc_mmu_map(vcpu, eaddr, raddr >> PAGE_SHIFT, asid, flags);
171 }
172
173 KVMTRACE_5D(GTLB_WRITE, vcpu, index,
174 tlbe->tid, tlbe->word0, tlbe->word1, tlbe->word2,
175 handler);
176
177 return EMULATE_DONE;
178 }
179
180 static void kvmppc_emulate_dec(struct kvm_vcpu *vcpu)
181 {
182 if (vcpu->arch.tcr & TCR_DIE) {
183 /* The decrementer ticks at the same rate as the timebase, so
184 * that's how we convert the guest DEC value to the number of
185 * host ticks. */
186 unsigned long nr_jiffies;
187
188 nr_jiffies = vcpu->arch.dec / tb_ticks_per_jiffy;
189 mod_timer(&vcpu->arch.dec_timer,
190 get_jiffies_64() + nr_jiffies);
191 } else {
192 del_timer(&vcpu->arch.dec_timer);
193 }
194 }
195
196 static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
197 {
198 vcpu->arch.pc = vcpu->arch.srr0;
199 kvmppc_set_msr(vcpu, vcpu->arch.srr1);
200 }
201
202 /* XXX to do:
203 * lhax
204 * lhaux
205 * lswx
206 * lswi
207 * stswx
208 * stswi
209 * lha
210 * lhau
211 * lmw
212 * stmw
213 *
214 * XXX is_bigendian should depend on MMU mapping or MSR[LE]
215 */
216 int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
217 {
218 u32 inst = vcpu->arch.last_inst;
219 u32 ea;
220 int ra;
221 int rb;
222 int rc;
223 int rs;
224 int rt;
225 int sprn;
226 int dcrn;
227 enum emulation_result emulated = EMULATE_DONE;
228 int advance = 1;
229
230 switch (get_op(inst)) {
231 case 3: /* trap */
232 printk("trap!\n");
233 kvmppc_queue_exception(vcpu, BOOKE_INTERRUPT_PROGRAM);
234 advance = 0;
235 break;
236
237 case 19:
238 switch (get_xop(inst)) {
239 case 50: /* rfi */
240 kvmppc_emul_rfi(vcpu);
241 advance = 0;
242 break;
243
244 default:
245 emulated = EMULATE_FAIL;
246 break;
247 }
248 break;
249
250 case 31:
251 switch (get_xop(inst)) {
252
253 case 23: /* lwzx */
254 rt = get_rt(inst);
255 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
256 break;
257
258 case 83: /* mfmsr */
259 rt = get_rt(inst);
260 vcpu->arch.gpr[rt] = vcpu->arch.msr;
261 break;
262
263 case 87: /* lbzx */
264 rt = get_rt(inst);
265 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
266 break;
267
268 case 131: /* wrtee */
269 rs = get_rs(inst);
270 vcpu->arch.msr = (vcpu->arch.msr & ~MSR_EE)
271 | (vcpu->arch.gpr[rs] & MSR_EE);
272 break;
273
274 case 146: /* mtmsr */
275 rs = get_rs(inst);
276 kvmppc_set_msr(vcpu, vcpu->arch.gpr[rs]);
277 break;
278
279 case 151: /* stwx */
280 rs = get_rs(inst);
281 emulated = kvmppc_handle_store(run, vcpu,
282 vcpu->arch.gpr[rs],
283 4, 1);
284 break;
285
286 case 163: /* wrteei */
287 vcpu->arch.msr = (vcpu->arch.msr & ~MSR_EE)
288 | (inst & MSR_EE);
289 break;
290
291 case 215: /* stbx */
292 rs = get_rs(inst);
293 emulated = kvmppc_handle_store(run, vcpu,
294 vcpu->arch.gpr[rs],
295 1, 1);
296 break;
297
298 case 247: /* stbux */
299 rs = get_rs(inst);
300 ra = get_ra(inst);
301 rb = get_rb(inst);
302
303 ea = vcpu->arch.gpr[rb];
304 if (ra)
305 ea += vcpu->arch.gpr[ra];
306
307 emulated = kvmppc_handle_store(run, vcpu,
308 vcpu->arch.gpr[rs],
309 1, 1);
310 vcpu->arch.gpr[rs] = ea;
311 break;
312
313 case 279: /* lhzx */
314 rt = get_rt(inst);
315 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
316 break;
317
318 case 311: /* lhzux */
319 rt = get_rt(inst);
320 ra = get_ra(inst);
321 rb = get_rb(inst);
322
323 ea = vcpu->arch.gpr[rb];
324 if (ra)
325 ea += vcpu->arch.gpr[ra];
326
327 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
328 vcpu->arch.gpr[ra] = ea;
329 break;
330
331 case 323: /* mfdcr */
332 dcrn = get_dcrn(inst);
333 rt = get_rt(inst);
334
335 /* The guest may access CPR0 registers to determine the timebase
336 * frequency, and it must know the real host frequency because it
337 * can directly access the timebase registers.
338 *
339 * It would be possible to emulate those accesses in userspace,
340 * but userspace can really only figure out the end frequency.
341 * We could decompose that into the factors that compute it, but
342 * that's tricky math, and it's easier to just report the real
343 * CPR0 values.
344 */
345 switch (dcrn) {
346 case DCRN_CPR0_CONFIG_ADDR:
347 vcpu->arch.gpr[rt] = vcpu->arch.cpr0_cfgaddr;
348 break;
349 case DCRN_CPR0_CONFIG_DATA:
350 local_irq_disable();
351 mtdcr(DCRN_CPR0_CONFIG_ADDR,
352 vcpu->arch.cpr0_cfgaddr);
353 vcpu->arch.gpr[rt] = mfdcr(DCRN_CPR0_CONFIG_DATA);
354 local_irq_enable();
355 break;
356 default:
357 run->dcr.dcrn = dcrn;
358 run->dcr.data = 0;
359 run->dcr.is_write = 0;
360 vcpu->arch.io_gpr = rt;
361 vcpu->arch.dcr_needed = 1;
362 emulated = EMULATE_DO_DCR;
363 }
364
365 break;
366
367 case 339: /* mfspr */
368 sprn = get_sprn(inst);
369 rt = get_rt(inst);
370
371 switch (sprn) {
372 case SPRN_SRR0:
373 vcpu->arch.gpr[rt] = vcpu->arch.srr0; break;
374 case SPRN_SRR1:
375 vcpu->arch.gpr[rt] = vcpu->arch.srr1; break;
376 case SPRN_MMUCR:
377 vcpu->arch.gpr[rt] = vcpu->arch.mmucr; break;
378 case SPRN_PID:
379 vcpu->arch.gpr[rt] = vcpu->arch.pid; break;
380 case SPRN_IVPR:
381 vcpu->arch.gpr[rt] = vcpu->arch.ivpr; break;
382 case SPRN_CCR0:
383 vcpu->arch.gpr[rt] = vcpu->arch.ccr0; break;
384 case SPRN_CCR1:
385 vcpu->arch.gpr[rt] = vcpu->arch.ccr1; break;
386 case SPRN_PVR:
387 vcpu->arch.gpr[rt] = vcpu->arch.pvr; break;
388 case SPRN_DEAR:
389 vcpu->arch.gpr[rt] = vcpu->arch.dear; break;
390 case SPRN_ESR:
391 vcpu->arch.gpr[rt] = vcpu->arch.esr; break;
392 case SPRN_DBCR0:
393 vcpu->arch.gpr[rt] = vcpu->arch.dbcr0; break;
394 case SPRN_DBCR1:
395 vcpu->arch.gpr[rt] = vcpu->arch.dbcr1; break;
396
397 /* Note: mftb and TBRL/TBWL are user-accessible, so
398 * the guest can always access the real TB anyways.
399 * In fact, we probably will never see these traps. */
400 case SPRN_TBWL:
401 vcpu->arch.gpr[rt] = mftbl(); break;
402 case SPRN_TBWU:
403 vcpu->arch.gpr[rt] = mftbu(); break;
404
405 case SPRN_SPRG0:
406 vcpu->arch.gpr[rt] = vcpu->arch.sprg0; break;
407 case SPRN_SPRG1:
408 vcpu->arch.gpr[rt] = vcpu->arch.sprg1; break;
409 case SPRN_SPRG2:
410 vcpu->arch.gpr[rt] = vcpu->arch.sprg2; break;
411 case SPRN_SPRG3:
412 vcpu->arch.gpr[rt] = vcpu->arch.sprg3; break;
413 /* Note: SPRG4-7 are user-readable, so we don't get
414 * a trap. */
415
416 case SPRN_IVOR0:
417 vcpu->arch.gpr[rt] = vcpu->arch.ivor[0]; break;
418 case SPRN_IVOR1:
419 vcpu->arch.gpr[rt] = vcpu->arch.ivor[1]; break;
420 case SPRN_IVOR2:
421 vcpu->arch.gpr[rt] = vcpu->arch.ivor[2]; break;
422 case SPRN_IVOR3:
423 vcpu->arch.gpr[rt] = vcpu->arch.ivor[3]; break;
424 case SPRN_IVOR4:
425 vcpu->arch.gpr[rt] = vcpu->arch.ivor[4]; break;
426 case SPRN_IVOR5:
427 vcpu->arch.gpr[rt] = vcpu->arch.ivor[5]; break;
428 case SPRN_IVOR6:
429 vcpu->arch.gpr[rt] = vcpu->arch.ivor[6]; break;
430 case SPRN_IVOR7:
431 vcpu->arch.gpr[rt] = vcpu->arch.ivor[7]; break;
432 case SPRN_IVOR8:
433 vcpu->arch.gpr[rt] = vcpu->arch.ivor[8]; break;
434 case SPRN_IVOR9:
435 vcpu->arch.gpr[rt] = vcpu->arch.ivor[9]; break;
436 case SPRN_IVOR10:
437 vcpu->arch.gpr[rt] = vcpu->arch.ivor[10]; break;
438 case SPRN_IVOR11:
439 vcpu->arch.gpr[rt] = vcpu->arch.ivor[11]; break;
440 case SPRN_IVOR12:
441 vcpu->arch.gpr[rt] = vcpu->arch.ivor[12]; break;
442 case SPRN_IVOR13:
443 vcpu->arch.gpr[rt] = vcpu->arch.ivor[13]; break;
444 case SPRN_IVOR14:
445 vcpu->arch.gpr[rt] = vcpu->arch.ivor[14]; break;
446 case SPRN_IVOR15:
447 vcpu->arch.gpr[rt] = vcpu->arch.ivor[15]; break;
448
449 default:
450 printk("mfspr: unknown spr %x\n", sprn);
451 vcpu->arch.gpr[rt] = 0;
452 break;
453 }
454 break;
455
456 case 407: /* sthx */
457 rs = get_rs(inst);
458 ra = get_ra(inst);
459 rb = get_rb(inst);
460
461 emulated = kvmppc_handle_store(run, vcpu,
462 vcpu->arch.gpr[rs],
463 2, 1);
464 break;
465
466 case 439: /* sthux */
467 rs = get_rs(inst);
468 ra = get_ra(inst);
469 rb = get_rb(inst);
470
471 ea = vcpu->arch.gpr[rb];
472 if (ra)
473 ea += vcpu->arch.gpr[ra];
474
475 emulated = kvmppc_handle_store(run, vcpu,
476 vcpu->arch.gpr[rs],
477 2, 1);
478 vcpu->arch.gpr[ra] = ea;
479 break;
480
481 case 451: /* mtdcr */
482 dcrn = get_dcrn(inst);
483 rs = get_rs(inst);
484
485 /* emulate some access in kernel */
486 switch (dcrn) {
487 case DCRN_CPR0_CONFIG_ADDR:
488 vcpu->arch.cpr0_cfgaddr = vcpu->arch.gpr[rs];
489 break;
490 default:
491 run->dcr.dcrn = dcrn;
492 run->dcr.data = vcpu->arch.gpr[rs];
493 run->dcr.is_write = 1;
494 vcpu->arch.dcr_needed = 1;
495 emulated = EMULATE_DO_DCR;
496 }
497
498 break;
499
500 case 467: /* mtspr */
501 sprn = get_sprn(inst);
502 rs = get_rs(inst);
503 switch (sprn) {
504 case SPRN_SRR0:
505 vcpu->arch.srr0 = vcpu->arch.gpr[rs]; break;
506 case SPRN_SRR1:
507 vcpu->arch.srr1 = vcpu->arch.gpr[rs]; break;
508 case SPRN_MMUCR:
509 vcpu->arch.mmucr = vcpu->arch.gpr[rs]; break;
510 case SPRN_PID:
511 kvmppc_set_pid(vcpu, vcpu->arch.gpr[rs]); break;
512 case SPRN_CCR0:
513 vcpu->arch.ccr0 = vcpu->arch.gpr[rs]; break;
514 case SPRN_CCR1:
515 vcpu->arch.ccr1 = vcpu->arch.gpr[rs]; break;
516 case SPRN_DEAR:
517 vcpu->arch.dear = vcpu->arch.gpr[rs]; break;
518 case SPRN_ESR:
519 vcpu->arch.esr = vcpu->arch.gpr[rs]; break;
520 case SPRN_DBCR0:
521 vcpu->arch.dbcr0 = vcpu->arch.gpr[rs]; break;
522 case SPRN_DBCR1:
523 vcpu->arch.dbcr1 = vcpu->arch.gpr[rs]; break;
524
525 /* XXX We need to context-switch the timebase for
526 * watchdog and FIT. */
527 case SPRN_TBWL: break;
528 case SPRN_TBWU: break;
529
530 case SPRN_DEC:
531 vcpu->arch.dec = vcpu->arch.gpr[rs];
532 kvmppc_emulate_dec(vcpu);
533 break;
534
535 case SPRN_TSR:
536 vcpu->arch.tsr &= ~vcpu->arch.gpr[rs]; break;
537
538 case SPRN_TCR:
539 vcpu->arch.tcr = vcpu->arch.gpr[rs];
540 kvmppc_emulate_dec(vcpu);
541 break;
542
543 case SPRN_SPRG0:
544 vcpu->arch.sprg0 = vcpu->arch.gpr[rs]; break;
545 case SPRN_SPRG1:
546 vcpu->arch.sprg1 = vcpu->arch.gpr[rs]; break;
547 case SPRN_SPRG2:
548 vcpu->arch.sprg2 = vcpu->arch.gpr[rs]; break;
549 case SPRN_SPRG3:
550 vcpu->arch.sprg3 = vcpu->arch.gpr[rs]; break;
551
552 /* Note: SPRG4-7 are user-readable. These values are
553 * loaded into the real SPRGs when resuming the
554 * guest. */
555 case SPRN_SPRG4:
556 vcpu->arch.sprg4 = vcpu->arch.gpr[rs]; break;
557 case SPRN_SPRG5:
558 vcpu->arch.sprg5 = vcpu->arch.gpr[rs]; break;
559 case SPRN_SPRG6:
560 vcpu->arch.sprg6 = vcpu->arch.gpr[rs]; break;
561 case SPRN_SPRG7:
562 vcpu->arch.sprg7 = vcpu->arch.gpr[rs]; break;
563
564 case SPRN_IVPR:
565 vcpu->arch.ivpr = vcpu->arch.gpr[rs]; break;
566 case SPRN_IVOR0:
567 vcpu->arch.ivor[0] = vcpu->arch.gpr[rs]; break;
568 case SPRN_IVOR1:
569 vcpu->arch.ivor[1] = vcpu->arch.gpr[rs]; break;
570 case SPRN_IVOR2:
571 vcpu->arch.ivor[2] = vcpu->arch.gpr[rs]; break;
572 case SPRN_IVOR3:
573 vcpu->arch.ivor[3] = vcpu->arch.gpr[rs]; break;
574 case SPRN_IVOR4:
575 vcpu->arch.ivor[4] = vcpu->arch.gpr[rs]; break;
576 case SPRN_IVOR5:
577 vcpu->arch.ivor[5] = vcpu->arch.gpr[rs]; break;
578 case SPRN_IVOR6:
579 vcpu->arch.ivor[6] = vcpu->arch.gpr[rs]; break;
580 case SPRN_IVOR7:
581 vcpu->arch.ivor[7] = vcpu->arch.gpr[rs]; break;
582 case SPRN_IVOR8:
583 vcpu->arch.ivor[8] = vcpu->arch.gpr[rs]; break;
584 case SPRN_IVOR9:
585 vcpu->arch.ivor[9] = vcpu->arch.gpr[rs]; break;
586 case SPRN_IVOR10:
587 vcpu->arch.ivor[10] = vcpu->arch.gpr[rs]; break;
588 case SPRN_IVOR11:
589 vcpu->arch.ivor[11] = vcpu->arch.gpr[rs]; break;
590 case SPRN_IVOR12:
591 vcpu->arch.ivor[12] = vcpu->arch.gpr[rs]; break;
592 case SPRN_IVOR13:
593 vcpu->arch.ivor[13] = vcpu->arch.gpr[rs]; break;
594 case SPRN_IVOR14:
595 vcpu->arch.ivor[14] = vcpu->arch.gpr[rs]; break;
596 case SPRN_IVOR15:
597 vcpu->arch.ivor[15] = vcpu->arch.gpr[rs]; break;
598
599 default:
600 printk("mtspr: unknown spr %x\n", sprn);
601 emulated = EMULATE_FAIL;
602 break;
603 }
604 break;
605
606 case 470: /* dcbi */
607 /* Do nothing. The guest is performing dcbi because
608 * hardware DMA is not snooped by the dcache, but
609 * emulated DMA either goes through the dcache as
610 * normal writes, or the host kernel has handled dcache
611 * coherence. */
612 break;
613
614 case 534: /* lwbrx */
615 rt = get_rt(inst);
616 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 0);
617 break;
618
619 case 566: /* tlbsync */
620 break;
621
622 case 662: /* stwbrx */
623 rs = get_rs(inst);
624 ra = get_ra(inst);
625 rb = get_rb(inst);
626
627 emulated = kvmppc_handle_store(run, vcpu,
628 vcpu->arch.gpr[rs],
629 4, 0);
630 break;
631
632 case 978: /* tlbwe */
633 emulated = kvmppc_emul_tlbwe(vcpu, inst);
634 break;
635
636 case 914: { /* tlbsx */
637 int index;
638 unsigned int as = get_mmucr_sts(vcpu);
639 unsigned int pid = get_mmucr_stid(vcpu);
640
641 rt = get_rt(inst);
642 ra = get_ra(inst);
643 rb = get_rb(inst);
644 rc = get_rc(inst);
645
646 ea = vcpu->arch.gpr[rb];
647 if (ra)
648 ea += vcpu->arch.gpr[ra];
649
650 index = kvmppc_44x_tlb_index(vcpu, ea, pid, as);
651 if (rc) {
652 if (index < 0)
653 vcpu->arch.cr &= ~0x20000000;
654 else
655 vcpu->arch.cr |= 0x20000000;
656 }
657 vcpu->arch.gpr[rt] = index;
658
659 }
660 break;
661
662 case 790: /* lhbrx */
663 rt = get_rt(inst);
664 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 0);
665 break;
666
667 case 918: /* sthbrx */
668 rs = get_rs(inst);
669 ra = get_ra(inst);
670 rb = get_rb(inst);
671
672 emulated = kvmppc_handle_store(run, vcpu,
673 vcpu->arch.gpr[rs],
674 2, 0);
675 break;
676
677 case 966: /* iccci */
678 break;
679
680 default:
681 printk("unknown: op %d xop %d\n", get_op(inst),
682 get_xop(inst));
683 emulated = EMULATE_FAIL;
684 break;
685 }
686 break;
687
688 case 32: /* lwz */
689 rt = get_rt(inst);
690 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
691 break;
692
693 case 33: /* lwzu */
694 ra = get_ra(inst);
695 rt = get_rt(inst);
696 emulated = kvmppc_handle_load(run, vcpu, rt, 4, 1);
697 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
698 break;
699
700 case 34: /* lbz */
701 rt = get_rt(inst);
702 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
703 break;
704
705 case 35: /* lbzu */
706 ra = get_ra(inst);
707 rt = get_rt(inst);
708 emulated = kvmppc_handle_load(run, vcpu, rt, 1, 1);
709 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
710 break;
711
712 case 36: /* stw */
713 rs = get_rs(inst);
714 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
715 4, 1);
716 break;
717
718 case 37: /* stwu */
719 ra = get_ra(inst);
720 rs = get_rs(inst);
721 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
722 4, 1);
723 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
724 break;
725
726 case 38: /* stb */
727 rs = get_rs(inst);
728 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
729 1, 1);
730 break;
731
732 case 39: /* stbu */
733 ra = get_ra(inst);
734 rs = get_rs(inst);
735 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
736 1, 1);
737 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
738 break;
739
740 case 40: /* lhz */
741 rt = get_rt(inst);
742 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
743 break;
744
745 case 41: /* lhzu */
746 ra = get_ra(inst);
747 rt = get_rt(inst);
748 emulated = kvmppc_handle_load(run, vcpu, rt, 2, 1);
749 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
750 break;
751
752 case 44: /* sth */
753 rs = get_rs(inst);
754 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
755 2, 1);
756 break;
757
758 case 45: /* sthu */
759 ra = get_ra(inst);
760 rs = get_rs(inst);
761 emulated = kvmppc_handle_store(run, vcpu, vcpu->arch.gpr[rs],
762 2, 1);
763 vcpu->arch.gpr[ra] = vcpu->arch.paddr_accessed;
764 break;
765
766 default:
767 printk("unknown op %d\n", get_op(inst));
768 emulated = EMULATE_FAIL;
769 break;
770 }
771
772 KVMTRACE_3D(PPC_INSTR, vcpu, inst, vcpu->arch.pc, emulated, entryexit);
773
774 if (advance)
775 vcpu->arch.pc += 4; /* Advance past emulated instruction. */
776
777 return emulated;
778 }
kernel source for telekom puls (alcatel/mediatek)