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Merge remote-tracking branch 'regmap/fix/debugfs' into regmap-linus
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / ptrace.c
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
9 *
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
11 * and Paul Mackerras (paulus@samba.org).
12 *
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/sched.h>
20 #include <linux/mm.h>
21 #include <linux/smp.h>
22 #include <linux/errno.h>
23 #include <linux/ptrace.h>
24 #include <linux/regset.h>
25 #include <linux/tracehook.h>
26 #include <linux/elf.h>
27 #include <linux/user.h>
28 #include <linux/security.h>
29 #include <linux/signal.h>
30 #include <linux/seccomp.h>
31 #include <linux/audit.h>
32 #include <trace/syscall.h>
33 #include <linux/hw_breakpoint.h>
34 #include <linux/perf_event.h>
35 #include <linux/context_tracking.h>
36
37 #include <asm/uaccess.h>
38 #include <asm/page.h>
39 #include <asm/pgtable.h>
40 #include <asm/switch_to.h>
41
42 #define CREATE_TRACE_POINTS
43 #include <trace/events/syscalls.h>
44
45 /*
46 * The parameter save area on the stack is used to store arguments being passed
47 * to callee function and is located at fixed offset from stack pointer.
48 */
49 #ifdef CONFIG_PPC32
50 #define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
51 #else /* CONFIG_PPC32 */
52 #define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
53 #endif
54
55 struct pt_regs_offset {
56 const char *name;
57 int offset;
58 };
59
60 #define STR(s) #s /* convert to string */
61 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
62 #define GPR_OFFSET_NAME(num) \
63 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
64 #define REG_OFFSET_END {.name = NULL, .offset = 0}
65
66 static const struct pt_regs_offset regoffset_table[] = {
67 GPR_OFFSET_NAME(0),
68 GPR_OFFSET_NAME(1),
69 GPR_OFFSET_NAME(2),
70 GPR_OFFSET_NAME(3),
71 GPR_OFFSET_NAME(4),
72 GPR_OFFSET_NAME(5),
73 GPR_OFFSET_NAME(6),
74 GPR_OFFSET_NAME(7),
75 GPR_OFFSET_NAME(8),
76 GPR_OFFSET_NAME(9),
77 GPR_OFFSET_NAME(10),
78 GPR_OFFSET_NAME(11),
79 GPR_OFFSET_NAME(12),
80 GPR_OFFSET_NAME(13),
81 GPR_OFFSET_NAME(14),
82 GPR_OFFSET_NAME(15),
83 GPR_OFFSET_NAME(16),
84 GPR_OFFSET_NAME(17),
85 GPR_OFFSET_NAME(18),
86 GPR_OFFSET_NAME(19),
87 GPR_OFFSET_NAME(20),
88 GPR_OFFSET_NAME(21),
89 GPR_OFFSET_NAME(22),
90 GPR_OFFSET_NAME(23),
91 GPR_OFFSET_NAME(24),
92 GPR_OFFSET_NAME(25),
93 GPR_OFFSET_NAME(26),
94 GPR_OFFSET_NAME(27),
95 GPR_OFFSET_NAME(28),
96 GPR_OFFSET_NAME(29),
97 GPR_OFFSET_NAME(30),
98 GPR_OFFSET_NAME(31),
99 REG_OFFSET_NAME(nip),
100 REG_OFFSET_NAME(msr),
101 REG_OFFSET_NAME(ctr),
102 REG_OFFSET_NAME(link),
103 REG_OFFSET_NAME(xer),
104 REG_OFFSET_NAME(ccr),
105 #ifdef CONFIG_PPC64
106 REG_OFFSET_NAME(softe),
107 #else
108 REG_OFFSET_NAME(mq),
109 #endif
110 REG_OFFSET_NAME(trap),
111 REG_OFFSET_NAME(dar),
112 REG_OFFSET_NAME(dsisr),
113 REG_OFFSET_END,
114 };
115
116 /**
117 * regs_query_register_offset() - query register offset from its name
118 * @name: the name of a register
119 *
120 * regs_query_register_offset() returns the offset of a register in struct
121 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
122 */
123 int regs_query_register_offset(const char *name)
124 {
125 const struct pt_regs_offset *roff;
126 for (roff = regoffset_table; roff->name != NULL; roff++)
127 if (!strcmp(roff->name, name))
128 return roff->offset;
129 return -EINVAL;
130 }
131
132 /**
133 * regs_query_register_name() - query register name from its offset
134 * @offset: the offset of a register in struct pt_regs.
135 *
136 * regs_query_register_name() returns the name of a register from its
137 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
138 */
139 const char *regs_query_register_name(unsigned int offset)
140 {
141 const struct pt_regs_offset *roff;
142 for (roff = regoffset_table; roff->name != NULL; roff++)
143 if (roff->offset == offset)
144 return roff->name;
145 return NULL;
146 }
147
148 /*
149 * does not yet catch signals sent when the child dies.
150 * in exit.c or in signal.c.
151 */
152
153 /*
154 * Set of msr bits that gdb can change on behalf of a process.
155 */
156 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
157 #define MSR_DEBUGCHANGE 0
158 #else
159 #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
160 #endif
161
162 /*
163 * Max register writeable via put_reg
164 */
165 #ifdef CONFIG_PPC32
166 #define PT_MAX_PUT_REG PT_MQ
167 #else
168 #define PT_MAX_PUT_REG PT_CCR
169 #endif
170
171 static unsigned long get_user_msr(struct task_struct *task)
172 {
173 return task->thread.regs->msr | task->thread.fpexc_mode;
174 }
175
176 static int set_user_msr(struct task_struct *task, unsigned long msr)
177 {
178 task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
179 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
180 return 0;
181 }
182
183 #ifdef CONFIG_PPC64
184 static int get_user_dscr(struct task_struct *task, unsigned long *data)
185 {
186 *data = task->thread.dscr;
187 return 0;
188 }
189
190 static int set_user_dscr(struct task_struct *task, unsigned long dscr)
191 {
192 task->thread.dscr = dscr;
193 task->thread.dscr_inherit = 1;
194 return 0;
195 }
196 #else
197 static int get_user_dscr(struct task_struct *task, unsigned long *data)
198 {
199 return -EIO;
200 }
201
202 static int set_user_dscr(struct task_struct *task, unsigned long dscr)
203 {
204 return -EIO;
205 }
206 #endif
207
208 /*
209 * We prevent mucking around with the reserved area of trap
210 * which are used internally by the kernel.
211 */
212 static int set_user_trap(struct task_struct *task, unsigned long trap)
213 {
214 task->thread.regs->trap = trap & 0xfff0;
215 return 0;
216 }
217
218 /*
219 * Get contents of register REGNO in task TASK.
220 */
221 int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data)
222 {
223 if ((task->thread.regs == NULL) || !data)
224 return -EIO;
225
226 if (regno == PT_MSR) {
227 *data = get_user_msr(task);
228 return 0;
229 }
230
231 if (regno == PT_DSCR)
232 return get_user_dscr(task, data);
233
234 if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
235 *data = ((unsigned long *)task->thread.regs)[regno];
236 return 0;
237 }
238
239 return -EIO;
240 }
241
242 /*
243 * Write contents of register REGNO in task TASK.
244 */
245 int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
246 {
247 if (task->thread.regs == NULL)
248 return -EIO;
249
250 if (regno == PT_MSR)
251 return set_user_msr(task, data);
252 if (regno == PT_TRAP)
253 return set_user_trap(task, data);
254 if (regno == PT_DSCR)
255 return set_user_dscr(task, data);
256
257 if (regno <= PT_MAX_PUT_REG) {
258 ((unsigned long *)task->thread.regs)[regno] = data;
259 return 0;
260 }
261 return -EIO;
262 }
263
264 static int gpr_get(struct task_struct *target, const struct user_regset *regset,
265 unsigned int pos, unsigned int count,
266 void *kbuf, void __user *ubuf)
267 {
268 int i, ret;
269
270 if (target->thread.regs == NULL)
271 return -EIO;
272
273 if (!FULL_REGS(target->thread.regs)) {
274 /* We have a partial register set. Fill 14-31 with bogus values */
275 for (i = 14; i < 32; i++)
276 target->thread.regs->gpr[i] = NV_REG_POISON;
277 }
278
279 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
280 target->thread.regs,
281 0, offsetof(struct pt_regs, msr));
282 if (!ret) {
283 unsigned long msr = get_user_msr(target);
284 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
285 offsetof(struct pt_regs, msr),
286 offsetof(struct pt_regs, msr) +
287 sizeof(msr));
288 }
289
290 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
291 offsetof(struct pt_regs, msr) + sizeof(long));
292
293 if (!ret)
294 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
295 &target->thread.regs->orig_gpr3,
296 offsetof(struct pt_regs, orig_gpr3),
297 sizeof(struct pt_regs));
298 if (!ret)
299 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
300 sizeof(struct pt_regs), -1);
301
302 return ret;
303 }
304
305 static int gpr_set(struct task_struct *target, const struct user_regset *regset,
306 unsigned int pos, unsigned int count,
307 const void *kbuf, const void __user *ubuf)
308 {
309 unsigned long reg;
310 int ret;
311
312 if (target->thread.regs == NULL)
313 return -EIO;
314
315 CHECK_FULL_REGS(target->thread.regs);
316
317 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
318 target->thread.regs,
319 0, PT_MSR * sizeof(reg));
320
321 if (!ret && count > 0) {
322 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
323 PT_MSR * sizeof(reg),
324 (PT_MSR + 1) * sizeof(reg));
325 if (!ret)
326 ret = set_user_msr(target, reg);
327 }
328
329 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
330 offsetof(struct pt_regs, msr) + sizeof(long));
331
332 if (!ret)
333 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
334 &target->thread.regs->orig_gpr3,
335 PT_ORIG_R3 * sizeof(reg),
336 (PT_MAX_PUT_REG + 1) * sizeof(reg));
337
338 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
339 ret = user_regset_copyin_ignore(
340 &pos, &count, &kbuf, &ubuf,
341 (PT_MAX_PUT_REG + 1) * sizeof(reg),
342 PT_TRAP * sizeof(reg));
343
344 if (!ret && count > 0) {
345 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
346 PT_TRAP * sizeof(reg),
347 (PT_TRAP + 1) * sizeof(reg));
348 if (!ret)
349 ret = set_user_trap(target, reg);
350 }
351
352 if (!ret)
353 ret = user_regset_copyin_ignore(
354 &pos, &count, &kbuf, &ubuf,
355 (PT_TRAP + 1) * sizeof(reg), -1);
356
357 return ret;
358 }
359
360 static int fpr_get(struct task_struct *target, const struct user_regset *regset,
361 unsigned int pos, unsigned int count,
362 void *kbuf, void __user *ubuf)
363 {
364 #ifdef CONFIG_VSX
365 double buf[33];
366 int i;
367 #endif
368 flush_fp_to_thread(target);
369
370 #ifdef CONFIG_VSX
371 /* copy to local buffer then write that out */
372 for (i = 0; i < 32 ; i++)
373 buf[i] = target->thread.TS_FPR(i);
374 memcpy(&buf[32], &target->thread.fpscr, sizeof(double));
375 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
376
377 #else
378 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
379 offsetof(struct thread_struct, TS_FPR(32)));
380
381 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
382 &target->thread.fpr, 0, -1);
383 #endif
384 }
385
386 static int fpr_set(struct task_struct *target, const struct user_regset *regset,
387 unsigned int pos, unsigned int count,
388 const void *kbuf, const void __user *ubuf)
389 {
390 #ifdef CONFIG_VSX
391 double buf[33];
392 int i;
393 #endif
394 flush_fp_to_thread(target);
395
396 #ifdef CONFIG_VSX
397 /* copy to local buffer then write that out */
398 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
399 if (i)
400 return i;
401 for (i = 0; i < 32 ; i++)
402 target->thread.TS_FPR(i) = buf[i];
403 memcpy(&target->thread.fpscr, &buf[32], sizeof(double));
404 return 0;
405 #else
406 BUILD_BUG_ON(offsetof(struct thread_struct, fpscr) !=
407 offsetof(struct thread_struct, TS_FPR(32)));
408
409 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
410 &target->thread.fpr, 0, -1);
411 #endif
412 }
413
414 #ifdef CONFIG_ALTIVEC
415 /*
416 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
417 * The transfer totals 34 quadword. Quadwords 0-31 contain the
418 * corresponding vector registers. Quadword 32 contains the vscr as the
419 * last word (offset 12) within that quadword. Quadword 33 contains the
420 * vrsave as the first word (offset 0) within the quadword.
421 *
422 * This definition of the VMX state is compatible with the current PPC32
423 * ptrace interface. This allows signal handling and ptrace to use the
424 * same structures. This also simplifies the implementation of a bi-arch
425 * (combined (32- and 64-bit) gdb.
426 */
427
428 static int vr_active(struct task_struct *target,
429 const struct user_regset *regset)
430 {
431 flush_altivec_to_thread(target);
432 return target->thread.used_vr ? regset->n : 0;
433 }
434
435 static int vr_get(struct task_struct *target, const struct user_regset *regset,
436 unsigned int pos, unsigned int count,
437 void *kbuf, void __user *ubuf)
438 {
439 int ret;
440
441 flush_altivec_to_thread(target);
442
443 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
444 offsetof(struct thread_struct, vr[32]));
445
446 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
447 &target->thread.vr, 0,
448 33 * sizeof(vector128));
449 if (!ret) {
450 /*
451 * Copy out only the low-order word of vrsave.
452 */
453 union {
454 elf_vrreg_t reg;
455 u32 word;
456 } vrsave;
457 memset(&vrsave, 0, sizeof(vrsave));
458 vrsave.word = target->thread.vrsave;
459 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
460 33 * sizeof(vector128), -1);
461 }
462
463 return ret;
464 }
465
466 static int vr_set(struct task_struct *target, const struct user_regset *regset,
467 unsigned int pos, unsigned int count,
468 const void *kbuf, const void __user *ubuf)
469 {
470 int ret;
471
472 flush_altivec_to_thread(target);
473
474 BUILD_BUG_ON(offsetof(struct thread_struct, vscr) !=
475 offsetof(struct thread_struct, vr[32]));
476
477 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
478 &target->thread.vr, 0, 33 * sizeof(vector128));
479 if (!ret && count > 0) {
480 /*
481 * We use only the first word of vrsave.
482 */
483 union {
484 elf_vrreg_t reg;
485 u32 word;
486 } vrsave;
487 memset(&vrsave, 0, sizeof(vrsave));
488 vrsave.word = target->thread.vrsave;
489 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
490 33 * sizeof(vector128), -1);
491 if (!ret)
492 target->thread.vrsave = vrsave.word;
493 }
494
495 return ret;
496 }
497 #endif /* CONFIG_ALTIVEC */
498
499 #ifdef CONFIG_VSX
500 /*
501 * Currently to set and and get all the vsx state, you need to call
502 * the fp and VMX calls as well. This only get/sets the lower 32
503 * 128bit VSX registers.
504 */
505
506 static int vsr_active(struct task_struct *target,
507 const struct user_regset *regset)
508 {
509 flush_vsx_to_thread(target);
510 return target->thread.used_vsr ? regset->n : 0;
511 }
512
513 static int vsr_get(struct task_struct *target, const struct user_regset *regset,
514 unsigned int pos, unsigned int count,
515 void *kbuf, void __user *ubuf)
516 {
517 double buf[32];
518 int ret, i;
519
520 flush_vsx_to_thread(target);
521
522 for (i = 0; i < 32 ; i++)
523 buf[i] = target->thread.fpr[i][TS_VSRLOWOFFSET];
524 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
525 buf, 0, 32 * sizeof(double));
526
527 return ret;
528 }
529
530 static int vsr_set(struct task_struct *target, const struct user_regset *regset,
531 unsigned int pos, unsigned int count,
532 const void *kbuf, const void __user *ubuf)
533 {
534 double buf[32];
535 int ret,i;
536
537 flush_vsx_to_thread(target);
538
539 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
540 buf, 0, 32 * sizeof(double));
541 for (i = 0; i < 32 ; i++)
542 target->thread.fpr[i][TS_VSRLOWOFFSET] = buf[i];
543
544
545 return ret;
546 }
547 #endif /* CONFIG_VSX */
548
549 #ifdef CONFIG_SPE
550
551 /*
552 * For get_evrregs/set_evrregs functions 'data' has the following layout:
553 *
554 * struct {
555 * u32 evr[32];
556 * u64 acc;
557 * u32 spefscr;
558 * }
559 */
560
561 static int evr_active(struct task_struct *target,
562 const struct user_regset *regset)
563 {
564 flush_spe_to_thread(target);
565 return target->thread.used_spe ? regset->n : 0;
566 }
567
568 static int evr_get(struct task_struct *target, const struct user_regset *regset,
569 unsigned int pos, unsigned int count,
570 void *kbuf, void __user *ubuf)
571 {
572 int ret;
573
574 flush_spe_to_thread(target);
575
576 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
577 &target->thread.evr,
578 0, sizeof(target->thread.evr));
579
580 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
581 offsetof(struct thread_struct, spefscr));
582
583 if (!ret)
584 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
585 &target->thread.acc,
586 sizeof(target->thread.evr), -1);
587
588 return ret;
589 }
590
591 static int evr_set(struct task_struct *target, const struct user_regset *regset,
592 unsigned int pos, unsigned int count,
593 const void *kbuf, const void __user *ubuf)
594 {
595 int ret;
596
597 flush_spe_to_thread(target);
598
599 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
600 &target->thread.evr,
601 0, sizeof(target->thread.evr));
602
603 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
604 offsetof(struct thread_struct, spefscr));
605
606 if (!ret)
607 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
608 &target->thread.acc,
609 sizeof(target->thread.evr), -1);
610
611 return ret;
612 }
613 #endif /* CONFIG_SPE */
614
615
616 /*
617 * These are our native regset flavors.
618 */
619 enum powerpc_regset {
620 REGSET_GPR,
621 REGSET_FPR,
622 #ifdef CONFIG_ALTIVEC
623 REGSET_VMX,
624 #endif
625 #ifdef CONFIG_VSX
626 REGSET_VSX,
627 #endif
628 #ifdef CONFIG_SPE
629 REGSET_SPE,
630 #endif
631 };
632
633 static const struct user_regset native_regsets[] = {
634 [REGSET_GPR] = {
635 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
636 .size = sizeof(long), .align = sizeof(long),
637 .get = gpr_get, .set = gpr_set
638 },
639 [REGSET_FPR] = {
640 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
641 .size = sizeof(double), .align = sizeof(double),
642 .get = fpr_get, .set = fpr_set
643 },
644 #ifdef CONFIG_ALTIVEC
645 [REGSET_VMX] = {
646 .core_note_type = NT_PPC_VMX, .n = 34,
647 .size = sizeof(vector128), .align = sizeof(vector128),
648 .active = vr_active, .get = vr_get, .set = vr_set
649 },
650 #endif
651 #ifdef CONFIG_VSX
652 [REGSET_VSX] = {
653 .core_note_type = NT_PPC_VSX, .n = 32,
654 .size = sizeof(double), .align = sizeof(double),
655 .active = vsr_active, .get = vsr_get, .set = vsr_set
656 },
657 #endif
658 #ifdef CONFIG_SPE
659 [REGSET_SPE] = {
660 .n = 35,
661 .size = sizeof(u32), .align = sizeof(u32),
662 .active = evr_active, .get = evr_get, .set = evr_set
663 },
664 #endif
665 };
666
667 static const struct user_regset_view user_ppc_native_view = {
668 .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
669 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
670 };
671
672 #ifdef CONFIG_PPC64
673 #include <linux/compat.h>
674
675 static int gpr32_get(struct task_struct *target,
676 const struct user_regset *regset,
677 unsigned int pos, unsigned int count,
678 void *kbuf, void __user *ubuf)
679 {
680 const unsigned long *regs = &target->thread.regs->gpr[0];
681 compat_ulong_t *k = kbuf;
682 compat_ulong_t __user *u = ubuf;
683 compat_ulong_t reg;
684 int i;
685
686 if (target->thread.regs == NULL)
687 return -EIO;
688
689 if (!FULL_REGS(target->thread.regs)) {
690 /* We have a partial register set. Fill 14-31 with bogus values */
691 for (i = 14; i < 32; i++)
692 target->thread.regs->gpr[i] = NV_REG_POISON;
693 }
694
695 pos /= sizeof(reg);
696 count /= sizeof(reg);
697
698 if (kbuf)
699 for (; count > 0 && pos < PT_MSR; --count)
700 *k++ = regs[pos++];
701 else
702 for (; count > 0 && pos < PT_MSR; --count)
703 if (__put_user((compat_ulong_t) regs[pos++], u++))
704 return -EFAULT;
705
706 if (count > 0 && pos == PT_MSR) {
707 reg = get_user_msr(target);
708 if (kbuf)
709 *k++ = reg;
710 else if (__put_user(reg, u++))
711 return -EFAULT;
712 ++pos;
713 --count;
714 }
715
716 if (kbuf)
717 for (; count > 0 && pos < PT_REGS_COUNT; --count)
718 *k++ = regs[pos++];
719 else
720 for (; count > 0 && pos < PT_REGS_COUNT; --count)
721 if (__put_user((compat_ulong_t) regs[pos++], u++))
722 return -EFAULT;
723
724 kbuf = k;
725 ubuf = u;
726 pos *= sizeof(reg);
727 count *= sizeof(reg);
728 return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
729 PT_REGS_COUNT * sizeof(reg), -1);
730 }
731
732 static int gpr32_set(struct task_struct *target,
733 const struct user_regset *regset,
734 unsigned int pos, unsigned int count,
735 const void *kbuf, const void __user *ubuf)
736 {
737 unsigned long *regs = &target->thread.regs->gpr[0];
738 const compat_ulong_t *k = kbuf;
739 const compat_ulong_t __user *u = ubuf;
740 compat_ulong_t reg;
741
742 if (target->thread.regs == NULL)
743 return -EIO;
744
745 CHECK_FULL_REGS(target->thread.regs);
746
747 pos /= sizeof(reg);
748 count /= sizeof(reg);
749
750 if (kbuf)
751 for (; count > 0 && pos < PT_MSR; --count)
752 regs[pos++] = *k++;
753 else
754 for (; count > 0 && pos < PT_MSR; --count) {
755 if (__get_user(reg, u++))
756 return -EFAULT;
757 regs[pos++] = reg;
758 }
759
760
761 if (count > 0 && pos == PT_MSR) {
762 if (kbuf)
763 reg = *k++;
764 else if (__get_user(reg, u++))
765 return -EFAULT;
766 set_user_msr(target, reg);
767 ++pos;
768 --count;
769 }
770
771 if (kbuf) {
772 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
773 regs[pos++] = *k++;
774 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
775 ++k;
776 } else {
777 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
778 if (__get_user(reg, u++))
779 return -EFAULT;
780 regs[pos++] = reg;
781 }
782 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
783 if (__get_user(reg, u++))
784 return -EFAULT;
785 }
786
787 if (count > 0 && pos == PT_TRAP) {
788 if (kbuf)
789 reg = *k++;
790 else if (__get_user(reg, u++))
791 return -EFAULT;
792 set_user_trap(target, reg);
793 ++pos;
794 --count;
795 }
796
797 kbuf = k;
798 ubuf = u;
799 pos *= sizeof(reg);
800 count *= sizeof(reg);
801 return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
802 (PT_TRAP + 1) * sizeof(reg), -1);
803 }
804
805 /*
806 * These are the regset flavors matching the CONFIG_PPC32 native set.
807 */
808 static const struct user_regset compat_regsets[] = {
809 [REGSET_GPR] = {
810 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
811 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
812 .get = gpr32_get, .set = gpr32_set
813 },
814 [REGSET_FPR] = {
815 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
816 .size = sizeof(double), .align = sizeof(double),
817 .get = fpr_get, .set = fpr_set
818 },
819 #ifdef CONFIG_ALTIVEC
820 [REGSET_VMX] = {
821 .core_note_type = NT_PPC_VMX, .n = 34,
822 .size = sizeof(vector128), .align = sizeof(vector128),
823 .active = vr_active, .get = vr_get, .set = vr_set
824 },
825 #endif
826 #ifdef CONFIG_SPE
827 [REGSET_SPE] = {
828 .core_note_type = NT_PPC_SPE, .n = 35,
829 .size = sizeof(u32), .align = sizeof(u32),
830 .active = evr_active, .get = evr_get, .set = evr_set
831 },
832 #endif
833 };
834
835 static const struct user_regset_view user_ppc_compat_view = {
836 .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
837 .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
838 };
839 #endif /* CONFIG_PPC64 */
840
841 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
842 {
843 #ifdef CONFIG_PPC64
844 if (test_tsk_thread_flag(task, TIF_32BIT))
845 return &user_ppc_compat_view;
846 #endif
847 return &user_ppc_native_view;
848 }
849
850
851 void user_enable_single_step(struct task_struct *task)
852 {
853 struct pt_regs *regs = task->thread.regs;
854
855 if (regs != NULL) {
856 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
857 task->thread.dbcr0 &= ~DBCR0_BT;
858 task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC;
859 regs->msr |= MSR_DE;
860 #else
861 regs->msr &= ~MSR_BE;
862 regs->msr |= MSR_SE;
863 #endif
864 }
865 set_tsk_thread_flag(task, TIF_SINGLESTEP);
866 }
867
868 void user_enable_block_step(struct task_struct *task)
869 {
870 struct pt_regs *regs = task->thread.regs;
871
872 if (regs != NULL) {
873 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
874 task->thread.dbcr0 &= ~DBCR0_IC;
875 task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT;
876 regs->msr |= MSR_DE;
877 #else
878 regs->msr &= ~MSR_SE;
879 regs->msr |= MSR_BE;
880 #endif
881 }
882 set_tsk_thread_flag(task, TIF_SINGLESTEP);
883 }
884
885 void user_disable_single_step(struct task_struct *task)
886 {
887 struct pt_regs *regs = task->thread.regs;
888
889 if (regs != NULL) {
890 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
891 /*
892 * The logic to disable single stepping should be as
893 * simple as turning off the Instruction Complete flag.
894 * And, after doing so, if all debug flags are off, turn
895 * off DBCR0(IDM) and MSR(DE) .... Torez
896 */
897 task->thread.dbcr0 &= ~DBCR0_IC;
898 /*
899 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
900 */
901 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
902 task->thread.dbcr1)) {
903 /*
904 * All debug events were off.....
905 */
906 task->thread.dbcr0 &= ~DBCR0_IDM;
907 regs->msr &= ~MSR_DE;
908 }
909 #else
910 regs->msr &= ~(MSR_SE | MSR_BE);
911 #endif
912 }
913 clear_tsk_thread_flag(task, TIF_SINGLESTEP);
914 }
915
916 #ifdef CONFIG_HAVE_HW_BREAKPOINT
917 void ptrace_triggered(struct perf_event *bp,
918 struct perf_sample_data *data, struct pt_regs *regs)
919 {
920 struct perf_event_attr attr;
921
922 /*
923 * Disable the breakpoint request here since ptrace has defined a
924 * one-shot behaviour for breakpoint exceptions in PPC64.
925 * The SIGTRAP signal is generated automatically for us in do_dabr().
926 * We don't have to do anything about that here
927 */
928 attr = bp->attr;
929 attr.disabled = true;
930 modify_user_hw_breakpoint(bp, &attr);
931 }
932 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
933
934 int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
935 unsigned long data)
936 {
937 #ifdef CONFIG_HAVE_HW_BREAKPOINT
938 int ret;
939 struct thread_struct *thread = &(task->thread);
940 struct perf_event *bp;
941 struct perf_event_attr attr;
942 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
943 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
944 struct arch_hw_breakpoint hw_brk;
945 #endif
946
947 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
948 * For embedded processors we support one DAC and no IAC's at the
949 * moment.
950 */
951 if (addr > 0)
952 return -EINVAL;
953
954 /* The bottom 3 bits in dabr are flags */
955 if ((data & ~0x7UL) >= TASK_SIZE)
956 return -EIO;
957
958 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
959 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
960 * It was assumed, on previous implementations, that 3 bits were
961 * passed together with the data address, fitting the design of the
962 * DABR register, as follows:
963 *
964 * bit 0: Read flag
965 * bit 1: Write flag
966 * bit 2: Breakpoint translation
967 *
968 * Thus, we use them here as so.
969 */
970
971 /* Ensure breakpoint translation bit is set */
972 if (data && !(data & HW_BRK_TYPE_TRANSLATE))
973 return -EIO;
974 hw_brk.address = data & (~HW_BRK_TYPE_DABR);
975 hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL;
976 hw_brk.len = 8;
977 #ifdef CONFIG_HAVE_HW_BREAKPOINT
978 if (ptrace_get_breakpoints(task) < 0)
979 return -ESRCH;
980
981 bp = thread->ptrace_bps[0];
982 if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) {
983 if (bp) {
984 unregister_hw_breakpoint(bp);
985 thread->ptrace_bps[0] = NULL;
986 }
987 ptrace_put_breakpoints(task);
988 return 0;
989 }
990 if (bp) {
991 attr = bp->attr;
992 attr.bp_addr = hw_brk.address;
993 arch_bp_generic_fields(hw_brk.type, &attr.bp_type);
994
995 /* Enable breakpoint */
996 attr.disabled = false;
997
998 ret = modify_user_hw_breakpoint(bp, &attr);
999 if (ret) {
1000 ptrace_put_breakpoints(task);
1001 return ret;
1002 }
1003 thread->ptrace_bps[0] = bp;
1004 ptrace_put_breakpoints(task);
1005 thread->hw_brk = hw_brk;
1006 return 0;
1007 }
1008
1009 /* Create a new breakpoint request if one doesn't exist already */
1010 hw_breakpoint_init(&attr);
1011 attr.bp_addr = hw_brk.address;
1012 arch_bp_generic_fields(hw_brk.type,
1013 &attr.bp_type);
1014
1015 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
1016 ptrace_triggered, NULL, task);
1017 if (IS_ERR(bp)) {
1018 thread->ptrace_bps[0] = NULL;
1019 ptrace_put_breakpoints(task);
1020 return PTR_ERR(bp);
1021 }
1022
1023 ptrace_put_breakpoints(task);
1024
1025 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1026 task->thread.hw_brk = hw_brk;
1027 #else /* CONFIG_PPC_ADV_DEBUG_REGS */
1028 /* As described above, it was assumed 3 bits were passed with the data
1029 * address, but we will assume only the mode bits will be passed
1030 * as to not cause alignment restrictions for DAC-based processors.
1031 */
1032
1033 /* DAC's hold the whole address without any mode flags */
1034 task->thread.dac1 = data & ~0x3UL;
1035
1036 if (task->thread.dac1 == 0) {
1037 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1038 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0,
1039 task->thread.dbcr1)) {
1040 task->thread.regs->msr &= ~MSR_DE;
1041 task->thread.dbcr0 &= ~DBCR0_IDM;
1042 }
1043 return 0;
1044 }
1045
1046 /* Read or Write bits must be set */
1047
1048 if (!(data & 0x3UL))
1049 return -EINVAL;
1050
1051 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
1052 register */
1053 task->thread.dbcr0 |= DBCR0_IDM;
1054
1055 /* Check for write and read flags and set DBCR0
1056 accordingly */
1057 dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
1058 if (data & 0x1UL)
1059 dbcr_dac(task) |= DBCR_DAC1R;
1060 if (data & 0x2UL)
1061 dbcr_dac(task) |= DBCR_DAC1W;
1062 task->thread.regs->msr |= MSR_DE;
1063 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1064 return 0;
1065 }
1066
1067 /*
1068 * Called by kernel/ptrace.c when detaching..
1069 *
1070 * Make sure single step bits etc are not set.
1071 */
1072 void ptrace_disable(struct task_struct *child)
1073 {
1074 /* make sure the single step bit is not set. */
1075 user_disable_single_step(child);
1076 }
1077
1078 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1079 static long set_instruction_bp(struct task_struct *child,
1080 struct ppc_hw_breakpoint *bp_info)
1081 {
1082 int slot;
1083 int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0);
1084 int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0);
1085 int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0);
1086 int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0);
1087
1088 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1089 slot2_in_use = 1;
1090 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1091 slot4_in_use = 1;
1092
1093 if (bp_info->addr >= TASK_SIZE)
1094 return -EIO;
1095
1096 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
1097
1098 /* Make sure range is valid. */
1099 if (bp_info->addr2 >= TASK_SIZE)
1100 return -EIO;
1101
1102 /* We need a pair of IAC regsisters */
1103 if ((!slot1_in_use) && (!slot2_in_use)) {
1104 slot = 1;
1105 child->thread.iac1 = bp_info->addr;
1106 child->thread.iac2 = bp_info->addr2;
1107 child->thread.dbcr0 |= DBCR0_IAC1;
1108 if (bp_info->addr_mode ==
1109 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1110 dbcr_iac_range(child) |= DBCR_IAC12X;
1111 else
1112 dbcr_iac_range(child) |= DBCR_IAC12I;
1113 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1114 } else if ((!slot3_in_use) && (!slot4_in_use)) {
1115 slot = 3;
1116 child->thread.iac3 = bp_info->addr;
1117 child->thread.iac4 = bp_info->addr2;
1118 child->thread.dbcr0 |= DBCR0_IAC3;
1119 if (bp_info->addr_mode ==
1120 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1121 dbcr_iac_range(child) |= DBCR_IAC34X;
1122 else
1123 dbcr_iac_range(child) |= DBCR_IAC34I;
1124 #endif
1125 } else
1126 return -ENOSPC;
1127 } else {
1128 /* We only need one. If possible leave a pair free in
1129 * case a range is needed later
1130 */
1131 if (!slot1_in_use) {
1132 /*
1133 * Don't use iac1 if iac1-iac2 are free and either
1134 * iac3 or iac4 (but not both) are free
1135 */
1136 if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
1137 slot = 1;
1138 child->thread.iac1 = bp_info->addr;
1139 child->thread.dbcr0 |= DBCR0_IAC1;
1140 goto out;
1141 }
1142 }
1143 if (!slot2_in_use) {
1144 slot = 2;
1145 child->thread.iac2 = bp_info->addr;
1146 child->thread.dbcr0 |= DBCR0_IAC2;
1147 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1148 } else if (!slot3_in_use) {
1149 slot = 3;
1150 child->thread.iac3 = bp_info->addr;
1151 child->thread.dbcr0 |= DBCR0_IAC3;
1152 } else if (!slot4_in_use) {
1153 slot = 4;
1154 child->thread.iac4 = bp_info->addr;
1155 child->thread.dbcr0 |= DBCR0_IAC4;
1156 #endif
1157 } else
1158 return -ENOSPC;
1159 }
1160 out:
1161 child->thread.dbcr0 |= DBCR0_IDM;
1162 child->thread.regs->msr |= MSR_DE;
1163
1164 return slot;
1165 }
1166
1167 static int del_instruction_bp(struct task_struct *child, int slot)
1168 {
1169 switch (slot) {
1170 case 1:
1171 if ((child->thread.dbcr0 & DBCR0_IAC1) == 0)
1172 return -ENOENT;
1173
1174 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
1175 /* address range - clear slots 1 & 2 */
1176 child->thread.iac2 = 0;
1177 dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
1178 }
1179 child->thread.iac1 = 0;
1180 child->thread.dbcr0 &= ~DBCR0_IAC1;
1181 break;
1182 case 2:
1183 if ((child->thread.dbcr0 & DBCR0_IAC2) == 0)
1184 return -ENOENT;
1185
1186 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1187 /* used in a range */
1188 return -EINVAL;
1189 child->thread.iac2 = 0;
1190 child->thread.dbcr0 &= ~DBCR0_IAC2;
1191 break;
1192 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
1193 case 3:
1194 if ((child->thread.dbcr0 & DBCR0_IAC3) == 0)
1195 return -ENOENT;
1196
1197 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
1198 /* address range - clear slots 3 & 4 */
1199 child->thread.iac4 = 0;
1200 dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
1201 }
1202 child->thread.iac3 = 0;
1203 child->thread.dbcr0 &= ~DBCR0_IAC3;
1204 break;
1205 case 4:
1206 if ((child->thread.dbcr0 & DBCR0_IAC4) == 0)
1207 return -ENOENT;
1208
1209 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1210 /* Used in a range */
1211 return -EINVAL;
1212 child->thread.iac4 = 0;
1213 child->thread.dbcr0 &= ~DBCR0_IAC4;
1214 break;
1215 #endif
1216 default:
1217 return -EINVAL;
1218 }
1219 return 0;
1220 }
1221
1222 static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
1223 {
1224 int byte_enable =
1225 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
1226 & 0xf;
1227 int condition_mode =
1228 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
1229 int slot;
1230
1231 if (byte_enable && (condition_mode == 0))
1232 return -EINVAL;
1233
1234 if (bp_info->addr >= TASK_SIZE)
1235 return -EIO;
1236
1237 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
1238 slot = 1;
1239 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1240 dbcr_dac(child) |= DBCR_DAC1R;
1241 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1242 dbcr_dac(child) |= DBCR_DAC1W;
1243 child->thread.dac1 = (unsigned long)bp_info->addr;
1244 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1245 if (byte_enable) {
1246 child->thread.dvc1 =
1247 (unsigned long)bp_info->condition_value;
1248 child->thread.dbcr2 |=
1249 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
1250 (condition_mode << DBCR2_DVC1M_SHIFT));
1251 }
1252 #endif
1253 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1254 } else if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
1255 /* Both dac1 and dac2 are part of a range */
1256 return -ENOSPC;
1257 #endif
1258 } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
1259 slot = 2;
1260 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1261 dbcr_dac(child) |= DBCR_DAC2R;
1262 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1263 dbcr_dac(child) |= DBCR_DAC2W;
1264 child->thread.dac2 = (unsigned long)bp_info->addr;
1265 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1266 if (byte_enable) {
1267 child->thread.dvc2 =
1268 (unsigned long)bp_info->condition_value;
1269 child->thread.dbcr2 |=
1270 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
1271 (condition_mode << DBCR2_DVC2M_SHIFT));
1272 }
1273 #endif
1274 } else
1275 return -ENOSPC;
1276 child->thread.dbcr0 |= DBCR0_IDM;
1277 child->thread.regs->msr |= MSR_DE;
1278
1279 return slot + 4;
1280 }
1281
1282 static int del_dac(struct task_struct *child, int slot)
1283 {
1284 if (slot == 1) {
1285 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
1286 return -ENOENT;
1287
1288 child->thread.dac1 = 0;
1289 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1290 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1291 if (child->thread.dbcr2 & DBCR2_DAC12MODE) {
1292 child->thread.dac2 = 0;
1293 child->thread.dbcr2 &= ~DBCR2_DAC12MODE;
1294 }
1295 child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
1296 #endif
1297 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1298 child->thread.dvc1 = 0;
1299 #endif
1300 } else if (slot == 2) {
1301 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
1302 return -ENOENT;
1303
1304 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1305 if (child->thread.dbcr2 & DBCR2_DAC12MODE)
1306 /* Part of a range */
1307 return -EINVAL;
1308 child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
1309 #endif
1310 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1311 child->thread.dvc2 = 0;
1312 #endif
1313 child->thread.dac2 = 0;
1314 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1315 } else
1316 return -EINVAL;
1317
1318 return 0;
1319 }
1320 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1321
1322 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1323 static int set_dac_range(struct task_struct *child,
1324 struct ppc_hw_breakpoint *bp_info)
1325 {
1326 int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
1327
1328 /* We don't allow range watchpoints to be used with DVC */
1329 if (bp_info->condition_mode)
1330 return -EINVAL;
1331
1332 /*
1333 * Best effort to verify the address range. The user/supervisor bits
1334 * prevent trapping in kernel space, but let's fail on an obvious bad
1335 * range. The simple test on the mask is not fool-proof, and any
1336 * exclusive range will spill over into kernel space.
1337 */
1338 if (bp_info->addr >= TASK_SIZE)
1339 return -EIO;
1340 if (mode == PPC_BREAKPOINT_MODE_MASK) {
1341 /*
1342 * dac2 is a bitmask. Don't allow a mask that makes a
1343 * kernel space address from a valid dac1 value
1344 */
1345 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
1346 return -EIO;
1347 } else {
1348 /*
1349 * For range breakpoints, addr2 must also be a valid address
1350 */
1351 if (bp_info->addr2 >= TASK_SIZE)
1352 return -EIO;
1353 }
1354
1355 if (child->thread.dbcr0 &
1356 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
1357 return -ENOSPC;
1358
1359 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1360 child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
1361 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1362 child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
1363 child->thread.dac1 = bp_info->addr;
1364 child->thread.dac2 = bp_info->addr2;
1365 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
1366 child->thread.dbcr2 |= DBCR2_DAC12M;
1367 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1368 child->thread.dbcr2 |= DBCR2_DAC12MX;
1369 else /* PPC_BREAKPOINT_MODE_MASK */
1370 child->thread.dbcr2 |= DBCR2_DAC12MM;
1371 child->thread.regs->msr |= MSR_DE;
1372
1373 return 5;
1374 }
1375 #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
1376
1377 static long ppc_set_hwdebug(struct task_struct *child,
1378 struct ppc_hw_breakpoint *bp_info)
1379 {
1380 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1381 int len = 0;
1382 struct thread_struct *thread = &(child->thread);
1383 struct perf_event *bp;
1384 struct perf_event_attr attr;
1385 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1386 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
1387 struct arch_hw_breakpoint brk;
1388 #endif
1389
1390 if (bp_info->version != 1)
1391 return -ENOTSUPP;
1392 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1393 /*
1394 * Check for invalid flags and combinations
1395 */
1396 if ((bp_info->trigger_type == 0) ||
1397 (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
1398 PPC_BREAKPOINT_TRIGGER_RW)) ||
1399 (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
1400 (bp_info->condition_mode &
1401 ~(PPC_BREAKPOINT_CONDITION_MODE |
1402 PPC_BREAKPOINT_CONDITION_BE_ALL)))
1403 return -EINVAL;
1404 #if CONFIG_PPC_ADV_DEBUG_DVCS == 0
1405 if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
1406 return -EINVAL;
1407 #endif
1408
1409 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
1410 if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
1411 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
1412 return -EINVAL;
1413 return set_instruction_bp(child, bp_info);
1414 }
1415 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
1416 return set_dac(child, bp_info);
1417
1418 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1419 return set_dac_range(child, bp_info);
1420 #else
1421 return -EINVAL;
1422 #endif
1423 #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
1424 /*
1425 * We only support one data breakpoint
1426 */
1427 if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
1428 (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
1429 bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
1430 return -EINVAL;
1431
1432 if ((unsigned long)bp_info->addr >= TASK_SIZE)
1433 return -EIO;
1434
1435 brk.address = bp_info->addr & ~7UL;
1436 brk.type = HW_BRK_TYPE_TRANSLATE;
1437 brk.len = 8;
1438 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1439 brk.type |= HW_BRK_TYPE_READ;
1440 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1441 brk.type |= HW_BRK_TYPE_WRITE;
1442 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1443 if (ptrace_get_breakpoints(child) < 0)
1444 return -ESRCH;
1445
1446 /*
1447 * Check if the request is for 'range' breakpoints. We can
1448 * support it if range < 8 bytes.
1449 */
1450 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) {
1451 len = bp_info->addr2 - bp_info->addr;
1452 } else if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
1453 ptrace_put_breakpoints(child);
1454 return -EINVAL;
1455 }
1456 bp = thread->ptrace_bps[0];
1457 if (bp) {
1458 ptrace_put_breakpoints(child);
1459 return -ENOSPC;
1460 }
1461
1462 /* Create a new breakpoint request if one doesn't exist already */
1463 hw_breakpoint_init(&attr);
1464 attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN;
1465 attr.bp_len = len;
1466 arch_bp_generic_fields(brk.type, &attr.bp_type);
1467
1468 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
1469 ptrace_triggered, NULL, child);
1470 if (IS_ERR(bp)) {
1471 thread->ptrace_bps[0] = NULL;
1472 ptrace_put_breakpoints(child);
1473 return PTR_ERR(bp);
1474 }
1475
1476 ptrace_put_breakpoints(child);
1477 return 1;
1478 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1479
1480 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
1481 return -EINVAL;
1482
1483 if (child->thread.hw_brk.address)
1484 return -ENOSPC;
1485
1486 child->thread.hw_brk = brk;
1487
1488 return 1;
1489 #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
1490 }
1491
1492 static long ppc_del_hwdebug(struct task_struct *child, long data)
1493 {
1494 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1495 int ret = 0;
1496 struct thread_struct *thread = &(child->thread);
1497 struct perf_event *bp;
1498 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1499 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1500 int rc;
1501
1502 if (data <= 4)
1503 rc = del_instruction_bp(child, (int)data);
1504 else
1505 rc = del_dac(child, (int)data - 4);
1506
1507 if (!rc) {
1508 if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0,
1509 child->thread.dbcr1)) {
1510 child->thread.dbcr0 &= ~DBCR0_IDM;
1511 child->thread.regs->msr &= ~MSR_DE;
1512 }
1513 }
1514 return rc;
1515 #else
1516 if (data != 1)
1517 return -EINVAL;
1518
1519 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1520 if (ptrace_get_breakpoints(child) < 0)
1521 return -ESRCH;
1522
1523 bp = thread->ptrace_bps[0];
1524 if (bp) {
1525 unregister_hw_breakpoint(bp);
1526 thread->ptrace_bps[0] = NULL;
1527 } else
1528 ret = -ENOENT;
1529 ptrace_put_breakpoints(child);
1530 return ret;
1531 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1532 if (child->thread.hw_brk.address == 0)
1533 return -ENOENT;
1534
1535 child->thread.hw_brk.address = 0;
1536 child->thread.hw_brk.type = 0;
1537 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1538
1539 return 0;
1540 #endif
1541 }
1542
1543 long arch_ptrace(struct task_struct *child, long request,
1544 unsigned long addr, unsigned long data)
1545 {
1546 int ret = -EPERM;
1547 void __user *datavp = (void __user *) data;
1548 unsigned long __user *datalp = datavp;
1549
1550 switch (request) {
1551 /* read the word at location addr in the USER area. */
1552 case PTRACE_PEEKUSR: {
1553 unsigned long index, tmp;
1554
1555 ret = -EIO;
1556 /* convert to index and check */
1557 #ifdef CONFIG_PPC32
1558 index = addr >> 2;
1559 if ((addr & 3) || (index > PT_FPSCR)
1560 || (child->thread.regs == NULL))
1561 #else
1562 index = addr >> 3;
1563 if ((addr & 7) || (index > PT_FPSCR))
1564 #endif
1565 break;
1566
1567 CHECK_FULL_REGS(child->thread.regs);
1568 if (index < PT_FPR0) {
1569 ret = ptrace_get_reg(child, (int) index, &tmp);
1570 if (ret)
1571 break;
1572 } else {
1573 unsigned int fpidx = index - PT_FPR0;
1574
1575 flush_fp_to_thread(child);
1576 if (fpidx < (PT_FPSCR - PT_FPR0))
1577 tmp = ((unsigned long *)child->thread.fpr)
1578 [fpidx * TS_FPRWIDTH];
1579 else
1580 tmp = child->thread.fpscr.val;
1581 }
1582 ret = put_user(tmp, datalp);
1583 break;
1584 }
1585
1586 /* write the word at location addr in the USER area */
1587 case PTRACE_POKEUSR: {
1588 unsigned long index;
1589
1590 ret = -EIO;
1591 /* convert to index and check */
1592 #ifdef CONFIG_PPC32
1593 index = addr >> 2;
1594 if ((addr & 3) || (index > PT_FPSCR)
1595 || (child->thread.regs == NULL))
1596 #else
1597 index = addr >> 3;
1598 if ((addr & 7) || (index > PT_FPSCR))
1599 #endif
1600 break;
1601
1602 CHECK_FULL_REGS(child->thread.regs);
1603 if (index < PT_FPR0) {
1604 ret = ptrace_put_reg(child, index, data);
1605 } else {
1606 unsigned int fpidx = index - PT_FPR0;
1607
1608 flush_fp_to_thread(child);
1609 if (fpidx < (PT_FPSCR - PT_FPR0))
1610 ((unsigned long *)child->thread.fpr)
1611 [fpidx * TS_FPRWIDTH] = data;
1612 else
1613 child->thread.fpscr.val = data;
1614 ret = 0;
1615 }
1616 break;
1617 }
1618
1619 case PPC_PTRACE_GETHWDBGINFO: {
1620 struct ppc_debug_info dbginfo;
1621
1622 dbginfo.version = 1;
1623 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1624 dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
1625 dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
1626 dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
1627 dbginfo.data_bp_alignment = 4;
1628 dbginfo.sizeof_condition = 4;
1629 dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
1630 PPC_DEBUG_FEATURE_INSN_BP_MASK;
1631 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1632 dbginfo.features |=
1633 PPC_DEBUG_FEATURE_DATA_BP_RANGE |
1634 PPC_DEBUG_FEATURE_DATA_BP_MASK;
1635 #endif
1636 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
1637 dbginfo.num_instruction_bps = 0;
1638 dbginfo.num_data_bps = 1;
1639 dbginfo.num_condition_regs = 0;
1640 #ifdef CONFIG_PPC64
1641 dbginfo.data_bp_alignment = 8;
1642 #else
1643 dbginfo.data_bp_alignment = 4;
1644 #endif
1645 dbginfo.sizeof_condition = 0;
1646 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1647 dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
1648 if (cpu_has_feature(CPU_FTR_DAWR))
1649 dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR;
1650 #else
1651 dbginfo.features = 0;
1652 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1653 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1654
1655 if (!access_ok(VERIFY_WRITE, datavp,
1656 sizeof(struct ppc_debug_info)))
1657 return -EFAULT;
1658 ret = __copy_to_user(datavp, &dbginfo,
1659 sizeof(struct ppc_debug_info)) ?
1660 -EFAULT : 0;
1661 break;
1662 }
1663
1664 case PPC_PTRACE_SETHWDEBUG: {
1665 struct ppc_hw_breakpoint bp_info;
1666
1667 if (!access_ok(VERIFY_READ, datavp,
1668 sizeof(struct ppc_hw_breakpoint)))
1669 return -EFAULT;
1670 ret = __copy_from_user(&bp_info, datavp,
1671 sizeof(struct ppc_hw_breakpoint)) ?
1672 -EFAULT : 0;
1673 if (!ret)
1674 ret = ppc_set_hwdebug(child, &bp_info);
1675 break;
1676 }
1677
1678 case PPC_PTRACE_DELHWDEBUG: {
1679 ret = ppc_del_hwdebug(child, data);
1680 break;
1681 }
1682
1683 case PTRACE_GET_DEBUGREG: {
1684 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
1685 unsigned long dabr_fake;
1686 #endif
1687 ret = -EINVAL;
1688 /* We only support one DABR and no IABRS at the moment */
1689 if (addr > 0)
1690 break;
1691 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1692 ret = put_user(child->thread.dac1, datalp);
1693 #else
1694 dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
1695 (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
1696 ret = put_user(dabr_fake, datalp);
1697 #endif
1698 break;
1699 }
1700
1701 case PTRACE_SET_DEBUGREG:
1702 ret = ptrace_set_debugreg(child, addr, data);
1703 break;
1704
1705 #ifdef CONFIG_PPC64
1706 case PTRACE_GETREGS64:
1707 #endif
1708 case PTRACE_GETREGS: /* Get all pt_regs from the child. */
1709 return copy_regset_to_user(child, &user_ppc_native_view,
1710 REGSET_GPR,
1711 0, sizeof(struct pt_regs),
1712 datavp);
1713
1714 #ifdef CONFIG_PPC64
1715 case PTRACE_SETREGS64:
1716 #endif
1717 case PTRACE_SETREGS: /* Set all gp regs in the child. */
1718 return copy_regset_from_user(child, &user_ppc_native_view,
1719 REGSET_GPR,
1720 0, sizeof(struct pt_regs),
1721 datavp);
1722
1723 case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
1724 return copy_regset_to_user(child, &user_ppc_native_view,
1725 REGSET_FPR,
1726 0, sizeof(elf_fpregset_t),
1727 datavp);
1728
1729 case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
1730 return copy_regset_from_user(child, &user_ppc_native_view,
1731 REGSET_FPR,
1732 0, sizeof(elf_fpregset_t),
1733 datavp);
1734
1735 #ifdef CONFIG_ALTIVEC
1736 case PTRACE_GETVRREGS:
1737 return copy_regset_to_user(child, &user_ppc_native_view,
1738 REGSET_VMX,
1739 0, (33 * sizeof(vector128) +
1740 sizeof(u32)),
1741 datavp);
1742
1743 case PTRACE_SETVRREGS:
1744 return copy_regset_from_user(child, &user_ppc_native_view,
1745 REGSET_VMX,
1746 0, (33 * sizeof(vector128) +
1747 sizeof(u32)),
1748 datavp);
1749 #endif
1750 #ifdef CONFIG_VSX
1751 case PTRACE_GETVSRREGS:
1752 return copy_regset_to_user(child, &user_ppc_native_view,
1753 REGSET_VSX,
1754 0, 32 * sizeof(double),
1755 datavp);
1756
1757 case PTRACE_SETVSRREGS:
1758 return copy_regset_from_user(child, &user_ppc_native_view,
1759 REGSET_VSX,
1760 0, 32 * sizeof(double),
1761 datavp);
1762 #endif
1763 #ifdef CONFIG_SPE
1764 case PTRACE_GETEVRREGS:
1765 /* Get the child spe register state. */
1766 return copy_regset_to_user(child, &user_ppc_native_view,
1767 REGSET_SPE, 0, 35 * sizeof(u32),
1768 datavp);
1769
1770 case PTRACE_SETEVRREGS:
1771 /* Set the child spe register state. */
1772 return copy_regset_from_user(child, &user_ppc_native_view,
1773 REGSET_SPE, 0, 35 * sizeof(u32),
1774 datavp);
1775 #endif
1776
1777 default:
1778 ret = ptrace_request(child, request, addr, data);
1779 break;
1780 }
1781 return ret;
1782 }
1783
1784 /*
1785 * We must return the syscall number to actually look up in the table.
1786 * This can be -1L to skip running any syscall at all.
1787 */
1788 long do_syscall_trace_enter(struct pt_regs *regs)
1789 {
1790 long ret = 0;
1791
1792 user_exit();
1793
1794 secure_computing_strict(regs->gpr[0]);
1795
1796 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
1797 tracehook_report_syscall_entry(regs))
1798 /*
1799 * Tracing decided this syscall should not happen.
1800 * We'll return a bogus call number to get an ENOSYS
1801 * error, but leave the original number in regs->gpr[0].
1802 */
1803 ret = -1L;
1804
1805 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1806 trace_sys_enter(regs, regs->gpr[0]);
1807
1808 #ifdef CONFIG_PPC64
1809 if (!is_32bit_task())
1810 audit_syscall_entry(AUDIT_ARCH_PPC64,
1811 regs->gpr[0],
1812 regs->gpr[3], regs->gpr[4],
1813 regs->gpr[5], regs->gpr[6]);
1814 else
1815 #endif
1816 audit_syscall_entry(AUDIT_ARCH_PPC,
1817 regs->gpr[0],
1818 regs->gpr[3] & 0xffffffff,
1819 regs->gpr[4] & 0xffffffff,
1820 regs->gpr[5] & 0xffffffff,
1821 regs->gpr[6] & 0xffffffff);
1822
1823 return ret ?: regs->gpr[0];
1824 }
1825
1826 void do_syscall_trace_leave(struct pt_regs *regs)
1827 {
1828 int step;
1829
1830 audit_syscall_exit(regs);
1831
1832 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1833 trace_sys_exit(regs, regs->result);
1834
1835 step = test_thread_flag(TIF_SINGLESTEP);
1836 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
1837 tracehook_report_syscall_exit(regs, step);
1838
1839 user_enter();
1840 }
kernel source for telekom puls (alcatel/mediatek)