2 * Derived from "arch/i386/kernel/process.c"
3 * Copyright (C) 1995 Linus Torvalds
5 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6 * Paul Mackerras (paulus@cs.anu.edu.au)
9 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/init.h>
29 #include <linux/prctl.h>
30 #include <linux/init_task.h>
31 #include <linux/export.h>
32 #include <linux/kallsyms.h>
33 #include <linux/mqueue.h>
34 #include <linux/hardirq.h>
35 #include <linux/utsname.h>
36 #include <linux/ftrace.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/personality.h>
39 #include <linux/random.h>
40 #include <linux/hw_breakpoint.h>
42 #include <asm/pgtable.h>
43 #include <asm/uaccess.h>
45 #include <asm/processor.h>
48 #include <asm/machdep.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
54 #include <asm/debug.h>
56 #include <asm/firmware.h>
58 #include <linux/kprobes.h>
59 #include <linux/kdebug.h>
61 /* Transactional Memory debug */
63 #define TM_DEBUG(x...) printk(KERN_INFO x)
65 #define TM_DEBUG(x...) do { } while(0)
68 extern unsigned long _get_SP(void);
71 struct task_struct
*last_task_used_math
= NULL
;
72 struct task_struct
*last_task_used_altivec
= NULL
;
73 struct task_struct
*last_task_used_vsx
= NULL
;
74 struct task_struct
*last_task_used_spe
= NULL
;
78 * Make sure the floating-point register state in the
79 * the thread_struct is up to date for task tsk.
81 void flush_fp_to_thread(struct task_struct
*tsk
)
83 if (tsk
->thread
.regs
) {
85 * We need to disable preemption here because if we didn't,
86 * another process could get scheduled after the regs->msr
87 * test but before we have finished saving the FP registers
88 * to the thread_struct. That process could take over the
89 * FPU, and then when we get scheduled again we would store
90 * bogus values for the remaining FP registers.
93 if (tsk
->thread
.regs
->msr
& MSR_FP
) {
96 * This should only ever be called for current or
97 * for a stopped child process. Since we save away
98 * the FP register state on context switch on SMP,
99 * there is something wrong if a stopped child appears
100 * to still have its FP state in the CPU registers.
102 BUG_ON(tsk
!= current
);
109 EXPORT_SYMBOL_GPL(flush_fp_to_thread
);
111 void enable_kernel_fp(void)
113 WARN_ON(preemptible());
116 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_FP
))
119 giveup_fpu(NULL
); /* just enables FP for kernel */
121 giveup_fpu(last_task_used_math
);
122 #endif /* CONFIG_SMP */
124 EXPORT_SYMBOL(enable_kernel_fp
);
126 #ifdef CONFIG_ALTIVEC
127 void enable_kernel_altivec(void)
129 WARN_ON(preemptible());
132 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VEC
))
133 giveup_altivec(current
);
135 giveup_altivec_notask();
137 giveup_altivec(last_task_used_altivec
);
138 #endif /* CONFIG_SMP */
140 EXPORT_SYMBOL(enable_kernel_altivec
);
143 * Make sure the VMX/Altivec register state in the
144 * the thread_struct is up to date for task tsk.
146 void flush_altivec_to_thread(struct task_struct
*tsk
)
148 if (tsk
->thread
.regs
) {
150 if (tsk
->thread
.regs
->msr
& MSR_VEC
) {
152 BUG_ON(tsk
!= current
);
159 EXPORT_SYMBOL_GPL(flush_altivec_to_thread
);
160 #endif /* CONFIG_ALTIVEC */
164 /* not currently used, but some crazy RAID module might want to later */
165 void enable_kernel_vsx(void)
167 WARN_ON(preemptible());
170 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_VSX
))
173 giveup_vsx(NULL
); /* just enable vsx for kernel - force */
175 giveup_vsx(last_task_used_vsx
);
176 #endif /* CONFIG_SMP */
178 EXPORT_SYMBOL(enable_kernel_vsx
);
181 void giveup_vsx(struct task_struct
*tsk
)
188 void flush_vsx_to_thread(struct task_struct
*tsk
)
190 if (tsk
->thread
.regs
) {
192 if (tsk
->thread
.regs
->msr
& MSR_VSX
) {
194 BUG_ON(tsk
!= current
);
201 EXPORT_SYMBOL_GPL(flush_vsx_to_thread
);
202 #endif /* CONFIG_VSX */
206 void enable_kernel_spe(void)
208 WARN_ON(preemptible());
211 if (current
->thread
.regs
&& (current
->thread
.regs
->msr
& MSR_SPE
))
214 giveup_spe(NULL
); /* just enable SPE for kernel - force */
216 giveup_spe(last_task_used_spe
);
217 #endif /* __SMP __ */
219 EXPORT_SYMBOL(enable_kernel_spe
);
221 void flush_spe_to_thread(struct task_struct
*tsk
)
223 if (tsk
->thread
.regs
) {
225 if (tsk
->thread
.regs
->msr
& MSR_SPE
) {
227 BUG_ON(tsk
!= current
);
229 tsk
->thread
.spefscr
= mfspr(SPRN_SPEFSCR
);
235 #endif /* CONFIG_SPE */
239 * If we are doing lazy switching of CPU state (FP, altivec or SPE),
240 * and the current task has some state, discard it.
242 void discard_lazy_cpu_state(void)
245 if (last_task_used_math
== current
)
246 last_task_used_math
= NULL
;
247 #ifdef CONFIG_ALTIVEC
248 if (last_task_used_altivec
== current
)
249 last_task_used_altivec
= NULL
;
250 #endif /* CONFIG_ALTIVEC */
252 if (last_task_used_vsx
== current
)
253 last_task_used_vsx
= NULL
;
254 #endif /* CONFIG_VSX */
256 if (last_task_used_spe
== current
)
257 last_task_used_spe
= NULL
;
261 #endif /* CONFIG_SMP */
263 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
264 void do_send_trap(struct pt_regs
*regs
, unsigned long address
,
265 unsigned long error_code
, int signal_code
, int breakpt
)
269 current
->thread
.trap_nr
= signal_code
;
270 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
271 11, SIGSEGV
) == NOTIFY_STOP
)
274 /* Deliver the signal to userspace */
275 info
.si_signo
= SIGTRAP
;
276 info
.si_errno
= breakpt
; /* breakpoint or watchpoint id */
277 info
.si_code
= signal_code
;
278 info
.si_addr
= (void __user
*)address
;
279 force_sig_info(SIGTRAP
, &info
, current
);
281 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
282 void do_break (struct pt_regs
*regs
, unsigned long address
,
283 unsigned long error_code
)
287 current
->thread
.trap_nr
= TRAP_HWBKPT
;
288 if (notify_die(DIE_DABR_MATCH
, "dabr_match", regs
, error_code
,
289 11, SIGSEGV
) == NOTIFY_STOP
)
292 if (debugger_break_match(regs
))
295 /* Clear the breakpoint */
296 hw_breakpoint_disable();
298 /* Deliver the signal to userspace */
299 info
.si_signo
= SIGTRAP
;
301 info
.si_code
= TRAP_HWBKPT
;
302 info
.si_addr
= (void __user
*)address
;
303 force_sig_info(SIGTRAP
, &info
, current
);
305 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
307 static DEFINE_PER_CPU(struct arch_hw_breakpoint
, current_brk
);
309 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
311 * Set the debug registers back to their default "safe" values.
313 static void set_debug_reg_defaults(struct thread_struct
*thread
)
315 thread
->iac1
= thread
->iac2
= 0;
316 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
317 thread
->iac3
= thread
->iac4
= 0;
319 thread
->dac1
= thread
->dac2
= 0;
320 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
321 thread
->dvc1
= thread
->dvc2
= 0;
326 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
328 thread
->dbcr1
= DBCR1_IAC1US
| DBCR1_IAC2US
| \
329 DBCR1_IAC3US
| DBCR1_IAC4US
;
331 * Force Data Address Compare User/Supervisor bits to be User-only
332 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
334 thread
->dbcr2
= DBCR2_DAC1US
| DBCR2_DAC2US
;
340 static void prime_debug_regs(struct thread_struct
*thread
)
343 * We could have inherited MSR_DE from userspace, since
344 * it doesn't get cleared on exception entry. Make sure
345 * MSR_DE is clear before we enable any debug events.
347 mtmsr(mfmsr() & ~MSR_DE
);
349 mtspr(SPRN_IAC1
, thread
->iac1
);
350 mtspr(SPRN_IAC2
, thread
->iac2
);
351 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
352 mtspr(SPRN_IAC3
, thread
->iac3
);
353 mtspr(SPRN_IAC4
, thread
->iac4
);
355 mtspr(SPRN_DAC1
, thread
->dac1
);
356 mtspr(SPRN_DAC2
, thread
->dac2
);
357 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
358 mtspr(SPRN_DVC1
, thread
->dvc1
);
359 mtspr(SPRN_DVC2
, thread
->dvc2
);
361 mtspr(SPRN_DBCR0
, thread
->dbcr0
);
362 mtspr(SPRN_DBCR1
, thread
->dbcr1
);
364 mtspr(SPRN_DBCR2
, thread
->dbcr2
);
368 * Unless neither the old or new thread are making use of the
369 * debug registers, set the debug registers from the values
370 * stored in the new thread.
372 static void switch_booke_debug_regs(struct thread_struct
*new_thread
)
374 if ((current
->thread
.dbcr0
& DBCR0_IDM
)
375 || (new_thread
->dbcr0
& DBCR0_IDM
))
376 prime_debug_regs(new_thread
);
378 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
379 #ifndef CONFIG_HAVE_HW_BREAKPOINT
380 static void set_debug_reg_defaults(struct thread_struct
*thread
)
382 thread
->hw_brk
.address
= 0;
383 thread
->hw_brk
.type
= 0;
384 set_breakpoint(&thread
->hw_brk
);
386 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
387 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
389 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
390 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
392 mtspr(SPRN_DAC1
, dabr
);
393 #ifdef CONFIG_PPC_47x
398 #elif defined(CONFIG_PPC_BOOK3S)
399 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
401 mtspr(SPRN_DABR
, dabr
);
402 mtspr(SPRN_DABRX
, dabrx
);
406 static inline int __set_dabr(unsigned long dabr
, unsigned long dabrx
)
412 static inline int set_dabr(struct arch_hw_breakpoint
*brk
)
414 unsigned long dabr
, dabrx
;
416 dabr
= brk
->address
| (brk
->type
& HW_BRK_TYPE_DABR
);
417 dabrx
= ((brk
->type
>> 3) & 0x7);
420 return ppc_md
.set_dabr(dabr
, dabrx
);
422 return __set_dabr(dabr
, dabrx
);
425 static inline int set_dawr(struct arch_hw_breakpoint
*brk
)
427 unsigned long dawr
, dawrx
, mrd
;
431 dawrx
= (brk
->type
& (HW_BRK_TYPE_READ
| HW_BRK_TYPE_WRITE
)) \
432 << (63 - 58); //* read/write bits */
433 dawrx
|= ((brk
->type
& (HW_BRK_TYPE_TRANSLATE
)) >> 2) \
434 << (63 - 59); //* translate */
435 dawrx
|= (brk
->type
& (HW_BRK_TYPE_PRIV_ALL
)) \
436 >> 3; //* PRIM bits */
437 /* dawr length is stored in field MDR bits 48:53. Matches range in
438 doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
440 brk->len is in bytes.
441 This aligns up to double word size, shifts and does the bias.
443 mrd
= ((brk
->len
+ 7) >> 3) - 1;
444 dawrx
|= (mrd
& 0x3f) << (63 - 53);
447 return ppc_md
.set_dawr(dawr
, dawrx
);
448 mtspr(SPRN_DAWR
, dawr
);
449 mtspr(SPRN_DAWRX
, dawrx
);
453 int set_breakpoint(struct arch_hw_breakpoint
*brk
)
455 __get_cpu_var(current_brk
) = *brk
;
457 if (cpu_has_feature(CPU_FTR_DAWR
))
458 return set_dawr(brk
);
460 return set_dabr(brk
);
464 DEFINE_PER_CPU(struct cpu_usage
, cpu_usage_array
);
467 static inline bool hw_brk_match(struct arch_hw_breakpoint
*a
,
468 struct arch_hw_breakpoint
*b
)
470 if (a
->address
!= b
->address
)
472 if (a
->type
!= b
->type
)
474 if (a
->len
!= b
->len
)
478 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
479 static inline void tm_reclaim_task(struct task_struct
*tsk
)
481 /* We have to work out if we're switching from/to a task that's in the
482 * middle of a transaction.
484 * In switching we need to maintain a 2nd register state as
485 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
486 * checkpointed (tbegin) state in ckpt_regs and saves the transactional
487 * (current) FPRs into oldtask->thread.transact_fpr[].
489 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
491 struct thread_struct
*thr
= &tsk
->thread
;
496 if (!MSR_TM_ACTIVE(thr
->regs
->msr
))
497 goto out_and_saveregs
;
499 /* Stash the original thread MSR, as giveup_fpu et al will
500 * modify it. We hold onto it to see whether the task used
503 thr
->tm_orig_msr
= thr
->regs
->msr
;
505 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
506 "ccr=%lx, msr=%lx, trap=%lx)\n",
507 tsk
->pid
, thr
->regs
->nip
,
508 thr
->regs
->ccr
, thr
->regs
->msr
,
511 tm_reclaim(thr
, thr
->regs
->msr
, TM_CAUSE_RESCHED
);
513 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
517 /* Always save the regs here, even if a transaction's not active.
518 * This context-switches a thread's TM info SPRs. We do it here to
519 * be consistent with the restore path (in recheckpoint) which
520 * cannot happen later in _switch().
525 static inline void tm_recheckpoint_new_task(struct task_struct
*new)
529 if (!cpu_has_feature(CPU_FTR_TM
))
532 /* Recheckpoint the registers of the thread we're about to switch to.
534 * If the task was using FP, we non-lazily reload both the original and
535 * the speculative FP register states. This is because the kernel
536 * doesn't see if/when a TM rollback occurs, so if we take an FP
537 * unavoidable later, we are unable to determine which set of FP regs
538 * need to be restored.
540 if (!new->thread
.regs
)
543 /* The TM SPRs are restored here, so that TEXASR.FS can be set
544 * before the trecheckpoint and no explosion occurs.
546 tm_restore_sprs(&new->thread
);
548 if (!MSR_TM_ACTIVE(new->thread
.regs
->msr
))
550 msr
= new->thread
.tm_orig_msr
;
551 /* Recheckpoint to restore original checkpointed register state. */
552 TM_DEBUG("*** tm_recheckpoint of pid %d "
553 "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
554 new->pid
, new->thread
.regs
->msr
, msr
);
556 /* This loads the checkpointed FP/VEC state, if used */
557 tm_recheckpoint(&new->thread
, msr
);
559 /* This loads the speculative FP/VEC state, if used */
561 do_load_up_transact_fpu(&new->thread
);
562 new->thread
.regs
->msr
|=
563 (MSR_FP
| new->thread
.fpexc_mode
);
565 #ifdef CONFIG_ALTIVEC
567 do_load_up_transact_altivec(&new->thread
);
568 new->thread
.regs
->msr
|= MSR_VEC
;
571 /* We may as well turn on VSX too since all the state is restored now */
573 new->thread
.regs
->msr
|= MSR_VSX
;
575 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
576 "(kernel msr 0x%lx)\n",
580 static inline void __switch_to_tm(struct task_struct
*prev
)
582 if (cpu_has_feature(CPU_FTR_TM
)) {
584 tm_reclaim_task(prev
);
588 #define tm_recheckpoint_new_task(new)
589 #define __switch_to_tm(prev)
590 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
592 struct task_struct
*__switch_to(struct task_struct
*prev
,
593 struct task_struct
*new)
595 struct thread_struct
*new_thread
, *old_thread
;
597 struct task_struct
*last
;
598 #ifdef CONFIG_PPC_BOOK3S_64
599 struct ppc64_tlb_batch
*batch
;
602 __switch_to_tm(prev
);
605 /* avoid complexity of lazy save/restore of fpu
606 * by just saving it every time we switch out if
607 * this task used the fpu during the last quantum.
609 * If it tries to use the fpu again, it'll trap and
610 * reload its fp regs. So we don't have to do a restore
611 * every switch, just a save.
614 if (prev
->thread
.regs
&& (prev
->thread
.regs
->msr
& MSR_FP
))
616 #ifdef CONFIG_ALTIVEC
618 * If the previous thread used altivec in the last quantum
619 * (thus changing altivec regs) then save them.
620 * We used to check the VRSAVE register but not all apps
621 * set it, so we don't rely on it now (and in fact we need
622 * to save & restore VSCR even if VRSAVE == 0). -- paulus
624 * On SMP we always save/restore altivec regs just to avoid the
625 * complexity of changing processors.
628 if (prev
->thread
.regs
&& (prev
->thread
.regs
->msr
& MSR_VEC
))
629 giveup_altivec(prev
);
630 #endif /* CONFIG_ALTIVEC */
632 if (prev
->thread
.regs
&& (prev
->thread
.regs
->msr
& MSR_VSX
))
633 /* VMX and FPU registers are already save here */
635 #endif /* CONFIG_VSX */
638 * If the previous thread used spe in the last quantum
639 * (thus changing spe regs) then save them.
641 * On SMP we always save/restore spe regs just to avoid the
642 * complexity of changing processors.
644 if ((prev
->thread
.regs
&& (prev
->thread
.regs
->msr
& MSR_SPE
)))
646 #endif /* CONFIG_SPE */
648 #else /* CONFIG_SMP */
649 #ifdef CONFIG_ALTIVEC
650 /* Avoid the trap. On smp this this never happens since
651 * we don't set last_task_used_altivec -- Cort
653 if (new->thread
.regs
&& last_task_used_altivec
== new)
654 new->thread
.regs
->msr
|= MSR_VEC
;
655 #endif /* CONFIG_ALTIVEC */
657 if (new->thread
.regs
&& last_task_used_vsx
== new)
658 new->thread
.regs
->msr
|= MSR_VSX
;
659 #endif /* CONFIG_VSX */
661 /* Avoid the trap. On smp this this never happens since
662 * we don't set last_task_used_spe
664 if (new->thread
.regs
&& last_task_used_spe
== new)
665 new->thread
.regs
->msr
|= MSR_SPE
;
666 #endif /* CONFIG_SPE */
668 #endif /* CONFIG_SMP */
670 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
671 switch_booke_debug_regs(&new->thread
);
674 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
677 #ifndef CONFIG_HAVE_HW_BREAKPOINT
678 if (unlikely(hw_brk_match(&__get_cpu_var(current_brk
), &new->thread
.hw_brk
)))
679 set_breakpoint(&new->thread
.hw_brk
);
680 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
684 new_thread
= &new->thread
;
685 old_thread
= ¤t
->thread
;
689 * Collect processor utilization data per process
691 if (firmware_has_feature(FW_FEATURE_SPLPAR
)) {
692 struct cpu_usage
*cu
= &__get_cpu_var(cpu_usage_array
);
693 long unsigned start_tb
, current_tb
;
694 start_tb
= old_thread
->start_tb
;
695 cu
->current_tb
= current_tb
= mfspr(SPRN_PURR
);
696 old_thread
->accum_tb
+= (current_tb
- start_tb
);
697 new_thread
->start_tb
= current_tb
;
699 #endif /* CONFIG_PPC64 */
701 #ifdef CONFIG_PPC_BOOK3S_64
702 batch
= &__get_cpu_var(ppc64_tlb_batch
);
704 current_thread_info()->local_flags
|= _TLF_LAZY_MMU
;
706 __flush_tlb_pending(batch
);
709 #endif /* CONFIG_PPC_BOOK3S_64 */
711 local_irq_save(flags
);
714 * We can't take a PMU exception inside _switch() since there is a
715 * window where the kernel stack SLB and the kernel stack are out
716 * of sync. Hard disable here.
720 tm_recheckpoint_new_task(new);
722 last
= _switch(old_thread
, new_thread
);
724 #ifdef CONFIG_PPC_BOOK3S_64
725 if (current_thread_info()->local_flags
& _TLF_LAZY_MMU
) {
726 current_thread_info()->local_flags
&= ~_TLF_LAZY_MMU
;
727 batch
= &__get_cpu_var(ppc64_tlb_batch
);
730 #endif /* CONFIG_PPC_BOOK3S_64 */
732 local_irq_restore(flags
);
737 static int instructions_to_print
= 16;
739 static void show_instructions(struct pt_regs
*regs
)
742 unsigned long pc
= regs
->nip
- (instructions_to_print
* 3 / 4 *
745 printk("Instruction dump:");
747 for (i
= 0; i
< instructions_to_print
; i
++) {
753 #if !defined(CONFIG_BOOKE)
754 /* If executing with the IMMU off, adjust pc rather
755 * than print XXXXXXXX.
757 if (!(regs
->msr
& MSR_IR
))
758 pc
= (unsigned long)phys_to_virt(pc
);
761 /* We use __get_user here *only* to avoid an OOPS on a
762 * bad address because the pc *should* only be a
765 if (!__kernel_text_address(pc
) ||
766 __get_user(instr
, (unsigned int __user
*)pc
)) {
767 printk(KERN_CONT
"XXXXXXXX ");
770 printk(KERN_CONT
"<%08x> ", instr
);
772 printk(KERN_CONT
"%08x ", instr
);
781 static struct regbit
{
785 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
814 static void printbits(unsigned long val
, struct regbit
*bits
)
816 const char *sep
= "";
819 for (; bits
->bit
; ++bits
)
820 if (val
& bits
->bit
) {
821 printk("%s%s", sep
, bits
->name
);
829 #define REGS_PER_LINE 4
830 #define LAST_VOLATILE 13
833 #define REGS_PER_LINE 8
834 #define LAST_VOLATILE 12
837 void show_regs(struct pt_regs
* regs
)
841 show_regs_print_info(KERN_DEFAULT
);
843 printk("NIP: "REG
" LR: "REG
" CTR: "REG
"\n",
844 regs
->nip
, regs
->link
, regs
->ctr
);
845 printk("REGS: %p TRAP: %04lx %s (%s)\n",
846 regs
, regs
->trap
, print_tainted(), init_utsname()->release
);
847 printk("MSR: "REG
" ", regs
->msr
);
848 printbits(regs
->msr
, msr_bits
);
849 printk(" CR: %08lx XER: %08lx\n", regs
->ccr
, regs
->xer
);
851 printk("SOFTE: %ld\n", regs
->softe
);
854 if ((regs
->trap
!= 0xc00) && cpu_has_feature(CPU_FTR_CFAR
))
855 printk("CFAR: "REG
"\n", regs
->orig_gpr3
);
856 if (trap
== 0x300 || trap
== 0x600)
857 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
858 printk("DEAR: "REG
", ESR: "REG
"\n", regs
->dar
, regs
->dsisr
);
860 printk("DAR: "REG
", DSISR: %08lx\n", regs
->dar
, regs
->dsisr
);
863 for (i
= 0; i
< 32; i
++) {
864 if ((i
% REGS_PER_LINE
) == 0)
865 printk("\nGPR%02d: ", i
);
866 printk(REG
" ", regs
->gpr
[i
]);
867 if (i
== LAST_VOLATILE
&& !FULL_REGS(regs
))
871 #ifdef CONFIG_KALLSYMS
873 * Lookup NIP late so we have the best change of getting the
874 * above info out without failing
876 printk("NIP ["REG
"] %pS\n", regs
->nip
, (void *)regs
->nip
);
877 printk("LR ["REG
"] %pS\n", regs
->link
, (void *)regs
->link
);
879 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
880 printk("PACATMSCRATCH [%llx]\n", get_paca()->tm_scratch
);
882 show_stack(current
, (unsigned long *) regs
->gpr
[1]);
883 if (!user_mode(regs
))
884 show_instructions(regs
);
887 void exit_thread(void)
889 discard_lazy_cpu_state();
892 void flush_thread(void)
894 discard_lazy_cpu_state();
896 #ifdef CONFIG_HAVE_HW_BREAKPOINT
897 flush_ptrace_hw_breakpoint(current
);
898 #else /* CONFIG_HAVE_HW_BREAKPOINT */
899 set_debug_reg_defaults(¤t
->thread
);
900 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
904 release_thread(struct task_struct
*t
)
909 * this gets called so that we can store coprocessor state into memory and
910 * copy the current task into the new thread.
912 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
914 flush_fp_to_thread(src
);
915 flush_altivec_to_thread(src
);
916 flush_vsx_to_thread(src
);
917 flush_spe_to_thread(src
);
925 extern unsigned long dscr_default
; /* defined in arch/powerpc/kernel/sysfs.c */
927 int copy_thread(unsigned long clone_flags
, unsigned long usp
,
928 unsigned long arg
, struct task_struct
*p
)
930 struct pt_regs
*childregs
, *kregs
;
931 extern void ret_from_fork(void);
932 extern void ret_from_kernel_thread(void);
934 unsigned long sp
= (unsigned long)task_stack_page(p
) + THREAD_SIZE
;
937 sp
-= sizeof(struct pt_regs
);
938 childregs
= (struct pt_regs
*) sp
;
939 if (unlikely(p
->flags
& PF_KTHREAD
)) {
940 struct thread_info
*ti
= (void *)task_stack_page(p
);
941 memset(childregs
, 0, sizeof(struct pt_regs
));
942 childregs
->gpr
[1] = sp
+ sizeof(struct pt_regs
);
943 childregs
->gpr
[14] = usp
; /* function */
945 clear_tsk_thread_flag(p
, TIF_32BIT
);
946 childregs
->softe
= 1;
948 childregs
->gpr
[15] = arg
;
949 p
->thread
.regs
= NULL
; /* no user register state */
950 ti
->flags
|= _TIF_RESTOREALL
;
951 f
= ret_from_kernel_thread
;
953 struct pt_regs
*regs
= current_pt_regs();
954 CHECK_FULL_REGS(regs
);
957 childregs
->gpr
[1] = usp
;
958 p
->thread
.regs
= childregs
;
959 childregs
->gpr
[3] = 0; /* Result from fork() */
960 if (clone_flags
& CLONE_SETTLS
) {
962 if (!is_32bit_task())
963 childregs
->gpr
[13] = childregs
->gpr
[6];
966 childregs
->gpr
[2] = childregs
->gpr
[6];
971 sp
-= STACK_FRAME_OVERHEAD
;
974 * The way this works is that at some point in the future
975 * some task will call _switch to switch to the new task.
976 * That will pop off the stack frame created below and start
977 * the new task running at ret_from_fork. The new task will
978 * do some house keeping and then return from the fork or clone
979 * system call, using the stack frame created above.
981 ((unsigned long *)sp
)[0] = 0;
982 sp
-= sizeof(struct pt_regs
);
983 kregs
= (struct pt_regs
*) sp
;
984 sp
-= STACK_FRAME_OVERHEAD
;
986 p
->thread
.ksp_limit
= (unsigned long)task_stack_page(p
) +
987 _ALIGN_UP(sizeof(struct thread_info
), 16);
989 #ifdef CONFIG_HAVE_HW_BREAKPOINT
990 p
->thread
.ptrace_bps
[0] = NULL
;
993 #ifdef CONFIG_PPC_STD_MMU_64
994 if (mmu_has_feature(MMU_FTR_SLB
)) {
995 unsigned long sp_vsid
;
996 unsigned long llp
= mmu_psize_defs
[mmu_linear_psize
].sllp
;
998 if (mmu_has_feature(MMU_FTR_1T_SEGMENT
))
999 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_1T
)
1000 << SLB_VSID_SHIFT_1T
;
1002 sp_vsid
= get_kernel_vsid(sp
, MMU_SEGSIZE_256M
)
1004 sp_vsid
|= SLB_VSID_KERNEL
| llp
;
1005 p
->thread
.ksp_vsid
= sp_vsid
;
1007 #endif /* CONFIG_PPC_STD_MMU_64 */
1009 if (cpu_has_feature(CPU_FTR_DSCR
)) {
1010 p
->thread
.dscr_inherit
= current
->thread
.dscr_inherit
;
1011 p
->thread
.dscr
= current
->thread
.dscr
;
1013 if (cpu_has_feature(CPU_FTR_HAS_PPR
))
1014 p
->thread
.ppr
= INIT_PPR
;
1017 * The PPC64 ABI makes use of a TOC to contain function
1018 * pointers. The function (ret_from_except) is actually a pointer
1019 * to the TOC entry. The first entry is a pointer to the actual
1023 kregs
->nip
= *((unsigned long *)f
);
1025 kregs
->nip
= (unsigned long)f
;
1031 * Set up a thread for executing a new program
1033 void start_thread(struct pt_regs
*regs
, unsigned long start
, unsigned long sp
)
1036 unsigned long load_addr
= regs
->gpr
[2]; /* saved by ELF_PLAT_INIT */
1040 * If we exec out of a kernel thread then thread.regs will not be
1043 if (!current
->thread
.regs
) {
1044 struct pt_regs
*regs
= task_stack_page(current
) + THREAD_SIZE
;
1045 current
->thread
.regs
= regs
- 1;
1048 memset(regs
->gpr
, 0, sizeof(regs
->gpr
));
1056 * We have just cleared all the nonvolatile GPRs, so make
1057 * FULL_REGS(regs) return true. This is necessary to allow
1058 * ptrace to examine the thread immediately after exec.
1065 regs
->msr
= MSR_USER
;
1067 if (!is_32bit_task()) {
1068 unsigned long entry
, toc
;
1070 /* start is a relocated pointer to the function descriptor for
1071 * the elf _start routine. The first entry in the function
1072 * descriptor is the entry address of _start and the second
1073 * entry is the TOC value we need to use.
1075 __get_user(entry
, (unsigned long __user
*)start
);
1076 __get_user(toc
, (unsigned long __user
*)start
+1);
1078 /* Check whether the e_entry function descriptor entries
1079 * need to be relocated before we can use them.
1081 if (load_addr
!= 0) {
1087 regs
->msr
= MSR_USER64
;
1091 regs
->msr
= MSR_USER32
;
1094 discard_lazy_cpu_state();
1096 current
->thread
.used_vsr
= 0;
1098 memset(current
->thread
.fpr
, 0, sizeof(current
->thread
.fpr
));
1099 current
->thread
.fpscr
.val
= 0;
1100 #ifdef CONFIG_ALTIVEC
1101 memset(current
->thread
.vr
, 0, sizeof(current
->thread
.vr
));
1102 memset(¤t
->thread
.vscr
, 0, sizeof(current
->thread
.vscr
));
1103 current
->thread
.vscr
.u
[3] = 0x00010000; /* Java mode disabled */
1104 current
->thread
.vrsave
= 0;
1105 current
->thread
.used_vr
= 0;
1106 #endif /* CONFIG_ALTIVEC */
1108 memset(current
->thread
.evr
, 0, sizeof(current
->thread
.evr
));
1109 current
->thread
.acc
= 0;
1110 current
->thread
.spefscr
= 0;
1111 current
->thread
.used_spe
= 0;
1112 #endif /* CONFIG_SPE */
1113 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1114 if (cpu_has_feature(CPU_FTR_TM
))
1115 regs
->msr
|= MSR_TM
;
1116 current
->thread
.tm_tfhar
= 0;
1117 current
->thread
.tm_texasr
= 0;
1118 current
->thread
.tm_tfiar
= 0;
1119 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1122 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1123 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1125 int set_fpexc_mode(struct task_struct
*tsk
, unsigned int val
)
1127 struct pt_regs
*regs
= tsk
->thread
.regs
;
1129 /* This is a bit hairy. If we are an SPE enabled processor
1130 * (have embedded fp) we store the IEEE exception enable flags in
1131 * fpexc_mode. fpexc_mode is also used for setting FP exception
1132 * mode (asyn, precise, disabled) for 'Classic' FP. */
1133 if (val
& PR_FP_EXC_SW_ENABLE
) {
1135 if (cpu_has_feature(CPU_FTR_SPE
)) {
1136 tsk
->thread
.fpexc_mode
= val
&
1137 (PR_FP_EXC_SW_ENABLE
| PR_FP_ALL_EXCEPT
);
1147 /* on a CONFIG_SPE this does not hurt us. The bits that
1148 * __pack_fe01 use do not overlap with bits used for
1149 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1150 * on CONFIG_SPE implementations are reserved so writing to
1151 * them does not change anything */
1152 if (val
> PR_FP_EXC_PRECISE
)
1154 tsk
->thread
.fpexc_mode
= __pack_fe01(val
);
1155 if (regs
!= NULL
&& (regs
->msr
& MSR_FP
) != 0)
1156 regs
->msr
= (regs
->msr
& ~(MSR_FE0
|MSR_FE1
))
1157 | tsk
->thread
.fpexc_mode
;
1161 int get_fpexc_mode(struct task_struct
*tsk
, unsigned long adr
)
1165 if (tsk
->thread
.fpexc_mode
& PR_FP_EXC_SW_ENABLE
)
1167 if (cpu_has_feature(CPU_FTR_SPE
))
1168 val
= tsk
->thread
.fpexc_mode
;
1175 val
= __unpack_fe01(tsk
->thread
.fpexc_mode
);
1176 return put_user(val
, (unsigned int __user
*) adr
);
1179 int set_endian(struct task_struct
*tsk
, unsigned int val
)
1181 struct pt_regs
*regs
= tsk
->thread
.regs
;
1183 if ((val
== PR_ENDIAN_LITTLE
&& !cpu_has_feature(CPU_FTR_REAL_LE
)) ||
1184 (val
== PR_ENDIAN_PPC_LITTLE
&& !cpu_has_feature(CPU_FTR_PPC_LE
)))
1190 if (val
== PR_ENDIAN_BIG
)
1191 regs
->msr
&= ~MSR_LE
;
1192 else if (val
== PR_ENDIAN_LITTLE
|| val
== PR_ENDIAN_PPC_LITTLE
)
1193 regs
->msr
|= MSR_LE
;
1200 int get_endian(struct task_struct
*tsk
, unsigned long adr
)
1202 struct pt_regs
*regs
= tsk
->thread
.regs
;
1205 if (!cpu_has_feature(CPU_FTR_PPC_LE
) &&
1206 !cpu_has_feature(CPU_FTR_REAL_LE
))
1212 if (regs
->msr
& MSR_LE
) {
1213 if (cpu_has_feature(CPU_FTR_REAL_LE
))
1214 val
= PR_ENDIAN_LITTLE
;
1216 val
= PR_ENDIAN_PPC_LITTLE
;
1218 val
= PR_ENDIAN_BIG
;
1220 return put_user(val
, (unsigned int __user
*)adr
);
1223 int set_unalign_ctl(struct task_struct
*tsk
, unsigned int val
)
1225 tsk
->thread
.align_ctl
= val
;
1229 int get_unalign_ctl(struct task_struct
*tsk
, unsigned long adr
)
1231 return put_user(tsk
->thread
.align_ctl
, (unsigned int __user
*)adr
);
1234 static inline int valid_irq_stack(unsigned long sp
, struct task_struct
*p
,
1235 unsigned long nbytes
)
1237 unsigned long stack_page
;
1238 unsigned long cpu
= task_cpu(p
);
1241 * Avoid crashing if the stack has overflowed and corrupted
1242 * task_cpu(p), which is in the thread_info struct.
1244 if (cpu
< NR_CPUS
&& cpu_possible(cpu
)) {
1245 stack_page
= (unsigned long) hardirq_ctx
[cpu
];
1246 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1247 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1250 stack_page
= (unsigned long) softirq_ctx
[cpu
];
1251 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1252 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1258 int validate_sp(unsigned long sp
, struct task_struct
*p
,
1259 unsigned long nbytes
)
1261 unsigned long stack_page
= (unsigned long)task_stack_page(p
);
1263 if (sp
>= stack_page
+ sizeof(struct thread_struct
)
1264 && sp
<= stack_page
+ THREAD_SIZE
- nbytes
)
1267 return valid_irq_stack(sp
, p
, nbytes
);
1270 EXPORT_SYMBOL(validate_sp
);
1272 unsigned long get_wchan(struct task_struct
*p
)
1274 unsigned long ip
, sp
;
1277 if (!p
|| p
== current
|| p
->state
== TASK_RUNNING
)
1281 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1285 sp
= *(unsigned long *)sp
;
1286 if (!validate_sp(sp
, p
, STACK_FRAME_OVERHEAD
))
1289 ip
= ((unsigned long *)sp
)[STACK_FRAME_LR_SAVE
];
1290 if (!in_sched_functions(ip
))
1293 } while (count
++ < 16);
1297 static int kstack_depth_to_print
= CONFIG_PRINT_STACK_DEPTH
;
1299 void show_stack(struct task_struct
*tsk
, unsigned long *stack
)
1301 unsigned long sp
, ip
, lr
, newsp
;
1304 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1305 int curr_frame
= current
->curr_ret_stack
;
1306 extern void return_to_handler(void);
1307 unsigned long rth
= (unsigned long)return_to_handler
;
1308 unsigned long mrth
= -1;
1310 extern void mod_return_to_handler(void);
1311 rth
= *(unsigned long *)rth
;
1312 mrth
= (unsigned long)mod_return_to_handler
;
1313 mrth
= *(unsigned long *)mrth
;
1317 sp
= (unsigned long) stack
;
1322 asm("mr %0,1" : "=r" (sp
));
1324 sp
= tsk
->thread
.ksp
;
1328 printk("Call Trace:\n");
1330 if (!validate_sp(sp
, tsk
, STACK_FRAME_OVERHEAD
))
1333 stack
= (unsigned long *) sp
;
1335 ip
= stack
[STACK_FRAME_LR_SAVE
];
1336 if (!firstframe
|| ip
!= lr
) {
1337 printk("["REG
"] ["REG
"] %pS", sp
, ip
, (void *)ip
);
1338 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1339 if ((ip
== rth
|| ip
== mrth
) && curr_frame
>= 0) {
1341 (void *)current
->ret_stack
[curr_frame
].ret
);
1346 printk(" (unreliable)");
1352 * See if this is an exception frame.
1353 * We look for the "regshere" marker in the current frame.
1355 if (validate_sp(sp
, tsk
, STACK_INT_FRAME_SIZE
)
1356 && stack
[STACK_FRAME_MARKER
] == STACK_FRAME_REGS_MARKER
) {
1357 struct pt_regs
*regs
= (struct pt_regs
*)
1358 (sp
+ STACK_FRAME_OVERHEAD
);
1360 printk("--- Exception: %lx at %pS\n LR = %pS\n",
1361 regs
->trap
, (void *)regs
->nip
, (void *)lr
);
1366 } while (count
++ < kstack_depth_to_print
);
1370 /* Called with hard IRQs off */
1371 void __ppc64_runlatch_on(void)
1373 struct thread_info
*ti
= current_thread_info();
1376 ctrl
= mfspr(SPRN_CTRLF
);
1377 ctrl
|= CTRL_RUNLATCH
;
1378 mtspr(SPRN_CTRLT
, ctrl
);
1380 ti
->local_flags
|= _TLF_RUNLATCH
;
1383 /* Called with hard IRQs off */
1384 void __ppc64_runlatch_off(void)
1386 struct thread_info
*ti
= current_thread_info();
1389 ti
->local_flags
&= ~_TLF_RUNLATCH
;
1391 ctrl
= mfspr(SPRN_CTRLF
);
1392 ctrl
&= ~CTRL_RUNLATCH
;
1393 mtspr(SPRN_CTRLT
, ctrl
);
1395 #endif /* CONFIG_PPC64 */
1397 unsigned long arch_align_stack(unsigned long sp
)
1399 if (!(current
->personality
& ADDR_NO_RANDOMIZE
) && randomize_va_space
)
1400 sp
-= get_random_int() & ~PAGE_MASK
;
1404 static inline unsigned long brk_rnd(void)
1406 unsigned long rnd
= 0;
1408 /* 8MB for 32bit, 1GB for 64bit */
1409 if (is_32bit_task())
1410 rnd
= (long)(get_random_int() % (1<<(23-PAGE_SHIFT
)));
1412 rnd
= (long)(get_random_int() % (1<<(30-PAGE_SHIFT
)));
1414 return rnd
<< PAGE_SHIFT
;
1417 unsigned long arch_randomize_brk(struct mm_struct
*mm
)
1419 unsigned long base
= mm
->brk
;
1422 #ifdef CONFIG_PPC_STD_MMU_64
1424 * If we are using 1TB segments and we are allowed to randomise
1425 * the heap, we can put it above 1TB so it is backed by a 1TB
1426 * segment. Otherwise the heap will be in the bottom 1TB
1427 * which always uses 256MB segments and this may result in a
1428 * performance penalty.
1430 if (!is_32bit_task() && (mmu_highuser_ssize
== MMU_SEGSIZE_1T
))
1431 base
= max_t(unsigned long, mm
->brk
, 1UL << SID_SHIFT_1T
);
1434 ret
= PAGE_ALIGN(base
+ brk_rnd());
1442 unsigned long randomize_et_dyn(unsigned long base
)
1444 unsigned long ret
= PAGE_ALIGN(base
+ brk_rnd());