7531f9abf10d05dd0ffb2d7b3cc1f35adb56f84f
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / hw_breakpoint.c
1 /*
2 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
3 * using the CPU's debug registers. Derived from
4 * "arch/x86/kernel/hw_breakpoint.c"
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 * Copyright 2010 IBM Corporation
21 * Author: K.Prasad <prasad@linux.vnet.ibm.com>
22 *
23 */
24
25 #include <linux/hw_breakpoint.h>
26 #include <linux/notifier.h>
27 #include <linux/kprobes.h>
28 #include <linux/percpu.h>
29 #include <linux/kernel.h>
30 #include <linux/sched.h>
31 #include <linux/init.h>
32 #include <linux/smp.h>
33
34 #include <asm/hw_breakpoint.h>
35 #include <asm/processor.h>
36 #include <asm/sstep.h>
37 #include <asm/uaccess.h>
38
39 /*
40 * Stores the breakpoints currently in use on each breakpoint address
41 * register for every cpu
42 */
43 static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
44
45 /*
46 * Returns total number of data or instruction breakpoints available.
47 */
48 int hw_breakpoint_slots(int type)
49 {
50 if (type == TYPE_DATA)
51 return HBP_NUM;
52 return 0; /* no instruction breakpoints available */
53 }
54
55 /*
56 * Install a perf counter breakpoint.
57 *
58 * We seek a free debug address register and use it for this
59 * breakpoint.
60 *
61 * Atomic: we hold the counter->ctx->lock and we only handle variables
62 * and registers local to this cpu.
63 */
64 int arch_install_hw_breakpoint(struct perf_event *bp)
65 {
66 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
67 struct perf_event **slot = &__get_cpu_var(bp_per_reg);
68
69 *slot = bp;
70
71 /*
72 * Do not install DABR values if the instruction must be single-stepped.
73 * If so, DABR will be populated in single_step_dabr_instruction().
74 */
75 if (current->thread.last_hit_ubp != bp)
76 set_breakpoint(info);
77
78 return 0;
79 }
80
81 /*
82 * Uninstall the breakpoint contained in the given counter.
83 *
84 * First we search the debug address register it uses and then we disable
85 * it.
86 *
87 * Atomic: we hold the counter->ctx->lock and we only handle variables
88 * and registers local to this cpu.
89 */
90 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
91 {
92 struct perf_event **slot = &__get_cpu_var(bp_per_reg);
93
94 if (*slot != bp) {
95 WARN_ONCE(1, "Can't find the breakpoint");
96 return;
97 }
98
99 *slot = NULL;
100 hw_breakpoint_disable();
101 }
102
103 /*
104 * Perform cleanup of arch-specific counters during unregistration
105 * of the perf-event
106 */
107 void arch_unregister_hw_breakpoint(struct perf_event *bp)
108 {
109 /*
110 * If the breakpoint is unregistered between a hw_breakpoint_handler()
111 * and the single_step_dabr_instruction(), then cleanup the breakpoint
112 * restoration variables to prevent dangling pointers.
113 */
114 if (bp->ctx && bp->ctx->task)
115 bp->ctx->task->thread.last_hit_ubp = NULL;
116 }
117
118 /*
119 * Check for virtual address in kernel space.
120 */
121 int arch_check_bp_in_kernelspace(struct perf_event *bp)
122 {
123 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
124
125 return is_kernel_addr(info->address);
126 }
127
128 int arch_bp_generic_fields(int type, int *gen_bp_type)
129 {
130 *gen_bp_type = 0;
131 if (type & HW_BRK_TYPE_READ)
132 *gen_bp_type |= HW_BREAKPOINT_R;
133 if (type & HW_BRK_TYPE_WRITE)
134 *gen_bp_type |= HW_BREAKPOINT_W;
135 if (*gen_bp_type == 0)
136 return -EINVAL;
137 return 0;
138 }
139
140 /*
141 * Validate the arch-specific HW Breakpoint register settings
142 */
143 int arch_validate_hwbkpt_settings(struct perf_event *bp)
144 {
145 int ret = -EINVAL, length_max;
146 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
147
148 if (!bp)
149 return ret;
150
151 info->type = HW_BRK_TYPE_TRANSLATE;
152 if (bp->attr.bp_type & HW_BREAKPOINT_R)
153 info->type |= HW_BRK_TYPE_READ;
154 if (bp->attr.bp_type & HW_BREAKPOINT_W)
155 info->type |= HW_BRK_TYPE_WRITE;
156 if (info->type == HW_BRK_TYPE_TRANSLATE)
157 /* must set alteast read or write */
158 return ret;
159 if (!(bp->attr.exclude_user))
160 info->type |= HW_BRK_TYPE_USER;
161 if (!(bp->attr.exclude_kernel))
162 info->type |= HW_BRK_TYPE_KERNEL;
163 if (!(bp->attr.exclude_hv))
164 info->type |= HW_BRK_TYPE_HYP;
165 info->address = bp->attr.bp_addr;
166 info->len = bp->attr.bp_len;
167
168 /*
169 * Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
170 * and breakpoint addresses are aligned to nearest double-word
171 * HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
172 * 'symbolsize' should satisfy the check below.
173 */
174 length_max = 8; /* DABR */
175 if (cpu_has_feature(CPU_FTR_DAWR)) {
176 length_max = 512 ; /* 64 doublewords */
177 /* DAWR region can't cross 512 boundary */
178 if ((bp->attr.bp_addr >> 10) !=
179 ((bp->attr.bp_addr + bp->attr.bp_len - 1) >> 10))
180 return -EINVAL;
181 }
182 if (info->len >
183 (length_max - (info->address & HW_BREAKPOINT_ALIGN)))
184 return -EINVAL;
185 return 0;
186 }
187
188 /*
189 * Restores the breakpoint on the debug registers.
190 * Invoke this function if it is known that the execution context is
191 * about to change to cause loss of MSR_SE settings.
192 */
193 void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
194 {
195 struct arch_hw_breakpoint *info;
196
197 if (likely(!tsk->thread.last_hit_ubp))
198 return;
199
200 info = counter_arch_bp(tsk->thread.last_hit_ubp);
201 regs->msr &= ~MSR_SE;
202 set_breakpoint(info);
203 tsk->thread.last_hit_ubp = NULL;
204 }
205
206 /*
207 * Handle debug exception notifications.
208 */
209 int __kprobes hw_breakpoint_handler(struct die_args *args)
210 {
211 int rc = NOTIFY_STOP;
212 struct perf_event *bp;
213 struct pt_regs *regs = args->regs;
214 int stepped = 1;
215 struct arch_hw_breakpoint *info;
216 unsigned int instr;
217 unsigned long dar = regs->dar;
218
219 /* Disable breakpoints during exception handling */
220 hw_breakpoint_disable();
221
222 /*
223 * The counter may be concurrently released but that can only
224 * occur from a call_rcu() path. We can then safely fetch
225 * the breakpoint, use its callback, touch its counter
226 * while we are in an rcu_read_lock() path.
227 */
228 rcu_read_lock();
229
230 bp = __get_cpu_var(bp_per_reg);
231 if (!bp) {
232 rc = NOTIFY_DONE;
233 goto out;
234 }
235 info = counter_arch_bp(bp);
236
237 /*
238 * Return early after invoking user-callback function without restoring
239 * DABR if the breakpoint is from ptrace which always operates in
240 * one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
241 * generated in do_dabr().
242 */
243 if (bp->overflow_handler == ptrace_triggered) {
244 perf_bp_event(bp, regs);
245 rc = NOTIFY_DONE;
246 goto out;
247 }
248
249 /*
250 * Verify if dar lies within the address range occupied by the symbol
251 * being watched to filter extraneous exceptions. If it doesn't,
252 * we still need to single-step the instruction, but we don't
253 * generate an event.
254 */
255 info->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;
256 if (!((bp->attr.bp_addr <= dar) &&
257 (dar - bp->attr.bp_addr < bp->attr.bp_len)))
258 info->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
259
260 /* Do not emulate user-space instructions, instead single-step them */
261 if (user_mode(regs)) {
262 current->thread.last_hit_ubp = bp;
263 regs->msr |= MSR_SE;
264 goto out;
265 }
266
267 stepped = 0;
268 instr = 0;
269 if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
270 stepped = emulate_step(regs, instr);
271
272 /*
273 * emulate_step() could not execute it. We've failed in reliably
274 * handling the hw-breakpoint. Unregister it and throw a warning
275 * message to let the user know about it.
276 */
277 if (!stepped) {
278 WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
279 "0x%lx will be disabled.", info->address);
280 perf_event_disable(bp);
281 goto out;
282 }
283 /*
284 * As a policy, the callback is invoked in a 'trigger-after-execute'
285 * fashion
286 */
287 if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
288 perf_bp_event(bp, regs);
289
290 set_breakpoint(info);
291 out:
292 rcu_read_unlock();
293 return rc;
294 }
295
296 /*
297 * Handle single-step exceptions following a DABR hit.
298 */
299 int __kprobes single_step_dabr_instruction(struct die_args *args)
300 {
301 struct pt_regs *regs = args->regs;
302 struct perf_event *bp = NULL;
303 struct arch_hw_breakpoint *info;
304
305 bp = current->thread.last_hit_ubp;
306 /*
307 * Check if we are single-stepping as a result of a
308 * previous HW Breakpoint exception
309 */
310 if (!bp)
311 return NOTIFY_DONE;
312
313 info = counter_arch_bp(bp);
314
315 /*
316 * We shall invoke the user-defined callback function in the single
317 * stepping handler to confirm to 'trigger-after-execute' semantics
318 */
319 if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
320 perf_bp_event(bp, regs);
321
322 set_breakpoint(info);
323 current->thread.last_hit_ubp = NULL;
324
325 /*
326 * If the process was being single-stepped by ptrace, let the
327 * other single-step actions occur (e.g. generate SIGTRAP).
328 */
329 if (test_thread_flag(TIF_SINGLESTEP))
330 return NOTIFY_DONE;
331
332 return NOTIFY_STOP;
333 }
334
335 /*
336 * Handle debug exception notifications.
337 */
338 int __kprobes hw_breakpoint_exceptions_notify(
339 struct notifier_block *unused, unsigned long val, void *data)
340 {
341 int ret = NOTIFY_DONE;
342
343 switch (val) {
344 case DIE_DABR_MATCH:
345 ret = hw_breakpoint_handler(data);
346 break;
347 case DIE_SSTEP:
348 ret = single_step_dabr_instruction(data);
349 break;
350 }
351
352 return ret;
353 }
354
355 /*
356 * Release the user breakpoints used by ptrace
357 */
358 void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
359 {
360 struct thread_struct *t = &tsk->thread;
361
362 unregister_hw_breakpoint(t->ptrace_bps[0]);
363 t->ptrace_bps[0] = NULL;
364 }
365
366 void hw_breakpoint_pmu_read(struct perf_event *bp)
367 {
368 /* TODO */
369 }