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powerpc: Don't try to fix up misaligned load-with-reservation instructions
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / kernel / align.c
1 /* align.c - handle alignment exceptions for the Power PC.
2 *
3 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
4 * Copyright (c) 1998-1999 TiVo, Inc.
5 * PowerPC 403GCX modifications.
6 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
7 * PowerPC 403GCX/405GP modifications.
8 * Copyright (c) 2001-2002 PPC64 team, IBM Corp
9 * 64-bit and Power4 support
10 * Copyright (c) 2005 Benjamin Herrenschmidt, IBM Corp
11 * <benh@kernel.crashing.org>
12 * Merge ppc32 and ppc64 implementations
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
18 */
19
20 #include <linux/kernel.h>
21 #include <linux/mm.h>
22 #include <asm/processor.h>
23 #include <asm/uaccess.h>
24 #include <asm/cache.h>
25 #include <asm/cputable.h>
26 #include <asm/emulated_ops.h>
27 #include <asm/switch_to.h>
28 #include <asm/disassemble.h>
29
30 struct aligninfo {
31 unsigned char len;
32 unsigned char flags;
33 };
34
35 #define IS_XFORM(inst) (((inst) >> 26) == 31)
36 #define IS_DSFORM(inst) (((inst) >> 26) >= 56)
37
38 #define INVALID { 0, 0 }
39
40 /* Bits in the flags field */
41 #define LD 0 /* load */
42 #define ST 1 /* store */
43 #define SE 2 /* sign-extend value, or FP ld/st as word */
44 #define F 4 /* to/from fp regs */
45 #define U 8 /* update index register */
46 #define M 0x10 /* multiple load/store */
47 #define SW 0x20 /* byte swap */
48 #define S 0x40 /* single-precision fp or... */
49 #define SX 0x40 /* ... byte count in XER */
50 #define HARD 0x80 /* string, stwcx. */
51 #define E4 0x40 /* SPE endianness is word */
52 #define E8 0x80 /* SPE endianness is double word */
53 #define SPLT 0x80 /* VSX SPLAT load */
54
55 /* DSISR bits reported for a DCBZ instruction: */
56 #define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
57
58 #define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
59
60 /*
61 * The PowerPC stores certain bits of the instruction that caused the
62 * alignment exception in the DSISR register. This array maps those
63 * bits to information about the operand length and what the
64 * instruction would do.
65 */
66 static struct aligninfo aligninfo[128] = {
67 { 4, LD }, /* 00 0 0000: lwz / lwarx */
68 INVALID, /* 00 0 0001 */
69 { 4, ST }, /* 00 0 0010: stw */
70 INVALID, /* 00 0 0011 */
71 { 2, LD }, /* 00 0 0100: lhz */
72 { 2, LD+SE }, /* 00 0 0101: lha */
73 { 2, ST }, /* 00 0 0110: sth */
74 { 4, LD+M }, /* 00 0 0111: lmw */
75 { 4, LD+F+S }, /* 00 0 1000: lfs */
76 { 8, LD+F }, /* 00 0 1001: lfd */
77 { 4, ST+F+S }, /* 00 0 1010: stfs */
78 { 8, ST+F }, /* 00 0 1011: stfd */
79 INVALID, /* 00 0 1100 */
80 { 8, LD }, /* 00 0 1101: ld/ldu/lwa */
81 INVALID, /* 00 0 1110 */
82 { 8, ST }, /* 00 0 1111: std/stdu */
83 { 4, LD+U }, /* 00 1 0000: lwzu */
84 INVALID, /* 00 1 0001 */
85 { 4, ST+U }, /* 00 1 0010: stwu */
86 INVALID, /* 00 1 0011 */
87 { 2, LD+U }, /* 00 1 0100: lhzu */
88 { 2, LD+SE+U }, /* 00 1 0101: lhau */
89 { 2, ST+U }, /* 00 1 0110: sthu */
90 { 4, ST+M }, /* 00 1 0111: stmw */
91 { 4, LD+F+S+U }, /* 00 1 1000: lfsu */
92 { 8, LD+F+U }, /* 00 1 1001: lfdu */
93 { 4, ST+F+S+U }, /* 00 1 1010: stfsu */
94 { 8, ST+F+U }, /* 00 1 1011: stfdu */
95 { 16, LD+F }, /* 00 1 1100: lfdp */
96 INVALID, /* 00 1 1101 */
97 { 16, ST+F }, /* 00 1 1110: stfdp */
98 INVALID, /* 00 1 1111 */
99 { 8, LD }, /* 01 0 0000: ldx */
100 INVALID, /* 01 0 0001 */
101 { 8, ST }, /* 01 0 0010: stdx */
102 INVALID, /* 01 0 0011 */
103 INVALID, /* 01 0 0100 */
104 { 4, LD+SE }, /* 01 0 0101: lwax */
105 INVALID, /* 01 0 0110 */
106 INVALID, /* 01 0 0111 */
107 { 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
108 { 4, LD+M+HARD }, /* 01 0 1001: lswi */
109 { 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
110 { 4, ST+M+HARD }, /* 01 0 1011: stswi */
111 INVALID, /* 01 0 1100 */
112 { 8, LD+U }, /* 01 0 1101: ldu */
113 INVALID, /* 01 0 1110 */
114 { 8, ST+U }, /* 01 0 1111: stdu */
115 { 8, LD+U }, /* 01 1 0000: ldux */
116 INVALID, /* 01 1 0001 */
117 { 8, ST+U }, /* 01 1 0010: stdux */
118 INVALID, /* 01 1 0011 */
119 INVALID, /* 01 1 0100 */
120 { 4, LD+SE+U }, /* 01 1 0101: lwaux */
121 INVALID, /* 01 1 0110 */
122 INVALID, /* 01 1 0111 */
123 INVALID, /* 01 1 1000 */
124 INVALID, /* 01 1 1001 */
125 INVALID, /* 01 1 1010 */
126 INVALID, /* 01 1 1011 */
127 INVALID, /* 01 1 1100 */
128 INVALID, /* 01 1 1101 */
129 INVALID, /* 01 1 1110 */
130 INVALID, /* 01 1 1111 */
131 INVALID, /* 10 0 0000 */
132 INVALID, /* 10 0 0001 */
133 INVALID, /* 10 0 0010: stwcx. */
134 INVALID, /* 10 0 0011 */
135 INVALID, /* 10 0 0100 */
136 INVALID, /* 10 0 0101 */
137 INVALID, /* 10 0 0110 */
138 INVALID, /* 10 0 0111 */
139 { 4, LD+SW }, /* 10 0 1000: lwbrx */
140 INVALID, /* 10 0 1001 */
141 { 4, ST+SW }, /* 10 0 1010: stwbrx */
142 INVALID, /* 10 0 1011 */
143 { 2, LD+SW }, /* 10 0 1100: lhbrx */
144 { 4, LD+SE }, /* 10 0 1101 lwa */
145 { 2, ST+SW }, /* 10 0 1110: sthbrx */
146 INVALID, /* 10 0 1111 */
147 INVALID, /* 10 1 0000 */
148 INVALID, /* 10 1 0001 */
149 INVALID, /* 10 1 0010 */
150 INVALID, /* 10 1 0011 */
151 INVALID, /* 10 1 0100 */
152 INVALID, /* 10 1 0101 */
153 INVALID, /* 10 1 0110 */
154 INVALID, /* 10 1 0111 */
155 INVALID, /* 10 1 1000 */
156 INVALID, /* 10 1 1001 */
157 INVALID, /* 10 1 1010 */
158 INVALID, /* 10 1 1011 */
159 INVALID, /* 10 1 1100 */
160 INVALID, /* 10 1 1101 */
161 INVALID, /* 10 1 1110 */
162 { 0, ST+HARD }, /* 10 1 1111: dcbz */
163 { 4, LD }, /* 11 0 0000: lwzx */
164 INVALID, /* 11 0 0001 */
165 { 4, ST }, /* 11 0 0010: stwx */
166 INVALID, /* 11 0 0011 */
167 { 2, LD }, /* 11 0 0100: lhzx */
168 { 2, LD+SE }, /* 11 0 0101: lhax */
169 { 2, ST }, /* 11 0 0110: sthx */
170 INVALID, /* 11 0 0111 */
171 { 4, LD+F+S }, /* 11 0 1000: lfsx */
172 { 8, LD+F }, /* 11 0 1001: lfdx */
173 { 4, ST+F+S }, /* 11 0 1010: stfsx */
174 { 8, ST+F }, /* 11 0 1011: stfdx */
175 { 16, LD+F }, /* 11 0 1100: lfdpx */
176 { 4, LD+F+SE }, /* 11 0 1101: lfiwax */
177 { 16, ST+F }, /* 11 0 1110: stfdpx */
178 { 4, ST+F }, /* 11 0 1111: stfiwx */
179 { 4, LD+U }, /* 11 1 0000: lwzux */
180 INVALID, /* 11 1 0001 */
181 { 4, ST+U }, /* 11 1 0010: stwux */
182 INVALID, /* 11 1 0011 */
183 { 2, LD+U }, /* 11 1 0100: lhzux */
184 { 2, LD+SE+U }, /* 11 1 0101: lhaux */
185 { 2, ST+U }, /* 11 1 0110: sthux */
186 INVALID, /* 11 1 0111 */
187 { 4, LD+F+S+U }, /* 11 1 1000: lfsux */
188 { 8, LD+F+U }, /* 11 1 1001: lfdux */
189 { 4, ST+F+S+U }, /* 11 1 1010: stfsux */
190 { 8, ST+F+U }, /* 11 1 1011: stfdux */
191 INVALID, /* 11 1 1100 */
192 { 4, LD+F }, /* 11 1 1101: lfiwzx */
193 INVALID, /* 11 1 1110 */
194 INVALID, /* 11 1 1111 */
195 };
196
197 /*
198 * Create a DSISR value from the instruction
199 */
200 static inline unsigned make_dsisr(unsigned instr)
201 {
202 unsigned dsisr;
203
204
205 /* bits 6:15 --> 22:31 */
206 dsisr = (instr & 0x03ff0000) >> 16;
207
208 if (IS_XFORM(instr)) {
209 /* bits 29:30 --> 15:16 */
210 dsisr |= (instr & 0x00000006) << 14;
211 /* bit 25 --> 17 */
212 dsisr |= (instr & 0x00000040) << 8;
213 /* bits 21:24 --> 18:21 */
214 dsisr |= (instr & 0x00000780) << 3;
215 } else {
216 /* bit 5 --> 17 */
217 dsisr |= (instr & 0x04000000) >> 12;
218 /* bits 1: 4 --> 18:21 */
219 dsisr |= (instr & 0x78000000) >> 17;
220 /* bits 30:31 --> 12:13 */
221 if (IS_DSFORM(instr))
222 dsisr |= (instr & 0x00000003) << 18;
223 }
224
225 return dsisr;
226 }
227
228 /*
229 * The dcbz (data cache block zero) instruction
230 * gives an alignment fault if used on non-cacheable
231 * memory. We handle the fault mainly for the
232 * case when we are running with the cache disabled
233 * for debugging.
234 */
235 static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr)
236 {
237 long __user *p;
238 int i, size;
239
240 #ifdef __powerpc64__
241 size = ppc64_caches.dline_size;
242 #else
243 size = L1_CACHE_BYTES;
244 #endif
245 p = (long __user *) (regs->dar & -size);
246 if (user_mode(regs) && !access_ok(VERIFY_WRITE, p, size))
247 return -EFAULT;
248 for (i = 0; i < size / sizeof(long); ++i)
249 if (__put_user_inatomic(0, p+i))
250 return -EFAULT;
251 return 1;
252 }
253
254 /*
255 * Emulate load & store multiple instructions
256 * On 64-bit machines, these instructions only affect/use the
257 * bottom 4 bytes of each register, and the loads clear the
258 * top 4 bytes of the affected register.
259 */
260 #ifdef CONFIG_PPC64
261 #define REG_BYTE(rp, i) *((u8 *)((rp) + ((i) >> 2)) + ((i) & 3) + 4)
262 #else
263 #define REG_BYTE(rp, i) *((u8 *)(rp) + (i))
264 #endif
265
266 #define SWIZ_PTR(p) ((unsigned char __user *)((p) ^ swiz))
267
268 static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
269 unsigned int reg, unsigned int nb,
270 unsigned int flags, unsigned int instr,
271 unsigned long swiz)
272 {
273 unsigned long *rptr;
274 unsigned int nb0, i, bswiz;
275 unsigned long p;
276
277 /*
278 * We do not try to emulate 8 bytes multiple as they aren't really
279 * available in our operating environments and we don't try to
280 * emulate multiples operations in kernel land as they should never
281 * be used/generated there at least not on unaligned boundaries
282 */
283 if (unlikely((nb > 4) || !user_mode(regs)))
284 return 0;
285
286 /* lmw, stmw, lswi/x, stswi/x */
287 nb0 = 0;
288 if (flags & HARD) {
289 if (flags & SX) {
290 nb = regs->xer & 127;
291 if (nb == 0)
292 return 1;
293 } else {
294 unsigned long pc = regs->nip ^ (swiz & 4);
295
296 if (__get_user_inatomic(instr,
297 (unsigned int __user *)pc))
298 return -EFAULT;
299 if (swiz == 0 && (flags & SW))
300 instr = cpu_to_le32(instr);
301 nb = (instr >> 11) & 0x1f;
302 if (nb == 0)
303 nb = 32;
304 }
305 if (nb + reg * 4 > 128) {
306 nb0 = nb + reg * 4 - 128;
307 nb = 128 - reg * 4;
308 }
309 } else {
310 /* lwm, stmw */
311 nb = (32 - reg) * 4;
312 }
313
314 if (!access_ok((flags & ST ? VERIFY_WRITE: VERIFY_READ), addr, nb+nb0))
315 return -EFAULT; /* bad address */
316
317 rptr = &regs->gpr[reg];
318 p = (unsigned long) addr;
319 bswiz = (flags & SW)? 3: 0;
320
321 if (!(flags & ST)) {
322 /*
323 * This zeroes the top 4 bytes of the affected registers
324 * in 64-bit mode, and also zeroes out any remaining
325 * bytes of the last register for lsw*.
326 */
327 memset(rptr, 0, ((nb + 3) / 4) * sizeof(unsigned long));
328 if (nb0 > 0)
329 memset(&regs->gpr[0], 0,
330 ((nb0 + 3) / 4) * sizeof(unsigned long));
331
332 for (i = 0; i < nb; ++i, ++p)
333 if (__get_user_inatomic(REG_BYTE(rptr, i ^ bswiz),
334 SWIZ_PTR(p)))
335 return -EFAULT;
336 if (nb0 > 0) {
337 rptr = &regs->gpr[0];
338 addr += nb;
339 for (i = 0; i < nb0; ++i, ++p)
340 if (__get_user_inatomic(REG_BYTE(rptr,
341 i ^ bswiz),
342 SWIZ_PTR(p)))
343 return -EFAULT;
344 }
345
346 } else {
347 for (i = 0; i < nb; ++i, ++p)
348 if (__put_user_inatomic(REG_BYTE(rptr, i ^ bswiz),
349 SWIZ_PTR(p)))
350 return -EFAULT;
351 if (nb0 > 0) {
352 rptr = &regs->gpr[0];
353 addr += nb;
354 for (i = 0; i < nb0; ++i, ++p)
355 if (__put_user_inatomic(REG_BYTE(rptr,
356 i ^ bswiz),
357 SWIZ_PTR(p)))
358 return -EFAULT;
359 }
360 }
361 return 1;
362 }
363
364 /*
365 * Emulate floating-point pair loads and stores.
366 * Only POWER6 has these instructions, and it does true little-endian,
367 * so we don't need the address swizzling.
368 */
369 static int emulate_fp_pair(unsigned char __user *addr, unsigned int reg,
370 unsigned int flags)
371 {
372 char *ptr0 = (char *) &current->thread.TS_FPR(reg);
373 char *ptr1 = (char *) &current->thread.TS_FPR(reg+1);
374 int i, ret, sw = 0;
375
376 if (!(flags & F))
377 return 0;
378 if (reg & 1)
379 return 0; /* invalid form: FRS/FRT must be even */
380 if (flags & SW)
381 sw = 7;
382 ret = 0;
383 for (i = 0; i < 8; ++i) {
384 if (!(flags & ST)) {
385 ret |= __get_user(ptr0[i^sw], addr + i);
386 ret |= __get_user(ptr1[i^sw], addr + i + 8);
387 } else {
388 ret |= __put_user(ptr0[i^sw], addr + i);
389 ret |= __put_user(ptr1[i^sw], addr + i + 8);
390 }
391 }
392 if (ret)
393 return -EFAULT;
394 return 1; /* exception handled and fixed up */
395 }
396
397 #ifdef CONFIG_SPE
398
399 static struct aligninfo spe_aligninfo[32] = {
400 { 8, LD+E8 }, /* 0 00 00: evldd[x] */
401 { 8, LD+E4 }, /* 0 00 01: evldw[x] */
402 { 8, LD }, /* 0 00 10: evldh[x] */
403 INVALID, /* 0 00 11 */
404 { 2, LD }, /* 0 01 00: evlhhesplat[x] */
405 INVALID, /* 0 01 01 */
406 { 2, LD }, /* 0 01 10: evlhhousplat[x] */
407 { 2, LD+SE }, /* 0 01 11: evlhhossplat[x] */
408 { 4, LD }, /* 0 10 00: evlwhe[x] */
409 INVALID, /* 0 10 01 */
410 { 4, LD }, /* 0 10 10: evlwhou[x] */
411 { 4, LD+SE }, /* 0 10 11: evlwhos[x] */
412 { 4, LD+E4 }, /* 0 11 00: evlwwsplat[x] */
413 INVALID, /* 0 11 01 */
414 { 4, LD }, /* 0 11 10: evlwhsplat[x] */
415 INVALID, /* 0 11 11 */
416
417 { 8, ST+E8 }, /* 1 00 00: evstdd[x] */
418 { 8, ST+E4 }, /* 1 00 01: evstdw[x] */
419 { 8, ST }, /* 1 00 10: evstdh[x] */
420 INVALID, /* 1 00 11 */
421 INVALID, /* 1 01 00 */
422 INVALID, /* 1 01 01 */
423 INVALID, /* 1 01 10 */
424 INVALID, /* 1 01 11 */
425 { 4, ST }, /* 1 10 00: evstwhe[x] */
426 INVALID, /* 1 10 01 */
427 { 4, ST }, /* 1 10 10: evstwho[x] */
428 INVALID, /* 1 10 11 */
429 { 4, ST+E4 }, /* 1 11 00: evstwwe[x] */
430 INVALID, /* 1 11 01 */
431 { 4, ST+E4 }, /* 1 11 10: evstwwo[x] */
432 INVALID, /* 1 11 11 */
433 };
434
435 #define EVLDD 0x00
436 #define EVLDW 0x01
437 #define EVLDH 0x02
438 #define EVLHHESPLAT 0x04
439 #define EVLHHOUSPLAT 0x06
440 #define EVLHHOSSPLAT 0x07
441 #define EVLWHE 0x08
442 #define EVLWHOU 0x0A
443 #define EVLWHOS 0x0B
444 #define EVLWWSPLAT 0x0C
445 #define EVLWHSPLAT 0x0E
446 #define EVSTDD 0x10
447 #define EVSTDW 0x11
448 #define EVSTDH 0x12
449 #define EVSTWHE 0x18
450 #define EVSTWHO 0x1A
451 #define EVSTWWE 0x1C
452 #define EVSTWWO 0x1E
453
454 /*
455 * Emulate SPE loads and stores.
456 * Only Book-E has these instructions, and it does true little-endian,
457 * so we don't need the address swizzling.
458 */
459 static int emulate_spe(struct pt_regs *regs, unsigned int reg,
460 unsigned int instr)
461 {
462 int t, ret;
463 union {
464 u64 ll;
465 u32 w[2];
466 u16 h[4];
467 u8 v[8];
468 } data, temp;
469 unsigned char __user *p, *addr;
470 unsigned long *evr = &current->thread.evr[reg];
471 unsigned int nb, flags;
472
473 instr = (instr >> 1) & 0x1f;
474
475 /* DAR has the operand effective address */
476 addr = (unsigned char __user *)regs->dar;
477
478 nb = spe_aligninfo[instr].len;
479 flags = spe_aligninfo[instr].flags;
480
481 /* Verify the address of the operand */
482 if (unlikely(user_mode(regs) &&
483 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
484 addr, nb)))
485 return -EFAULT;
486
487 /* userland only */
488 if (unlikely(!user_mode(regs)))
489 return 0;
490
491 flush_spe_to_thread(current);
492
493 /* If we are loading, get the data from user space, else
494 * get it from register values
495 */
496 if (flags & ST) {
497 data.ll = 0;
498 switch (instr) {
499 case EVSTDD:
500 case EVSTDW:
501 case EVSTDH:
502 data.w[0] = *evr;
503 data.w[1] = regs->gpr[reg];
504 break;
505 case EVSTWHE:
506 data.h[2] = *evr >> 16;
507 data.h[3] = regs->gpr[reg] >> 16;
508 break;
509 case EVSTWHO:
510 data.h[2] = *evr & 0xffff;
511 data.h[3] = regs->gpr[reg] & 0xffff;
512 break;
513 case EVSTWWE:
514 data.w[1] = *evr;
515 break;
516 case EVSTWWO:
517 data.w[1] = regs->gpr[reg];
518 break;
519 default:
520 return -EINVAL;
521 }
522 } else {
523 temp.ll = data.ll = 0;
524 ret = 0;
525 p = addr;
526
527 switch (nb) {
528 case 8:
529 ret |= __get_user_inatomic(temp.v[0], p++);
530 ret |= __get_user_inatomic(temp.v[1], p++);
531 ret |= __get_user_inatomic(temp.v[2], p++);
532 ret |= __get_user_inatomic(temp.v[3], p++);
533 case 4:
534 ret |= __get_user_inatomic(temp.v[4], p++);
535 ret |= __get_user_inatomic(temp.v[5], p++);
536 case 2:
537 ret |= __get_user_inatomic(temp.v[6], p++);
538 ret |= __get_user_inatomic(temp.v[7], p++);
539 if (unlikely(ret))
540 return -EFAULT;
541 }
542
543 switch (instr) {
544 case EVLDD:
545 case EVLDW:
546 case EVLDH:
547 data.ll = temp.ll;
548 break;
549 case EVLHHESPLAT:
550 data.h[0] = temp.h[3];
551 data.h[2] = temp.h[3];
552 break;
553 case EVLHHOUSPLAT:
554 case EVLHHOSSPLAT:
555 data.h[1] = temp.h[3];
556 data.h[3] = temp.h[3];
557 break;
558 case EVLWHE:
559 data.h[0] = temp.h[2];
560 data.h[2] = temp.h[3];
561 break;
562 case EVLWHOU:
563 case EVLWHOS:
564 data.h[1] = temp.h[2];
565 data.h[3] = temp.h[3];
566 break;
567 case EVLWWSPLAT:
568 data.w[0] = temp.w[1];
569 data.w[1] = temp.w[1];
570 break;
571 case EVLWHSPLAT:
572 data.h[0] = temp.h[2];
573 data.h[1] = temp.h[2];
574 data.h[2] = temp.h[3];
575 data.h[3] = temp.h[3];
576 break;
577 default:
578 return -EINVAL;
579 }
580 }
581
582 if (flags & SW) {
583 switch (flags & 0xf0) {
584 case E8:
585 SWAP(data.v[0], data.v[7]);
586 SWAP(data.v[1], data.v[6]);
587 SWAP(data.v[2], data.v[5]);
588 SWAP(data.v[3], data.v[4]);
589 break;
590 case E4:
591
592 SWAP(data.v[0], data.v[3]);
593 SWAP(data.v[1], data.v[2]);
594 SWAP(data.v[4], data.v[7]);
595 SWAP(data.v[5], data.v[6]);
596 break;
597 /* Its half word endian */
598 default:
599 SWAP(data.v[0], data.v[1]);
600 SWAP(data.v[2], data.v[3]);
601 SWAP(data.v[4], data.v[5]);
602 SWAP(data.v[6], data.v[7]);
603 break;
604 }
605 }
606
607 if (flags & SE) {
608 data.w[0] = (s16)data.h[1];
609 data.w[1] = (s16)data.h[3];
610 }
611
612 /* Store result to memory or update registers */
613 if (flags & ST) {
614 ret = 0;
615 p = addr;
616 switch (nb) {
617 case 8:
618 ret |= __put_user_inatomic(data.v[0], p++);
619 ret |= __put_user_inatomic(data.v[1], p++);
620 ret |= __put_user_inatomic(data.v[2], p++);
621 ret |= __put_user_inatomic(data.v[3], p++);
622 case 4:
623 ret |= __put_user_inatomic(data.v[4], p++);
624 ret |= __put_user_inatomic(data.v[5], p++);
625 case 2:
626 ret |= __put_user_inatomic(data.v[6], p++);
627 ret |= __put_user_inatomic(data.v[7], p++);
628 }
629 if (unlikely(ret))
630 return -EFAULT;
631 } else {
632 *evr = data.w[0];
633 regs->gpr[reg] = data.w[1];
634 }
635
636 return 1;
637 }
638 #endif /* CONFIG_SPE */
639
640 #ifdef CONFIG_VSX
641 /*
642 * Emulate VSX instructions...
643 */
644 static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
645 unsigned int areg, struct pt_regs *regs,
646 unsigned int flags, unsigned int length,
647 unsigned int elsize)
648 {
649 char *ptr;
650 unsigned long *lptr;
651 int ret = 0;
652 int sw = 0;
653 int i, j;
654
655 flush_vsx_to_thread(current);
656
657 if (reg < 32)
658 ptr = (char *) &current->thread.TS_FPR(reg);
659 else
660 ptr = (char *) &current->thread.vr[reg - 32];
661
662 lptr = (unsigned long *) ptr;
663
664 if (flags & SW)
665 sw = elsize-1;
666
667 for (j = 0; j < length; j += elsize) {
668 for (i = 0; i < elsize; ++i) {
669 if (flags & ST)
670 ret |= __put_user(ptr[i^sw], addr + i);
671 else
672 ret |= __get_user(ptr[i^sw], addr + i);
673 }
674 ptr += elsize;
675 addr += elsize;
676 }
677
678 if (!ret) {
679 if (flags & U)
680 regs->gpr[areg] = regs->dar;
681
682 /* Splat load copies the same data to top and bottom 8 bytes */
683 if (flags & SPLT)
684 lptr[1] = lptr[0];
685 /* For 8 byte loads, zero the top 8 bytes */
686 else if (!(flags & ST) && (8 == length))
687 lptr[1] = 0;
688 } else
689 return -EFAULT;
690
691 return 1;
692 }
693 #endif
694
695 /*
696 * Called on alignment exception. Attempts to fixup
697 *
698 * Return 1 on success
699 * Return 0 if unable to handle the interrupt
700 * Return -EFAULT if data address is bad
701 */
702
703 int fix_alignment(struct pt_regs *regs)
704 {
705 unsigned int instr, nb, flags, instruction = 0;
706 unsigned int reg, areg;
707 unsigned int dsisr;
708 unsigned char __user *addr;
709 unsigned long p, swiz;
710 int ret, t;
711 union {
712 u64 ll;
713 double dd;
714 unsigned char v[8];
715 struct {
716 unsigned hi32;
717 int low32;
718 } x32;
719 struct {
720 unsigned char hi48[6];
721 short low16;
722 } x16;
723 } data;
724
725 /*
726 * We require a complete register set, if not, then our assembly
727 * is broken
728 */
729 CHECK_FULL_REGS(regs);
730
731 dsisr = regs->dsisr;
732
733 /* Some processors don't provide us with a DSISR we can use here,
734 * let's make one up from the instruction
735 */
736 if (cpu_has_feature(CPU_FTR_NODSISRALIGN)) {
737 unsigned long pc = regs->nip;
738
739 if (cpu_has_feature(CPU_FTR_PPC_LE) && (regs->msr & MSR_LE))
740 pc ^= 4;
741 if (unlikely(__get_user_inatomic(instr,
742 (unsigned int __user *)pc)))
743 return -EFAULT;
744 if (cpu_has_feature(CPU_FTR_REAL_LE) && (regs->msr & MSR_LE))
745 instr = cpu_to_le32(instr);
746 dsisr = make_dsisr(instr);
747 instruction = instr;
748 }
749
750 /* extract the operation and registers from the dsisr */
751 reg = (dsisr >> 5) & 0x1f; /* source/dest register */
752 areg = dsisr & 0x1f; /* register to update */
753
754 #ifdef CONFIG_SPE
755 if ((instr >> 26) == 0x4) {
756 PPC_WARN_ALIGNMENT(spe, regs);
757 return emulate_spe(regs, reg, instr);
758 }
759 #endif
760
761 instr = (dsisr >> 10) & 0x7f;
762 instr |= (dsisr >> 13) & 0x60;
763
764 /* Lookup the operation in our table */
765 nb = aligninfo[instr].len;
766 flags = aligninfo[instr].flags;
767
768 /*
769 * Handle some cases which give overlaps in the DSISR values.
770 */
771 if (IS_XFORM(instruction)) {
772 switch (get_xop(instruction)) {
773 case 532: /* ldbrx */
774 nb = 8;
775 flags = LD+SW;
776 break;
777 case 660: /* stdbrx */
778 nb = 8;
779 flags = ST+SW;
780 break;
781 case 20: /* lwarx */
782 case 84: /* ldarx */
783 case 116: /* lharx */
784 case 276: /* lqarx */
785 return 0; /* not emulated ever */
786 }
787 }
788
789 /* Byteswap little endian loads and stores */
790 swiz = 0;
791 if (regs->msr & MSR_LE) {
792 flags ^= SW;
793 /*
794 * So-called "PowerPC little endian" mode works by
795 * swizzling addresses rather than by actually doing
796 * any byte-swapping. To emulate this, we XOR each
797 * byte address with 7. We also byte-swap, because
798 * the processor's address swizzling depends on the
799 * operand size (it xors the address with 7 for bytes,
800 * 6 for halfwords, 4 for words, 0 for doublewords) but
801 * we will xor with 7 and load/store each byte separately.
802 */
803 if (cpu_has_feature(CPU_FTR_PPC_LE))
804 swiz = 7;
805 }
806
807 /* DAR has the operand effective address */
808 addr = (unsigned char __user *)regs->dar;
809
810 #ifdef CONFIG_VSX
811 if ((instruction & 0xfc00003e) == 0x7c000018) {
812 unsigned int elsize;
813
814 /* Additional register addressing bit (64 VSX vs 32 FPR/GPR) */
815 reg |= (instruction & 0x1) << 5;
816 /* Simple inline decoder instead of a table */
817 /* VSX has only 8 and 16 byte memory accesses */
818 nb = 8;
819 if (instruction & 0x200)
820 nb = 16;
821
822 /* Vector stores in little-endian mode swap individual
823 elements, so process them separately */
824 elsize = 4;
825 if (instruction & 0x80)
826 elsize = 8;
827
828 flags = 0;
829 if (regs->msr & MSR_LE)
830 flags |= SW;
831 if (instruction & 0x100)
832 flags |= ST;
833 if (instruction & 0x040)
834 flags |= U;
835 /* splat load needs a special decoder */
836 if ((instruction & 0x400) == 0){
837 flags |= SPLT;
838 nb = 8;
839 }
840 PPC_WARN_ALIGNMENT(vsx, regs);
841 return emulate_vsx(addr, reg, areg, regs, flags, nb, elsize);
842 }
843 #endif
844 /* A size of 0 indicates an instruction we don't support, with
845 * the exception of DCBZ which is handled as a special case here
846 */
847 if (instr == DCBZ) {
848 PPC_WARN_ALIGNMENT(dcbz, regs);
849 return emulate_dcbz(regs, addr);
850 }
851 if (unlikely(nb == 0))
852 return 0;
853
854 /* Load/Store Multiple instructions are handled in their own
855 * function
856 */
857 if (flags & M) {
858 PPC_WARN_ALIGNMENT(multiple, regs);
859 return emulate_multiple(regs, addr, reg, nb,
860 flags, instr, swiz);
861 }
862
863 /* Verify the address of the operand */
864 if (unlikely(user_mode(regs) &&
865 !access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
866 addr, nb)))
867 return -EFAULT;
868
869 /* Force the fprs into the save area so we can reference them */
870 if (flags & F) {
871 /* userland only */
872 if (unlikely(!user_mode(regs)))
873 return 0;
874 flush_fp_to_thread(current);
875 }
876
877 /* Special case for 16-byte FP loads and stores */
878 if (nb == 16) {
879 PPC_WARN_ALIGNMENT(fp_pair, regs);
880 return emulate_fp_pair(addr, reg, flags);
881 }
882
883 PPC_WARN_ALIGNMENT(unaligned, regs);
884
885 /* If we are loading, get the data from user space, else
886 * get it from register values
887 */
888 if (!(flags & ST)) {
889 data.ll = 0;
890 ret = 0;
891 p = (unsigned long) addr;
892 switch (nb) {
893 case 8:
894 ret |= __get_user_inatomic(data.v[0], SWIZ_PTR(p++));
895 ret |= __get_user_inatomic(data.v[1], SWIZ_PTR(p++));
896 ret |= __get_user_inatomic(data.v[2], SWIZ_PTR(p++));
897 ret |= __get_user_inatomic(data.v[3], SWIZ_PTR(p++));
898 case 4:
899 ret |= __get_user_inatomic(data.v[4], SWIZ_PTR(p++));
900 ret |= __get_user_inatomic(data.v[5], SWIZ_PTR(p++));
901 case 2:
902 ret |= __get_user_inatomic(data.v[6], SWIZ_PTR(p++));
903 ret |= __get_user_inatomic(data.v[7], SWIZ_PTR(p++));
904 if (unlikely(ret))
905 return -EFAULT;
906 }
907 } else if (flags & F) {
908 data.dd = current->thread.TS_FPR(reg);
909 if (flags & S) {
910 /* Single-precision FP store requires conversion... */
911 #ifdef CONFIG_PPC_FPU
912 preempt_disable();
913 enable_kernel_fp();
914 cvt_df(&data.dd, (float *)&data.v[4]);
915 preempt_enable();
916 #else
917 return 0;
918 #endif
919 }
920 } else
921 data.ll = regs->gpr[reg];
922
923 if (flags & SW) {
924 switch (nb) {
925 case 8:
926 SWAP(data.v[0], data.v[7]);
927 SWAP(data.v[1], data.v[6]);
928 SWAP(data.v[2], data.v[5]);
929 SWAP(data.v[3], data.v[4]);
930 break;
931 case 4:
932 SWAP(data.v[4], data.v[7]);
933 SWAP(data.v[5], data.v[6]);
934 break;
935 case 2:
936 SWAP(data.v[6], data.v[7]);
937 break;
938 }
939 }
940
941 /* Perform other misc operations like sign extension
942 * or floating point single precision conversion
943 */
944 switch (flags & ~(U|SW)) {
945 case LD+SE: /* sign extending integer loads */
946 case LD+F+SE: /* sign extend for lfiwax */
947 if ( nb == 2 )
948 data.ll = data.x16.low16;
949 else /* nb must be 4 */
950 data.ll = data.x32.low32;
951 break;
952
953 /* Single-precision FP load requires conversion... */
954 case LD+F+S:
955 #ifdef CONFIG_PPC_FPU
956 preempt_disable();
957 enable_kernel_fp();
958 cvt_fd((float *)&data.v[4], &data.dd);
959 preempt_enable();
960 #else
961 return 0;
962 #endif
963 break;
964 }
965
966 /* Store result to memory or update registers */
967 if (flags & ST) {
968 ret = 0;
969 p = (unsigned long) addr;
970 switch (nb) {
971 case 8:
972 ret |= __put_user_inatomic(data.v[0], SWIZ_PTR(p++));
973 ret |= __put_user_inatomic(data.v[1], SWIZ_PTR(p++));
974 ret |= __put_user_inatomic(data.v[2], SWIZ_PTR(p++));
975 ret |= __put_user_inatomic(data.v[3], SWIZ_PTR(p++));
976 case 4:
977 ret |= __put_user_inatomic(data.v[4], SWIZ_PTR(p++));
978 ret |= __put_user_inatomic(data.v[5], SWIZ_PTR(p++));
979 case 2:
980 ret |= __put_user_inatomic(data.v[6], SWIZ_PTR(p++));
981 ret |= __put_user_inatomic(data.v[7], SWIZ_PTR(p++));
982 }
983 if (unlikely(ret))
984 return -EFAULT;
985 } else if (flags & F)
986 current->thread.TS_FPR(reg) = data.dd;
987 else
988 regs->gpr[reg] = data.ll;
989
990 /* Update RA as needed */
991 if (flags & U)
992 regs->gpr[areg] = regs->dar;
993
994 return 1;
995 }
kernel source for telekom puls (alcatel/mediatek)