arch/mips/sibyte/sb1250/irq_handler.S

   1 /*
   2  * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 /*
  20  * sb1250_handle_int() is the routine that is actually called when an interrupt
  21  * occurs.  It is installed as the exception vector handler in arch_init_irq()
  22  * in arch/mips/sibyte/sb1250/irq.c
  23  *
  24  * In the handle we figure out which interrupts need handling, and use that to
  25  * call the dispatcher, which will take care of actually calling registered
  26  * handlers
  27  *
  28  * Note that we take care of all raised interrupts in one go at the handler.
  29  * This is more BSDish than the Indy code, and also, IMHO, more sane.
  30  */
  31 #include <linux/config.h>
  32
  33 #include <asm/addrspace.h>
  34 #include <asm/asm.h>
  35 #include <asm/mipsregs.h>
  36 #include <asm/regdef.h>
  37 #include <asm/stackframe.h>
  38 #include <asm/sibyte/sb1250_defs.h>
  39 #include <asm/sibyte/sb1250_regs.h>
  40 #include <asm/sibyte/sb1250_int.h>
  41
  42 /*
  43  * What a pain. We have to be really careful saving the upper 32 bits of any
  44  * register across function calls if we don't want them trashed--since were
  45  * running in -o32, the calling routing never saves the full 64 bits of a
  46  * register across a function call.  Being the interrupt handler, we're
  47  * guaranteed that interrupts are disabled during this code so we don't have
  48  * to worry about random interrupts blasting the high 32 bits.
  49  */
  50
  51         .text
  52         .set    push
  53         .set    noreorder
  54         .set    noat
  55         .set    mips64
  56         .align  5
  57         NESTED(sb1250_irq_handler, PT_SIZE, sp)
  58         SAVE_ALL
  59         CLI
  60
  61 #ifdef CONFIG_SIBYTE_SB1250_PROF
  62         /* Set compare to count to silence count/compare timer interrupts */
  63         mfc0    t1, CP0_COUNT
  64         mtc0    t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */
  65 #endif
  66         /* Read cause */
  67         mfc0    s0, CP0_CAUSE
  68
  69 #ifdef CONFIG_SIBYTE_SB1250_PROF
  70         /* Cpu performance counter interrupt is routed to IP[7] */
  71         andi    t1, s0, CAUSEF_IP7
  72         beqz    t1, 0f
  73          srl    t1, s0, (CAUSEB_BD-2)  /* Shift BD bit to bit 2 */
  74         and     t1, t1, 0x4             /* mask to get just BD bit */
  75         mfc0    a0, CP0_EPC
  76         jal     sbprof_cpu_intr
  77          addu   a0, a0, t1              /* a0 = EPC + (BD ? 4 : 0) */
  78         j       ret_from_irq
  79          nop
  80 0:
  81 #endif
  82
  83         /* Timer interrupt is routed to IP[4] */
  84         andi    t1, s0, CAUSEF_IP4
  85         beqz    t1, 1f
  86          nop
  87         jal     sb1250_timer_interrupt
  88          move   a0, sp                  /* Pass the registers along */
  89         j       ret_from_irq
  90          nop                            # delay slot
  91 1:
  92
  93 #ifdef CONFIG_SMP
  94         /* Mailbox interrupt is routed to IP[3] */
  95         andi     t1, s0, CAUSEF_IP3
  96         beqz     t1, 2f
  97          nop
  98         jal      sb1250_mailbox_interrupt
  99          move    a0, sp
 100         j       ret_from_irq
 101          nop                            # delay slot
 102 2:
 103 #endif
 104
 105 #ifdef CONFIG_KGDB
 106         /* KGDB (uart 1) interrupt is routed to IP[6] */
 107         andi    t1, s0, CAUSEF_IP6
 108         beqz    t1, 1f
 109         nop                            # delay slot
 110         jal     sb1250_kgdb_interrupt
 111          move   a0, sp
 112         j       ret_from_irq
 113         nop                            # delay slot
 114 1:
 115 #endif
 116
 117         and      t1, s0, CAUSEF_IP2
 118         beqz     t1, 4f
 119          nop
 120
 121         /*
 122          * Default...we've hit an IP[2] interrupt, which means we've got to
 123          * check the 1250 interrupt registers to figure out what to do
 124          * Need to detect which CPU we're on, now that smp_affinity is supported.
 125          */
 126         PTR_LA  v0, CKSEG1 + A_IMR_CPU0_BASE
 127 #ifdef CONFIG_SMP
 128         lw      t1, TI_CPU($28)
 129         sll     t1, IMR_REGISTER_SPACING_SHIFT
 130         addu    v0, t1
 131 #endif
 132         ld      s0, R_IMR_INTERRUPT_STATUS_BASE(v0)     /* read IP[2] status */
 133
 134         beqz    s0, 4f          /* No interrupts.  Return */
 135          move   a1, sp
 136
 137 3:      dclz    s1, s0          /* Find the next interrupt */
 138         dsubu   a0, zero, s1
 139         daddiu  a0, a0, 63
 140         jal      do_IRQ
 141          nop
 142
 143 4:      j        ret_from_irq
 144          nop
 145
 146         .set pop
 147         END(sb1250_irq_handler)