arch/mips/mm/cache.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 2003 by Ralf Baechle
   7  */
   8 #include <linux/config.h>
   9 #include <linux/init.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/sched.h>
  13 #include <linux/mm.h>
  14
  15 #include <asm/cacheflush.h>
  16 #include <asm/processor.h>
  17 #include <asm/cpu.h>
  18 #include <asm/cpu-features.h>
  19
  20 /* Cache operations. */
  21 void (*flush_cache_all)(void);
  22 void (*__flush_cache_all)(void);
  23 void (*flush_cache_mm)(struct mm_struct *mm);
  24 void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
  25         unsigned long end);
  26 void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
  27         unsigned long pfn);
  28 void (*flush_icache_range)(unsigned long __user start,
  29         unsigned long __user end);
  30 void (*flush_icache_page)(struct vm_area_struct *vma, struct page *page);
  31
  32 /* MIPS specific cache operations */
  33 void (*flush_cache_sigtramp)(unsigned long addr);
  34 void (*flush_data_cache_page)(unsigned long addr);
  35 void (*flush_icache_all)(void);
  36
  37 EXPORT_SYMBOL(flush_data_cache_page);
  38
  39 #ifdef CONFIG_DMA_NONCOHERENT
  40
  41 /* DMA cache operations. */
  42 void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
  43 void (*_dma_cache_wback)(unsigned long start, unsigned long size);
  44 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
  45
  46 EXPORT_SYMBOL(_dma_cache_wback_inv);
  47 EXPORT_SYMBOL(_dma_cache_wback);
  48 EXPORT_SYMBOL(_dma_cache_inv);
  49
  50 #endif /* CONFIG_DMA_NONCOHERENT */
  51
  52 /*
  53  * We could optimize the case where the cache argument is not BCACHE but
  54  * that seems very atypical use ...
  55  */
  56 asmlinkage int sys_cacheflush(unsigned long __user addr,
  57         unsigned long bytes, unsigned int cache)
  58 {
  59         if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes))
  60                 return -EFAULT;
  61
  62         flush_icache_range(addr, addr + bytes);
  63
  64         return 0;
  65 }
  66
  67 void __flush_dcache_page(struct page *page)
  68 {
  69         struct address_space *mapping = page_mapping(page);
  70         unsigned long addr;
  71
  72         if (mapping && !mapping_mapped(mapping)) {
  73                 SetPageDcacheDirty(page);
  74                 return;
  75         }
  76
  77         /*
  78          * We could delay the flush for the !page_mapping case too.  But that
  79          * case is for exec env/arg pages and those are %99 certainly going to
  80          * get faulted into the tlb (and thus flushed) anyways.
  81          */
  82         addr = (unsigned long) page_address(page);
  83         flush_data_cache_page(addr);
  84 }
  85
  86 EXPORT_SYMBOL(__flush_dcache_page);
  87
  88 void __update_cache(struct vm_area_struct *vma, unsigned long address,
  89         pte_t pte)
  90 {
  91         struct page *page;
  92         unsigned long pfn, addr;
  93
  94         pfn = pte_pfn(pte);
  95         if (pfn_valid(pfn) && (page = pfn_to_page(pfn), page_mapping(page)) &&
  96             Page_dcache_dirty(page)) {
  97                 if (pages_do_alias((unsigned long)page_address(page),
  98                                    address & PAGE_MASK)) {
  99                         addr = (unsigned long) page_address(page);
 100                         flush_data_cache_page(addr);
 101                 }
 102
 103                 ClearPageDcacheDirty(page);
 104         }
 105 }
 106
 107 extern void ld_mmu_r23000(void);
 108 extern void ld_mmu_r4xx0(void);
 109 extern void ld_mmu_tx39(void);
 110 extern void ld_mmu_r6000(void);
 111 extern void ld_mmu_tfp(void);
 112 extern void ld_mmu_andes(void);
 113 extern void ld_mmu_sb1(void);
 114
 115 void __init cpu_cache_init(void)
 116 {
 117         if (cpu_has_4ktlb) {
 118 #if defined(CONFIG_CPU_R4X00)  || defined(CONFIG_CPU_VR41XX) || \
 119     defined(CONFIG_CPU_R4300)  || defined(CONFIG_CPU_R5000)  || \
 120     defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432)  || \
 121     defined(CONFIG_CPU_R5500)  || defined(CONFIG_CPU_MIPS32_R1) || \
 122     defined(CONFIG_CPU_MIPS64_R1) || defined(CONFIG_CPU_TX49XX) || \
 123     defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000)
 124                 ld_mmu_r4xx0();
 125 #endif
 126         } else switch (current_cpu_data.cputype) {
 127 #ifdef CONFIG_CPU_R3000
 128         case CPU_R2000:
 129         case CPU_R3000:
 130         case CPU_R3000A:
 131         case CPU_R3081E:
 132                 ld_mmu_r23000();
 133                 break;
 134 #endif
 135 #ifdef CONFIG_CPU_TX39XX
 136         case CPU_TX3912:
 137         case CPU_TX3922:
 138         case CPU_TX3927:
 139                 ld_mmu_tx39();
 140                 break;
 141 #endif
 142 #ifdef CONFIG_CPU_R10000
 143         case CPU_R10000:
 144         case CPU_R12000:
 145                 ld_mmu_r4xx0();
 146                 break;
 147 #endif
 148 #ifdef CONFIG_CPU_SB1
 149         case CPU_SB1:
 150                 ld_mmu_sb1();
 151                 break;
 152 #endif
 153
 154         case CPU_R8000:
 155                 panic("R8000 is unsupported");
 156                 break;
 157
 158         default:
 159                 panic("Yeee, unsupported cache architecture.");
 160         }
 161 }