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x86, suspend: Avoid unnecessary smp alternatives switch during suspend/resume
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / kernel / traps.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
13 */
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
17 #include <linux/mm.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26 #include <linux/kgdb.h>
27 #include <linux/kdebug.h>
28 #include <linux/kprobes.h>
29 #include <linux/notifier.h>
30 #include <linux/kdb.h>
31 #include <linux/irq.h>
32 #include <linux/perf_event.h>
33
34 #include <asm/bootinfo.h>
35 #include <asm/branch.h>
36 #include <asm/break.h>
37 #include <asm/cop2.h>
38 #include <asm/cpu.h>
39 #include <asm/dsp.h>
40 #include <asm/fpu.h>
41 #include <asm/fpu_emulator.h>
42 #include <asm/mipsregs.h>
43 #include <asm/mipsmtregs.h>
44 #include <asm/module.h>
45 #include <asm/pgtable.h>
46 #include <asm/ptrace.h>
47 #include <asm/sections.h>
48 #include <asm/system.h>
49 #include <asm/tlbdebug.h>
50 #include <asm/traps.h>
51 #include <asm/uaccess.h>
52 #include <asm/watch.h>
53 #include <asm/mmu_context.h>
54 #include <asm/types.h>
55 #include <asm/stacktrace.h>
56 #include <asm/uasm.h>
57
58 extern void check_wait(void);
59 extern asmlinkage void r4k_wait(void);
60 extern asmlinkage void rollback_handle_int(void);
61 extern asmlinkage void handle_int(void);
62 extern asmlinkage void handle_tlbm(void);
63 extern asmlinkage void handle_tlbl(void);
64 extern asmlinkage void handle_tlbs(void);
65 extern asmlinkage void handle_adel(void);
66 extern asmlinkage void handle_ades(void);
67 extern asmlinkage void handle_ibe(void);
68 extern asmlinkage void handle_dbe(void);
69 extern asmlinkage void handle_sys(void);
70 extern asmlinkage void handle_bp(void);
71 extern asmlinkage void handle_ri(void);
72 extern asmlinkage void handle_ri_rdhwr_vivt(void);
73 extern asmlinkage void handle_ri_rdhwr(void);
74 extern asmlinkage void handle_cpu(void);
75 extern asmlinkage void handle_ov(void);
76 extern asmlinkage void handle_tr(void);
77 extern asmlinkage void handle_fpe(void);
78 extern asmlinkage void handle_mdmx(void);
79 extern asmlinkage void handle_watch(void);
80 extern asmlinkage void handle_mt(void);
81 extern asmlinkage void handle_dsp(void);
82 extern asmlinkage void handle_mcheck(void);
83 extern asmlinkage void handle_reserved(void);
84
85 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
86 struct mips_fpu_struct *ctx, int has_fpu);
87
88 void (*board_be_init)(void);
89 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
90 void (*board_nmi_handler_setup)(void);
91 void (*board_ejtag_handler_setup)(void);
92 void (*board_bind_eic_interrupt)(int irq, int regset);
93
94
95 static void show_raw_backtrace(unsigned long reg29)
96 {
97 unsigned long *sp = (unsigned long *)(reg29 & ~3);
98 unsigned long addr;
99
100 printk("Call Trace:");
101 #ifdef CONFIG_KALLSYMS
102 printk("\n");
103 #endif
104 while (!kstack_end(sp)) {
105 unsigned long __user *p =
106 (unsigned long __user *)(unsigned long)sp++;
107 if (__get_user(addr, p)) {
108 printk(" (Bad stack address)");
109 break;
110 }
111 if (__kernel_text_address(addr))
112 print_ip_sym(addr);
113 }
114 printk("\n");
115 }
116
117 #ifdef CONFIG_KALLSYMS
118 int raw_show_trace;
119 static int __init set_raw_show_trace(char *str)
120 {
121 raw_show_trace = 1;
122 return 1;
123 }
124 __setup("raw_show_trace", set_raw_show_trace);
125 #endif
126
127 static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
128 {
129 unsigned long sp = regs->regs[29];
130 unsigned long ra = regs->regs[31];
131 unsigned long pc = regs->cp0_epc;
132
133 if (raw_show_trace || !__kernel_text_address(pc)) {
134 show_raw_backtrace(sp);
135 return;
136 }
137 printk("Call Trace:\n");
138 do {
139 print_ip_sym(pc);
140 pc = unwind_stack(task, &sp, pc, &ra);
141 } while (pc);
142 printk("\n");
143 }
144
145 /*
146 * This routine abuses get_user()/put_user() to reference pointers
147 * with at least a bit of error checking ...
148 */
149 static void show_stacktrace(struct task_struct *task,
150 const struct pt_regs *regs)
151 {
152 const int field = 2 * sizeof(unsigned long);
153 long stackdata;
154 int i;
155 unsigned long __user *sp = (unsigned long __user *)regs->regs[29];
156
157 printk("Stack :");
158 i = 0;
159 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
160 if (i && ((i % (64 / field)) == 0))
161 printk("\n ");
162 if (i > 39) {
163 printk(" ...");
164 break;
165 }
166
167 if (__get_user(stackdata, sp++)) {
168 printk(" (Bad stack address)");
169 break;
170 }
171
172 printk(" %0*lx", field, stackdata);
173 i++;
174 }
175 printk("\n");
176 show_backtrace(task, regs);
177 }
178
179 void show_stack(struct task_struct *task, unsigned long *sp)
180 {
181 struct pt_regs regs;
182 if (sp) {
183 regs.regs[29] = (unsigned long)sp;
184 regs.regs[31] = 0;
185 regs.cp0_epc = 0;
186 } else {
187 if (task && task != current) {
188 regs.regs[29] = task->thread.reg29;
189 regs.regs[31] = 0;
190 regs.cp0_epc = task->thread.reg31;
191 #ifdef CONFIG_KGDB_KDB
192 } else if (atomic_read(&kgdb_active) != -1 &&
193 kdb_current_regs) {
194 memcpy(&regs, kdb_current_regs, sizeof(regs));
195 #endif /* CONFIG_KGDB_KDB */
196 } else {
197 prepare_frametrace(&regs);
198 }
199 }
200 show_stacktrace(task, &regs);
201 }
202
203 /*
204 * The architecture-independent dump_stack generator
205 */
206 void dump_stack(void)
207 {
208 struct pt_regs regs;
209
210 prepare_frametrace(&regs);
211 show_backtrace(current, &regs);
212 }
213
214 EXPORT_SYMBOL(dump_stack);
215
216 static void show_code(unsigned int __user *pc)
217 {
218 long i;
219 unsigned short __user *pc16 = NULL;
220
221 printk("\nCode:");
222
223 if ((unsigned long)pc & 1)
224 pc16 = (unsigned short __user *)((unsigned long)pc & ~1);
225 for(i = -3 ; i < 6 ; i++) {
226 unsigned int insn;
227 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) {
228 printk(" (Bad address in epc)\n");
229 break;
230 }
231 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>'));
232 }
233 }
234
235 static void __show_regs(const struct pt_regs *regs)
236 {
237 const int field = 2 * sizeof(unsigned long);
238 unsigned int cause = regs->cp0_cause;
239 int i;
240
241 printk("Cpu %d\n", smp_processor_id());
242
243 /*
244 * Saved main processor registers
245 */
246 for (i = 0; i < 32; ) {
247 if ((i % 4) == 0)
248 printk("$%2d :", i);
249 if (i == 0)
250 printk(" %0*lx", field, 0UL);
251 else if (i == 26 || i == 27)
252 printk(" %*s", field, "");
253 else
254 printk(" %0*lx", field, regs->regs[i]);
255
256 i++;
257 if ((i % 4) == 0)
258 printk("\n");
259 }
260
261 #ifdef CONFIG_CPU_HAS_SMARTMIPS
262 printk("Acx : %0*lx\n", field, regs->acx);
263 #endif
264 printk("Hi : %0*lx\n", field, regs->hi);
265 printk("Lo : %0*lx\n", field, regs->lo);
266
267 /*
268 * Saved cp0 registers
269 */
270 printk("epc : %0*lx %pS\n", field, regs->cp0_epc,
271 (void *) regs->cp0_epc);
272 printk(" %s\n", print_tainted());
273 printk("ra : %0*lx %pS\n", field, regs->regs[31],
274 (void *) regs->regs[31]);
275
276 printk("Status: %08x ", (uint32_t) regs->cp0_status);
277
278 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
279 if (regs->cp0_status & ST0_KUO)
280 printk("KUo ");
281 if (regs->cp0_status & ST0_IEO)
282 printk("IEo ");
283 if (regs->cp0_status & ST0_KUP)
284 printk("KUp ");
285 if (regs->cp0_status & ST0_IEP)
286 printk("IEp ");
287 if (regs->cp0_status & ST0_KUC)
288 printk("KUc ");
289 if (regs->cp0_status & ST0_IEC)
290 printk("IEc ");
291 } else {
292 if (regs->cp0_status & ST0_KX)
293 printk("KX ");
294 if (regs->cp0_status & ST0_SX)
295 printk("SX ");
296 if (regs->cp0_status & ST0_UX)
297 printk("UX ");
298 switch (regs->cp0_status & ST0_KSU) {
299 case KSU_USER:
300 printk("USER ");
301 break;
302 case KSU_SUPERVISOR:
303 printk("SUPERVISOR ");
304 break;
305 case KSU_KERNEL:
306 printk("KERNEL ");
307 break;
308 default:
309 printk("BAD_MODE ");
310 break;
311 }
312 if (regs->cp0_status & ST0_ERL)
313 printk("ERL ");
314 if (regs->cp0_status & ST0_EXL)
315 printk("EXL ");
316 if (regs->cp0_status & ST0_IE)
317 printk("IE ");
318 }
319 printk("\n");
320
321 printk("Cause : %08x\n", cause);
322
323 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
324 if (1 <= cause && cause <= 5)
325 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
326
327 printk("PrId : %08x (%s)\n", read_c0_prid(),
328 cpu_name_string());
329 }
330
331 /*
332 * FIXME: really the generic show_regs should take a const pointer argument.
333 */
334 void show_regs(struct pt_regs *regs)
335 {
336 __show_regs((struct pt_regs *)regs);
337 }
338
339 void show_registers(struct pt_regs *regs)
340 {
341 const int field = 2 * sizeof(unsigned long);
342
343 __show_regs(regs);
344 print_modules();
345 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
346 current->comm, current->pid, current_thread_info(), current,
347 field, current_thread_info()->tp_value);
348 if (cpu_has_userlocal) {
349 unsigned long tls;
350
351 tls = read_c0_userlocal();
352 if (tls != current_thread_info()->tp_value)
353 printk("*HwTLS: %0*lx\n", field, tls);
354 }
355
356 show_stacktrace(current, regs);
357 show_code((unsigned int __user *) regs->cp0_epc);
358 printk("\n");
359 }
360
361 static int regs_to_trapnr(struct pt_regs *regs)
362 {
363 return (regs->cp0_cause >> 2) & 0x1f;
364 }
365
366 static DEFINE_SPINLOCK(die_lock);
367
368 void __noreturn die(const char *str, struct pt_regs *regs)
369 {
370 static int die_counter;
371 int sig = SIGSEGV;
372 #ifdef CONFIG_MIPS_MT_SMTC
373 unsigned long dvpret = dvpe();
374 #endif /* CONFIG_MIPS_MT_SMTC */
375
376 notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV);
377
378 console_verbose();
379 spin_lock_irq(&die_lock);
380 bust_spinlocks(1);
381 #ifdef CONFIG_MIPS_MT_SMTC
382 mips_mt_regdump(dvpret);
383 #endif /* CONFIG_MIPS_MT_SMTC */
384
385 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), SIGSEGV) == NOTIFY_STOP)
386 sig = 0;
387
388 printk("%s[#%d]:\n", str, ++die_counter);
389 show_registers(regs);
390 add_taint(TAINT_DIE);
391 spin_unlock_irq(&die_lock);
392
393 if (in_interrupt())
394 panic("Fatal exception in interrupt");
395
396 if (panic_on_oops) {
397 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
398 ssleep(5);
399 panic("Fatal exception");
400 }
401
402 do_exit(sig);
403 }
404
405 extern struct exception_table_entry __start___dbe_table[];
406 extern struct exception_table_entry __stop___dbe_table[];
407
408 __asm__(
409 " .section __dbe_table, \"a\"\n"
410 " .previous \n");
411
412 /* Given an address, look for it in the exception tables. */
413 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
414 {
415 const struct exception_table_entry *e;
416
417 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
418 if (!e)
419 e = search_module_dbetables(addr);
420 return e;
421 }
422
423 asmlinkage void do_be(struct pt_regs *regs)
424 {
425 const int field = 2 * sizeof(unsigned long);
426 const struct exception_table_entry *fixup = NULL;
427 int data = regs->cp0_cause & 4;
428 int action = MIPS_BE_FATAL;
429
430 /* XXX For now. Fixme, this searches the wrong table ... */
431 if (data && !user_mode(regs))
432 fixup = search_dbe_tables(exception_epc(regs));
433
434 if (fixup)
435 action = MIPS_BE_FIXUP;
436
437 if (board_be_handler)
438 action = board_be_handler(regs, fixup != NULL);
439
440 switch (action) {
441 case MIPS_BE_DISCARD:
442 return;
443 case MIPS_BE_FIXUP:
444 if (fixup) {
445 regs->cp0_epc = fixup->nextinsn;
446 return;
447 }
448 break;
449 default:
450 break;
451 }
452
453 /*
454 * Assume it would be too dangerous to continue ...
455 */
456 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
457 data ? "Data" : "Instruction",
458 field, regs->cp0_epc, field, regs->regs[31]);
459 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), SIGBUS)
460 == NOTIFY_STOP)
461 return;
462
463 die_if_kernel("Oops", regs);
464 force_sig(SIGBUS, current);
465 }
466
467 /*
468 * ll/sc, rdhwr, sync emulation
469 */
470
471 #define OPCODE 0xfc000000
472 #define BASE 0x03e00000
473 #define RT 0x001f0000
474 #define OFFSET 0x0000ffff
475 #define LL 0xc0000000
476 #define SC 0xe0000000
477 #define SPEC0 0x00000000
478 #define SPEC3 0x7c000000
479 #define RD 0x0000f800
480 #define FUNC 0x0000003f
481 #define SYNC 0x0000000f
482 #define RDHWR 0x0000003b
483
484 /*
485 * The ll_bit is cleared by r*_switch.S
486 */
487
488 unsigned int ll_bit;
489 struct task_struct *ll_task;
490
491 static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
492 {
493 unsigned long value, __user *vaddr;
494 long offset;
495
496 /*
497 * analyse the ll instruction that just caused a ri exception
498 * and put the referenced address to addr.
499 */
500
501 /* sign extend offset */
502 offset = opcode & OFFSET;
503 offset <<= 16;
504 offset >>= 16;
505
506 vaddr = (unsigned long __user *)
507 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
508
509 if ((unsigned long)vaddr & 3)
510 return SIGBUS;
511 if (get_user(value, vaddr))
512 return SIGSEGV;
513
514 preempt_disable();
515
516 if (ll_task == NULL || ll_task == current) {
517 ll_bit = 1;
518 } else {
519 ll_bit = 0;
520 }
521 ll_task = current;
522
523 preempt_enable();
524
525 regs->regs[(opcode & RT) >> 16] = value;
526
527 return 0;
528 }
529
530 static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode)
531 {
532 unsigned long __user *vaddr;
533 unsigned long reg;
534 long offset;
535
536 /*
537 * analyse the sc instruction that just caused a ri exception
538 * and put the referenced address to addr.
539 */
540
541 /* sign extend offset */
542 offset = opcode & OFFSET;
543 offset <<= 16;
544 offset >>= 16;
545
546 vaddr = (unsigned long __user *)
547 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
548 reg = (opcode & RT) >> 16;
549
550 if ((unsigned long)vaddr & 3)
551 return SIGBUS;
552
553 preempt_disable();
554
555 if (ll_bit == 0 || ll_task != current) {
556 regs->regs[reg] = 0;
557 preempt_enable();
558 return 0;
559 }
560
561 preempt_enable();
562
563 if (put_user(regs->regs[reg], vaddr))
564 return SIGSEGV;
565
566 regs->regs[reg] = 1;
567
568 return 0;
569 }
570
571 /*
572 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
573 * opcodes are supposed to result in coprocessor unusable exceptions if
574 * executed on ll/sc-less processors. That's the theory. In practice a
575 * few processors such as NEC's VR4100 throw reserved instruction exceptions
576 * instead, so we're doing the emulation thing in both exception handlers.
577 */
578 static int simulate_llsc(struct pt_regs *regs, unsigned int opcode)
579 {
580 if ((opcode & OPCODE) == LL) {
581 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
582 1, 0, regs, 0);
583 return simulate_ll(regs, opcode);
584 }
585 if ((opcode & OPCODE) == SC) {
586 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
587 1, 0, regs, 0);
588 return simulate_sc(regs, opcode);
589 }
590
591 return -1; /* Must be something else ... */
592 }
593
594 /*
595 * Simulate trapping 'rdhwr' instructions to provide user accessible
596 * registers not implemented in hardware.
597 */
598 static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode)
599 {
600 struct thread_info *ti = task_thread_info(current);
601
602 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
603 int rd = (opcode & RD) >> 11;
604 int rt = (opcode & RT) >> 16;
605 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
606 1, 0, regs, 0);
607 switch (rd) {
608 case 0: /* CPU number */
609 regs->regs[rt] = smp_processor_id();
610 return 0;
611 case 1: /* SYNCI length */
612 regs->regs[rt] = min(current_cpu_data.dcache.linesz,
613 current_cpu_data.icache.linesz);
614 return 0;
615 case 2: /* Read count register */
616 regs->regs[rt] = read_c0_count();
617 return 0;
618 case 3: /* Count register resolution */
619 switch (current_cpu_data.cputype) {
620 case CPU_20KC:
621 case CPU_25KF:
622 regs->regs[rt] = 1;
623 break;
624 default:
625 regs->regs[rt] = 2;
626 }
627 return 0;
628 case 29:
629 regs->regs[rt] = ti->tp_value;
630 return 0;
631 default:
632 return -1;
633 }
634 }
635
636 /* Not ours. */
637 return -1;
638 }
639
640 static int simulate_sync(struct pt_regs *regs, unsigned int opcode)
641 {
642 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) {
643 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS,
644 1, 0, regs, 0);
645 return 0;
646 }
647
648 return -1; /* Must be something else ... */
649 }
650
651 asmlinkage void do_ov(struct pt_regs *regs)
652 {
653 siginfo_t info;
654
655 die_if_kernel("Integer overflow", regs);
656
657 info.si_code = FPE_INTOVF;
658 info.si_signo = SIGFPE;
659 info.si_errno = 0;
660 info.si_addr = (void __user *) regs->cp0_epc;
661 force_sig_info(SIGFPE, &info, current);
662 }
663
664 /*
665 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
666 */
667 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
668 {
669 siginfo_t info;
670
671 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
672 == NOTIFY_STOP)
673 return;
674 die_if_kernel("FP exception in kernel code", regs);
675
676 if (fcr31 & FPU_CSR_UNI_X) {
677 int sig;
678
679 /*
680 * Unimplemented operation exception. If we've got the full
681 * software emulator on-board, let's use it...
682 *
683 * Force FPU to dump state into task/thread context. We're
684 * moving a lot of data here for what is probably a single
685 * instruction, but the alternative is to pre-decode the FP
686 * register operands before invoking the emulator, which seems
687 * a bit extreme for what should be an infrequent event.
688 */
689 /* Ensure 'resume' not overwrite saved fp context again. */
690 lose_fpu(1);
691
692 /* Run the emulator */
693 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1);
694
695 /*
696 * We can't allow the emulated instruction to leave any of
697 * the cause bit set in $fcr31.
698 */
699 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
700
701 /* Restore the hardware register state */
702 own_fpu(1); /* Using the FPU again. */
703
704 /* If something went wrong, signal */
705 if (sig)
706 force_sig(sig, current);
707
708 return;
709 } else if (fcr31 & FPU_CSR_INV_X)
710 info.si_code = FPE_FLTINV;
711 else if (fcr31 & FPU_CSR_DIV_X)
712 info.si_code = FPE_FLTDIV;
713 else if (fcr31 & FPU_CSR_OVF_X)
714 info.si_code = FPE_FLTOVF;
715 else if (fcr31 & FPU_CSR_UDF_X)
716 info.si_code = FPE_FLTUND;
717 else if (fcr31 & FPU_CSR_INE_X)
718 info.si_code = FPE_FLTRES;
719 else
720 info.si_code = __SI_FAULT;
721 info.si_signo = SIGFPE;
722 info.si_errno = 0;
723 info.si_addr = (void __user *) regs->cp0_epc;
724 force_sig_info(SIGFPE, &info, current);
725 }
726
727 static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
728 const char *str)
729 {
730 siginfo_t info;
731 char b[40];
732
733 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
734 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
735 return;
736 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
737
738 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
739 return;
740
741 /*
742 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
743 * insns, even for trap and break codes that indicate arithmetic
744 * failures. Weird ...
745 * But should we continue the brokenness??? --macro
746 */
747 switch (code) {
748 case BRK_OVERFLOW:
749 case BRK_DIVZERO:
750 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
751 die_if_kernel(b, regs);
752 if (code == BRK_DIVZERO)
753 info.si_code = FPE_INTDIV;
754 else
755 info.si_code = FPE_INTOVF;
756 info.si_signo = SIGFPE;
757 info.si_errno = 0;
758 info.si_addr = (void __user *) regs->cp0_epc;
759 force_sig_info(SIGFPE, &info, current);
760 break;
761 case BRK_BUG:
762 die_if_kernel("Kernel bug detected", regs);
763 force_sig(SIGTRAP, current);
764 break;
765 case BRK_MEMU:
766 /*
767 * Address errors may be deliberately induced by the FPU
768 * emulator to retake control of the CPU after executing the
769 * instruction in the delay slot of an emulated branch.
770 *
771 * Terminate if exception was recognized as a delay slot return
772 * otherwise handle as normal.
773 */
774 if (do_dsemulret(regs))
775 return;
776
777 die_if_kernel("Math emu break/trap", regs);
778 force_sig(SIGTRAP, current);
779 break;
780 default:
781 scnprintf(b, sizeof(b), "%s instruction in kernel code", str);
782 die_if_kernel(b, regs);
783 force_sig(SIGTRAP, current);
784 }
785 }
786
787 asmlinkage void do_bp(struct pt_regs *regs)
788 {
789 unsigned int opcode, bcode;
790
791 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
792 goto out_sigsegv;
793
794 /*
795 * There is the ancient bug in the MIPS assemblers that the break
796 * code starts left to bit 16 instead to bit 6 in the opcode.
797 * Gas is bug-compatible, but not always, grrr...
798 * We handle both cases with a simple heuristics. --macro
799 */
800 bcode = ((opcode >> 6) & ((1 << 20) - 1));
801 if (bcode >= (1 << 10))
802 bcode >>= 10;
803
804 /*
805 * notify the kprobe handlers, if instruction is likely to
806 * pertain to them.
807 */
808 switch (bcode) {
809 case BRK_KPROBE_BP:
810 if (notify_die(DIE_BREAK, "debug", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
811 return;
812 else
813 break;
814 case BRK_KPROBE_SSTEPBP:
815 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP)
816 return;
817 else
818 break;
819 default:
820 break;
821 }
822
823 do_trap_or_bp(regs, bcode, "Break");
824 return;
825
826 out_sigsegv:
827 force_sig(SIGSEGV, current);
828 }
829
830 asmlinkage void do_tr(struct pt_regs *regs)
831 {
832 unsigned int opcode, tcode = 0;
833
834 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
835 goto out_sigsegv;
836
837 /* Immediate versions don't provide a code. */
838 if (!(opcode & OPCODE))
839 tcode = ((opcode >> 6) & ((1 << 10) - 1));
840
841 do_trap_or_bp(regs, tcode, "Trap");
842 return;
843
844 out_sigsegv:
845 force_sig(SIGSEGV, current);
846 }
847
848 asmlinkage void do_ri(struct pt_regs *regs)
849 {
850 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs);
851 unsigned long old_epc = regs->cp0_epc;
852 unsigned int opcode = 0;
853 int status = -1;
854
855 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), SIGILL)
856 == NOTIFY_STOP)
857 return;
858
859 die_if_kernel("Reserved instruction in kernel code", regs);
860
861 if (unlikely(compute_return_epc(regs) < 0))
862 return;
863
864 if (unlikely(get_user(opcode, epc) < 0))
865 status = SIGSEGV;
866
867 if (!cpu_has_llsc && status < 0)
868 status = simulate_llsc(regs, opcode);
869
870 if (status < 0)
871 status = simulate_rdhwr(regs, opcode);
872
873 if (status < 0)
874 status = simulate_sync(regs, opcode);
875
876 if (status < 0)
877 status = SIGILL;
878
879 if (unlikely(status > 0)) {
880 regs->cp0_epc = old_epc; /* Undo skip-over. */
881 force_sig(status, current);
882 }
883 }
884
885 /*
886 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
887 * emulated more than some threshold number of instructions, force migration to
888 * a "CPU" that has FP support.
889 */
890 static void mt_ase_fp_affinity(void)
891 {
892 #ifdef CONFIG_MIPS_MT_FPAFF
893 if (mt_fpemul_threshold > 0 &&
894 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
895 /*
896 * If there's no FPU present, or if the application has already
897 * restricted the allowed set to exclude any CPUs with FPUs,
898 * we'll skip the procedure.
899 */
900 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
901 cpumask_t tmask;
902
903 current->thread.user_cpus_allowed
904 = current->cpus_allowed;
905 cpus_and(tmask, current->cpus_allowed,
906 mt_fpu_cpumask);
907 set_cpus_allowed_ptr(current, &tmask);
908 set_thread_flag(TIF_FPUBOUND);
909 }
910 }
911 #endif /* CONFIG_MIPS_MT_FPAFF */
912 }
913
914 /*
915 * No lock; only written during early bootup by CPU 0.
916 */
917 static RAW_NOTIFIER_HEAD(cu2_chain);
918
919 int __ref register_cu2_notifier(struct notifier_block *nb)
920 {
921 return raw_notifier_chain_register(&cu2_chain, nb);
922 }
923
924 int cu2_notifier_call_chain(unsigned long val, void *v)
925 {
926 return raw_notifier_call_chain(&cu2_chain, val, v);
927 }
928
929 static int default_cu2_call(struct notifier_block *nfb, unsigned long action,
930 void *data)
931 {
932 struct pt_regs *regs = data;
933
934 switch (action) {
935 default:
936 die_if_kernel("Unhandled kernel unaligned access or invalid "
937 "instruction", regs);
938 /* Fall through */
939
940 case CU2_EXCEPTION:
941 force_sig(SIGILL, current);
942 }
943
944 return NOTIFY_OK;
945 }
946
947 asmlinkage void do_cpu(struct pt_regs *regs)
948 {
949 unsigned int __user *epc;
950 unsigned long old_epc;
951 unsigned int opcode;
952 unsigned int cpid;
953 int status;
954 unsigned long __maybe_unused flags;
955
956 die_if_kernel("do_cpu invoked from kernel context!", regs);
957
958 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
959
960 switch (cpid) {
961 case 0:
962 epc = (unsigned int __user *)exception_epc(regs);
963 old_epc = regs->cp0_epc;
964 opcode = 0;
965 status = -1;
966
967 if (unlikely(compute_return_epc(regs) < 0))
968 return;
969
970 if (unlikely(get_user(opcode, epc) < 0))
971 status = SIGSEGV;
972
973 if (!cpu_has_llsc && status < 0)
974 status = simulate_llsc(regs, opcode);
975
976 if (status < 0)
977 status = simulate_rdhwr(regs, opcode);
978
979 if (status < 0)
980 status = SIGILL;
981
982 if (unlikely(status > 0)) {
983 regs->cp0_epc = old_epc; /* Undo skip-over. */
984 force_sig(status, current);
985 }
986
987 return;
988
989 case 1:
990 if (used_math()) /* Using the FPU again. */
991 own_fpu(1);
992 else { /* First time FPU user. */
993 init_fpu();
994 set_used_math();
995 }
996
997 if (!raw_cpu_has_fpu) {
998 int sig;
999 sig = fpu_emulator_cop1Handler(regs,
1000 &current->thread.fpu, 0);
1001 if (sig)
1002 force_sig(sig, current);
1003 else
1004 mt_ase_fp_affinity();
1005 }
1006
1007 return;
1008
1009 case 2:
1010 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs);
1011 return;
1012
1013 case 3:
1014 break;
1015 }
1016
1017 force_sig(SIGILL, current);
1018 }
1019
1020 asmlinkage void do_mdmx(struct pt_regs *regs)
1021 {
1022 force_sig(SIGILL, current);
1023 }
1024
1025 /*
1026 * Called with interrupts disabled.
1027 */
1028 asmlinkage void do_watch(struct pt_regs *regs)
1029 {
1030 u32 cause;
1031
1032 /*
1033 * Clear WP (bit 22) bit of cause register so we don't loop
1034 * forever.
1035 */
1036 cause = read_c0_cause();
1037 cause &= ~(1 << 22);
1038 write_c0_cause(cause);
1039
1040 /*
1041 * If the current thread has the watch registers loaded, save
1042 * their values and send SIGTRAP. Otherwise another thread
1043 * left the registers set, clear them and continue.
1044 */
1045 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
1046 mips_read_watch_registers();
1047 local_irq_enable();
1048 force_sig(SIGTRAP, current);
1049 } else {
1050 mips_clear_watch_registers();
1051 local_irq_enable();
1052 }
1053 }
1054
1055 asmlinkage void do_mcheck(struct pt_regs *regs)
1056 {
1057 const int field = 2 * sizeof(unsigned long);
1058 int multi_match = regs->cp0_status & ST0_TS;
1059
1060 show_regs(regs);
1061
1062 if (multi_match) {
1063 printk("Index : %0x\n", read_c0_index());
1064 printk("Pagemask: %0x\n", read_c0_pagemask());
1065 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
1066 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
1067 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
1068 printk("\n");
1069 dump_tlb_all();
1070 }
1071
1072 show_code((unsigned int __user *) regs->cp0_epc);
1073
1074 /*
1075 * Some chips may have other causes of machine check (e.g. SB1
1076 * graduation timer)
1077 */
1078 panic("Caught Machine Check exception - %scaused by multiple "
1079 "matching entries in the TLB.",
1080 (multi_match) ? "" : "not ");
1081 }
1082
1083 asmlinkage void do_mt(struct pt_regs *regs)
1084 {
1085 int subcode;
1086
1087 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
1088 >> VPECONTROL_EXCPT_SHIFT;
1089 switch (subcode) {
1090 case 0:
1091 printk(KERN_DEBUG "Thread Underflow\n");
1092 break;
1093 case 1:
1094 printk(KERN_DEBUG "Thread Overflow\n");
1095 break;
1096 case 2:
1097 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
1098 break;
1099 case 3:
1100 printk(KERN_DEBUG "Gating Storage Exception\n");
1101 break;
1102 case 4:
1103 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
1104 break;
1105 case 5:
1106 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
1107 break;
1108 default:
1109 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
1110 subcode);
1111 break;
1112 }
1113 die_if_kernel("MIPS MT Thread exception in kernel", regs);
1114
1115 force_sig(SIGILL, current);
1116 }
1117
1118
1119 asmlinkage void do_dsp(struct pt_regs *regs)
1120 {
1121 if (cpu_has_dsp)
1122 panic("Unexpected DSP exception\n");
1123
1124 force_sig(SIGILL, current);
1125 }
1126
1127 asmlinkage void do_reserved(struct pt_regs *regs)
1128 {
1129 /*
1130 * Game over - no way to handle this if it ever occurs. Most probably
1131 * caused by a new unknown cpu type or after another deadly
1132 * hard/software error.
1133 */
1134 show_regs(regs);
1135 panic("Caught reserved exception %ld - should not happen.",
1136 (regs->cp0_cause & 0x7f) >> 2);
1137 }
1138
1139 static int __initdata l1parity = 1;
1140 static int __init nol1parity(char *s)
1141 {
1142 l1parity = 0;
1143 return 1;
1144 }
1145 __setup("nol1par", nol1parity);
1146 static int __initdata l2parity = 1;
1147 static int __init nol2parity(char *s)
1148 {
1149 l2parity = 0;
1150 return 1;
1151 }
1152 __setup("nol2par", nol2parity);
1153
1154 /*
1155 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1156 * it different ways.
1157 */
1158 static inline void parity_protection_init(void)
1159 {
1160 switch (current_cpu_type()) {
1161 case CPU_24K:
1162 case CPU_34K:
1163 case CPU_74K:
1164 case CPU_1004K:
1165 {
1166 #define ERRCTL_PE 0x80000000
1167 #define ERRCTL_L2P 0x00800000
1168 unsigned long errctl;
1169 unsigned int l1parity_present, l2parity_present;
1170
1171 errctl = read_c0_ecc();
1172 errctl &= ~(ERRCTL_PE|ERRCTL_L2P);
1173
1174 /* probe L1 parity support */
1175 write_c0_ecc(errctl | ERRCTL_PE);
1176 back_to_back_c0_hazard();
1177 l1parity_present = (read_c0_ecc() & ERRCTL_PE);
1178
1179 /* probe L2 parity support */
1180 write_c0_ecc(errctl|ERRCTL_L2P);
1181 back_to_back_c0_hazard();
1182 l2parity_present = (read_c0_ecc() & ERRCTL_L2P);
1183
1184 if (l1parity_present && l2parity_present) {
1185 if (l1parity)
1186 errctl |= ERRCTL_PE;
1187 if (l1parity ^ l2parity)
1188 errctl |= ERRCTL_L2P;
1189 } else if (l1parity_present) {
1190 if (l1parity)
1191 errctl |= ERRCTL_PE;
1192 } else if (l2parity_present) {
1193 if (l2parity)
1194 errctl |= ERRCTL_L2P;
1195 } else {
1196 /* No parity available */
1197 }
1198
1199 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl);
1200
1201 write_c0_ecc(errctl);
1202 back_to_back_c0_hazard();
1203 errctl = read_c0_ecc();
1204 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl);
1205
1206 if (l1parity_present)
1207 printk(KERN_INFO "Cache parity protection %sabled\n",
1208 (errctl & ERRCTL_PE) ? "en" : "dis");
1209
1210 if (l2parity_present) {
1211 if (l1parity_present && l1parity)
1212 errctl ^= ERRCTL_L2P;
1213 printk(KERN_INFO "L2 cache parity protection %sabled\n",
1214 (errctl & ERRCTL_L2P) ? "en" : "dis");
1215 }
1216 }
1217 break;
1218
1219 case CPU_5KC:
1220 write_c0_ecc(0x80000000);
1221 back_to_back_c0_hazard();
1222 /* Set the PE bit (bit 31) in the c0_errctl register. */
1223 printk(KERN_INFO "Cache parity protection %sabled\n",
1224 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1225 break;
1226 case CPU_20KC:
1227 case CPU_25KF:
1228 /* Clear the DE bit (bit 16) in the c0_status register. */
1229 printk(KERN_INFO "Enable cache parity protection for "
1230 "MIPS 20KC/25KF CPUs.\n");
1231 clear_c0_status(ST0_DE);
1232 break;
1233 default:
1234 break;
1235 }
1236 }
1237
1238 asmlinkage void cache_parity_error(void)
1239 {
1240 const int field = 2 * sizeof(unsigned long);
1241 unsigned int reg_val;
1242
1243 /* For the moment, report the problem and hang. */
1244 printk("Cache error exception:\n");
1245 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
1246 reg_val = read_c0_cacheerr();
1247 printk("c0_cacheerr == %08x\n", reg_val);
1248
1249 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1250 reg_val & (1<<30) ? "secondary" : "primary",
1251 reg_val & (1<<31) ? "data" : "insn");
1252 printk("Error bits: %s%s%s%s%s%s%s\n",
1253 reg_val & (1<<29) ? "ED " : "",
1254 reg_val & (1<<28) ? "ET " : "",
1255 reg_val & (1<<26) ? "EE " : "",
1256 reg_val & (1<<25) ? "EB " : "",
1257 reg_val & (1<<24) ? "EI " : "",
1258 reg_val & (1<<23) ? "E1 " : "",
1259 reg_val & (1<<22) ? "E0 " : "");
1260 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
1261
1262 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1263 if (reg_val & (1<<22))
1264 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
1265
1266 if (reg_val & (1<<23))
1267 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
1268 #endif
1269
1270 panic("Can't handle the cache error!");
1271 }
1272
1273 /*
1274 * SDBBP EJTAG debug exception handler.
1275 * We skip the instruction and return to the next instruction.
1276 */
1277 void ejtag_exception_handler(struct pt_regs *regs)
1278 {
1279 const int field = 2 * sizeof(unsigned long);
1280 unsigned long depc, old_epc;
1281 unsigned int debug;
1282
1283 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1284 depc = read_c0_depc();
1285 debug = read_c0_debug();
1286 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1287 if (debug & 0x80000000) {
1288 /*
1289 * In branch delay slot.
1290 * We cheat a little bit here and use EPC to calculate the
1291 * debug return address (DEPC). EPC is restored after the
1292 * calculation.
1293 */
1294 old_epc = regs->cp0_epc;
1295 regs->cp0_epc = depc;
1296 __compute_return_epc(regs);
1297 depc = regs->cp0_epc;
1298 regs->cp0_epc = old_epc;
1299 } else
1300 depc += 4;
1301 write_c0_depc(depc);
1302
1303 #if 0
1304 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1305 write_c0_debug(debug | 0x100);
1306 #endif
1307 }
1308
1309 /*
1310 * NMI exception handler.
1311 */
1312 NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs)
1313 {
1314 bust_spinlocks(1);
1315 printk("NMI taken!!!!\n");
1316 die("NMI", regs);
1317 }
1318
1319 #define VECTORSPACING 0x100 /* for EI/VI mode */
1320
1321 unsigned long ebase;
1322 unsigned long exception_handlers[32];
1323 unsigned long vi_handlers[64];
1324
1325 void __init *set_except_vector(int n, void *addr)
1326 {
1327 unsigned long handler = (unsigned long) addr;
1328 unsigned long old_handler = exception_handlers[n];
1329
1330 exception_handlers[n] = handler;
1331 if (n == 0 && cpu_has_divec) {
1332 unsigned long jump_mask = ~((1 << 28) - 1);
1333 u32 *buf = (u32 *)(ebase + 0x200);
1334 unsigned int k0 = 26;
1335 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) {
1336 uasm_i_j(&buf, handler & ~jump_mask);
1337 uasm_i_nop(&buf);
1338 } else {
1339 UASM_i_LA(&buf, k0, handler);
1340 uasm_i_jr(&buf, k0);
1341 uasm_i_nop(&buf);
1342 }
1343 local_flush_icache_range(ebase + 0x200, (unsigned long)buf);
1344 }
1345 return (void *)old_handler;
1346 }
1347
1348 static asmlinkage void do_default_vi(void)
1349 {
1350 show_regs(get_irq_regs());
1351 panic("Caught unexpected vectored interrupt.");
1352 }
1353
1354 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1355 {
1356 unsigned long handler;
1357 unsigned long old_handler = vi_handlers[n];
1358 int srssets = current_cpu_data.srsets;
1359 u32 *w;
1360 unsigned char *b;
1361
1362 BUG_ON(!cpu_has_veic && !cpu_has_vint);
1363
1364 if (addr == NULL) {
1365 handler = (unsigned long) do_default_vi;
1366 srs = 0;
1367 } else
1368 handler = (unsigned long) addr;
1369 vi_handlers[n] = (unsigned long) addr;
1370
1371 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1372
1373 if (srs >= srssets)
1374 panic("Shadow register set %d not supported", srs);
1375
1376 if (cpu_has_veic) {
1377 if (board_bind_eic_interrupt)
1378 board_bind_eic_interrupt(n, srs);
1379 } else if (cpu_has_vint) {
1380 /* SRSMap is only defined if shadow sets are implemented */
1381 if (srssets > 1)
1382 change_c0_srsmap(0xf << n*4, srs << n*4);
1383 }
1384
1385 if (srs == 0) {
1386 /*
1387 * If no shadow set is selected then use the default handler
1388 * that does normal register saving and a standard interrupt exit
1389 */
1390
1391 extern char except_vec_vi, except_vec_vi_lui;
1392 extern char except_vec_vi_ori, except_vec_vi_end;
1393 extern char rollback_except_vec_vi;
1394 char *vec_start = (cpu_wait == r4k_wait) ?
1395 &rollback_except_vec_vi : &except_vec_vi;
1396 #ifdef CONFIG_MIPS_MT_SMTC
1397 /*
1398 * We need to provide the SMTC vectored interrupt handler
1399 * not only with the address of the handler, but with the
1400 * Status.IM bit to be masked before going there.
1401 */
1402 extern char except_vec_vi_mori;
1403 const int mori_offset = &except_vec_vi_mori - vec_start;
1404 #endif /* CONFIG_MIPS_MT_SMTC */
1405 const int handler_len = &except_vec_vi_end - vec_start;
1406 const int lui_offset = &except_vec_vi_lui - vec_start;
1407 const int ori_offset = &except_vec_vi_ori - vec_start;
1408
1409 if (handler_len > VECTORSPACING) {
1410 /*
1411 * Sigh... panicing won't help as the console
1412 * is probably not configured :(
1413 */
1414 panic("VECTORSPACING too small");
1415 }
1416
1417 memcpy(b, vec_start, handler_len);
1418 #ifdef CONFIG_MIPS_MT_SMTC
1419 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1420
1421 w = (u32 *)(b + mori_offset);
1422 *w = (*w & 0xffff0000) | (0x100 << n);
1423 #endif /* CONFIG_MIPS_MT_SMTC */
1424 w = (u32 *)(b + lui_offset);
1425 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1426 w = (u32 *)(b + ori_offset);
1427 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1428 local_flush_icache_range((unsigned long)b,
1429 (unsigned long)(b+handler_len));
1430 }
1431 else {
1432 /*
1433 * In other cases jump directly to the interrupt handler
1434 *
1435 * It is the handlers responsibility to save registers if required
1436 * (eg hi/lo) and return from the exception using "eret"
1437 */
1438 w = (u32 *)b;
1439 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1440 *w = 0;
1441 local_flush_icache_range((unsigned long)b,
1442 (unsigned long)(b+8));
1443 }
1444
1445 return (void *)old_handler;
1446 }
1447
1448 void *set_vi_handler(int n, vi_handler_t addr)
1449 {
1450 return set_vi_srs_handler(n, addr, 0);
1451 }
1452
1453 extern void cpu_cache_init(void);
1454 extern void tlb_init(void);
1455 extern void flush_tlb_handlers(void);
1456
1457 /*
1458 * Timer interrupt
1459 */
1460 int cp0_compare_irq;
1461 int cp0_compare_irq_shift;
1462
1463 /*
1464 * Performance counter IRQ or -1 if shared with timer
1465 */
1466 int cp0_perfcount_irq;
1467 EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
1468
1469 static int __cpuinitdata noulri;
1470
1471 static int __init ulri_disable(char *s)
1472 {
1473 pr_info("Disabling ulri\n");
1474 noulri = 1;
1475
1476 return 1;
1477 }
1478 __setup("noulri", ulri_disable);
1479
1480 void __cpuinit per_cpu_trap_init(void)
1481 {
1482 unsigned int cpu = smp_processor_id();
1483 unsigned int status_set = ST0_CU0;
1484 unsigned int hwrena = cpu_hwrena_impl_bits;
1485 #ifdef CONFIG_MIPS_MT_SMTC
1486 int secondaryTC = 0;
1487 int bootTC = (cpu == 0);
1488
1489 /*
1490 * Only do per_cpu_trap_init() for first TC of Each VPE.
1491 * Note that this hack assumes that the SMTC init code
1492 * assigns TCs consecutively and in ascending order.
1493 */
1494
1495 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1496 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1497 secondaryTC = 1;
1498 #endif /* CONFIG_MIPS_MT_SMTC */
1499
1500 /*
1501 * Disable coprocessors and select 32-bit or 64-bit addressing
1502 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1503 * flag that some firmware may have left set and the TS bit (for
1504 * IP27). Set XX for ISA IV code to work.
1505 */
1506 #ifdef CONFIG_64BIT
1507 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1508 #endif
1509 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1510 status_set |= ST0_XX;
1511 if (cpu_has_dsp)
1512 status_set |= ST0_MX;
1513
1514 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1515 status_set);
1516
1517 if (cpu_has_mips_r2)
1518 hwrena |= 0x0000000f;
1519
1520 if (!noulri && cpu_has_userlocal)
1521 hwrena |= (1 << 29);
1522
1523 if (hwrena)
1524 write_c0_hwrena(hwrena);
1525
1526 #ifdef CONFIG_MIPS_MT_SMTC
1527 if (!secondaryTC) {
1528 #endif /* CONFIG_MIPS_MT_SMTC */
1529
1530 if (cpu_has_veic || cpu_has_vint) {
1531 unsigned long sr = set_c0_status(ST0_BEV);
1532 write_c0_ebase(ebase);
1533 write_c0_status(sr);
1534 /* Setting vector spacing enables EI/VI mode */
1535 change_c0_intctl(0x3e0, VECTORSPACING);
1536 }
1537 if (cpu_has_divec) {
1538 if (cpu_has_mipsmt) {
1539 unsigned int vpflags = dvpe();
1540 set_c0_cause(CAUSEF_IV);
1541 evpe(vpflags);
1542 } else
1543 set_c0_cause(CAUSEF_IV);
1544 }
1545
1546 /*
1547 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1548 *
1549 * o read IntCtl.IPTI to determine the timer interrupt
1550 * o read IntCtl.IPPCI to determine the performance counter interrupt
1551 */
1552 if (cpu_has_mips_r2) {
1553 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP;
1554 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7;
1555 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7;
1556 if (cp0_perfcount_irq == cp0_compare_irq)
1557 cp0_perfcount_irq = -1;
1558 } else {
1559 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1560 cp0_compare_irq_shift = cp0_compare_irq;
1561 cp0_perfcount_irq = -1;
1562 }
1563
1564 #ifdef CONFIG_MIPS_MT_SMTC
1565 }
1566 #endif /* CONFIG_MIPS_MT_SMTC */
1567
1568 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1569 TLBMISS_HANDLER_SETUP();
1570
1571 atomic_inc(&init_mm.mm_count);
1572 current->active_mm = &init_mm;
1573 BUG_ON(current->mm);
1574 enter_lazy_tlb(&init_mm, current);
1575
1576 #ifdef CONFIG_MIPS_MT_SMTC
1577 if (bootTC) {
1578 #endif /* CONFIG_MIPS_MT_SMTC */
1579 cpu_cache_init();
1580 tlb_init();
1581 #ifdef CONFIG_MIPS_MT_SMTC
1582 } else if (!secondaryTC) {
1583 /*
1584 * First TC in non-boot VPE must do subset of tlb_init()
1585 * for MMU countrol registers.
1586 */
1587 write_c0_pagemask(PM_DEFAULT_MASK);
1588 write_c0_wired(0);
1589 }
1590 #endif /* CONFIG_MIPS_MT_SMTC */
1591 }
1592
1593 /* Install CPU exception handler */
1594 void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1595 {
1596 memcpy((void *)(ebase + offset), addr, size);
1597 local_flush_icache_range(ebase + offset, ebase + offset + size);
1598 }
1599
1600 static char panic_null_cerr[] __cpuinitdata =
1601 "Trying to set NULL cache error exception handler";
1602
1603 /*
1604 * Install uncached CPU exception handler.
1605 * This is suitable only for the cache error exception which is the only
1606 * exception handler that is being run uncached.
1607 */
1608 void __cpuinit set_uncached_handler(unsigned long offset, void *addr,
1609 unsigned long size)
1610 {
1611 unsigned long uncached_ebase = CKSEG1ADDR(ebase);
1612
1613 if (!addr)
1614 panic(panic_null_cerr);
1615
1616 memcpy((void *)(uncached_ebase + offset), addr, size);
1617 }
1618
1619 static int __initdata rdhwr_noopt;
1620 static int __init set_rdhwr_noopt(char *str)
1621 {
1622 rdhwr_noopt = 1;
1623 return 1;
1624 }
1625
1626 __setup("rdhwr_noopt", set_rdhwr_noopt);
1627
1628 void __init trap_init(void)
1629 {
1630 extern char except_vec3_generic, except_vec3_r4000;
1631 extern char except_vec4;
1632 unsigned long i;
1633 int rollback;
1634
1635 check_wait();
1636 rollback = (cpu_wait == r4k_wait);
1637
1638 #if defined(CONFIG_KGDB)
1639 if (kgdb_early_setup)
1640 return; /* Already done */
1641 #endif
1642
1643 if (cpu_has_veic || cpu_has_vint) {
1644 unsigned long size = 0x200 + VECTORSPACING*64;
1645 ebase = (unsigned long)
1646 __alloc_bootmem(size, 1 << fls(size), 0);
1647 } else {
1648 ebase = CKSEG0;
1649 if (cpu_has_mips_r2)
1650 ebase += (read_c0_ebase() & 0x3ffff000);
1651 }
1652
1653 per_cpu_trap_init();
1654
1655 /*
1656 * Copy the generic exception handlers to their final destination.
1657 * This will be overriden later as suitable for a particular
1658 * configuration.
1659 */
1660 set_handler(0x180, &except_vec3_generic, 0x80);
1661
1662 /*
1663 * Setup default vectors
1664 */
1665 for (i = 0; i <= 31; i++)
1666 set_except_vector(i, handle_reserved);
1667
1668 /*
1669 * Copy the EJTAG debug exception vector handler code to it's final
1670 * destination.
1671 */
1672 if (cpu_has_ejtag && board_ejtag_handler_setup)
1673 board_ejtag_handler_setup();
1674
1675 /*
1676 * Only some CPUs have the watch exceptions.
1677 */
1678 if (cpu_has_watch)
1679 set_except_vector(23, handle_watch);
1680
1681 /*
1682 * Initialise interrupt handlers
1683 */
1684 if (cpu_has_veic || cpu_has_vint) {
1685 int nvec = cpu_has_veic ? 64 : 8;
1686 for (i = 0; i < nvec; i++)
1687 set_vi_handler(i, NULL);
1688 }
1689 else if (cpu_has_divec)
1690 set_handler(0x200, &except_vec4, 0x8);
1691
1692 /*
1693 * Some CPUs can enable/disable for cache parity detection, but does
1694 * it different ways.
1695 */
1696 parity_protection_init();
1697
1698 /*
1699 * The Data Bus Errors / Instruction Bus Errors are signaled
1700 * by external hardware. Therefore these two exceptions
1701 * may have board specific handlers.
1702 */
1703 if (board_be_init)
1704 board_be_init();
1705
1706 set_except_vector(0, rollback ? rollback_handle_int : handle_int);
1707 set_except_vector(1, handle_tlbm);
1708 set_except_vector(2, handle_tlbl);
1709 set_except_vector(3, handle_tlbs);
1710
1711 set_except_vector(4, handle_adel);
1712 set_except_vector(5, handle_ades);
1713
1714 set_except_vector(6, handle_ibe);
1715 set_except_vector(7, handle_dbe);
1716
1717 set_except_vector(8, handle_sys);
1718 set_except_vector(9, handle_bp);
1719 set_except_vector(10, rdhwr_noopt ? handle_ri :
1720 (cpu_has_vtag_icache ?
1721 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1722 set_except_vector(11, handle_cpu);
1723 set_except_vector(12, handle_ov);
1724 set_except_vector(13, handle_tr);
1725
1726 if (current_cpu_type() == CPU_R6000 ||
1727 current_cpu_type() == CPU_R6000A) {
1728 /*
1729 * The R6000 is the only R-series CPU that features a machine
1730 * check exception (similar to the R4000 cache error) and
1731 * unaligned ldc1/sdc1 exception. The handlers have not been
1732 * written yet. Well, anyway there is no R6000 machine on the
1733 * current list of targets for Linux/MIPS.
1734 * (Duh, crap, there is someone with a triple R6k machine)
1735 */
1736 //set_except_vector(14, handle_mc);
1737 //set_except_vector(15, handle_ndc);
1738 }
1739
1740
1741 if (board_nmi_handler_setup)
1742 board_nmi_handler_setup();
1743
1744 if (cpu_has_fpu && !cpu_has_nofpuex)
1745 set_except_vector(15, handle_fpe);
1746
1747 set_except_vector(22, handle_mdmx);
1748
1749 if (cpu_has_mcheck)
1750 set_except_vector(24, handle_mcheck);
1751
1752 if (cpu_has_mipsmt)
1753 set_except_vector(25, handle_mt);
1754
1755 set_except_vector(26, handle_dsp);
1756
1757 if (cpu_has_vce)
1758 /* Special exception: R4[04]00 uses also the divec space. */
1759 memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100);
1760 else if (cpu_has_4kex)
1761 memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80);
1762 else
1763 memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80);
1764
1765 local_flush_icache_range(ebase, ebase + 0x400);
1766 flush_tlb_handlers();
1767
1768 sort_extable(__start___dbe_table, __stop___dbe_table);
1769
1770 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */
1771 }
kernel source for telekom puls (alcatel/mediatek)