arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/config.h>
  15 #include <linux/init.h>
  16 #include <linux/kernel.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/stddef.h>
  19
  20 #include <asm/cpu.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/system.h>
  24
  25 /*
  26  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  27  * the implementation of the "wait" feature differs between CPU families. This
  28  * points to the function that implements CPU specific wait.
  29  * The wait instruction stops the pipeline and reduces the power consumption of
  30  * the CPU very much.
  31  */
  32 void (*cpu_wait)(void) = NULL;
  33
  34 static void r3081_wait(void)
  35 {
  36         unsigned long cfg = read_c0_conf();
  37         write_c0_conf(cfg | R30XX_CONF_HALT);
  38 }
  39
  40 static void r39xx_wait(void)
  41 {
  42         unsigned long cfg = read_c0_conf();
  43         write_c0_conf(cfg | TX39_CONF_HALT);
  44 }
  45
  46 static void r4k_wait(void)
  47 {
  48         __asm__(".set\tmips3\n\t"
  49                 "wait\n\t"
  50                 ".set\tmips0");
  51 }
  52
  53 /* The Au1xxx wait is available only if using 32khz counter or
  54  * external timer source, but specifically not CP0 Counter. */
  55 int allow_au1k_wait;
  56
  57 static void au1k_wait(void)
  58 {
  59         /* using the wait instruction makes CP0 counter unusable */
  60         __asm__(".set mips3\n\t"
  61                 "cache 0x14, 0(%0)\n\t"
  62                 "cache 0x14, 32(%0)\n\t"
  63                 "sync\n\t"
  64                 "nop\n\t"
  65                 "wait\n\t"
  66                 "nop\n\t"
  67                 "nop\n\t"
  68                 "nop\n\t"
  69                 "nop\n\t"
  70                 ".set mips0\n\t"
  71                 : : "r" (au1k_wait));
  72 }
  73
  74 static int __initdata nowait = 0;
  75
  76 int __init wait_disable(char *s)
  77 {
  78         nowait = 1;
  79
  80         return 1;
  81 }
  82
  83 __setup("nowait", wait_disable);
  84
  85 static inline void check_wait(void)
  86 {
  87         struct cpuinfo_mips *c = &current_cpu_data;
  88
  89         printk("Checking for 'wait' instruction... ");
  90         if (nowait) {
  91                 printk (" disabled.\n");
  92                 return;
  93         }
  94
  95         switch (c->cputype) {
  96         case CPU_R3081:
  97         case CPU_R3081E:
  98                 cpu_wait = r3081_wait;
  99                 printk(" available.\n");
 100                 break;
 101         case CPU_TX3927:
 102                 cpu_wait = r39xx_wait;
 103                 printk(" available.\n");
 104                 break;
 105         case CPU_R4200:
 106 /*      case CPU_R4300: */
 107         case CPU_R4600:
 108         case CPU_R4640:
 109         case CPU_R4650:
 110         case CPU_R4700:
 111         case CPU_R5000:
 112         case CPU_NEVADA:
 113         case CPU_RM7000:
 114         case CPU_RM9000:
 115         case CPU_TX49XX:
 116         case CPU_4KC:
 117         case CPU_4KEC:
 118         case CPU_4KSC:
 119         case CPU_5KC:
 120 /*      case CPU_20KC:*/
 121         case CPU_24K:
 122         case CPU_25KF:
 123         case CPU_34K:
 124         case CPU_74K:
 125         case CPU_PR4450:
 126                 cpu_wait = r4k_wait;
 127                 printk(" available.\n");
 128                 break;
 129         case CPU_AU1000:
 130         case CPU_AU1100:
 131         case CPU_AU1500:
 132         case CPU_AU1550:
 133         case CPU_AU1200:
 134                 if (allow_au1k_wait) {
 135                         cpu_wait = au1k_wait;
 136                         printk(" available.\n");
 137                 } else
 138                         printk(" unavailable.\n");
 139                 break;
 140         default:
 141                 printk(" unavailable.\n");
 142                 break;
 143         }
 144 }
 145
 146 void __init check_bugs32(void)
 147 {
 148         check_wait();
 149 }
 150
 151 /*
 152  * Probe whether cpu has config register by trying to play with
 153  * alternate cache bit and see whether it matters.
 154  * It's used by cpu_probe to distinguish between R3000A and R3081.
 155  */
 156 static inline int cpu_has_confreg(void)
 157 {
 158 #ifdef CONFIG_CPU_R3000
 159         extern unsigned long r3k_cache_size(unsigned long);
 160         unsigned long size1, size2;
 161         unsigned long cfg = read_c0_conf();
 162
 163         size1 = r3k_cache_size(ST0_ISC);
 164         write_c0_conf(cfg ^ R30XX_CONF_AC);
 165         size2 = r3k_cache_size(ST0_ISC);
 166         write_c0_conf(cfg);
 167         return size1 != size2;
 168 #else
 169         return 0;
 170 #endif
 171 }
 172
 173 /*
 174  * Get the FPU Implementation/Revision.
 175  */
 176 static inline unsigned long cpu_get_fpu_id(void)
 177 {
 178         unsigned long tmp, fpu_id;
 179
 180         tmp = read_c0_status();
 181         __enable_fpu();
 182         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 183         write_c0_status(tmp);
 184         return fpu_id;
 185 }
 186
 187 /*
 188  * Check the CPU has an FPU the official way.
 189  */
 190 static inline int __cpu_has_fpu(void)
 191 {
 192         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 193 }
 194
 195 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 196                 | MIPS_CPU_COUNTER)
 197
 198 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
 199 {
 200         switch (c->processor_id & 0xff00) {
 201         case PRID_IMP_R2000:
 202                 c->cputype = CPU_R2000;
 203                 c->isa_level = MIPS_CPU_ISA_I;
 204                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 205                              MIPS_CPU_NOFPUEX;
 206                 if (__cpu_has_fpu())
 207                         c->options |= MIPS_CPU_FPU;
 208                 c->tlbsize = 64;
 209                 break;
 210         case PRID_IMP_R3000:
 211                 if ((c->processor_id & 0xff) == PRID_REV_R3000A)
 212                         if (cpu_has_confreg())
 213                                 c->cputype = CPU_R3081E;
 214                         else
 215                                 c->cputype = CPU_R3000A;
 216                 else
 217                         c->cputype = CPU_R3000;
 218                 c->isa_level = MIPS_CPU_ISA_I;
 219                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 220                              MIPS_CPU_NOFPUEX;
 221                 if (__cpu_has_fpu())
 222                         c->options |= MIPS_CPU_FPU;
 223                 c->tlbsize = 64;
 224                 break;
 225         case PRID_IMP_R4000:
 226                 if (read_c0_config() & CONF_SC) {
 227                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 228                                 c->cputype = CPU_R4400PC;
 229                         else
 230                                 c->cputype = CPU_R4000PC;
 231                 } else {
 232                         if ((c->processor_id & 0xff) >= PRID_REV_R4400)
 233                                 c->cputype = CPU_R4400SC;
 234                         else
 235                                 c->cputype = CPU_R4000SC;
 236                 }
 237
 238                 c->isa_level = MIPS_CPU_ISA_III;
 239                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 240                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 241                              MIPS_CPU_LLSC;
 242                 c->tlbsize = 48;
 243                 break;
 244         case PRID_IMP_VR41XX:
 245                 switch (c->processor_id & 0xf0) {
 246                 case PRID_REV_VR4111:
 247                         c->cputype = CPU_VR4111;
 248                         break;
 249                 case PRID_REV_VR4121:
 250                         c->cputype = CPU_VR4121;
 251                         break;
 252                 case PRID_REV_VR4122:
 253                         if ((c->processor_id & 0xf) < 0x3)
 254                                 c->cputype = CPU_VR4122;
 255                         else
 256                                 c->cputype = CPU_VR4181A;
 257                         break;
 258                 case PRID_REV_VR4130:
 259                         if ((c->processor_id & 0xf) < 0x4)
 260                                 c->cputype = CPU_VR4131;
 261                         else
 262                                 c->cputype = CPU_VR4133;
 263                         break;
 264                 default:
 265                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 266                         c->cputype = CPU_VR41XX;
 267                         break;
 268                 }
 269                 c->isa_level = MIPS_CPU_ISA_III;
 270                 c->options = R4K_OPTS;
 271                 c->tlbsize = 32;
 272                 break;
 273         case PRID_IMP_R4300:
 274                 c->cputype = CPU_R4300;
 275                 c->isa_level = MIPS_CPU_ISA_III;
 276                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 277                              MIPS_CPU_LLSC;
 278                 c->tlbsize = 32;
 279                 break;
 280         case PRID_IMP_R4600:
 281                 c->cputype = CPU_R4600;
 282                 c->isa_level = MIPS_CPU_ISA_III;
 283                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 284                              MIPS_CPU_LLSC;
 285                 c->tlbsize = 48;
 286                 break;
 287         #if 0
 288         case PRID_IMP_R4650:
 289                 /*
 290                  * This processor doesn't have an MMU, so it's not
 291                  * "real easy" to run Linux on it. It is left purely
 292                  * for documentation.  Commented out because it shares
 293                  * it's c0_prid id number with the TX3900.
 294                  */
 295                 c->cputype = CPU_R4650;
 296                 c->isa_level = MIPS_CPU_ISA_III;
 297                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 298                 c->tlbsize = 48;
 299                 break;
 300         #endif
 301         case PRID_IMP_TX39:
 302                 c->isa_level = MIPS_CPU_ISA_I;
 303                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 304
 305                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 306                         c->cputype = CPU_TX3927;
 307                         c->tlbsize = 64;
 308                 } else {
 309                         switch (c->processor_id & 0xff) {
 310                         case PRID_REV_TX3912:
 311                                 c->cputype = CPU_TX3912;
 312                                 c->tlbsize = 32;
 313                                 break;
 314                         case PRID_REV_TX3922:
 315                                 c->cputype = CPU_TX3922;
 316                                 c->tlbsize = 64;
 317                                 break;
 318                         default:
 319                                 c->cputype = CPU_UNKNOWN;
 320                                 break;
 321                         }
 322                 }
 323                 break;
 324         case PRID_IMP_R4700:
 325                 c->cputype = CPU_R4700;
 326                 c->isa_level = MIPS_CPU_ISA_III;
 327                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 328                              MIPS_CPU_LLSC;
 329                 c->tlbsize = 48;
 330                 break;
 331         case PRID_IMP_TX49:
 332                 c->cputype = CPU_TX49XX;
 333                 c->isa_level = MIPS_CPU_ISA_III;
 334                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 335                 if (!(c->processor_id & 0x08))
 336                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 337                 c->tlbsize = 48;
 338                 break;
 339         case PRID_IMP_R5000:
 340                 c->cputype = CPU_R5000;
 341                 c->isa_level = MIPS_CPU_ISA_IV;
 342                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 343                              MIPS_CPU_LLSC;
 344                 c->tlbsize = 48;
 345                 break;
 346         case PRID_IMP_R5432:
 347                 c->cputype = CPU_R5432;
 348                 c->isa_level = MIPS_CPU_ISA_IV;
 349                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 350                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 351                 c->tlbsize = 48;
 352                 break;
 353         case PRID_IMP_R5500:
 354                 c->cputype = CPU_R5500;
 355                 c->isa_level = MIPS_CPU_ISA_IV;
 356                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 357                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 358                 c->tlbsize = 48;
 359                 break;
 360         case PRID_IMP_NEVADA:
 361                 c->cputype = CPU_NEVADA;
 362                 c->isa_level = MIPS_CPU_ISA_IV;
 363                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 364                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 365                 c->tlbsize = 48;
 366                 break;
 367         case PRID_IMP_R6000:
 368                 c->cputype = CPU_R6000;
 369                 c->isa_level = MIPS_CPU_ISA_II;
 370                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 371                              MIPS_CPU_LLSC;
 372                 c->tlbsize = 32;
 373                 break;
 374         case PRID_IMP_R6000A:
 375                 c->cputype = CPU_R6000A;
 376                 c->isa_level = MIPS_CPU_ISA_II;
 377                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 378                              MIPS_CPU_LLSC;
 379                 c->tlbsize = 32;
 380                 break;
 381         case PRID_IMP_RM7000:
 382                 c->cputype = CPU_RM7000;
 383                 c->isa_level = MIPS_CPU_ISA_IV;
 384                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 385                              MIPS_CPU_LLSC;
 386                 /*
 387                  * Undocumented RM7000:  Bit 29 in the info register of
 388                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 389                  * entries.
 390                  *
 391                  * 29      1 =>    64 entry JTLB
 392                  *         0 =>    48 entry JTLB
 393                  */
 394                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 395                 break;
 396         case PRID_IMP_RM9000:
 397                 c->cputype = CPU_RM9000;
 398                 c->isa_level = MIPS_CPU_ISA_IV;
 399                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 400                              MIPS_CPU_LLSC;
 401                 /*
 402                  * Bit 29 in the info register of the RM9000
 403                  * indicates if the TLB has 48 or 64 entries.
 404                  *
 405                  * 29      1 =>    64 entry JTLB
 406                  *         0 =>    48 entry JTLB
 407                  */
 408                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 409                 break;
 410         case PRID_IMP_R8000:
 411                 c->cputype = CPU_R8000;
 412                 c->isa_level = MIPS_CPU_ISA_IV;
 413                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 414                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 415                              MIPS_CPU_LLSC;
 416                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 417                 break;
 418         case PRID_IMP_R10000:
 419                 c->cputype = CPU_R10000;
 420                 c->isa_level = MIPS_CPU_ISA_IV;
 421                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 422                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 423                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 424                              MIPS_CPU_LLSC;
 425                 c->tlbsize = 64;
 426                 break;
 427         case PRID_IMP_R12000:
 428                 c->cputype = CPU_R12000;
 429                 c->isa_level = MIPS_CPU_ISA_IV;
 430                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 431                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 432                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 433                              MIPS_CPU_LLSC;
 434                 c->tlbsize = 64;
 435                 break;
 436         case PRID_IMP_R14000:
 437                 c->cputype = CPU_R14000;
 438                 c->isa_level = MIPS_CPU_ISA_IV;
 439                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 440                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 441                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 442                              MIPS_CPU_LLSC;
 443                 c->tlbsize = 64;
 444                 break;
 445         }
 446 }
 447
 448 static char unknown_isa[] __initdata = KERN_ERR \
 449         "Unsupported ISA type, c0.config0: %d.";
 450
 451 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 452 {
 453         unsigned int config0;
 454         int isa;
 455
 456         config0 = read_c0_config();
 457
 458         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 459                 c->options |= MIPS_CPU_TLB;
 460         isa = (config0 & MIPS_CONF_AT) >> 13;
 461         switch (isa) {
 462         case 0:
 463                 switch ((config0 >> 10) & 7) {
 464                 case 0:
 465                         c->isa_level = MIPS_CPU_ISA_M32R1;
 466                         break;
 467                 case 1:
 468                         c->isa_level = MIPS_CPU_ISA_M32R2;
 469                         break;
 470                 default:
 471                         goto unknown;
 472                 }
 473                 break;
 474         case 2:
 475                 switch ((config0 >> 10) & 7) {
 476                 case 0:
 477                         c->isa_level = MIPS_CPU_ISA_M64R1;
 478                         break;
 479                 case 1:
 480                         c->isa_level = MIPS_CPU_ISA_M64R2;
 481                         break;
 482                 default:
 483                         goto unknown;
 484                 }
 485                 break;
 486         default:
 487                 goto unknown;
 488         }
 489
 490         return config0 & MIPS_CONF_M;
 491
 492 unknown:
 493         panic(unknown_isa, config0);
 494 }
 495
 496 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 497 {
 498         unsigned int config1;
 499
 500         config1 = read_c0_config1();
 501
 502         if (config1 & MIPS_CONF1_MD)
 503                 c->ases |= MIPS_ASE_MDMX;
 504         if (config1 & MIPS_CONF1_WR)
 505                 c->options |= MIPS_CPU_WATCH;
 506         if (config1 & MIPS_CONF1_CA)
 507                 c->ases |= MIPS_ASE_MIPS16;
 508         if (config1 & MIPS_CONF1_EP)
 509                 c->options |= MIPS_CPU_EJTAG;
 510         if (config1 & MIPS_CONF1_FP) {
 511                 c->options |= MIPS_CPU_FPU;
 512                 c->options |= MIPS_CPU_32FPR;
 513         }
 514         if (cpu_has_tlb)
 515                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 516
 517         return config1 & MIPS_CONF_M;
 518 }
 519
 520 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 521 {
 522         unsigned int config2;
 523
 524         config2 = read_c0_config2();
 525
 526         if (config2 & MIPS_CONF2_SL)
 527                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 528
 529         return config2 & MIPS_CONF_M;
 530 }
 531
 532 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 533 {
 534         unsigned int config3;
 535
 536         config3 = read_c0_config3();
 537
 538         if (config3 & MIPS_CONF3_SM)
 539                 c->ases |= MIPS_ASE_SMARTMIPS;
 540         if (config3 & MIPS_CONF3_DSP)
 541                 c->ases |= MIPS_ASE_DSP;
 542         if (config3 & MIPS_CONF3_VINT)
 543                 c->options |= MIPS_CPU_VINT;
 544         if (config3 & MIPS_CONF3_VEIC)
 545                 c->options |= MIPS_CPU_VEIC;
 546         if (config3 & MIPS_CONF3_MT)
 547                 c->ases |= MIPS_ASE_MIPSMT;
 548
 549         return config3 & MIPS_CONF_M;
 550 }
 551
 552 static inline void decode_configs(struct cpuinfo_mips *c)
 553 {
 554         /* MIPS32 or MIPS64 compliant CPU.  */
 555         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 556                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 557
 558         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 559
 560         /* Read Config registers.  */
 561         if (!decode_config0(c))
 562                 return;                 /* actually worth a panic() */
 563         if (!decode_config1(c))
 564                 return;
 565         if (!decode_config2(c))
 566                 return;
 567         if (!decode_config3(c))
 568                 return;
 569 }
 570
 571 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 572 {
 573         decode_configs(c);
 574         switch (c->processor_id & 0xff00) {
 575         case PRID_IMP_4KC:
 576                 c->cputype = CPU_4KC;
 577                 break;
 578         case PRID_IMP_4KEC:
 579                 c->cputype = CPU_4KEC;
 580                 break;
 581         case PRID_IMP_4KECR2:
 582                 c->cputype = CPU_4KEC;
 583                 break;
 584         case PRID_IMP_4KSC:
 585         case PRID_IMP_4KSD:
 586                 c->cputype = CPU_4KSC;
 587                 break;
 588         case PRID_IMP_5KC:
 589                 c->cputype = CPU_5KC;
 590                 break;
 591         case PRID_IMP_20KC:
 592                 c->cputype = CPU_20KC;
 593                 break;
 594         case PRID_IMP_24K:
 595         case PRID_IMP_24KE:
 596                 c->cputype = CPU_24K;
 597                 break;
 598         case PRID_IMP_25KF:
 599                 c->cputype = CPU_25KF;
 600                 /* Probe for L2 cache */
 601                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 602                 break;
 603         case PRID_IMP_34K:
 604                 c->cputype = CPU_34K;
 605                 break;
 606         case PRID_IMP_74K:
 607                 c->cputype = CPU_74K;
 608                 break;
 609         }
 610 }
 611
 612 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 613 {
 614         decode_configs(c);
 615         switch (c->processor_id & 0xff00) {
 616         case PRID_IMP_AU1_REV1:
 617         case PRID_IMP_AU1_REV2:
 618                 switch ((c->processor_id >> 24) & 0xff) {
 619                 case 0:
 620                         c->cputype = CPU_AU1000;
 621                         break;
 622                 case 1:
 623                         c->cputype = CPU_AU1500;
 624                         break;
 625                 case 2:
 626                         c->cputype = CPU_AU1100;
 627                         break;
 628                 case 3:
 629                         c->cputype = CPU_AU1550;
 630                         break;
 631                 case 4:
 632                         c->cputype = CPU_AU1200;
 633                         break;
 634                 default:
 635                         panic("Unknown Au Core!");
 636                         break;
 637                 }
 638                 break;
 639         }
 640 }
 641
 642 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 643 {
 644         decode_configs(c);
 645
 646         /*
 647          * For historical reasons the SB1 comes with it's own variant of
 648          * cache code which eventually will be folded into c-r4k.c.  Until
 649          * then we pretend it's got it's own cache architecture.
 650          */
 651         c->options &= ~MIPS_CPU_4K_CACHE;
 652         c->options |= MIPS_CPU_SB1_CACHE;
 653
 654         switch (c->processor_id & 0xff00) {
 655         case PRID_IMP_SB1:
 656                 c->cputype = CPU_SB1;
 657                 /* FPU in pass1 is known to have issues. */
 658                 if ((c->processor_id & 0xff) < 0x20)
 659                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 660                 break;
 661         case PRID_IMP_SB1A:
 662                 c->cputype = CPU_SB1A;
 663                 break;
 664         }
 665 }
 666
 667 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
 668 {
 669         decode_configs(c);
 670         switch (c->processor_id & 0xff00) {
 671         case PRID_IMP_SR71000:
 672                 c->cputype = CPU_SR71000;
 673                 c->scache.ways = 8;
 674                 c->tlbsize = 64;
 675                 break;
 676         }
 677 }
 678
 679 static inline void cpu_probe_philips(struct cpuinfo_mips *c)
 680 {
 681         decode_configs(c);
 682         switch (c->processor_id & 0xff00) {
 683         case PRID_IMP_PR4450:
 684                 c->cputype = CPU_PR4450;
 685                 c->isa_level = MIPS_CPU_ISA_M32R1;
 686                 break;
 687         default:
 688                 panic("Unknown Philips Core!"); /* REVISIT: die? */
 689                 break;
 690         }
 691 }
 692
 693
 694 __init void cpu_probe(void)
 695 {
 696         struct cpuinfo_mips *c = &current_cpu_data;
 697
 698         c->processor_id = PRID_IMP_UNKNOWN;
 699         c->fpu_id       = FPIR_IMP_NONE;
 700         c->cputype      = CPU_UNKNOWN;
 701
 702         c->processor_id = read_c0_prid();
 703         switch (c->processor_id & 0xff0000) {
 704         case PRID_COMP_LEGACY:
 705                 cpu_probe_legacy(c);
 706                 break;
 707         case PRID_COMP_MIPS:
 708                 cpu_probe_mips(c);
 709                 break;
 710         case PRID_COMP_ALCHEMY:
 711                 cpu_probe_alchemy(c);
 712                 break;
 713         case PRID_COMP_SIBYTE:
 714                 cpu_probe_sibyte(c);
 715                 break;
 716         case PRID_COMP_SANDCRAFT:
 717                 cpu_probe_sandcraft(c);
 718                 break;
 719         case PRID_COMP_PHILIPS:
 720                 cpu_probe_philips(c);
 721                 break;
 722         default:
 723                 c->cputype = CPU_UNKNOWN;
 724         }
 725         if (c->options & MIPS_CPU_FPU) {
 726                 c->fpu_id = cpu_get_fpu_id();
 727
 728                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
 729                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
 730                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
 731                     c->isa_level == MIPS_CPU_ISA_M64R2) {
 732                         if (c->fpu_id & MIPS_FPIR_3D)
 733                                 c->ases |= MIPS_ASE_MIPS3D;
 734                 }
 735         }
 736 }
 737
 738 __init void cpu_report(void)
 739 {
 740         struct cpuinfo_mips *c = &current_cpu_data;
 741
 742         printk("CPU revision is: %08x\n", c->processor_id);
 743         if (c->options & MIPS_CPU_FPU)
 744                 printk("FPU revision is: %08x\n", c->fpu_id);
 745 }