arch/mips/include/asm/war.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2002, 2004, 2007 by Ralf Baechle
   7  * Copyright (C) 2007  Maciej W. Rozycki
   8  */
   9 #ifndef _ASM_WAR_H
  10 #define _ASM_WAR_H
  11
  12 #include <war.h>
  13
  14 /*
  15  * Work around certain R4000 CPU errata (as implemented by GCC):
  16  *
  17  * - A double-word or a variable shift may give an incorrect result
  18  *   if executed immediately after starting an integer division:
  19  *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
  20  *   erratum #28
  21  *   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
  22  *   #19
  23  *
  24  * - A double-word or a variable shift may give an incorrect result
  25  *   if executed while an integer multiplication is in progress:
  26  *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
  27  *   errata #16 & #28
  28  *
  29  * - An integer division may give an incorrect result if started in
  30  *   a delay slot of a taken branch or a jump:
  31  *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
  32  *   erratum #52
  33  */
  34 #ifdef CONFIG_CPU_R4000_WORKAROUNDS
  35 #define R4000_WAR 1
  36 #else
  37 #define R4000_WAR 0
  38 #endif
  39
  40 /*
  41  * Work around certain R4400 CPU errata (as implemented by GCC):
  42  *
  43  * - A double-word or a variable shift may give an incorrect result
  44  *   if executed immediately after starting an integer division:
  45  *   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
  46  *   "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
  47  */
  48 #ifdef CONFIG_CPU_R4400_WORKAROUNDS
  49 #define R4400_WAR 1
  50 #else
  51 #define R4400_WAR 0
  52 #endif
  53
  54 /*
  55  * Work around the "daddi" and "daddiu" CPU errata:
  56  *
  57  * - The `daddi' instruction fails to trap on overflow.
  58  *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
  59  *   erratum #23
  60  *
  61  * - The `daddiu' instruction can produce an incorrect result.
  62  *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
  63  *   erratum #41
  64  *   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
  65  *   #15
  66  *   "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
  67  *   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
  68  */
  69 #ifdef CONFIG_CPU_DADDI_WORKAROUNDS
  70 #define DADDI_WAR 1
  71 #else
  72 #define DADDI_WAR 0
  73 #endif
  74
  75 /*
  76  * Another R4600 erratum.  Due to the lack of errata information the exact
  77  * technical details aren't known.  I've experimentally found that disabling
  78  * interrupts during indexed I-cache flushes seems to be sufficient to deal
  79  * with the issue.
  80  */
  81 #ifndef R4600_V1_INDEX_ICACHEOP_WAR
  82 #error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
  83 #endif
  84
  85 /*
  86  * Pleasures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:
  87  *
  88  *  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
  89  *      Hit_Invalidate_D and Create_Dirty_Excl_D should only be
  90  *      executed if there is no other dcache activity. If the dcache is
  91  *      accessed for another instruction immeidately preceding when these
  92  *      cache instructions are executing, it is possible that the dcache
  93  *      tag match outputs used by these cache instructions will be
  94  *      incorrect. These cache instructions should be preceded by at least
  95  *      four instructions that are not any kind of load or store
  96  *      instruction.
  97  *
  98  *      This is not allowed:    lw
  99  *                              nop
 100  *                              nop
 101  *                              nop
 102  *                              cache       Hit_Writeback_Invalidate_D
 103  *
 104  *      This is allowed:        lw
 105  *                              nop
 106  *                              nop
 107  *                              nop
 108  *                              nop
 109  *                              cache       Hit_Writeback_Invalidate_D
 110  */
 111 #ifndef R4600_V1_HIT_CACHEOP_WAR
 112 #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
 113 #endif
 114
 115
 116 /*
 117  * Writeback and invalidate the primary cache dcache before DMA.
 118  *
 119  * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
 120  * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
 121  * operate correctly if the internal data cache refill buffer is empty.  These
 122  * CACHE instructions should be separated from any potential data cache miss
 123  * by a load instruction to an uncached address to empty the response buffer."
 124  * (Revision 2.0 device errata from IDT available on http://www.idt.com/
 125  * in .pdf format.)
 126  */
 127 #ifndef R4600_V2_HIT_CACHEOP_WAR
 128 #error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
 129 #endif
 130
 131 /*
 132  * When an interrupt happens on a CP0 register read instruction, CPU may
 133  * lock up or read corrupted values of CP0 registers after it enters
 134  * the exception handler.
 135  *
 136  * This workaround makes sure that we read a "safe" CP0 register as the
 137  * first thing in the exception handler, which breaks one of the
 138  * pre-conditions for this problem.
 139  */
 140 #ifndef R5432_CP0_INTERRUPT_WAR
 141 #error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
 142 #endif
 143
 144 /*
 145  * Workaround for the Sibyte M3 errata the text of which can be found at
 146  *
 147  *   http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
 148  *
 149  * This will enable the use of a special TLB refill handler which does a
 150  * consistency check on the information in c0_badvaddr and c0_entryhi and
 151  * will just return and take the exception again if the information was
 152  * found to be inconsistent.
 153  */
 154 #ifndef BCM1250_M3_WAR
 155 #error Check setting of BCM1250_M3_WAR for your platform
 156 #endif
 157
 158 /*
 159  * This is a DUART workaround related to glitches around register accesses
 160  */
 161 #ifndef SIBYTE_1956_WAR
 162 #error Check setting of SIBYTE_1956_WAR for your platform
 163 #endif
 164
 165 /*
 166  * Fill buffers not flushed on CACHE instructions
 167  *
 168  * Hit_Invalidate_I cacheops invalidate an icache line but the refill
 169  * for that line can get stale data from the fill buffer instead of
 170  * accessing memory if the previous icache miss was also to that line.
 171  *
 172  * Workaround: generate an icache refill from a different line
 173  *
 174  * Affects:
 175  *  MIPS 4K             RTL revision <3.0, PRID revision <4
 176  */
 177 #ifndef MIPS4K_ICACHE_REFILL_WAR
 178 #error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
 179 #endif
 180
 181 /*
 182  * Missing implicit forced flush of evictions caused by CACHE
 183  * instruction
 184  *
 185  * Evictions caused by a CACHE instructions are not forced on to the
 186  * bus. The BIU gives higher priority to fetches than to the data from
 187  * the eviction buffer and no collision detection is performed between
 188  * fetches and pending data from the eviction buffer.
 189  *
 190  * Workaround: Execute a SYNC instruction after the cache instruction
 191  *
 192  * Affects:
 193  *   MIPS 5Kc,5Kf       RTL revision <2.3, PRID revision <8
 194  *   MIPS 20Kc          RTL revision <4.0, PRID revision <?
 195  */
 196 #ifndef MIPS_CACHE_SYNC_WAR
 197 #error Check setting of MIPS_CACHE_SYNC_WAR for your platform
 198 #endif
 199
 200 /*
 201  * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
 202  * the line which this instruction itself exists, the following
 203  * operation is not guaranteed."
 204  *
 205  * Workaround: do two phase flushing for Index_Invalidate_I
 206  */
 207 #ifndef TX49XX_ICACHE_INDEX_INV_WAR
 208 #error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
 209 #endif
 210
 211 /*
 212  * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
 213  * opposes it being called that) where invalid instructions in the same
 214  * I-cache line worth of instructions being fetched may case spurious
 215  * exceptions.
 216  */
 217 #ifndef ICACHE_REFILLS_WORKAROUND_WAR
 218 #error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
 219 #endif
 220
 221 /*
 222  * On the R10000 up to version 2.6 (not sure about 2.7) there is a bug that
 223  * may cause ll / sc and lld / scd sequences to execute non-atomically.
 224  */
 225 #ifndef R10000_LLSC_WAR
 226 #error Check setting of R10000_LLSC_WAR for your platform
 227 #endif
 228
 229 /*
 230  * 34K core erratum: "Problems Executing the TLBR Instruction"
 231  */
 232 #ifndef MIPS34K_MISSED_ITLB_WAR
 233 #error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
 234 #endif
 235
 236 #endif /* _ASM_WAR_H */