2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2004-2007 Cavium Networks
7 * Copyright (C) 2008, 2009 Wind River Systems
8 * written by Ralf Baechle <ralf@linux-mips.org>
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/console.h>
13 #include <linux/delay.h>
14 #include <linux/export.h>
15 #include <linux/interrupt.h>
17 #include <linux/serial.h>
18 #include <linux/smp.h>
19 #include <linux/types.h>
20 #include <linux/string.h> /* for memset */
21 #include <linux/tty.h>
22 #include <linux/time.h>
23 #include <linux/platform_device.h>
24 #include <linux/serial_core.h>
25 #include <linux/serial_8250.h>
26 #include <linux/of_fdt.h>
27 #include <linux/libfdt.h>
29 #include <asm/processor.h>
30 #include <asm/reboot.h>
31 #include <asm/smp-ops.h>
32 #include <asm/irq_cpu.h>
33 #include <asm/mipsregs.h>
34 #include <asm/bootinfo.h>
35 #include <asm/sections.h>
38 #include <asm/octeon/octeon.h>
39 #include <asm/octeon/pci-octeon.h>
40 #include <asm/octeon/cvmx-mio-defs.h>
42 #ifdef CONFIG_CAVIUM_DECODE_RSL
43 extern void cvmx_interrupt_rsl_decode(void);
44 extern int __cvmx_interrupt_ecc_report_single_bit_errors
;
45 extern void cvmx_interrupt_rsl_enable(void);
48 extern struct plat_smp_ops octeon_smp_ops
;
51 extern void pci_console_init(const char *arg
);
54 static unsigned long long MAX_MEMORY
= 512ull << 20;
56 struct octeon_boot_descriptor
*octeon_boot_desc_ptr
;
58 struct cvmx_bootinfo
*octeon_bootinfo
;
59 EXPORT_SYMBOL(octeon_bootinfo
);
61 #ifdef CONFIG_CAVIUM_RESERVE32
62 uint64_t octeon_reserve32_memory
;
63 EXPORT_SYMBOL(octeon_reserve32_memory
);
66 static int octeon_uart
;
68 extern asmlinkage
void handle_int(void);
69 extern asmlinkage
void plat_irq_dispatch(void);
72 * Return non zero if we are currently running in the Octeon simulator
76 int octeon_is_simulation(void)
78 return octeon_bootinfo
->board_type
== CVMX_BOARD_TYPE_SIM
;
80 EXPORT_SYMBOL(octeon_is_simulation
);
83 * Return true if Octeon is in PCI Host mode. This means
84 * Linux can control the PCI bus.
86 * Returns Non zero if Octeon in host mode.
88 int octeon_is_pci_host(void)
91 return octeon_bootinfo
->config_flags
& CVMX_BOOTINFO_CFG_FLAG_PCI_HOST
;
98 * Get the clock rate of Octeon
100 * Returns Clock rate in HZ
102 uint64_t octeon_get_clock_rate(void)
104 struct cvmx_sysinfo
*sysinfo
= cvmx_sysinfo_get();
106 return sysinfo
->cpu_clock_hz
;
108 EXPORT_SYMBOL(octeon_get_clock_rate
);
110 static u64 octeon_io_clock_rate
;
112 u64
octeon_get_io_clock_rate(void)
114 return octeon_io_clock_rate
;
116 EXPORT_SYMBOL(octeon_get_io_clock_rate
);
120 * Write to the LCD display connected to the bootbus. This display
121 * exists on most Cavium evaluation boards. If it doesn't exist, then
122 * this function doesn't do anything.
124 * @s: String to write
126 void octeon_write_lcd(const char *s
)
128 if (octeon_bootinfo
->led_display_base_addr
) {
129 void __iomem
*lcd_address
=
130 ioremap_nocache(octeon_bootinfo
->led_display_base_addr
,
133 for (i
= 0; i
< 8; i
++, s
++) {
135 iowrite8(*s
, lcd_address
+ i
);
137 iowrite8(' ', lcd_address
+ i
);
139 iounmap(lcd_address
);
144 * Return the console uart passed by the bootloader
146 * Returns uart (0 or 1)
148 int octeon_get_boot_uart(void)
151 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
154 uart
= (octeon_boot_desc_ptr
->flags
& OCTEON_BL_FLAG_CONSOLE_UART1
) ?
161 * Get the coremask Linux was booted on.
165 int octeon_get_boot_coremask(void)
167 return octeon_boot_desc_ptr
->core_mask
;
171 * Check the hardware BIST results for a CPU
173 void octeon_check_cpu_bist(void)
175 const int coreid
= cvmx_get_core_num();
176 unsigned long long mask
;
177 unsigned long long bist_val
;
179 /* Check BIST results for COP0 registers */
180 mask
= 0x1f00000000ull
;
181 bist_val
= read_octeon_c0_icacheerr();
183 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
186 bist_val
= read_octeon_c0_dcacheerr();
188 pr_err("Core%d L1 Dcache parity error: "
189 "CacheErr(dcache) = 0x%llx\n",
192 mask
= 0xfc00000000000000ull
;
193 bist_val
= read_c0_cvmmemctl();
195 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
198 write_octeon_c0_dcacheerr(0);
204 * @command: Command to pass to the bootloader. Currently ignored.
206 static void octeon_restart(char *command
)
208 /* Disable all watchdogs before soft reset. They don't get cleared */
211 for_each_online_cpu(cpu
)
212 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu
)), 0);
214 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
219 cvmx_write_csr(CVMX_CIU_SOFT_RST
, 1);
224 * Permanently stop a core.
228 static void octeon_kill_core(void *arg
)
231 if (octeon_is_simulation()) {
232 /* The simulator needs the watchdog to stop for dead cores */
233 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
234 /* A break instruction causes the simulator stop a core */
235 asm volatile ("sync\nbreak");
243 static void octeon_halt(void)
245 smp_call_function(octeon_kill_core
, NULL
, 0);
247 switch (octeon_bootinfo
->board_type
) {
248 case CVMX_BOARD_TYPE_NAO38
:
249 /* Driving a 1 to GPIO 12 shuts off this board */
250 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
251 cvmx_write_csr(CVMX_GPIO_TX_SET
, 0x1000);
254 octeon_write_lcd("PowerOff");
258 octeon_kill_core(NULL
);
262 * Handle all the error condition interrupts that might occur.
265 #ifdef CONFIG_CAVIUM_DECODE_RSL
266 static irqreturn_t
octeon_rlm_interrupt(int cpl
, void *dev_id
)
268 cvmx_interrupt_rsl_decode();
274 * Return a string representing the system type
278 const char *octeon_board_type_string(void)
280 static char name
[80];
281 sprintf(name
, "%s (%s)",
282 cvmx_board_type_to_string(octeon_bootinfo
->board_type
),
283 octeon_model_get_string(read_c0_prid()));
287 const char *get_system_type(void)
288 __attribute__ ((alias("octeon_board_type_string")));
290 void octeon_user_io_init(void)
292 union octeon_cvmemctl cvmmemctl
;
293 union cvmx_iob_fau_timeout fau_timeout
;
294 union cvmx_pow_nw_tim nm_tim
;
296 /* Get the current settings for CP0_CVMMEMCTL_REG */
297 cvmmemctl
.u64
= read_c0_cvmmemctl();
298 /* R/W If set, marked write-buffer entries time out the same
299 * as as other entries; if clear, marked write-buffer entries
300 * use the maximum timeout. */
301 cvmmemctl
.s
.dismarkwblongto
= 1;
302 /* R/W If set, a merged store does not clear the write-buffer
303 * entry timeout state. */
304 cvmmemctl
.s
.dismrgclrwbto
= 0;
305 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
306 * word location for an IOBDMA. The other 8 bits come from the
307 * SCRADDR field of the IOBDMA. */
308 cvmmemctl
.s
.iobdmascrmsb
= 0;
309 /* R/W If set, SYNCWS and SYNCS only order marked stores; if
310 * clear, SYNCWS and SYNCS only order unmarked
311 * stores. SYNCWSMARKED has no effect when DISSYNCWS is
313 cvmmemctl
.s
.syncwsmarked
= 0;
314 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
315 cvmmemctl
.s
.dissyncws
= 0;
316 /* R/W If set, no stall happens on write buffer full. */
317 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2
))
318 cvmmemctl
.s
.diswbfst
= 1;
320 cvmmemctl
.s
.diswbfst
= 0;
321 /* R/W If set (and SX set), supervisor-level loads/stores can
322 * use XKPHYS addresses with <48>==0 */
323 cvmmemctl
.s
.xkmemenas
= 0;
325 /* R/W If set (and UX set), user-level loads/stores can use
326 * XKPHYS addresses with VA<48>==0 */
327 cvmmemctl
.s
.xkmemenau
= 0;
329 /* R/W If set (and SX set), supervisor-level loads/stores can
330 * use XKPHYS addresses with VA<48>==1 */
331 cvmmemctl
.s
.xkioenas
= 0;
333 /* R/W If set (and UX set), user-level loads/stores can use
334 * XKPHYS addresses with VA<48>==1 */
335 cvmmemctl
.s
.xkioenau
= 0;
337 /* R/W If set, all stores act as SYNCW (NOMERGE must be set
338 * when this is set) RW, reset to 0. */
339 cvmmemctl
.s
.allsyncw
= 0;
341 /* R/W If set, no stores merge, and all stores reach the
342 * coherent bus in order. */
343 cvmmemctl
.s
.nomerge
= 0;
344 /* R/W Selects the bit in the counter used for DID time-outs 0
345 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
346 * between 1x and 2x this interval. For example, with
347 * DIDTTO=3, expiration interval is between 16K and 32K. */
348 cvmmemctl
.s
.didtto
= 0;
349 /* R/W If set, the (mem) CSR clock never turns off. */
350 cvmmemctl
.s
.csrckalwys
= 0;
351 /* R/W If set, mclk never turns off. */
352 cvmmemctl
.s
.mclkalwys
= 0;
353 /* R/W Selects the bit in the counter used for write buffer
354 * flush time-outs (WBFLT+11) is the bit position in an
355 * internal counter used to determine expiration. The write
356 * buffer expires between 1x and 2x this interval. For
357 * example, with WBFLT = 0, a write buffer expires between 2K
358 * and 4K cycles after the write buffer entry is allocated. */
359 cvmmemctl
.s
.wbfltime
= 0;
360 /* R/W If set, do not put Istream in the L2 cache. */
361 cvmmemctl
.s
.istrnol2
= 0;
364 * R/W The write buffer threshold. As per erratum Core-14752
365 * for CN63XX, a sc/scd might fail if the write buffer is
366 * full. Lowering WBTHRESH greatly lowers the chances of the
367 * write buffer ever being full and triggering the erratum.
369 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X
))
370 cvmmemctl
.s
.wbthresh
= 4;
372 cvmmemctl
.s
.wbthresh
= 10;
374 /* R/W If set, CVMSEG is available for loads/stores in
375 * kernel/debug mode. */
376 #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
377 cvmmemctl
.s
.cvmsegenak
= 1;
379 cvmmemctl
.s
.cvmsegenak
= 0;
381 /* R/W If set, CVMSEG is available for loads/stores in
382 * supervisor mode. */
383 cvmmemctl
.s
.cvmsegenas
= 0;
384 /* R/W If set, CVMSEG is available for loads/stores in user
386 cvmmemctl
.s
.cvmsegenau
= 0;
387 /* R/W Size of local memory in cache blocks, 54 (6912 bytes)
388 * is max legal value. */
389 cvmmemctl
.s
.lmemsz
= CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
;
391 write_c0_cvmmemctl(cvmmemctl
.u64
);
393 if (smp_processor_id() == 0)
394 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
395 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
,
396 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
* 128);
398 /* Set a default for the hardware timeouts */
400 fau_timeout
.s
.tout_val
= 0xfff;
401 /* Disable tagwait FAU timeout */
402 fau_timeout
.s
.tout_enb
= 0;
403 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT
, fau_timeout
.u64
);
408 cvmx_write_csr(CVMX_POW_NW_TIM
, nm_tim
.u64
);
410 write_octeon_c0_icacheerr(0);
411 write_c0_derraddr1(0);
415 * Early entry point for arch setup
417 void __init
prom_init(void)
419 struct cvmx_sysinfo
*sysinfo
;
422 #ifdef CONFIG_CAVIUM_RESERVE32
426 * The bootloader passes a pointer to the boot descriptor in
427 * $a3, this is available as fw_arg3.
429 octeon_boot_desc_ptr
= (struct octeon_boot_descriptor
*)fw_arg3
;
431 cvmx_phys_to_ptr(octeon_boot_desc_ptr
->cvmx_desc_vaddr
);
432 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo
->phy_mem_desc_addr
));
434 sysinfo
= cvmx_sysinfo_get();
435 memset(sysinfo
, 0, sizeof(*sysinfo
));
436 sysinfo
->system_dram_size
= octeon_bootinfo
->dram_size
<< 20;
437 sysinfo
->phy_mem_desc_ptr
=
438 cvmx_phys_to_ptr(octeon_bootinfo
->phy_mem_desc_addr
);
439 sysinfo
->core_mask
= octeon_bootinfo
->core_mask
;
440 sysinfo
->exception_base_addr
= octeon_bootinfo
->exception_base_addr
;
441 sysinfo
->cpu_clock_hz
= octeon_bootinfo
->eclock_hz
;
442 sysinfo
->dram_data_rate_hz
= octeon_bootinfo
->dclock_hz
* 2;
443 sysinfo
->board_type
= octeon_bootinfo
->board_type
;
444 sysinfo
->board_rev_major
= octeon_bootinfo
->board_rev_major
;
445 sysinfo
->board_rev_minor
= octeon_bootinfo
->board_rev_minor
;
446 memcpy(sysinfo
->mac_addr_base
, octeon_bootinfo
->mac_addr_base
,
447 sizeof(sysinfo
->mac_addr_base
));
448 sysinfo
->mac_addr_count
= octeon_bootinfo
->mac_addr_count
;
449 memcpy(sysinfo
->board_serial_number
,
450 octeon_bootinfo
->board_serial_number
,
451 sizeof(sysinfo
->board_serial_number
));
452 sysinfo
->compact_flash_common_base_addr
=
453 octeon_bootinfo
->compact_flash_common_base_addr
;
454 sysinfo
->compact_flash_attribute_base_addr
=
455 octeon_bootinfo
->compact_flash_attribute_base_addr
;
456 sysinfo
->led_display_base_addr
= octeon_bootinfo
->led_display_base_addr
;
457 sysinfo
->dfa_ref_clock_hz
= octeon_bootinfo
->dfa_ref_clock_hz
;
458 sysinfo
->bootloader_config_flags
= octeon_bootinfo
->config_flags
;
460 if (OCTEON_IS_MODEL(OCTEON_CN6XXX
)) {
461 /* I/O clock runs at a different rate than the CPU. */
462 union cvmx_mio_rst_boot rst_boot
;
463 rst_boot
.u64
= cvmx_read_csr(CVMX_MIO_RST_BOOT
);
464 octeon_io_clock_rate
= 50000000 * rst_boot
.s
.pnr_mul
;
466 octeon_io_clock_rate
= sysinfo
->cpu_clock_hz
;
470 * Only enable the LED controller if we're running on a CN38XX, CN58XX,
471 * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
473 if (!octeon_is_simulation() &&
474 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER
)) {
475 cvmx_write_csr(CVMX_LED_EN
, 0);
476 cvmx_write_csr(CVMX_LED_PRT
, 0);
477 cvmx_write_csr(CVMX_LED_DBG
, 0);
478 cvmx_write_csr(CVMX_LED_PRT_FMT
, 0);
479 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
480 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
481 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
482 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
483 cvmx_write_csr(CVMX_LED_EN
, 1);
485 #ifdef CONFIG_CAVIUM_RESERVE32
487 * We need to temporarily allocate all memory in the reserve32
488 * region. This makes sure the kernel doesn't allocate this
489 * memory when it is getting memory from the
490 * bootloader. Later, after the memory allocations are
491 * complete, the reserve32 will be freed.
493 * Allocate memory for RESERVED32 aligned on 2MB boundary. This
494 * is in case we later use hugetlb entries with it.
496 addr
= cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32
<< 20,
498 "CAVIUM_RESERVE32", 0);
500 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
502 octeon_reserve32_memory
= addr
;
505 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
506 if (cvmx_read_csr(CVMX_L2D_FUS3
) & (3ull << 34)) {
507 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
509 uint32_t ebase
= read_c0_ebase() & 0x3ffff000;
510 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
512 cvmx_l2c_lock_mem_region(ebase
, 0x100);
514 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
515 /* General exception */
516 cvmx_l2c_lock_mem_region(ebase
+ 0x180, 0x80);
518 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
519 /* Interrupt handler */
520 cvmx_l2c_lock_mem_region(ebase
+ 0x200, 0x80);
522 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
523 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int
), 0x100);
524 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch
), 0x80);
526 #ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
527 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy
), 0x480);
532 octeon_check_cpu_bist();
534 octeon_uart
= octeon_get_boot_uart();
537 octeon_write_lcd("LinuxSMP");
539 octeon_write_lcd("Linux");
542 #ifdef CONFIG_CAVIUM_GDB
544 * When debugging the linux kernel, force the cores to enter
545 * the debug exception handler to break in.
547 if (octeon_get_boot_debug_flag()) {
548 cvmx_write_csr(CVMX_CIU_DINT
, 1 << cvmx_get_core_num());
549 cvmx_read_csr(CVMX_CIU_DINT
);
553 octeon_setup_delays();
556 * BIST should always be enabled when doing a soft reset. L2
557 * Cache locking for instance is not cleared unless BIST is
558 * enabled. Unfortunately due to a chip errata G-200 for
559 * Cn38XX and CN31XX, BIST msut be disabled on these parts.
561 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2
) ||
562 OCTEON_IS_MODEL(OCTEON_CN31XX
))
563 cvmx_write_csr(CVMX_CIU_SOFT_BIST
, 0);
565 cvmx_write_csr(CVMX_CIU_SOFT_BIST
, 1);
567 /* Default to 64MB in the simulator to speed things up */
568 if (octeon_is_simulation())
569 MAX_MEMORY
= 64ull << 20;
572 argc
= octeon_boot_desc_ptr
->argc
;
573 for (i
= 0; i
< argc
; i
++) {
575 cvmx_phys_to_ptr(octeon_boot_desc_ptr
->argv
[i
]);
576 if ((strncmp(arg
, "MEM=", 4) == 0) ||
577 (strncmp(arg
, "mem=", 4) == 0)) {
578 sscanf(arg
+ 4, "%llu", &MAX_MEMORY
);
581 MAX_MEMORY
= 32ull << 30;
582 } else if (strcmp(arg
, "ecc_verbose") == 0) {
583 #ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
584 __cvmx_interrupt_ecc_report_single_bit_errors
= 1;
585 pr_notice("Reporting of single bit ECC errors is "
588 } else if (strlen(arcs_cmdline
) + strlen(arg
) + 1 <
589 sizeof(arcs_cmdline
) - 1) {
590 strcat(arcs_cmdline
, " ");
591 strcat(arcs_cmdline
, arg
);
595 if (strstr(arcs_cmdline
, "console=") == NULL
) {
596 #ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
597 strcat(arcs_cmdline
, " console=ttyS0,115200");
599 if (octeon_uart
== 1)
600 strcat(arcs_cmdline
, " console=ttyS1,115200");
602 strcat(arcs_cmdline
, " console=ttyS0,115200");
606 if (octeon_is_simulation()) {
608 * The simulator uses a mtdram device pre filled with
609 * the filesystem. Also specify the calibration delay
610 * to avoid calculating it every time.
612 strcat(arcs_cmdline
, " rw root=1f00 slram=root,0x40000000,+1073741824");
615 mips_hpt_frequency
= octeon_get_clock_rate();
617 octeon_init_cvmcount();
619 _machine_restart
= octeon_restart
;
620 _machine_halt
= octeon_halt
;
622 octeon_user_io_init();
623 register_smp_ops(&octeon_smp_ops
);
626 /* Exclude a single page from the regions obtained in plat_mem_setup. */
627 static __init
void memory_exclude_page(u64 addr
, u64
*mem
, u64
*size
)
629 if (addr
> *mem
&& addr
< *mem
+ *size
) {
630 u64 inc
= addr
- *mem
;
631 add_memory_region(*mem
, inc
, BOOT_MEM_RAM
);
636 if (addr
== *mem
&& *size
> PAGE_SIZE
) {
642 void __init
plat_mem_setup(void)
644 uint64_t mem_alloc_size
;
651 * The Mips memory init uses the first memory location for
652 * some memory vectors. When SPARSEMEM is in use, it doesn't
653 * verify that the size is big enough for the final
654 * vectors. Making the smallest chuck 4MB seems to be enough
655 * to consistently work.
657 mem_alloc_size
= 4 << 20;
658 if (mem_alloc_size
> MAX_MEMORY
)
659 mem_alloc_size
= MAX_MEMORY
;
662 * When allocating memory, we want incrementing addresses from
663 * bootmem_alloc so the code in add_memory_region can merge
664 * regions next to each other.
667 while ((boot_mem_map
.nr_map
< BOOT_MEM_MAP_MAX
)
668 && (total
< MAX_MEMORY
)) {
669 memory
= cvmx_bootmem_phy_alloc(mem_alloc_size
,
670 __pa_symbol(&__init_end
), -1,
672 CVMX_BOOTMEM_FLAG_NO_LOCKING
);
674 u64 size
= mem_alloc_size
;
677 * exclude a page at the beginning and end of
678 * the 256MB PCIe 'hole' so the kernel will not
679 * try to allocate multi-page buffers that
680 * span the discontinuity.
682 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE
,
684 memory_exclude_page(CVMX_PCIE_BAR1_PHYS_BASE
+
685 CVMX_PCIE_BAR1_PHYS_SIZE
,
689 * This function automatically merges address
690 * regions next to each other if they are
691 * received in incrementing order.
694 add_memory_region(memory
, size
, BOOT_MEM_RAM
);
695 total
+= mem_alloc_size
;
700 cvmx_bootmem_unlock();
702 #ifdef CONFIG_CAVIUM_RESERVE32
704 * Now that we've allocated the kernel memory it is safe to
705 * free the reserved region. We free it here so that builtin
706 * drivers can use the memory.
708 if (octeon_reserve32_memory
)
709 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
710 #endif /* CONFIG_CAVIUM_RESERVE32 */
713 panic("Unable to allocate memory from "
714 "cvmx_bootmem_phy_alloc\n");
718 * Emit one character to the boot UART. Exported for use by the
721 int prom_putchar(char c
)
725 /* Spin until there is room */
727 lsrval
= cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart
));
728 } while ((lsrval
& 0x20) == 0);
731 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart
), c
& 0xffull
);
734 EXPORT_SYMBOL(prom_putchar
);
736 void prom_free_prom_memory(void)
738 if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X
)) {
739 /* Check for presence of Core-14449 fix. */
745 asm volatile("# before" : : : "memory");
752 "1:\tlw %0,-12($31)\n\t"
754 : "=r" (insn
) : : "$31", "memory");
756 if ((insn
>> 26) != 0x33)
757 panic("No PREF instruction at Core-14449 probe point.");
759 if (((insn
>> 16) & 0x1f) != 28)
760 panic("Core-14449 WAR not in place (%04x).\n"
761 "Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).", insn
);
763 #ifdef CONFIG_CAVIUM_DECODE_RSL
764 cvmx_interrupt_rsl_enable();
766 /* Add an interrupt handler for general failures. */
767 if (request_irq(OCTEON_IRQ_RML
, octeon_rlm_interrupt
, IRQF_SHARED
,
768 "RML/RSL", octeon_rlm_interrupt
)) {
769 panic("Unable to request_irq(OCTEON_IRQ_RML)");
774 int octeon_prune_device_tree(void);
776 extern const char __dtb_octeon_3xxx_begin
;
777 extern const char __dtb_octeon_3xxx_end
;
778 extern const char __dtb_octeon_68xx_begin
;
779 extern const char __dtb_octeon_68xx_end
;
780 void __init
device_tree_init(void)
783 struct boot_param_header
*fdt
;
786 if (octeon_bootinfo
->minor_version
>= 3 && octeon_bootinfo
->fdt_addr
) {
787 fdt
= phys_to_virt(octeon_bootinfo
->fdt_addr
);
788 if (fdt_check_header(fdt
))
789 panic("Corrupt Device Tree passed to kernel.");
790 dt_size
= be32_to_cpu(fdt
->totalsize
);
792 } else if (OCTEON_IS_MODEL(OCTEON_CN68XX
)) {
793 fdt
= (struct boot_param_header
*)&__dtb_octeon_68xx_begin
;
794 dt_size
= &__dtb_octeon_68xx_end
- &__dtb_octeon_68xx_begin
;
797 fdt
= (struct boot_param_header
*)&__dtb_octeon_3xxx_begin
;
798 dt_size
= &__dtb_octeon_3xxx_end
- &__dtb_octeon_3xxx_begin
;
802 /* Copy the default tree from init memory. */
803 initial_boot_params
= early_init_dt_alloc_memory_arch(dt_size
, 8);
804 if (initial_boot_params
== NULL
)
805 panic("Could not allocate initial_boot_params\n");
806 memcpy(initial_boot_params
, fdt
, dt_size
);
809 octeon_prune_device_tree();
810 pr_info("Using internal Device Tree.\n");
812 pr_info("Using passed Device Tree.\n");
814 unflatten_device_tree();
817 static char *edac_device_names
[] = {
823 static int __init
edac_devinit(void)
825 struct platform_device
*dev
;
829 for (i
= 0; i
< ARRAY_SIZE(edac_device_names
); i
++) {
830 name
= edac_device_names
[i
];
831 dev
= platform_device_register_simple(name
, -1, NULL
, 0);
833 pr_err("Registation of %s failed!\n", name
);
841 device_initcall(edac_devinit
);