arch/i386/kernel/cpu/cyrix.c

   1 #include <linux/init.h>
   2 #include <linux/bitops.h>
   3 #include <linux/delay.h>
   4 #include <linux/pci.h>
   5 #include <asm/dma.h>
   6 #include <asm/io.h>
   7 #include <asm/processor.h>
   8 #include <asm/timer.h>
   9
  10 #include "cpu.h"
  11
  12 /*
  13  * Read NSC/Cyrix DEVID registers (DIR) to get more detailed info. about the CPU
  14  */
  15 static void __init do_cyrix_devid(unsigned char *dir0, unsigned char *dir1)
  16 {
  17         unsigned char ccr2, ccr3;
  18         unsigned long flags;
  19
  20         /* we test for DEVID by checking whether CCR3 is writable */
  21         local_irq_save(flags);
  22         ccr3 = getCx86(CX86_CCR3);
  23         setCx86(CX86_CCR3, ccr3 ^ 0x80);
  24         getCx86(0xc0);   /* dummy to change bus */
  25
  26         if (getCx86(CX86_CCR3) == ccr3) {       /* no DEVID regs. */
  27                 ccr2 = getCx86(CX86_CCR2);
  28                 setCx86(CX86_CCR2, ccr2 ^ 0x04);
  29                 getCx86(0xc0);  /* dummy */
  30
  31                 if (getCx86(CX86_CCR2) == ccr2) /* old Cx486SLC/DLC */
  32                         *dir0 = 0xfd;
  33                 else {                          /* Cx486S A step */
  34                         setCx86(CX86_CCR2, ccr2);
  35                         *dir0 = 0xfe;
  36                 }
  37         }
  38         else {
  39                 setCx86(CX86_CCR3, ccr3);  /* restore CCR3 */
  40
  41                 /* read DIR0 and DIR1 CPU registers */
  42                 *dir0 = getCx86(CX86_DIR0);
  43                 *dir1 = getCx86(CX86_DIR1);
  44         }
  45         local_irq_restore(flags);
  46 }
  47
  48 /*
  49  * Cx86_dir0_msb is a HACK needed by check_cx686_cpuid/slop in bugs.h in
  50  * order to identify the Cyrix CPU model after we're out of setup.c
  51  *
  52  * Actually since bugs.h doesn't even reference this perhaps someone should
  53  * fix the documentation ???
  54  */
  55 static unsigned char Cx86_dir0_msb __initdata = 0;
  56
  57 static char Cx86_model[][9] __initdata = {
  58         "Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
  59         "M II ", "Unknown"
  60 };
  61 static char Cx486_name[][5] __initdata = {
  62         "SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
  63         "SRx2", "DRx2"
  64 };
  65 static char Cx486S_name[][4] __initdata = {
  66         "S", "S2", "Se", "S2e"
  67 };
  68 static char Cx486D_name[][4] __initdata = {
  69         "DX", "DX2", "?", "?", "?", "DX4"
  70 };
  71 static char Cx86_cb[] __initdata = "?.5x Core/Bus Clock";
  72 static char cyrix_model_mult1[] __initdata = "12??43";
  73 static char cyrix_model_mult2[] __initdata = "12233445";
  74
  75 /*
  76  * Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
  77  * BIOSes for compatibility with DOS games.  This makes the udelay loop
  78  * work correctly, and improves performance.
  79  *
  80  * FIXME: our newer udelay uses the tsc. We don't need to frob with SLOP
  81  */
  82
  83 extern void calibrate_delay(void) __init;
  84
  85 static void __init check_cx686_slop(struct cpuinfo_x86 *c)
  86 {
  87         unsigned long flags;
  88
  89         if (Cx86_dir0_msb == 3) {
  90                 unsigned char ccr3, ccr5;
  91
  92                 local_irq_save(flags);
  93                 ccr3 = getCx86(CX86_CCR3);
  94                 setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
  95                 ccr5 = getCx86(CX86_CCR5);
  96                 if (ccr5 & 2)
  97                         setCx86(CX86_CCR5, ccr5 & 0xfd);  /* reset SLOP */
  98                 setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
  99                 local_irq_restore(flags);
 100
 101                 if (ccr5 & 2) { /* possible wrong calibration done */
 102                         printk(KERN_INFO "Recalibrating delay loop with SLOP bit reset\n");
 103                         calibrate_delay();
 104                         c->loops_per_jiffy = loops_per_jiffy;
 105                 }
 106         }
 107 }
 108
 109
 110 static void __init set_cx86_reorder(void)
 111 {
 112         u8 ccr3;
 113
 114         printk(KERN_INFO "Enable Memory access reorder on Cyrix/NSC processor.\n");
 115         ccr3 = getCx86(CX86_CCR3);
 116         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
 117
 118         /* Load/Store Serialize to mem access disable (=reorder it)  */
 119         setCx86(CX86_PCR0, getCx86(CX86_PCR0) & ~0x80);
 120         /* set load/store serialize from 1GB to 4GB */
 121         ccr3 |= 0xe0;
 122         setCx86(CX86_CCR3, ccr3);
 123 }
 124
 125 static void __init set_cx86_memwb(void)
 126 {
 127         u32 cr0;
 128
 129         printk(KERN_INFO "Enable Memory-Write-back mode on Cyrix/NSC processor.\n");
 130
 131         /* CCR2 bit 2: unlock NW bit */
 132         setCx86(CX86_CCR2, getCx86(CX86_CCR2) & ~0x04);
 133         /* set 'Not Write-through' */
 134         cr0 = 0x20000000;
 135         write_cr0(read_cr0() | cr0);
 136         /* CCR2 bit 2: lock NW bit and set WT1 */
 137         setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );
 138 }
 139
 140 static void __init set_cx86_inc(void)
 141 {
 142         unsigned char ccr3;
 143
 144         printk(KERN_INFO "Enable Incrementor on Cyrix/NSC processor.\n");
 145
 146         ccr3 = getCx86(CX86_CCR3);
 147         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
 148         /* PCR1 -- Performance Control */
 149         /* Incrementor on, whatever that is */
 150         setCx86(CX86_PCR1, getCx86(CX86_PCR1) | 0x02);
 151         /* PCR0 -- Performance Control */
 152         /* Incrementor Margin 10 */
 153         setCx86(CX86_PCR0, getCx86(CX86_PCR0) | 0x04);
 154         setCx86(CX86_CCR3, ccr3);       /* disable MAPEN */
 155 }
 156
 157 /*
 158  *      Configure later MediaGX and/or Geode processor.
 159  */
 160
 161 static void __init geode_configure(void)
 162 {
 163         unsigned long flags;
 164         u8 ccr3, ccr4;
 165         local_irq_save(flags);
 166
 167         /* Suspend on halt power saving and enable #SUSP pin */
 168         setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
 169
 170         ccr3 = getCx86(CX86_CCR3);
 171         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* Enable */
 172
 173         ccr4 = getCx86(CX86_CCR4);
 174         ccr4 |= 0x38;           /* FPU fast, DTE cache, Mem bypass */
 175
 176         setCx86(CX86_CCR3, ccr3);
 177
 178         set_cx86_memwb();
 179         set_cx86_reorder();
 180         set_cx86_inc();
 181
 182         local_irq_restore(flags);
 183 }
 184
 185
 186 #ifdef CONFIG_PCI
 187 static struct pci_device_id cyrix_55x0[] = {
 188         { PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510) },
 189         { PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520) },
 190         { },
 191 };
 192 #endif
 193
 194 static void __init init_cyrix(struct cpuinfo_x86 *c)
 195 {
 196         unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
 197         char *buf = c->x86_model_id;
 198         const char *p = NULL;
 199
 200         /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 201            3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
 202         clear_bit(0*32+31, c->x86_capability);
 203
 204         /* Cyrix used bit 24 in extended (AMD) CPUID for Cyrix MMX extensions */
 205         if ( test_bit(1*32+24, c->x86_capability) ) {
 206                 clear_bit(1*32+24, c->x86_capability);
 207                 set_bit(X86_FEATURE_CXMMX, c->x86_capability);
 208         }
 209
 210         do_cyrix_devid(&dir0, &dir1);
 211
 212         check_cx686_slop(c);
 213
 214         Cx86_dir0_msb = dir0_msn = dir0 >> 4; /* identifies CPU "family"   */
 215         dir0_lsn = dir0 & 0xf;                /* model or clock multiplier */
 216
 217         /* common case step number/rev -- exceptions handled below */
 218         c->x86_model = (dir1 >> 4) + 1;
 219         c->x86_mask = dir1 & 0xf;
 220
 221         /* Now cook; the original recipe is by Channing Corn, from Cyrix.
 222          * We do the same thing for each generation: we work out
 223          * the model, multiplier and stepping.  Black magic included,
 224          * to make the silicon step/rev numbers match the printed ones.
 225          */
 226
 227         switch (dir0_msn) {
 228                 unsigned char tmp;
 229
 230         case 0: /* Cx486SLC/DLC/SRx/DRx */
 231                 p = Cx486_name[dir0_lsn & 7];
 232                 break;
 233
 234         case 1: /* Cx486S/DX/DX2/DX4 */
 235                 p = (dir0_lsn & 8) ? Cx486D_name[dir0_lsn & 5]
 236                         : Cx486S_name[dir0_lsn & 3];
 237                 break;
 238
 239         case 2: /* 5x86 */
 240                 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
 241                 p = Cx86_cb+2;
 242                 break;
 243
 244         case 3: /* 6x86/6x86L */
 245                 Cx86_cb[1] = ' ';
 246                 Cx86_cb[2] = cyrix_model_mult1[dir0_lsn & 5];
 247                 if (dir1 > 0x21) { /* 686L */
 248                         Cx86_cb[0] = 'L';
 249                         p = Cx86_cb;
 250                         (c->x86_model)++;
 251                 } else             /* 686 */
 252                         p = Cx86_cb+1;
 253                 /* Emulate MTRRs using Cyrix's ARRs. */
 254                 set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability);
 255                 /* 6x86's contain this bug */
 256                 c->coma_bug = 1;
 257                 break;
 258
 259         case 4: /* MediaGX/GXm or Geode GXM/GXLV/GX1 */
 260 #ifdef CONFIG_PCI
 261                 /* It isn't really a PCI quirk directly, but the cure is the
 262                    same. The MediaGX has deep magic SMM stuff that handles the
 263                    SB emulation. It thows away the fifo on disable_dma() which
 264                    is wrong and ruins the audio.
 265
 266                    Bug2: VSA1 has a wrap bug so that using maximum sized DMA
 267                    causes bad things. According to NatSemi VSA2 has another
 268                    bug to do with 'hlt'. I've not seen any boards using VSA2
 269                    and X doesn't seem to support it either so who cares 8).
 270                    VSA1 we work around however.
 271                 */
 272
 273                 printk(KERN_INFO "Working around Cyrix MediaGX virtual DMA bugs.\n");
 274                 isa_dma_bridge_buggy = 2;
 275 #endif
 276                 c->x86_cache_size=16;   /* Yep 16K integrated cache thats it */
 277
 278                 /*
 279                  *  The 5510/5520 companion chips have a funky PIT.
 280                  */
 281                 if (pci_dev_present(cyrix_55x0))
 282                         pit_latch_buggy = 1;
 283
 284                 /* GXm supports extended cpuid levels 'ala' AMD */
 285                 if (c->cpuid_level == 2) {
 286                         /* Enable cxMMX extensions (GX1 Datasheet 54) */
 287                         setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
 288
 289                         /* GXlv/GXm/GX1 */
 290                         if((dir1 >= 0x50 && dir1 <= 0x54) || dir1 >= 0x63)
 291                                 geode_configure();
 292                         get_model_name(c);  /* get CPU marketing name */
 293                         return;
 294                 }
 295                 else {  /* MediaGX */
 296                         Cx86_cb[2] = (dir0_lsn & 1) ? '3' : '4';
 297                         p = Cx86_cb+2;
 298                         c->x86_model = (dir1 & 0x20) ? 1 : 2;
 299                 }
 300                 break;
 301
 302         case 5: /* 6x86MX/M II */
 303                 if (dir1 > 7)
 304                 {
 305                         dir0_msn++;  /* M II */
 306                         /* Enable MMX extensions (App note 108) */
 307                         setCx86(CX86_CCR7, getCx86(CX86_CCR7)|1);
 308                 }
 309                 else
 310                 {
 311                         c->coma_bug = 1;      /* 6x86MX, it has the bug. */
 312                 }
 313                 tmp = (!(dir0_lsn & 7) || dir0_lsn & 1) ? 2 : 0;
 314                 Cx86_cb[tmp] = cyrix_model_mult2[dir0_lsn & 7];
 315                 p = Cx86_cb+tmp;
 316                 if (((dir1 & 0x0f) > 4) || ((dir1 & 0xf0) == 0x20))
 317                         (c->x86_model)++;
 318                 /* Emulate MTRRs using Cyrix's ARRs. */
 319                 set_bit(X86_FEATURE_CYRIX_ARR, c->x86_capability);
 320                 break;
 321
 322         case 0xf:  /* Cyrix 486 without DEVID registers */
 323                 switch (dir0_lsn) {
 324                 case 0xd:  /* either a 486SLC or DLC w/o DEVID */
 325                         dir0_msn = 0;
 326                         p = Cx486_name[(c->hard_math) ? 1 : 0];
 327                         break;
 328
 329                 case 0xe:  /* a 486S A step */
 330                         dir0_msn = 0;
 331                         p = Cx486S_name[0];
 332                         break;
 333                 }
 334                 break;
 335
 336         default:  /* unknown (shouldn't happen, we know everyone ;-) */
 337                 dir0_msn = 7;
 338                 break;
 339         }
 340         strcpy(buf, Cx86_model[dir0_msn & 7]);
 341         if (p) strcat(buf, p);
 342         return;
 343 }
 344
 345 /*
 346  * Handle National Semiconductor branded processors
 347  */
 348 static void __devinit init_nsc(struct cpuinfo_x86 *c)
 349 {
 350         /* There may be GX1 processors in the wild that are branded
 351          * NSC and not Cyrix.
 352          *
 353          * This function only handles the GX processor, and kicks every
 354          * thing else to the Cyrix init function above - that should
 355          * cover any processors that might have been branded differently
 356          * after NSC aquired Cyrix.
 357          *
 358          * If this breaks your GX1 horribly, please e-mail
 359          * info-linux@ldcmail.amd.com to tell us.
 360          */
 361
 362         /* Handle the GX (Formally known as the GX2) */
 363
 364         if (c->x86 == 5 && c->x86_model == 5)
 365                 display_cacheinfo(c);
 366         else
 367                 init_cyrix(c);
 368 }
 369
 370 /*
 371  * Cyrix CPUs without cpuid or with cpuid not yet enabled can be detected
 372  * by the fact that they preserve the flags across the division of 5/2.
 373  * PII and PPro exhibit this behavior too, but they have cpuid available.
 374  */
 375
 376 /*
 377  * Perform the Cyrix 5/2 test. A Cyrix won't change
 378  * the flags, while other 486 chips will.
 379  */
 380 static inline int test_cyrix_52div(void)
 381 {
 382         unsigned int test;
 383
 384         __asm__ __volatile__(
 385              "sahf\n\t"         /* clear flags (%eax = 0x0005) */
 386              "div %b2\n\t"      /* divide 5 by 2 */
 387              "lahf"             /* store flags into %ah */
 388              : "=a" (test)
 389              : "0" (5), "q" (2)
 390              : "cc");
 391
 392         /* AH is 0x02 on Cyrix after the divide.. */
 393         return (unsigned char) (test >> 8) == 0x02;
 394 }
 395
 396 static void cyrix_identify(struct cpuinfo_x86 * c)
 397 {
 398         /* Detect Cyrix with disabled CPUID */
 399         if ( c->x86 == 4 && test_cyrix_52div() ) {
 400                 unsigned char dir0, dir1;
 401
 402                 strcpy(c->x86_vendor_id, "CyrixInstead");
 403                 c->x86_vendor = X86_VENDOR_CYRIX;
 404
 405                 /* Actually enable cpuid on the older cyrix */
 406
 407                 /* Retrieve CPU revisions */
 408
 409                 do_cyrix_devid(&dir0, &dir1);
 410
 411                 dir0>>=4;
 412
 413                 /* Check it is an affected model */
 414
 415                 if (dir0 == 5 || dir0 == 3)
 416                 {
 417                         unsigned char ccr3, ccr4;
 418                         unsigned long flags;
 419                         printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
 420                         local_irq_save(flags);
 421                         ccr3 = getCx86(CX86_CCR3);
 422                         setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10); /* enable MAPEN  */
 423                         ccr4 = getCx86(CX86_CCR4);
 424                         setCx86(CX86_CCR4, ccr4 | 0x80);          /* enable cpuid  */
 425                         setCx86(CX86_CCR3, ccr3);                 /* disable MAPEN */
 426                         local_irq_restore(flags);
 427                 }
 428         }
 429         generic_identify(c);
 430 }
 431
 432 static struct cpu_dev cyrix_cpu_dev __initdata = {
 433         .c_vendor       = "Cyrix",
 434         .c_ident        = { "CyrixInstead" },
 435         .c_init         = init_cyrix,
 436         .c_identify     = cyrix_identify,
 437 };
 438
 439 int __init cyrix_init_cpu(void)
 440 {
 441         cpu_devs[X86_VENDOR_CYRIX] = &cyrix_cpu_dev;
 442         return 0;
 443 }
 444
 445 //early_arch_initcall(cyrix_init_cpu);
 446
 447 static struct cpu_dev nsc_cpu_dev __initdata = {
 448         .c_vendor       = "NSC",
 449         .c_ident        = { "Geode by NSC" },
 450         .c_init         = init_nsc,
 451         .c_identify     = generic_identify,
 452 };
 453
 454 int __init nsc_init_cpu(void)
 455 {
 456         cpu_devs[X86_VENDOR_NSC] = &nsc_cpu_dev;
 457         return 0;
 458 }
 459
 460 //early_arch_initcall(nsc_init_cpu);