arch/cris/arch-v32/kernel/head.S

   1 /*
   2  * CRISv32 kernel startup code.
   3  *
   4  * Copyright (C) 2003, Axis Communications AB
   5  */
   6
   7 #define ASSEMBLER_MACROS_ONLY
   8
   9 /*
  10  * The macros found in mmu_defs_asm.h uses the ## concatenation operator, so
  11  * -traditional must not be used when assembling this file.
  12  */
  13 #include <hwregs/reg_rdwr.h>
  14 #include <arch/memmap.h>
  15 #include <hwregs/intr_vect.h>
  16 #include <hwregs/asm/mmu_defs_asm.h>
  17 #include <hwregs/asm/reg_map_asm.h>
  18 #include <mach/startup.inc>
  19
  20 #define CRAMFS_MAGIC 0x28cd3d45
  21 #define JHEAD_MAGIC 0x1FF528A6
  22 #define JHEAD_SIZE 8
  23 #define RAM_INIT_MAGIC 0x56902387
  24 #define COMMAND_LINE_MAGIC 0x87109563
  25 #define NAND_BOOT_MAGIC 0x9a9db001
  26
  27         ;; NOTE: R8 and R9 carry information from the decompressor (if the
  28         ;; kernel was compressed). They must not be used in the code below
  29         ;; until they are read!
  30
  31         ;; Exported symbols.
  32         .global etrax_irv
  33         .global romfs_start
  34         .global romfs_length
  35         .global romfs_in_flash
  36         .global nand_boot
  37         .global swapper_pg_dir
  38
  39         ;; Dummy section to make it bootable with current VCS simulator
  40 #ifdef CONFIG_ETRAX_VCS_SIM
  41         .section ".boot", "ax"
  42         ba tstart
  43         nop
  44 #endif
  45
  46         .text
  47 tstart:
  48         ;; This is the entry point of the kernel. The CPU is currently in
  49         ;; supervisor mode.
  50         ;;
  51         ;; 0x00000000 if flash.
  52         ;; 0x40004000 if DRAM.
  53         ;;
  54         di
  55
  56         START_CLOCKS
  57
  58         SETUP_WAIT_STATES
  59
  60         GIO_INIT
  61
  62 #ifdef CONFIG_SMP
  63 secondary_cpu_entry: /* Entry point for secondary CPUs */
  64         di
  65 #endif
  66
  67         ;; Setup and enable the MMU. Use same configuration for both the data
  68         ;; and the instruction MMU.
  69         ;;
  70         ;; Note; 3 cycles is needed for a bank-select to take effect. Further;
  71         ;; bank 1 is the instruction MMU, bank 2 is the data MMU.
  72 #ifndef CONFIG_ETRAX_VCS_SIM
  73         move.d  REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8)       \
  74                 | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4)     \
  75                 | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb), $r0
  76 #else
  77         ;; Map the virtual DRAM to the RW eprom area at address 0.
  78         ;; Also map 0xa for the hook calls,
  79         move.d  REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 8)       \
  80                 | REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 4)     \
  81                 | REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb)   \
  82                 | REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa), $r0
  83 #endif
  84
  85         ;; Temporary map of 0x40 -> 0x40 and 0x00 -> 0x00.
  86         move.d  REG_FIELD(mmu, rw_mm_kbase_lo, base_4, 4)  \
  87                 | REG_FIELD(mmu, rw_mm_kbase_lo, base_0, 0), $r1
  88
  89         ;; Enable certain page protections and setup linear mapping
  90         ;; for f,e,c,b,4,0.
  91 #ifndef CONFIG_ETRAX_VCS_SIM
  92         move.d  REG_STATE(mmu, rw_mm_cfg, we, on)               \
  93                 | REG_STATE(mmu, rw_mm_cfg, acc, on)            \
  94                 | REG_STATE(mmu, rw_mm_cfg, ex, on)             \
  95                 | REG_STATE(mmu, rw_mm_cfg, inv, on)            \
  96                 | REG_STATE(mmu, rw_mm_cfg, seg_f, linear)      \
  97                 | REG_STATE(mmu, rw_mm_cfg, seg_e, linear)      \
  98                 | REG_STATE(mmu, rw_mm_cfg, seg_d, page)        \
  99                 | REG_STATE(mmu, rw_mm_cfg, seg_c, linear)      \
 100                 | REG_STATE(mmu, rw_mm_cfg, seg_b, linear)      \
 101                 | REG_STATE(mmu, rw_mm_cfg, seg_a, page)        \
 102                 | REG_STATE(mmu, rw_mm_cfg, seg_9, page)        \
 103                 | REG_STATE(mmu, rw_mm_cfg, seg_8, page)        \
 104                 | REG_STATE(mmu, rw_mm_cfg, seg_7, page)        \
 105                 | REG_STATE(mmu, rw_mm_cfg, seg_6, page)        \
 106                 | REG_STATE(mmu, rw_mm_cfg, seg_5, page)        \
 107                 | REG_STATE(mmu, rw_mm_cfg, seg_4, linear)      \
 108                 | REG_STATE(mmu, rw_mm_cfg, seg_3, page)        \
 109                 | REG_STATE(mmu, rw_mm_cfg, seg_2, page)        \
 110                 | REG_STATE(mmu, rw_mm_cfg, seg_1, page)        \
 111                 | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
 112 #else
 113         move.d  REG_STATE(mmu, rw_mm_cfg, we, on)               \
 114                 | REG_STATE(mmu, rw_mm_cfg, acc, on)            \
 115                 | REG_STATE(mmu, rw_mm_cfg, ex, on)             \
 116                 | REG_STATE(mmu, rw_mm_cfg, inv, on)            \
 117                 | REG_STATE(mmu, rw_mm_cfg, seg_f, linear)      \
 118                 | REG_STATE(mmu, rw_mm_cfg, seg_e, linear)      \
 119                 | REG_STATE(mmu, rw_mm_cfg, seg_d, page)        \
 120                 | REG_STATE(mmu, rw_mm_cfg, seg_c, linear)      \
 121                 | REG_STATE(mmu, rw_mm_cfg, seg_b, linear)      \
 122                 | REG_STATE(mmu, rw_mm_cfg, seg_a, linear)      \
 123                 | REG_STATE(mmu, rw_mm_cfg, seg_9, page)        \
 124                 | REG_STATE(mmu, rw_mm_cfg, seg_8, page)        \
 125                 | REG_STATE(mmu, rw_mm_cfg, seg_7, page)        \
 126                 | REG_STATE(mmu, rw_mm_cfg, seg_6, page)        \
 127                 | REG_STATE(mmu, rw_mm_cfg, seg_5, page)        \
 128                 | REG_STATE(mmu, rw_mm_cfg, seg_4, linear)      \
 129                 | REG_STATE(mmu, rw_mm_cfg, seg_3, page)        \
 130                 | REG_STATE(mmu, rw_mm_cfg, seg_2, page)        \
 131                 | REG_STATE(mmu, rw_mm_cfg, seg_1, page)        \
 132                 | REG_STATE(mmu, rw_mm_cfg, seg_0, linear), $r2
 133 #endif
 134
 135         ;; Update instruction MMU.
 136         move    1, $srs
 137         nop
 138         nop
 139         nop
 140         move    $r0, $s2        ; kbase_hi.
 141         move    $r1, $s1        ; kbase_lo.
 142         move    $r2, $s0        ; mm_cfg, virtual memory configuration.
 143
 144         ;; Update data MMU.
 145         move    2, $srs
 146         nop
 147         nop
 148         nop
 149         move    $r0, $s2        ; kbase_hi.
 150         move    $r1, $s1        ; kbase_lo
 151         move    $r2, $s0        ; mm_cfg, virtual memory configuration.
 152
 153         ;; Enable data and instruction MMU.
 154         move    0, $srs
 155         moveq   0xf, $r0        ;  IMMU, DMMU, DCache, Icache on
 156         nop
 157         nop
 158         nop
 159         move    $r0, $s0
 160         nop
 161         nop
 162         nop
 163
 164 #ifdef CONFIG_SMP
 165         ;; Read CPU ID
 166         move    0, $srs
 167         nop
 168         nop
 169         nop
 170         move    $s12, $r0
 171         cmpq    0, $r0
 172         beq     master_cpu
 173         nop
 174 slave_cpu:
 175         ; Time to boot-up. Get stack location provided by master CPU.
 176         move.d  smp_init_current_idle_thread, $r1
 177         move.d  [$r1], $sp
 178         add.d   8192, $sp
 179         move.d  ebp_start, $r0  ; Defined in linker-script.
 180         move    $r0, $ebp
 181         jsr     smp_callin
 182         nop
 183 master_cpu:
 184         /* Set up entry point for secondary CPUs. The boot ROM has set up
 185          * EBP at start of internal memory. The CPU will get there
 186          * later when we issue an IPI to them... */
 187         move.d MEM_INTMEM_START + IPI_INTR_VECT * 4, $r0
 188         move.d secondary_cpu_entry, $r1
 189         move.d $r1, [$r0]
 190 #endif
 191 #ifndef CONFIG_ETRAX_VCS_SIM
 192         ; Check if starting from DRAM (network->RAM boot or unpacked
 193         ; compressed kernel), or directly from flash.
 194         lapcq   ., $r0
 195         and.d   0x7fffffff, $r0 ; Mask off the non-cache bit.
 196         cmp.d   0x10000, $r0    ; Arbitrary, something above this code.
 197         blo     _inflash0
 198         nop
 199 #endif
 200
 201         jump    _inram          ; Jump to cached RAM.
 202         nop
 203
 204         ;; Jumpgate.
 205 _inflash0:
 206         jump _inflash
 207         nop
 208
 209         ;; Put the following in a section so that storage for it can be
 210         ;; reclaimed after init is finished.
 211         .section ".init.text", "ax"
 212
 213 _inflash:
 214
 215         ;; Initialize DRAM.
 216         cmp.d   RAM_INIT_MAGIC, $r8 ; Already initialized?
 217         beq     _dram_initialized
 218         nop
 219
 220 #include "../mach/dram_init.S"
 221
 222 _dram_initialized:
 223         ;; Copy the text and data section to DRAM. This depends on that the
 224         ;; variables used below are correctly set up by the linker script.
 225         ;; The calculated value stored in R4 is used below.
 226         ;; Leave the cramfs file system (piggybacked after the kernel) in flash.
 227         moveq   0, $r0          ; Source.
 228         move.d  text_start, $r1 ; Destination.
 229         move.d  __vmlinux_end, $r2
 230         move.d  $r2, $r4
 231         sub.d   $r1, $r4
 232 1:      move.w  [$r0+], $r3
 233         move.w  $r3, [$r1+]
 234         cmp.d   $r2, $r1
 235         blo     1b
 236         nop
 237
 238         ;; Check for cramfs.
 239         moveq   0, $r0
 240         move.d  romfs_length, $r1
 241         move.d  $r0, [$r1]
 242         move.d  [$r4], $r0      ; cramfs_super.magic
 243         cmp.d   CRAMFS_MAGIC, $r0
 244         bne 1f
 245         nop
 246
 247         ;; Set length and start of cramfs, set romfs_in_flash flag
 248         addoq   +4, $r4, $acr
 249         move.d  [$acr], $r0
 250         move.d  romfs_length, $r1
 251         move.d  $r0, [$r1]
 252         add.d   0xf0000000, $r4 ; Add cached flash start in virtual memory.
 253         move.d  romfs_start, $r1
 254         move.d  $r4, [$r1]
 255 1:      moveq   1, $r0
 256         move.d  romfs_in_flash, $r1
 257         move.d  $r0, [$r1]
 258
 259         jump    _start_it       ; Jump to cached code.
 260         nop
 261
 262 _inram:
 263         ;; Check if booting from NAND flash; if so, set appropriate flags
 264         ;; and move on.
 265         cmp.d   NAND_BOOT_MAGIC, $r12
 266         bne     move_cramfs     ; not nand, jump
 267         moveq   1, $r0
 268         move.d  nand_boot, $r1  ; tell axisflashmap we're booting from NAND
 269         move.d  $r0, [$r1]
 270         moveq   0, $r0          ; tell axisflashmap romfs is not in
 271         move.d  romfs_in_flash, $r1 ; (directly accessed) flash
 272         move.d  $r0, [$r1]
 273         jump    _start_it       ; continue with boot
 274         nop
 275
 276 move_cramfs:
 277         ;; kernel is in DRAM.
 278         ;; Must figure out if there is a piggybacked rootfs image or not.
 279         ;; Set romfs_length to 0 => no rootfs image available by default.
 280         moveq   0, $r0
 281         move.d  romfs_length, $r1
 282         move.d  $r0, [$r1]
 283
 284 #ifndef CONFIG_ETRAX_VCS_SIM
 285         ;; The kernel could have been unpacked to DRAM by the loader, but
 286         ;; the cramfs image could still be in the flash immediately
 287         ;; following the compressed kernel image. The loader passes the address
 288         ;; of the byte succeeding the last compressed byte in the flash in
 289         ;; register R9 when starting the kernel.
 290         cmp.d   0x0ffffff8, $r9
 291         bhs     _no_romfs_in_flash ; R9 points outside the flash area.
 292         nop
 293 #else
 294         ba _no_romfs_in_flash
 295         nop
 296 #endif
 297         ;; cramfs rootfs might to be in flash. Check for it.
 298         move.d  [$r9], $r0      ; cramfs_super.magic
 299         cmp.d   CRAMFS_MAGIC, $r0
 300         bne     _no_romfs_in_flash
 301         nop
 302
 303         ;; found cramfs in flash. set address and size, and romfs_in_flash flag.
 304         addoq   +4, $r9, $acr
 305         move.d  [$acr], $r0
 306         move.d  romfs_length, $r1
 307         move.d  $r0, [$r1]
 308         add.d   0xf0000000, $r9 ; Add cached flash start in virtual memory.
 309         move.d  romfs_start, $r1
 310         move.d  $r9, [$r1]
 311         moveq   1, $r0
 312         move.d  romfs_in_flash, $r1
 313         move.d  $r0, [$r1]
 314
 315         jump    _start_it       ; Jump to cached code.
 316         nop
 317
 318 _no_romfs_in_flash:
 319         ;; No romfs in flash, so look for cramfs, or jffs2 with jhead,
 320         ;; after kernel in RAM, as is the case with network->RAM boot.
 321         ;; For cramfs, partition starts with magic and length.
 322         ;; For jffs2, a jhead is prepended which contains with magic and length.
 323         ;; The jhead is not part of the jffs2 partition however.
 324 #ifndef CONFIG_ETRAXFS_SIM
 325         move.d  __vmlinux_end, $r0
 326 #else
 327         move.d  __end, $r0
 328 #endif
 329         move.d  [$r0], $r1
 330         cmp.d   CRAMFS_MAGIC, $r1 ; cramfs magic?
 331         beq     2f                ; yes, jump
 332         nop
 333         cmp.d   JHEAD_MAGIC, $r1 ; jffs2 (jhead) magic?
 334         bne     4f              ; no, skip copy
 335         nop
 336         addq    4, $r0          ; location of jffs2 size
 337         move.d  [$r0+], $r2     ; fetch jffs2 size -> r2
 338                                 ; r0 now points to start of jffs2
 339         ba      3f
 340         nop
 341 2:
 342         addoq   +4, $r0, $acr   ; location of cramfs size
 343         move.d  [$acr], $r2     ; fetch cramfs size -> r2
 344                                 ; r0 still points to start of cramfs
 345 3:
 346         ;; Now, move the root fs to after kernel's BSS
 347
 348         move.d  _end, $r1       ; start of cramfs -> r1
 349         move.d  romfs_start, $r3
 350         move.d  $r1, [$r3]      ; store at romfs_start (for axisflashmap)
 351         move.d  romfs_length, $r3
 352         move.d  $r2, [$r3]      ; store size at romfs_length
 353
 354 #ifndef CONFIG_ETRAX_VCS_SIM
 355         add.d   $r2, $r0        ; copy from end and downwards
 356         add.d   $r2, $r1
 357
 358         lsrq    1, $r2          ; Size is in bytes, we copy words.
 359         addq    1, $r2
 360 1:
 361         move.w  [$r0], $r3
 362         move.w  $r3, [$r1]
 363         subq    2, $r0
 364         subq    2, $r1
 365         subq    1, $r2
 366         bne     1b
 367         nop
 368 #endif
 369
 370 4:
 371         ;; BSS move done.
 372         ;; Clear romfs_in_flash flag, as we now know romfs is in DRAM
 373         ;; Also clear nand_boot flag; if we got here, we know we've not
 374         ;; booted from NAND flash.
 375         moveq   0, $r0
 376         move.d  romfs_in_flash, $r1
 377         move.d  $r0, [$r1]
 378         moveq   0, $r0
 379         move.d  nand_boot, $r1
 380         move.d  $r0, [$r1]
 381
 382         jump    _start_it       ; Jump to cached code.
 383         nop
 384
 385 _start_it:
 386
 387         ;; Check if kernel command line is supplied
 388         cmp.d   COMMAND_LINE_MAGIC, $r10
 389         bne     no_command_line
 390         nop
 391
 392         move.d  256, $r13
 393         move.d  cris_command_line, $r10
 394         or.d    0x80000000, $r11 ; Make it virtual
 395 1:
 396         move.b  [$r11+], $r1
 397         move.b  $r1, [$r10+]
 398         subq    1, $r13
 399         bne     1b
 400         nop
 401
 402 no_command_line:
 403
 404         ;; The kernel stack contains a task structure for each task. This
 405         ;; the initial kernel stack is in the same page as the init_task,
 406         ;; but starts at the top of the page, i.e. + 8192 bytes.
 407         move.d  init_thread_union + 8192, $sp
 408         move.d  ebp_start, $r0  ; Defined in linker-script.
 409         move    $r0, $ebp
 410         move.d  etrax_irv, $r1  ; Set the exception base register and pointer.
 411         move.d  $r0, [$r1]
 412
 413 #ifndef CONFIG_ETRAX_VCS_SIM
 414         ;; Clear the BSS region from _bss_start to _end.
 415         move.d  __bss_start, $r0
 416         move.d  _end, $r1
 417 1:      clear.d [$r0+]
 418         cmp.d   $r1, $r0
 419         blo 1b
 420         nop
 421 #endif
 422
 423 #ifdef CONFIG_ETRAX_VCS_SIM
 424         /* Set the watchdog timeout to something big. Will be removed when */
 425         /* watchdog can be disabled with command line option */
 426         move.d  0x7fffffff, $r10
 427         jsr     CPU_WATCHDOG_TIMEOUT
 428         nop
 429 #endif
 430
 431         ; Initialize registers to increase determinism
 432         move.d __bss_start, $r0
 433         movem [$r0], $r13
 434
 435 #ifdef CONFIG_ETRAX_L2CACHE
 436         jsr     l2cache_init
 437         nop
 438 #endif
 439
 440         jump    start_kernel    ; Jump to start_kernel() in init/main.c.
 441         nop
 442
 443         .data
 444 etrax_irv:
 445         .dword 0
 446
 447 ; Variables for communication with the Axis flash map driver (axisflashmap),
 448 ; and for setting up memory in arch/cris/kernel/setup.c .
 449
 450 ; romfs_start is set to the start of the root file system, if it exists
 451 ; in directly accessible memory (i.e. NOR Flash when booting from Flash,
 452 ; or RAM when booting directly from a network-downloaded RAM image)
 453 romfs_start:
 454         .dword 0
 455
 456 ; romfs_length is set to the size of the root file system image, if it exists
 457 ; in directly accessible memory (see romfs_start). Otherwise it is set to 0.
 458 romfs_length:
 459         .dword 0
 460
 461 ; romfs_in_flash is set to 1 if the root file system resides in directly
 462 ; accessible flash memory (i.e. NOR flash). It is set to 0 for RAM boot
 463 ; or NAND flash boot.
 464 romfs_in_flash:
 465         .dword 0
 466
 467 ; nand_boot is set to 1 when the kernel has been booted from NAND flash
 468 nand_boot:
 469         .dword 0
 470
 471 swapper_pg_dir = 0xc0002000
 472
 473         .section ".init.data", "aw"
 474
 475 #include "../mach/hw_settings.S"