arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config SYMBOL_PREFIX
   9         string
  10         default "_"
  11
  12 config MMU
  13         def_bool n
  14
  15 config FPU
  16         def_bool n
  17
  18 config RWSEM_GENERIC_SPINLOCK
  19         def_bool y
  20
  21 config RWSEM_XCHGADD_ALGORITHM
  22         def_bool n
  23
  24 config BLACKFIN
  25         def_bool y
  26         select HAVE_ARCH_KGDB
  27         select HAVE_ARCH_TRACEHOOK
  28         select HAVE_FUNCTION_GRAPH_TRACER
  29         select HAVE_FUNCTION_TRACER
  30         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  31         select HAVE_IDE
  32         select HAVE_KERNEL_GZIP if RAMKERNEL
  33         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  34         select HAVE_KERNEL_LZMA if RAMKERNEL
  35         select HAVE_OPROFILE
  36         select ARCH_WANT_OPTIONAL_GPIOLIB
  37
  38 config GENERIC_CSUM
  39         def_bool y
  40
  41 config GENERIC_BUG
  42         def_bool y
  43         depends on BUG
  44
  45 config ZONE_DMA
  46         def_bool y
  47
  48 config GENERIC_FIND_NEXT_BIT
  49         def_bool y
  50
  51 config GENERIC_HARDIRQS
  52         def_bool y
  53
  54 config GENERIC_IRQ_PROBE
  55         def_bool y
  56
  57 config GENERIC_HARDIRQS_NO__DO_IRQ
  58         def_bool y
  59
  60 config GENERIC_GPIO
  61         def_bool y
  62
  63 config FORCE_MAX_ZONEORDER
  64         int
  65         default "14"
  66
  67 config GENERIC_CALIBRATE_DELAY
  68         def_bool y
  69
  70 config LOCKDEP_SUPPORT
  71         def_bool y
  72
  73 config STACKTRACE_SUPPORT
  74         def_bool y
  75
  76 config TRACE_IRQFLAGS_SUPPORT
  77         def_bool y
  78
  79 source "init/Kconfig"
  80
  81 source "kernel/Kconfig.preempt"
  82
  83 source "kernel/Kconfig.freezer"
  84
  85 menu "Blackfin Processor Options"
  86
  87 comment "Processor and Board Settings"
  88
  89 choice
  90         prompt "CPU"
  91         default BF533
  92
  93 config BF512
  94         bool "BF512"
  95         help
  96           BF512 Processor Support.
  97
  98 config BF514
  99         bool "BF514"
 100         help
 101           BF514 Processor Support.
 102
 103 config BF516
 104         bool "BF516"
 105         help
 106           BF516 Processor Support.
 107
 108 config BF518
 109         bool "BF518"
 110         help
 111           BF518 Processor Support.
 112
 113 config BF522
 114         bool "BF522"
 115         help
 116           BF522 Processor Support.
 117
 118 config BF523
 119         bool "BF523"
 120         help
 121           BF523 Processor Support.
 122
 123 config BF524
 124         bool "BF524"
 125         help
 126           BF524 Processor Support.
 127
 128 config BF525
 129         bool "BF525"
 130         help
 131           BF525 Processor Support.
 132
 133 config BF526
 134         bool "BF526"
 135         help
 136           BF526 Processor Support.
 137
 138 config BF527
 139         bool "BF527"
 140         help
 141           BF527 Processor Support.
 142
 143 config BF531
 144         bool "BF531"
 145         help
 146           BF531 Processor Support.
 147
 148 config BF532
 149         bool "BF532"
 150         help
 151           BF532 Processor Support.
 152
 153 config BF533
 154         bool "BF533"
 155         help
 156           BF533 Processor Support.
 157
 158 config BF534
 159         bool "BF534"
 160         help
 161           BF534 Processor Support.
 162
 163 config BF536
 164         bool "BF536"
 165         help
 166           BF536 Processor Support.
 167
 168 config BF537
 169         bool "BF537"
 170         help
 171           BF537 Processor Support.
 172
 173 config BF538
 174         bool "BF538"
 175         help
 176           BF538 Processor Support.
 177
 178 config BF539
 179         bool "BF539"
 180         help
 181           BF539 Processor Support.
 182
 183 config BF542_std
 184         bool "BF542"
 185         help
 186           BF542 Processor Support.
 187
 188 config BF542M
 189         bool "BF542m"
 190         help
 191           BF542 Processor Support.
 192
 193 config BF544_std
 194         bool "BF544"
 195         help
 196           BF544 Processor Support.
 197
 198 config BF544M
 199         bool "BF544m"
 200         help
 201           BF544 Processor Support.
 202
 203 config BF547_std
 204         bool "BF547"
 205         help
 206           BF547 Processor Support.
 207
 208 config BF547M
 209         bool "BF547m"
 210         help
 211           BF547 Processor Support.
 212
 213 config BF548_std
 214         bool "BF548"
 215         help
 216           BF548 Processor Support.
 217
 218 config BF548M
 219         bool "BF548m"
 220         help
 221           BF548 Processor Support.
 222
 223 config BF549_std
 224         bool "BF549"
 225         help
 226           BF549 Processor Support.
 227
 228 config BF549M
 229         bool "BF549m"
 230         help
 231           BF549 Processor Support.
 232
 233 config BF561
 234         bool "BF561"
 235         help
 236           BF561 Processor Support.
 237
 238 endchoice
 239
 240 config SMP
 241         depends on BF561
 242         select TICKSOURCE_CORETMR
 243         bool "Symmetric multi-processing support"
 244         ---help---
 245           This enables support for systems with more than one CPU,
 246           like the dual core BF561. If you have a system with only one
 247           CPU, say N. If you have a system with more than one CPU, say Y.
 248
 249           If you don't know what to do here, say N.
 250
 251 config NR_CPUS
 252         int
 253         depends on SMP
 254         default 2 if BF561
 255
 256 config HOTPLUG_CPU
 257         bool "Support for hot-pluggable CPUs"
 258         depends on SMP && HOTPLUG
 259         default y
 260
 261 config IRQ_PER_CPU
 262         bool
 263         depends on SMP
 264         default y
 265
 266 config HAVE_LEGACY_PER_CPU_AREA
 267         def_bool y
 268         depends on SMP
 269
 270 config BF_REV_MIN
 271         int
 272         default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
 273         default 2 if (BF537 || BF536 || BF534)
 274         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 275         default 4 if (BF538 || BF539)
 276
 277 config BF_REV_MAX
 278         int
 279         default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
 280         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 281         default 5 if (BF561 || BF538 || BF539)
 282         default 6 if (BF533 || BF532 || BF531)
 283
 284 choice
 285         prompt "Silicon Rev"
 286         default BF_REV_0_0 if (BF51x || BF52x)
 287         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 288         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 289
 290 config BF_REV_0_0
 291         bool "0.0"
 292         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 293
 294 config BF_REV_0_1
 295         bool "0.1"
 296         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 297
 298 config BF_REV_0_2
 299         bool "0.2"
 300         depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 301
 302 config BF_REV_0_3
 303         bool "0.3"
 304         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 305
 306 config BF_REV_0_4
 307         bool "0.4"
 308         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 309
 310 config BF_REV_0_5
 311         bool "0.5"
 312         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 313
 314 config BF_REV_0_6
 315         bool "0.6"
 316         depends on (BF533 || BF532 || BF531)
 317
 318 config BF_REV_ANY
 319         bool "any"
 320
 321 config BF_REV_NONE
 322         bool "none"
 323
 324 endchoice
 325
 326 config BF53x
 327         bool
 328         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 329         default y
 330
 331 config MEM_GENERIC_BOARD
 332         bool
 333         depends on GENERIC_BOARD
 334         default y
 335
 336 config MEM_MT48LC64M4A2FB_7E
 337         bool
 338         depends on (BFIN533_STAMP)
 339         default y
 340
 341 config MEM_MT48LC16M16A2TG_75
 342         bool
 343         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 344                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 345                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 346                 || BFIN527_BLUETECHNIX_CM)
 347         default y
 348
 349 config MEM_MT48LC32M8A2_75
 350         bool
 351         depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 352         default y
 353
 354 config MEM_MT48LC8M32B2B5_7
 355         bool
 356         depends on (BFIN561_BLUETECHNIX_CM)
 357         default y
 358
 359 config MEM_MT48LC32M16A2TG_75
 360         bool
 361         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
 362         default y
 363
 364 config MEM_MT48LC32M8A2_75
 365         bool
 366         depends on (BFIN518F_EZBRD)
 367         default y
 368
 369 config MEM_MT48H32M16LFCJ_75
 370         bool
 371         depends on (BFIN526_EZBRD)
 372         default y
 373
 374 source "arch/blackfin/mach-bf518/Kconfig"
 375 source "arch/blackfin/mach-bf527/Kconfig"
 376 source "arch/blackfin/mach-bf533/Kconfig"
 377 source "arch/blackfin/mach-bf561/Kconfig"
 378 source "arch/blackfin/mach-bf537/Kconfig"
 379 source "arch/blackfin/mach-bf538/Kconfig"
 380 source "arch/blackfin/mach-bf548/Kconfig"
 381
 382 menu "Board customizations"
 383
 384 config CMDLINE_BOOL
 385         bool "Default bootloader kernel arguments"
 386
 387 config CMDLINE
 388         string "Initial kernel command string"
 389         depends on CMDLINE_BOOL
 390         default "console=ttyBF0,57600"
 391         help
 392           If you don't have a boot loader capable of passing a command line string
 393           to the kernel, you may specify one here. As a minimum, you should specify
 394           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 395
 396 config BOOT_LOAD
 397         hex "Kernel load address for booting"
 398         default "0x1000"
 399         range 0x1000 0x20000000
 400         help
 401           This option allows you to set the load address of the kernel.
 402           This can be useful if you are on a board which has a small amount
 403           of memory or you wish to reserve some memory at the beginning of
 404           the address space.
 405
 406           Note that you need to keep this value above 4k (0x1000) as this
 407           memory region is used to capture NULL pointer references as well
 408           as some core kernel functions.
 409
 410 config ROM_BASE
 411         hex "Kernel ROM Base"
 412         depends on ROMKERNEL
 413         default "0x20040040"
 414         range 0x20000000 0x20400000 if !(BF54x || BF561)
 415         range 0x20000000 0x30000000 if (BF54x || BF561)
 416         help
 417           Make sure your ROM base does not include any file-header
 418           information that is prepended to the kernel.
 419
 420           For example, the bootable U-Boot format (created with
 421           mkimage) has a 64 byte header (0x40).  So while the image
 422           you write to flash might start at say 0x20080000, you have
 423           to add 0x40 to get the kernel's ROM base as it will come
 424           after the header.
 425
 426 comment "Clock/PLL Setup"
 427
 428 config CLKIN_HZ
 429         int "Frequency of the crystal on the board in Hz"
 430         default "10000000" if BFIN532_IP0X
 431         default "11059200" if BFIN533_STAMP
 432         default "24576000" if PNAV10
 433         default "25000000" # most people use this
 434         default "27000000" if BFIN533_EZKIT
 435         default "30000000" if BFIN561_EZKIT
 436         help
 437           The frequency of CLKIN crystal oscillator on the board in Hz.
 438           Warning: This value should match the crystal on the board. Otherwise,
 439           peripherals won't work properly.
 440
 441 config BFIN_KERNEL_CLOCK
 442         bool "Re-program Clocks while Kernel boots?"
 443         default n
 444         help
 445           This option decides if kernel clocks are re-programed from the
 446           bootloader settings. If the clocks are not set, the SDRAM settings
 447           are also not changed, and the Bootloader does 100% of the hardware
 448           configuration.
 449
 450 config PLL_BYPASS
 451         bool "Bypass PLL"
 452         depends on BFIN_KERNEL_CLOCK
 453         default n
 454
 455 config CLKIN_HALF
 456         bool "Half Clock In"
 457         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 458         default n
 459         help
 460           If this is set the clock will be divided by 2, before it goes to the PLL.
 461
 462 config VCO_MULT
 463         int "VCO Multiplier"
 464         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 465         range 1 64
 466         default "22" if BFIN533_EZKIT
 467         default "45" if BFIN533_STAMP
 468         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 469         default "22" if BFIN533_BLUETECHNIX_CM
 470         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 471         default "20" if BFIN561_EZKIT
 472         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 473         help
 474           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 475           PLL Frequency = (Crystal Frequency) * (this setting)
 476
 477 choice
 478         prompt "Core Clock Divider"
 479         depends on BFIN_KERNEL_CLOCK
 480         default CCLK_DIV_1
 481         help
 482           This sets the frequency of the core. It can be 1, 2, 4 or 8
 483           Core Frequency = (PLL frequency) / (this setting)
 484
 485 config CCLK_DIV_1
 486         bool "1"
 487
 488 config CCLK_DIV_2
 489         bool "2"
 490
 491 config CCLK_DIV_4
 492         bool "4"
 493
 494 config CCLK_DIV_8
 495         bool "8"
 496 endchoice
 497
 498 config SCLK_DIV
 499         int "System Clock Divider"
 500         depends on BFIN_KERNEL_CLOCK
 501         range 1 15
 502         default 5
 503         help
 504           This sets the frequency of the system clock (including SDRAM or DDR).
 505           This can be between 1 and 15
 506           System Clock = (PLL frequency) / (this setting)
 507
 508 choice
 509         prompt "DDR SDRAM Chip Type"
 510         depends on BFIN_KERNEL_CLOCK
 511         depends on BF54x
 512         default MEM_MT46V32M16_5B
 513
 514 config MEM_MT46V32M16_6T
 515         bool "MT46V32M16_6T"
 516
 517 config MEM_MT46V32M16_5B
 518         bool "MT46V32M16_5B"
 519 endchoice
 520
 521 choice
 522         prompt "DDR/SDRAM Timing"
 523         depends on BFIN_KERNEL_CLOCK
 524         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 525         help
 526           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 527           The calculated SDRAM timing parameters may not be 100%
 528           accurate - This option is therefore marked experimental.
 529
 530 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 531         bool "Calculate Timings (EXPERIMENTAL)"
 532         depends on EXPERIMENTAL
 533
 534 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 535         bool "Provide accurate Timings based on target SCLK"
 536         help
 537           Please consult the Blackfin Hardware Reference Manuals as well
 538           as the memory device datasheet.
 539           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 540 endchoice
 541
 542 menu "Memory Init Control"
 543         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 544
 545 config MEM_DDRCTL0
 546         depends on BF54x
 547         hex "DDRCTL0"
 548         default 0x0
 549
 550 config MEM_DDRCTL1
 551         depends on BF54x
 552         hex "DDRCTL1"
 553         default 0x0
 554
 555 config MEM_DDRCTL2
 556         depends on BF54x
 557         hex "DDRCTL2"
 558         default 0x0
 559
 560 config MEM_EBIU_DDRQUE
 561         depends on BF54x
 562         hex "DDRQUE"
 563         default 0x0
 564
 565 config MEM_SDRRC
 566         depends on !BF54x
 567         hex "SDRRC"
 568         default 0x0
 569
 570 config MEM_SDGCTL
 571         depends on !BF54x
 572         hex "SDGCTL"
 573         default 0x0
 574 endmenu
 575
 576 #
 577 # Max & Min Speeds for various Chips
 578 #
 579 config MAX_VCO_HZ
 580         int
 581         default 400000000 if BF512
 582         default 400000000 if BF514
 583         default 400000000 if BF516
 584         default 400000000 if BF518
 585         default 400000000 if BF522
 586         default 600000000 if BF523
 587         default 400000000 if BF524
 588         default 600000000 if BF525
 589         default 400000000 if BF526
 590         default 600000000 if BF527
 591         default 400000000 if BF531
 592         default 400000000 if BF532
 593         default 750000000 if BF533
 594         default 500000000 if BF534
 595         default 400000000 if BF536
 596         default 600000000 if BF537
 597         default 533333333 if BF538
 598         default 533333333 if BF539
 599         default 600000000 if BF542
 600         default 533333333 if BF544
 601         default 600000000 if BF547
 602         default 600000000 if BF548
 603         default 533333333 if BF549
 604         default 600000000 if BF561
 605
 606 config MIN_VCO_HZ
 607         int
 608         default 50000000
 609
 610 config MAX_SCLK_HZ
 611         int
 612         default 133333333
 613
 614 config MIN_SCLK_HZ
 615         int
 616         default 27000000
 617
 618 comment "Kernel Timer/Scheduler"
 619
 620 source kernel/Kconfig.hz
 621
 622 config GENERIC_TIME
 623         def_bool y
 624
 625 config GENERIC_CLOCKEVENTS
 626         bool "Generic clock events"
 627         default y
 628
 629 menu "Clock event device"
 630         depends on GENERIC_CLOCKEVENTS
 631 config TICKSOURCE_GPTMR0
 632         bool "GPTimer0"
 633         depends on !SMP
 634         select BFIN_GPTIMERS
 635
 636 config TICKSOURCE_CORETMR
 637         bool "Core timer"
 638         default y
 639 endmenu
 640
 641 menu "Clock souce"
 642         depends on GENERIC_CLOCKEVENTS
 643 config CYCLES_CLOCKSOURCE
 644         bool "CYCLES"
 645         default y
 646         depends on !BFIN_SCRATCH_REG_CYCLES
 647         depends on !SMP
 648         help
 649           If you say Y here, you will enable support for using the 'cycles'
 650           registers as a clock source.  Doing so means you will be unable to
 651           safely write to the 'cycles' register during runtime.  You will
 652           still be able to read it (such as for performance monitoring), but
 653           writing the registers will most likely crash the kernel.
 654
 655 config GPTMR0_CLOCKSOURCE
 656         bool "GPTimer0"
 657         select BFIN_GPTIMERS
 658         depends on !TICKSOURCE_GPTMR0
 659 endmenu
 660
 661 config ARCH_USES_GETTIMEOFFSET
 662         depends on !GENERIC_CLOCKEVENTS
 663         def_bool y
 664
 665 source kernel/time/Kconfig
 666
 667 comment "Misc"
 668
 669 choice
 670         prompt "Blackfin Exception Scratch Register"
 671         default BFIN_SCRATCH_REG_RETN
 672         help
 673           Select the resource to reserve for the Exception handler:
 674             - RETN: Non-Maskable Interrupt (NMI)
 675             - RETE: Exception Return (JTAG/ICE)
 676             - CYCLES: Performance counter
 677
 678           If you are unsure, please select "RETN".
 679
 680 config BFIN_SCRATCH_REG_RETN
 681         bool "RETN"
 682         help
 683           Use the RETN register in the Blackfin exception handler
 684           as a stack scratch register.  This means you cannot
 685           safely use NMI on the Blackfin while running Linux, but
 686           you can debug the system with a JTAG ICE and use the
 687           CYCLES performance registers.
 688
 689           If you are unsure, please select "RETN".
 690
 691 config BFIN_SCRATCH_REG_RETE
 692         bool "RETE"
 693         help
 694           Use the RETE register in the Blackfin exception handler
 695           as a stack scratch register.  This means you cannot
 696           safely use a JTAG ICE while debugging a Blackfin board,
 697           but you can safely use the CYCLES performance registers
 698           and the NMI.
 699
 700           If you are unsure, please select "RETN".
 701
 702 config BFIN_SCRATCH_REG_CYCLES
 703         bool "CYCLES"
 704         help
 705           Use the CYCLES register in the Blackfin exception handler
 706           as a stack scratch register.  This means you cannot
 707           safely use the CYCLES performance registers on a Blackfin
 708           board at anytime, but you can debug the system with a JTAG
 709           ICE and use the NMI.
 710
 711           If you are unsure, please select "RETN".
 712
 713 endchoice
 714
 715 endmenu
 716
 717
 718 menu "Blackfin Kernel Optimizations"
 719         depends on !SMP
 720
 721 comment "Memory Optimizations"
 722
 723 config I_ENTRY_L1
 724         bool "Locate interrupt entry code in L1 Memory"
 725         default y
 726         help
 727           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 728           into L1 instruction memory. (less latency)
 729
 730 config EXCPT_IRQ_SYSC_L1
 731         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 732         default y
 733         help
 734           If enabled, the entire ASM lowlevel exception and interrupt entry code
 735           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 736           (less latency)
 737
 738 config DO_IRQ_L1
 739         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 740         default y
 741         help
 742           If enabled, the frequently called do_irq dispatcher function is linked
 743           into L1 instruction memory. (less latency)
 744
 745 config CORE_TIMER_IRQ_L1
 746         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 747         default y
 748         help
 749           If enabled, the frequently called timer_interrupt() function is linked
 750           into L1 instruction memory. (less latency)
 751
 752 config IDLE_L1
 753         bool "Locate frequently idle function in L1 Memory"
 754         default y
 755         help
 756           If enabled, the frequently called idle function is linked
 757           into L1 instruction memory. (less latency)
 758
 759 config SCHEDULE_L1
 760         bool "Locate kernel schedule function in L1 Memory"
 761         default y
 762         help
 763           If enabled, the frequently called kernel schedule is linked
 764           into L1 instruction memory. (less latency)
 765
 766 config ARITHMETIC_OPS_L1
 767         bool "Locate kernel owned arithmetic functions in L1 Memory"
 768         default y
 769         help
 770           If enabled, arithmetic functions are linked
 771           into L1 instruction memory. (less latency)
 772
 773 config ACCESS_OK_L1
 774         bool "Locate access_ok function in L1 Memory"
 775         default y
 776         help
 777           If enabled, the access_ok function is linked
 778           into L1 instruction memory. (less latency)
 779
 780 config MEMSET_L1
 781         bool "Locate memset function in L1 Memory"
 782         default y
 783         help
 784           If enabled, the memset function is linked
 785           into L1 instruction memory. (less latency)
 786
 787 config MEMCPY_L1
 788         bool "Locate memcpy function in L1 Memory"
 789         default y
 790         help
 791           If enabled, the memcpy function is linked
 792           into L1 instruction memory. (less latency)
 793
 794 config SYS_BFIN_SPINLOCK_L1
 795         bool "Locate sys_bfin_spinlock function in L1 Memory"
 796         default y
 797         help
 798           If enabled, sys_bfin_spinlock function is linked
 799           into L1 instruction memory. (less latency)
 800
 801 config IP_CHECKSUM_L1
 802         bool "Locate IP Checksum function in L1 Memory"
 803         default n
 804         help
 805           If enabled, the IP Checksum function is linked
 806           into L1 instruction memory. (less latency)
 807
 808 config CACHELINE_ALIGNED_L1
 809         bool "Locate cacheline_aligned data to L1 Data Memory"
 810         default y if !BF54x
 811         default n if BF54x
 812         depends on !BF531
 813         help
 814           If enabled, cacheline_aligned data is linked
 815           into L1 data memory. (less latency)
 816
 817 config SYSCALL_TAB_L1
 818         bool "Locate Syscall Table L1 Data Memory"
 819         default n
 820         depends on !BF531
 821         help
 822           If enabled, the Syscall LUT is linked
 823           into L1 data memory. (less latency)
 824
 825 config CPLB_SWITCH_TAB_L1
 826         bool "Locate CPLB Switch Tables L1 Data Memory"
 827         default n
 828         depends on !BF531
 829         help
 830           If enabled, the CPLB Switch Tables are linked
 831           into L1 data memory. (less latency)
 832
 833 config APP_STACK_L1
 834         bool "Support locating application stack in L1 Scratch Memory"
 835         default y
 836         help
 837           If enabled the application stack can be located in L1
 838           scratch memory (less latency).
 839
 840           Currently only works with FLAT binaries.
 841
 842 config EXCEPTION_L1_SCRATCH
 843         bool "Locate exception stack in L1 Scratch Memory"
 844         default n
 845         depends on !APP_STACK_L1
 846         help
 847           Whenever an exception occurs, use the L1 Scratch memory for
 848           stack storage.  You cannot place the stacks of FLAT binaries
 849           in L1 when using this option.
 850
 851           If you don't use L1 Scratch, then you should say Y here.
 852
 853 comment "Speed Optimizations"
 854 config BFIN_INS_LOWOVERHEAD
 855         bool "ins[bwl] low overhead, higher interrupt latency"
 856         default y
 857         help
 858           Reads on the Blackfin are speculative. In Blackfin terms, this means
 859           they can be interrupted at any time (even after they have been issued
 860           on to the external bus), and re-issued after the interrupt occurs.
 861           For memory - this is not a big deal, since memory does not change if
 862           it sees a read.
 863
 864           If a FIFO is sitting on the end of the read, it will see two reads,
 865           when the core only sees one since the FIFO receives both the read
 866           which is cancelled (and not delivered to the core) and the one which
 867           is re-issued (which is delivered to the core).
 868
 869           To solve this, interrupts are turned off before reads occur to
 870           I/O space. This option controls which the overhead/latency of
 871           controlling interrupts during this time
 872            "n" turns interrupts off every read
 873                 (higher overhead, but lower interrupt latency)
 874            "y" turns interrupts off every loop
 875                 (low overhead, but longer interrupt latency)
 876
 877           default behavior is to leave this set to on (type "Y"). If you are experiencing
 878           interrupt latency issues, it is safe and OK to turn this off.
 879
 880 endmenu
 881
 882 choice
 883         prompt "Kernel executes from"
 884         help
 885           Choose the memory type that the kernel will be running in.
 886
 887 config RAMKERNEL
 888         bool "RAM"
 889         help
 890           The kernel will be resident in RAM when running.
 891
 892 config ROMKERNEL
 893         bool "ROM"
 894         help
 895           The kernel will be resident in FLASH/ROM when running.
 896
 897 endchoice
 898
 899 source "mm/Kconfig"
 900
 901 config BFIN_GPTIMERS
 902         tristate "Enable Blackfin General Purpose Timers API"
 903         default n
 904         help
 905           Enable support for the General Purpose Timers API.  If you
 906           are unsure, say N.
 907
 908           To compile this driver as a module, choose M here: the module
 909           will be called gptimers.
 910
 911 choice
 912         prompt "Uncached DMA region"
 913         default DMA_UNCACHED_1M
 914 config DMA_UNCACHED_4M
 915         bool "Enable 4M DMA region"
 916 config DMA_UNCACHED_2M
 917         bool "Enable 2M DMA region"
 918 config DMA_UNCACHED_1M
 919         bool "Enable 1M DMA region"
 920 config DMA_UNCACHED_512K
 921         bool "Enable 512K DMA region"
 922 config DMA_UNCACHED_256K
 923         bool "Enable 256K DMA region"
 924 config DMA_UNCACHED_128K
 925         bool "Enable 128K DMA region"
 926 config DMA_UNCACHED_NONE
 927         bool "Disable DMA region"
 928 endchoice
 929
 930
 931 comment "Cache Support"
 932
 933 config BFIN_ICACHE
 934         bool "Enable ICACHE"
 935         default y
 936 config BFIN_EXTMEM_ICACHEABLE
 937         bool "Enable ICACHE for external memory"
 938         depends on BFIN_ICACHE
 939         default y
 940 config BFIN_L2_ICACHEABLE
 941         bool "Enable ICACHE for L2 SRAM"
 942         depends on BFIN_ICACHE
 943         depends on BF54x || BF561
 944         default n
 945
 946 config BFIN_DCACHE
 947         bool "Enable DCACHE"
 948         default y
 949 config BFIN_DCACHE_BANKA
 950         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 951         depends on BFIN_DCACHE && !BF531
 952         default n
 953 config BFIN_EXTMEM_DCACHEABLE
 954         bool "Enable DCACHE for external memory"
 955         depends on BFIN_DCACHE
 956         default y
 957 choice
 958         prompt "External memory DCACHE policy"
 959         depends on BFIN_EXTMEM_DCACHEABLE
 960         default BFIN_EXTMEM_WRITEBACK if !SMP
 961         default BFIN_EXTMEM_WRITETHROUGH if SMP
 962 config BFIN_EXTMEM_WRITEBACK
 963         bool "Write back"
 964         depends on !SMP
 965         help
 966           Write Back Policy:
 967             Cached data will be written back to SDRAM only when needed.
 968             This can give a nice increase in performance, but beware of
 969             broken drivers that do not properly invalidate/flush their
 970             cache.
 971
 972           Write Through Policy:
 973             Cached data will always be written back to SDRAM when the
 974             cache is updated.  This is a completely safe setting, but
 975             performance is worse than Write Back.
 976
 977           If you are unsure of the options and you want to be safe,
 978           then go with Write Through.
 979
 980 config BFIN_EXTMEM_WRITETHROUGH
 981         bool "Write through"
 982         help
 983           Write Back Policy:
 984             Cached data will be written back to SDRAM only when needed.
 985             This can give a nice increase in performance, but beware of
 986             broken drivers that do not properly invalidate/flush their
 987             cache.
 988
 989           Write Through Policy:
 990             Cached data will always be written back to SDRAM when the
 991             cache is updated.  This is a completely safe setting, but
 992             performance is worse than Write Back.
 993
 994           If you are unsure of the options and you want to be safe,
 995           then go with Write Through.
 996
 997 endchoice
 998
 999 config BFIN_L2_DCACHEABLE
1000         bool "Enable DCACHE for L2 SRAM"
1001         depends on BFIN_DCACHE
1002         depends on (BF54x || BF561) && !SMP
1003         default n
1004 choice
1005         prompt "L2 SRAM DCACHE policy"
1006         depends on BFIN_L2_DCACHEABLE
1007         default BFIN_L2_WRITEBACK
1008 config BFIN_L2_WRITEBACK
1009         bool "Write back"
1010
1011 config BFIN_L2_WRITETHROUGH
1012         bool "Write through"
1013 endchoice
1014
1015
1016 comment "Memory Protection Unit"
1017 config MPU
1018         bool "Enable the memory protection unit (EXPERIMENTAL)"
1019         default n
1020         help
1021           Use the processor's MPU to protect applications from accessing
1022           memory they do not own.  This comes at a performance penalty
1023           and is recommended only for debugging.
1024
1025 comment "Asynchronous Memory Configuration"
1026
1027 menu "EBIU_AMGCTL Global Control"
1028 config C_AMCKEN
1029         bool "Enable CLKOUT"
1030         default y
1031
1032 config C_CDPRIO
1033         bool "DMA has priority over core for ext. accesses"
1034         default n
1035
1036 config C_B0PEN
1037         depends on BF561
1038         bool "Bank 0 16 bit packing enable"
1039         default y
1040
1041 config C_B1PEN
1042         depends on BF561
1043         bool "Bank 1 16 bit packing enable"
1044         default y
1045
1046 config C_B2PEN
1047         depends on BF561
1048         bool "Bank 2 16 bit packing enable"
1049         default y
1050
1051 config C_B3PEN
1052         depends on BF561
1053         bool "Bank 3 16 bit packing enable"
1054         default n
1055
1056 choice
1057         prompt "Enable Asynchronous Memory Banks"
1058         default C_AMBEN_ALL
1059
1060 config C_AMBEN
1061         bool "Disable All Banks"
1062
1063 config C_AMBEN_B0
1064         bool "Enable Bank 0"
1065
1066 config C_AMBEN_B0_B1
1067         bool "Enable Bank 0 & 1"
1068
1069 config C_AMBEN_B0_B1_B2
1070         bool "Enable Bank 0 & 1 & 2"
1071
1072 config C_AMBEN_ALL
1073         bool "Enable All Banks"
1074 endchoice
1075 endmenu
1076
1077 menu "EBIU_AMBCTL Control"
1078 config BANK_0
1079         hex "Bank 0 (AMBCTL0.L)"
1080         default 0x7BB0
1081         help
1082           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1083           used to control the Asynchronous Memory Bank 0 settings.
1084
1085 config BANK_1
1086         hex "Bank 1 (AMBCTL0.H)"
1087         default 0x7BB0
1088         default 0x5558 if BF54x
1089         help
1090           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1091           used to control the Asynchronous Memory Bank 1 settings.
1092
1093 config BANK_2
1094         hex "Bank 2 (AMBCTL1.L)"
1095         default 0x7BB0
1096         help
1097           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1098           used to control the Asynchronous Memory Bank 2 settings.
1099
1100 config BANK_3
1101         hex "Bank 3 (AMBCTL1.H)"
1102         default 0x99B3
1103         help
1104           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1105           used to control the Asynchronous Memory Bank 3 settings.
1106
1107 endmenu
1108
1109 config EBIU_MBSCTLVAL
1110         hex "EBIU Bank Select Control Register"
1111         depends on BF54x
1112         default 0
1113
1114 config EBIU_MODEVAL
1115         hex "Flash Memory Mode Control Register"
1116         depends on BF54x
1117         default 1
1118
1119 config EBIU_FCTLVAL
1120         hex "Flash Memory Bank Control Register"
1121         depends on BF54x
1122         default 6
1123 endmenu
1124
1125 #############################################################################
1126 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1127
1128 config PCI
1129         bool "PCI support"
1130         depends on BROKEN
1131         help
1132           Support for PCI bus.
1133
1134 source "drivers/pci/Kconfig"
1135
1136 source "drivers/pcmcia/Kconfig"
1137
1138 source "drivers/pci/hotplug/Kconfig"
1139
1140 endmenu
1141
1142 menu "Executable file formats"
1143
1144 source "fs/Kconfig.binfmt"
1145
1146 endmenu
1147
1148 menu "Power management options"
1149
1150 source "kernel/power/Kconfig"
1151
1152 config ARCH_SUSPEND_POSSIBLE
1153         def_bool y
1154
1155 choice
1156         prompt "Standby Power Saving Mode"
1157         depends on PM
1158         default PM_BFIN_SLEEP_DEEPER
1159 config  PM_BFIN_SLEEP_DEEPER
1160         bool "Sleep Deeper"
1161         help
1162           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1163           power dissipation by disabling the clock to the processor core (CCLK).
1164           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1165           to 0.85 V to provide the greatest power savings, while preserving the
1166           processor state.
1167           The PLL and system clock (SCLK) continue to operate at a very low
1168           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1169           the SDRAM is put into Self Refresh Mode. Typically an external event
1170           such as GPIO interrupt or RTC activity wakes up the processor.
1171           Various Peripherals such as UART, SPORT, PPI may not function as
1172           normal during Sleep Deeper, due to the reduced SCLK frequency.
1173           When in the sleep mode, system DMA access to L1 memory is not supported.
1174
1175           If unsure, select "Sleep Deeper".
1176
1177 config  PM_BFIN_SLEEP
1178         bool "Sleep"
1179         help
1180           Sleep Mode (High Power Savings) - The sleep mode reduces power
1181           dissipation by disabling the clock to the processor core (CCLK).
1182           The PLL and system clock (SCLK), however, continue to operate in
1183           this mode. Typically an external event or RTC activity will wake
1184           up the processor. When in the sleep mode, system DMA access to L1
1185           memory is not supported.
1186
1187           If unsure, select "Sleep Deeper".
1188 endchoice
1189
1190 config PM_WAKEUP_BY_GPIO
1191         bool "Allow Wakeup from Standby by GPIO"
1192         depends on PM && !BF54x
1193
1194 config PM_WAKEUP_GPIO_NUMBER
1195         int "GPIO number"
1196         range 0 47
1197         depends on PM_WAKEUP_BY_GPIO
1198         default 2
1199
1200 choice
1201         prompt "GPIO Polarity"
1202         depends on PM_WAKEUP_BY_GPIO
1203         default PM_WAKEUP_GPIO_POLAR_H
1204 config  PM_WAKEUP_GPIO_POLAR_H
1205         bool "Active High"
1206 config  PM_WAKEUP_GPIO_POLAR_L
1207         bool "Active Low"
1208 config  PM_WAKEUP_GPIO_POLAR_EDGE_F
1209         bool "Falling EDGE"
1210 config  PM_WAKEUP_GPIO_POLAR_EDGE_R
1211         bool "Rising EDGE"
1212 config  PM_WAKEUP_GPIO_POLAR_EDGE_B
1213         bool "Both EDGE"
1214 endchoice
1215
1216 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1217         depends on PM
1218
1219 config PM_BFIN_WAKE_PH6
1220         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1221         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1222         default n
1223         help
1224           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1225
1226 config PM_BFIN_WAKE_GP
1227         bool "Allow Wake-Up from GPIOs"
1228         depends on PM && BF54x
1229         default n
1230         help
1231           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1232           (all processors, except ADSP-BF549). This option sets
1233           the general-purpose wake-up enable (GPWE) control bit to enable
1234           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1235           On ADSP-BF549 this option enables the the same functionality on the
1236           /MRXON pin also PH7.
1237
1238 endmenu
1239
1240 menu "CPU Frequency scaling"
1241
1242 source "drivers/cpufreq/Kconfig"
1243
1244 config BFIN_CPU_FREQ
1245         bool
1246         depends on CPU_FREQ
1247         select CPU_FREQ_TABLE
1248         default y
1249
1250 config CPU_VOLTAGE
1251         bool "CPU Voltage scaling"
1252         depends on EXPERIMENTAL
1253         depends on CPU_FREQ
1254         default n
1255         help
1256           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1257           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1258           manuals. There is a theoretical risk that during VDDINT transitions
1259           the PLL may unlock.
1260
1261 endmenu
1262
1263 source "net/Kconfig"
1264
1265 source "drivers/Kconfig"
1266
1267 source "drivers/firmware/Kconfig"
1268
1269 source "fs/Kconfig"
1270
1271 source "arch/blackfin/Kconfig.debug"
1272
1273 source "security/Kconfig"
1274
1275 source "crypto/Kconfig"
1276
1277 source "lib/Kconfig"