arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config SYMBOL_PREFIX
   9         string
  10         default "_"
  11
  12 config MMU
  13         def_bool n
  14
  15 config FPU
  16         def_bool n
  17
  18 config RWSEM_GENERIC_SPINLOCK
  19         def_bool y
  20
  21 config RWSEM_XCHGADD_ALGORITHM
  22         def_bool n
  23
  24 config BLACKFIN
  25         def_bool y
  26         select HAVE_ARCH_KGDB
  27         select HAVE_ARCH_TRACEHOOK
  28         select HAVE_FUNCTION_GRAPH_TRACER
  29         select HAVE_FUNCTION_TRACER
  30         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  31         select HAVE_IDE
  32         select HAVE_KERNEL_GZIP if RAMKERNEL
  33         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  34         select HAVE_KERNEL_LZMA if RAMKERNEL
  35         select HAVE_OPROFILE
  36         select ARCH_WANT_OPTIONAL_GPIOLIB
  37
  38 config GENERIC_CSUM
  39         def_bool y
  40
  41 config GENERIC_BUG
  42         def_bool y
  43         depends on BUG
  44
  45 config ZONE_DMA
  46         def_bool y
  47
  48 config GENERIC_FIND_NEXT_BIT
  49         def_bool y
  50
  51 config GENERIC_HARDIRQS
  52         def_bool y
  53
  54 config GENERIC_IRQ_PROBE
  55         def_bool y
  56
  57 config GENERIC_HARDIRQS_NO__DO_IRQ
  58         def_bool y
  59
  60 config GENERIC_GPIO
  61         def_bool y
  62
  63 config FORCE_MAX_ZONEORDER
  64         int
  65         default "14"
  66
  67 config GENERIC_CALIBRATE_DELAY
  68         def_bool y
  69
  70 config LOCKDEP_SUPPORT
  71         def_bool y
  72
  73 config STACKTRACE_SUPPORT
  74         def_bool y
  75
  76 config TRACE_IRQFLAGS_SUPPORT
  77         def_bool y
  78
  79 source "init/Kconfig"
  80
  81 source "kernel/Kconfig.preempt"
  82
  83 source "kernel/Kconfig.freezer"
  84
  85 menu "Blackfin Processor Options"
  86
  87 comment "Processor and Board Settings"
  88
  89 choice
  90         prompt "CPU"
  91         default BF533
  92
  93 config BF512
  94         bool "BF512"
  95         help
  96           BF512 Processor Support.
  97
  98 config BF514
  99         bool "BF514"
 100         help
 101           BF514 Processor Support.
 102
 103 config BF516
 104         bool "BF516"
 105         help
 106           BF516 Processor Support.
 107
 108 config BF518
 109         bool "BF518"
 110         help
 111           BF518 Processor Support.
 112
 113 config BF522
 114         bool "BF522"
 115         help
 116           BF522 Processor Support.
 117
 118 config BF523
 119         bool "BF523"
 120         help
 121           BF523 Processor Support.
 122
 123 config BF524
 124         bool "BF524"
 125         help
 126           BF524 Processor Support.
 127
 128 config BF525
 129         bool "BF525"
 130         help
 131           BF525 Processor Support.
 132
 133 config BF526
 134         bool "BF526"
 135         help
 136           BF526 Processor Support.
 137
 138 config BF527
 139         bool "BF527"
 140         help
 141           BF527 Processor Support.
 142
 143 config BF531
 144         bool "BF531"
 145         help
 146           BF531 Processor Support.
 147
 148 config BF532
 149         bool "BF532"
 150         help
 151           BF532 Processor Support.
 152
 153 config BF533
 154         bool "BF533"
 155         help
 156           BF533 Processor Support.
 157
 158 config BF534
 159         bool "BF534"
 160         help
 161           BF534 Processor Support.
 162
 163 config BF536
 164         bool "BF536"
 165         help
 166           BF536 Processor Support.
 167
 168 config BF537
 169         bool "BF537"
 170         help
 171           BF537 Processor Support.
 172
 173 config BF538
 174         bool "BF538"
 175         help
 176           BF538 Processor Support.
 177
 178 config BF539
 179         bool "BF539"
 180         help
 181           BF539 Processor Support.
 182
 183 config BF542_std
 184         bool "BF542"
 185         help
 186           BF542 Processor Support.
 187
 188 config BF542M
 189         bool "BF542m"
 190         help
 191           BF542 Processor Support.
 192
 193 config BF544_std
 194         bool "BF544"
 195         help
 196           BF544 Processor Support.
 197
 198 config BF544M
 199         bool "BF544m"
 200         help
 201           BF544 Processor Support.
 202
 203 config BF547_std
 204         bool "BF547"
 205         help
 206           BF547 Processor Support.
 207
 208 config BF547M
 209         bool "BF547m"
 210         help
 211           BF547 Processor Support.
 212
 213 config BF548_std
 214         bool "BF548"
 215         help
 216           BF548 Processor Support.
 217
 218 config BF548M
 219         bool "BF548m"
 220         help
 221           BF548 Processor Support.
 222
 223 config BF549_std
 224         bool "BF549"
 225         help
 226           BF549 Processor Support.
 227
 228 config BF549M
 229         bool "BF549m"
 230         help
 231           BF549 Processor Support.
 232
 233 config BF561
 234         bool "BF561"
 235         help
 236           BF561 Processor Support.
 237
 238 endchoice
 239
 240 config SMP
 241         depends on BF561
 242         select TICKSOURCE_CORETMR
 243         bool "Symmetric multi-processing support"
 244         ---help---
 245           This enables support for systems with more than one CPU,
 246           like the dual core BF561. If you have a system with only one
 247           CPU, say N. If you have a system with more than one CPU, say Y.
 248
 249           If you don't know what to do here, say N.
 250
 251 config NR_CPUS
 252         int
 253         depends on SMP
 254         default 2 if BF561
 255
 256 config HOTPLUG_CPU
 257         bool "Support for hot-pluggable CPUs"
 258         depends on SMP && HOTPLUG
 259         default y
 260
 261 config IRQ_PER_CPU
 262         bool
 263         depends on SMP
 264         default y
 265
 266 config HAVE_LEGACY_PER_CPU_AREA
 267         def_bool y
 268         depends on SMP
 269
 270 config BF_REV_MIN
 271         int
 272         default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
 273         default 2 if (BF537 || BF536 || BF534)
 274         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 275         default 4 if (BF538 || BF539)
 276
 277 config BF_REV_MAX
 278         int
 279         default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
 280         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 281         default 5 if (BF561 || BF538 || BF539)
 282         default 6 if (BF533 || BF532 || BF531)
 283
 284 choice
 285         prompt "Silicon Rev"
 286         default BF_REV_0_0 if (BF51x || BF52x)
 287         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 288         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 289
 290 config BF_REV_0_0
 291         bool "0.0"
 292         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 293
 294 config BF_REV_0_1
 295         bool "0.1"
 296         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 297
 298 config BF_REV_0_2
 299         bool "0.2"
 300         depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 301
 302 config BF_REV_0_3
 303         bool "0.3"
 304         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 305
 306 config BF_REV_0_4
 307         bool "0.4"
 308         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 309
 310 config BF_REV_0_5
 311         bool "0.5"
 312         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 313
 314 config BF_REV_0_6
 315         bool "0.6"
 316         depends on (BF533 || BF532 || BF531)
 317
 318 config BF_REV_ANY
 319         bool "any"
 320
 321 config BF_REV_NONE
 322         bool "none"
 323
 324 endchoice
 325
 326 config BF53x
 327         bool
 328         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 329         default y
 330
 331 config MEM_GENERIC_BOARD
 332         bool
 333         depends on GENERIC_BOARD
 334         default y
 335
 336 config MEM_MT48LC64M4A2FB_7E
 337         bool
 338         depends on (BFIN533_STAMP)
 339         default y
 340
 341 config MEM_MT48LC16M16A2TG_75
 342         bool
 343         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 344                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 345                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 346                 || BFIN527_BLUETECHNIX_CM)
 347         default y
 348
 349 config MEM_MT48LC32M8A2_75
 350         bool
 351         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 352         default y
 353
 354 config MEM_MT48LC8M32B2B5_7
 355         bool
 356         depends on (BFIN561_BLUETECHNIX_CM)
 357         default y
 358
 359 config MEM_MT48LC32M16A2TG_75
 360         bool
 361         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
 362         default y
 363
 364 config MEM_MT48H32M16LFCJ_75
 365         bool
 366         depends on (BFIN526_EZBRD)
 367         default y
 368
 369 source "arch/blackfin/mach-bf518/Kconfig"
 370 source "arch/blackfin/mach-bf527/Kconfig"
 371 source "arch/blackfin/mach-bf533/Kconfig"
 372 source "arch/blackfin/mach-bf561/Kconfig"
 373 source "arch/blackfin/mach-bf537/Kconfig"
 374 source "arch/blackfin/mach-bf538/Kconfig"
 375 source "arch/blackfin/mach-bf548/Kconfig"
 376
 377 menu "Board customizations"
 378
 379 config CMDLINE_BOOL
 380         bool "Default bootloader kernel arguments"
 381
 382 config CMDLINE
 383         string "Initial kernel command string"
 384         depends on CMDLINE_BOOL
 385         default "console=ttyBF0,57600"
 386         help
 387           If you don't have a boot loader capable of passing a command line string
 388           to the kernel, you may specify one here. As a minimum, you should specify
 389           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 390
 391 config BOOT_LOAD
 392         hex "Kernel load address for booting"
 393         default "0x1000"
 394         range 0x1000 0x20000000
 395         help
 396           This option allows you to set the load address of the kernel.
 397           This can be useful if you are on a board which has a small amount
 398           of memory or you wish to reserve some memory at the beginning of
 399           the address space.
 400
 401           Note that you need to keep this value above 4k (0x1000) as this
 402           memory region is used to capture NULL pointer references as well
 403           as some core kernel functions.
 404
 405 config ROM_BASE
 406         hex "Kernel ROM Base"
 407         depends on ROMKERNEL
 408         default "0x20040040"
 409         range 0x20000000 0x20400000 if !(BF54x || BF561)
 410         range 0x20000000 0x30000000 if (BF54x || BF561)
 411         help
 412           Make sure your ROM base does not include any file-header
 413           information that is prepended to the kernel.
 414
 415           For example, the bootable U-Boot format (created with
 416           mkimage) has a 64 byte header (0x40).  So while the image
 417           you write to flash might start at say 0x20080000, you have
 418           to add 0x40 to get the kernel's ROM base as it will come
 419           after the header.
 420
 421 comment "Clock/PLL Setup"
 422
 423 config CLKIN_HZ
 424         int "Frequency of the crystal on the board in Hz"
 425         default "10000000" if BFIN532_IP0X
 426         default "11059200" if BFIN533_STAMP
 427         default "24576000" if PNAV10
 428         default "25000000" # most people use this
 429         default "27000000" if BFIN533_EZKIT
 430         default "30000000" if BFIN561_EZKIT
 431         help
 432           The frequency of CLKIN crystal oscillator on the board in Hz.
 433           Warning: This value should match the crystal on the board. Otherwise,
 434           peripherals won't work properly.
 435
 436 config BFIN_KERNEL_CLOCK
 437         bool "Re-program Clocks while Kernel boots?"
 438         default n
 439         help
 440           This option decides if kernel clocks are re-programed from the
 441           bootloader settings. If the clocks are not set, the SDRAM settings
 442           are also not changed, and the Bootloader does 100% of the hardware
 443           configuration.
 444
 445 config PLL_BYPASS
 446         bool "Bypass PLL"
 447         depends on BFIN_KERNEL_CLOCK
 448         default n
 449
 450 config CLKIN_HALF
 451         bool "Half Clock In"
 452         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 453         default n
 454         help
 455           If this is set the clock will be divided by 2, before it goes to the PLL.
 456
 457 config VCO_MULT
 458         int "VCO Multiplier"
 459         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 460         range 1 64
 461         default "22" if BFIN533_EZKIT
 462         default "45" if BFIN533_STAMP
 463         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 464         default "22" if BFIN533_BLUETECHNIX_CM
 465         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 466         default "20" if BFIN561_EZKIT
 467         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 468         help
 469           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 470           PLL Frequency = (Crystal Frequency) * (this setting)
 471
 472 choice
 473         prompt "Core Clock Divider"
 474         depends on BFIN_KERNEL_CLOCK
 475         default CCLK_DIV_1
 476         help
 477           This sets the frequency of the core. It can be 1, 2, 4 or 8
 478           Core Frequency = (PLL frequency) / (this setting)
 479
 480 config CCLK_DIV_1
 481         bool "1"
 482
 483 config CCLK_DIV_2
 484         bool "2"
 485
 486 config CCLK_DIV_4
 487         bool "4"
 488
 489 config CCLK_DIV_8
 490         bool "8"
 491 endchoice
 492
 493 config SCLK_DIV
 494         int "System Clock Divider"
 495         depends on BFIN_KERNEL_CLOCK
 496         range 1 15
 497         default 5
 498         help
 499           This sets the frequency of the system clock (including SDRAM or DDR).
 500           This can be between 1 and 15
 501           System Clock = (PLL frequency) / (this setting)
 502
 503 choice
 504         prompt "DDR SDRAM Chip Type"
 505         depends on BFIN_KERNEL_CLOCK
 506         depends on BF54x
 507         default MEM_MT46V32M16_5B
 508
 509 config MEM_MT46V32M16_6T
 510         bool "MT46V32M16_6T"
 511
 512 config MEM_MT46V32M16_5B
 513         bool "MT46V32M16_5B"
 514 endchoice
 515
 516 choice
 517         prompt "DDR/SDRAM Timing"
 518         depends on BFIN_KERNEL_CLOCK
 519         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 520         help
 521           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 522           The calculated SDRAM timing parameters may not be 100%
 523           accurate - This option is therefore marked experimental.
 524
 525 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 526         bool "Calculate Timings (EXPERIMENTAL)"
 527         depends on EXPERIMENTAL
 528
 529 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 530         bool "Provide accurate Timings based on target SCLK"
 531         help
 532           Please consult the Blackfin Hardware Reference Manuals as well
 533           as the memory device datasheet.
 534           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 535 endchoice
 536
 537 menu "Memory Init Control"
 538         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 539
 540 config MEM_DDRCTL0
 541         depends on BF54x
 542         hex "DDRCTL0"
 543         default 0x0
 544
 545 config MEM_DDRCTL1
 546         depends on BF54x
 547         hex "DDRCTL1"
 548         default 0x0
 549
 550 config MEM_DDRCTL2
 551         depends on BF54x
 552         hex "DDRCTL2"
 553         default 0x0
 554
 555 config MEM_EBIU_DDRQUE
 556         depends on BF54x
 557         hex "DDRQUE"
 558         default 0x0
 559
 560 config MEM_SDRRC
 561         depends on !BF54x
 562         hex "SDRRC"
 563         default 0x0
 564
 565 config MEM_SDGCTL
 566         depends on !BF54x
 567         hex "SDGCTL"
 568         default 0x0
 569 endmenu
 570
 571 #
 572 # Max & Min Speeds for various Chips
 573 #
 574 config MAX_VCO_HZ
 575         int
 576         default 400000000 if BF512
 577         default 400000000 if BF514
 578         default 400000000 if BF516
 579         default 400000000 if BF518
 580         default 400000000 if BF522
 581         default 600000000 if BF523
 582         default 400000000 if BF524
 583         default 600000000 if BF525
 584         default 400000000 if BF526
 585         default 600000000 if BF527
 586         default 400000000 if BF531
 587         default 400000000 if BF532
 588         default 750000000 if BF533
 589         default 500000000 if BF534
 590         default 400000000 if BF536
 591         default 600000000 if BF537
 592         default 533333333 if BF538
 593         default 533333333 if BF539
 594         default 600000000 if BF542
 595         default 533333333 if BF544
 596         default 600000000 if BF547
 597         default 600000000 if BF548
 598         default 533333333 if BF549
 599         default 600000000 if BF561
 600
 601 config MIN_VCO_HZ
 602         int
 603         default 50000000
 604
 605 config MAX_SCLK_HZ
 606         int
 607         default 133333333
 608
 609 config MIN_SCLK_HZ
 610         int
 611         default 27000000
 612
 613 comment "Kernel Timer/Scheduler"
 614
 615 source kernel/Kconfig.hz
 616
 617 config GENERIC_TIME
 618         def_bool y
 619
 620 config GENERIC_CLOCKEVENTS
 621         bool "Generic clock events"
 622         default y
 623
 624 menu "Clock event device"
 625         depends on GENERIC_CLOCKEVENTS
 626 config TICKSOURCE_GPTMR0
 627         bool "GPTimer0"
 628         depends on !SMP
 629         select BFIN_GPTIMERS
 630
 631 config TICKSOURCE_CORETMR
 632         bool "Core timer"
 633         default y
 634 endmenu
 635
 636 menu "Clock souce"
 637         depends on GENERIC_CLOCKEVENTS
 638 config CYCLES_CLOCKSOURCE
 639         bool "CYCLES"
 640         default y
 641         depends on !BFIN_SCRATCH_REG_CYCLES
 642         depends on !SMP
 643         help
 644           If you say Y here, you will enable support for using the 'cycles'
 645           registers as a clock source.  Doing so means you will be unable to
 646           safely write to the 'cycles' register during runtime.  You will
 647           still be able to read it (such as for performance monitoring), but
 648           writing the registers will most likely crash the kernel.
 649
 650 config GPTMR0_CLOCKSOURCE
 651         bool "GPTimer0"
 652         select BFIN_GPTIMERS
 653         depends on !TICKSOURCE_GPTMR0
 654 endmenu
 655
 656 config ARCH_USES_GETTIMEOFFSET
 657         depends on !GENERIC_CLOCKEVENTS
 658         def_bool y
 659
 660 source kernel/time/Kconfig
 661
 662 comment "Misc"
 663
 664 choice
 665         prompt "Blackfin Exception Scratch Register"
 666         default BFIN_SCRATCH_REG_RETN
 667         help
 668           Select the resource to reserve for the Exception handler:
 669             - RETN: Non-Maskable Interrupt (NMI)
 670             - RETE: Exception Return (JTAG/ICE)
 671             - CYCLES: Performance counter
 672
 673           If you are unsure, please select "RETN".
 674
 675 config BFIN_SCRATCH_REG_RETN
 676         bool "RETN"
 677         help
 678           Use the RETN register in the Blackfin exception handler
 679           as a stack scratch register.  This means you cannot
 680           safely use NMI on the Blackfin while running Linux, but
 681           you can debug the system with a JTAG ICE and use the
 682           CYCLES performance registers.
 683
 684           If you are unsure, please select "RETN".
 685
 686 config BFIN_SCRATCH_REG_RETE
 687         bool "RETE"
 688         help
 689           Use the RETE register in the Blackfin exception handler
 690           as a stack scratch register.  This means you cannot
 691           safely use a JTAG ICE while debugging a Blackfin board,
 692           but you can safely use the CYCLES performance registers
 693           and the NMI.
 694
 695           If you are unsure, please select "RETN".
 696
 697 config BFIN_SCRATCH_REG_CYCLES
 698         bool "CYCLES"
 699         help
 700           Use the CYCLES register in the Blackfin exception handler
 701           as a stack scratch register.  This means you cannot
 702           safely use the CYCLES performance registers on a Blackfin
 703           board at anytime, but you can debug the system with a JTAG
 704           ICE and use the NMI.
 705
 706           If you are unsure, please select "RETN".
 707
 708 endchoice
 709
 710 endmenu
 711
 712
 713 menu "Blackfin Kernel Optimizations"
 714         depends on !SMP
 715
 716 comment "Memory Optimizations"
 717
 718 config I_ENTRY_L1
 719         bool "Locate interrupt entry code in L1 Memory"
 720         default y
 721         help
 722           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 723           into L1 instruction memory. (less latency)
 724
 725 config EXCPT_IRQ_SYSC_L1
 726         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 727         default y
 728         help
 729           If enabled, the entire ASM lowlevel exception and interrupt entry code
 730           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 731           (less latency)
 732
 733 config DO_IRQ_L1
 734         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 735         default y
 736         help
 737           If enabled, the frequently called do_irq dispatcher function is linked
 738           into L1 instruction memory. (less latency)
 739
 740 config CORE_TIMER_IRQ_L1
 741         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 742         default y
 743         help
 744           If enabled, the frequently called timer_interrupt() function is linked
 745           into L1 instruction memory. (less latency)
 746
 747 config IDLE_L1
 748         bool "Locate frequently idle function in L1 Memory"
 749         default y
 750         help
 751           If enabled, the frequently called idle function is linked
 752           into L1 instruction memory. (less latency)
 753
 754 config SCHEDULE_L1
 755         bool "Locate kernel schedule function in L1 Memory"
 756         default y
 757         help
 758           If enabled, the frequently called kernel schedule is linked
 759           into L1 instruction memory. (less latency)
 760
 761 config ARITHMETIC_OPS_L1
 762         bool "Locate kernel owned arithmetic functions in L1 Memory"
 763         default y
 764         help
 765           If enabled, arithmetic functions are linked
 766           into L1 instruction memory. (less latency)
 767
 768 config ACCESS_OK_L1
 769         bool "Locate access_ok function in L1 Memory"
 770         default y
 771         help
 772           If enabled, the access_ok function is linked
 773           into L1 instruction memory. (less latency)
 774
 775 config MEMSET_L1
 776         bool "Locate memset function in L1 Memory"
 777         default y
 778         help
 779           If enabled, the memset function is linked
 780           into L1 instruction memory. (less latency)
 781
 782 config MEMCPY_L1
 783         bool "Locate memcpy function in L1 Memory"
 784         default y
 785         help
 786           If enabled, the memcpy function is linked
 787           into L1 instruction memory. (less latency)
 788
 789 config STRCMP_L1
 790         bool "locate strcmp function in L1 Memory"
 791         default y
 792         help
 793           If enabled, the strcmp function is linked
 794           into L1 instruction memory (less latency).
 795
 796 config STRNCMP_L1
 797         bool "locate strncmp function in L1 Memory"
 798         default y
 799         help
 800           If enabled, the strncmp function is linked
 801           into L1 instruction memory (less latency).
 802
 803 config STRCPY_L1
 804         bool "locate strcpy function in L1 Memory"
 805         default y
 806         help
 807           If enabled, the strcpy function is linked
 808           into L1 instruction memory (less latency).
 809
 810 config STRNCPY_L1
 811         bool "locate strncpy function in L1 Memory"
 812         default y
 813         help
 814           If enabled, the strncpy function is linked
 815           into L1 instruction memory (less latency).
 816
 817 config SYS_BFIN_SPINLOCK_L1
 818         bool "Locate sys_bfin_spinlock function in L1 Memory"
 819         default y
 820         help
 821           If enabled, sys_bfin_spinlock function is linked
 822           into L1 instruction memory. (less latency)
 823
 824 config IP_CHECKSUM_L1
 825         bool "Locate IP Checksum function in L1 Memory"
 826         default n
 827         help
 828           If enabled, the IP Checksum function is linked
 829           into L1 instruction memory. (less latency)
 830
 831 config CACHELINE_ALIGNED_L1
 832         bool "Locate cacheline_aligned data to L1 Data Memory"
 833         default y if !BF54x
 834         default n if BF54x
 835         depends on !BF531
 836         help
 837           If enabled, cacheline_aligned data is linked
 838           into L1 data memory. (less latency)
 839
 840 config SYSCALL_TAB_L1
 841         bool "Locate Syscall Table L1 Data Memory"
 842         default n
 843         depends on !BF531
 844         help
 845           If enabled, the Syscall LUT is linked
 846           into L1 data memory. (less latency)
 847
 848 config CPLB_SWITCH_TAB_L1
 849         bool "Locate CPLB Switch Tables L1 Data Memory"
 850         default n
 851         depends on !BF531
 852         help
 853           If enabled, the CPLB Switch Tables are linked
 854           into L1 data memory. (less latency)
 855
 856 config APP_STACK_L1
 857         bool "Support locating application stack in L1 Scratch Memory"
 858         default y
 859         help
 860           If enabled the application stack can be located in L1
 861           scratch memory (less latency).
 862
 863           Currently only works with FLAT binaries.
 864
 865 config EXCEPTION_L1_SCRATCH
 866         bool "Locate exception stack in L1 Scratch Memory"
 867         default n
 868         depends on !APP_STACK_L1
 869         help
 870           Whenever an exception occurs, use the L1 Scratch memory for
 871           stack storage.  You cannot place the stacks of FLAT binaries
 872           in L1 when using this option.
 873
 874           If you don't use L1 Scratch, then you should say Y here.
 875
 876 comment "Speed Optimizations"
 877 config BFIN_INS_LOWOVERHEAD
 878         bool "ins[bwl] low overhead, higher interrupt latency"
 879         default y
 880         help
 881           Reads on the Blackfin are speculative. In Blackfin terms, this means
 882           they can be interrupted at any time (even after they have been issued
 883           on to the external bus), and re-issued after the interrupt occurs.
 884           For memory - this is not a big deal, since memory does not change if
 885           it sees a read.
 886
 887           If a FIFO is sitting on the end of the read, it will see two reads,
 888           when the core only sees one since the FIFO receives both the read
 889           which is cancelled (and not delivered to the core) and the one which
 890           is re-issued (which is delivered to the core).
 891
 892           To solve this, interrupts are turned off before reads occur to
 893           I/O space. This option controls which the overhead/latency of
 894           controlling interrupts during this time
 895            "n" turns interrupts off every read
 896                 (higher overhead, but lower interrupt latency)
 897            "y" turns interrupts off every loop
 898                 (low overhead, but longer interrupt latency)
 899
 900           default behavior is to leave this set to on (type "Y"). If you are experiencing
 901           interrupt latency issues, it is safe and OK to turn this off.
 902
 903 endmenu
 904
 905 choice
 906         prompt "Kernel executes from"
 907         help
 908           Choose the memory type that the kernel will be running in.
 909
 910 config RAMKERNEL
 911         bool "RAM"
 912         help
 913           The kernel will be resident in RAM when running.
 914
 915 config ROMKERNEL
 916         bool "ROM"
 917         help
 918           The kernel will be resident in FLASH/ROM when running.
 919
 920 endchoice
 921
 922 source "mm/Kconfig"
 923
 924 config BFIN_GPTIMERS
 925         tristate "Enable Blackfin General Purpose Timers API"
 926         default n
 927         help
 928           Enable support for the General Purpose Timers API.  If you
 929           are unsure, say N.
 930
 931           To compile this driver as a module, choose M here: the module
 932           will be called gptimers.
 933
 934 choice
 935         prompt "Uncached DMA region"
 936         default DMA_UNCACHED_1M
 937 config DMA_UNCACHED_4M
 938         bool "Enable 4M DMA region"
 939 config DMA_UNCACHED_2M
 940         bool "Enable 2M DMA region"
 941 config DMA_UNCACHED_1M
 942         bool "Enable 1M DMA region"
 943 config DMA_UNCACHED_512K
 944         bool "Enable 512K DMA region"
 945 config DMA_UNCACHED_256K
 946         bool "Enable 256K DMA region"
 947 config DMA_UNCACHED_128K
 948         bool "Enable 128K DMA region"
 949 config DMA_UNCACHED_NONE
 950         bool "Disable DMA region"
 951 endchoice
 952
 953
 954 comment "Cache Support"
 955
 956 config BFIN_ICACHE
 957         bool "Enable ICACHE"
 958         default y
 959 config BFIN_EXTMEM_ICACHEABLE
 960         bool "Enable ICACHE for external memory"
 961         depends on BFIN_ICACHE
 962         default y
 963 config BFIN_L2_ICACHEABLE
 964         bool "Enable ICACHE for L2 SRAM"
 965         depends on BFIN_ICACHE
 966         depends on BF54x || BF561
 967         default n
 968
 969 config BFIN_DCACHE
 970         bool "Enable DCACHE"
 971         default y
 972 config BFIN_DCACHE_BANKA
 973         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 974         depends on BFIN_DCACHE && !BF531
 975         default n
 976 config BFIN_EXTMEM_DCACHEABLE
 977         bool "Enable DCACHE for external memory"
 978         depends on BFIN_DCACHE
 979         default y
 980 choice
 981         prompt "External memory DCACHE policy"
 982         depends on BFIN_EXTMEM_DCACHEABLE
 983         default BFIN_EXTMEM_WRITEBACK if !SMP
 984         default BFIN_EXTMEM_WRITETHROUGH if SMP
 985 config BFIN_EXTMEM_WRITEBACK
 986         bool "Write back"
 987         depends on !SMP
 988         help
 989           Write Back Policy:
 990             Cached data will be written back to SDRAM only when needed.
 991             This can give a nice increase in performance, but beware of
 992             broken drivers that do not properly invalidate/flush their
 993             cache.
 994
 995           Write Through Policy:
 996             Cached data will always be written back to SDRAM when the
 997             cache is updated.  This is a completely safe setting, but
 998             performance is worse than Write Back.
 999
1000           If you are unsure of the options and you want to be safe,
1001           then go with Write Through.
1002
1003 config BFIN_EXTMEM_WRITETHROUGH
1004         bool "Write through"
1005         help
1006           Write Back Policy:
1007             Cached data will be written back to SDRAM only when needed.
1008             This can give a nice increase in performance, but beware of
1009             broken drivers that do not properly invalidate/flush their
1010             cache.
1011
1012           Write Through Policy:
1013             Cached data will always be written back to SDRAM when the
1014             cache is updated.  This is a completely safe setting, but
1015             performance is worse than Write Back.
1016
1017           If you are unsure of the options and you want to be safe,
1018           then go with Write Through.
1019
1020 endchoice
1021
1022 config BFIN_L2_DCACHEABLE
1023         bool "Enable DCACHE for L2 SRAM"
1024         depends on BFIN_DCACHE
1025         depends on (BF54x || BF561) && !SMP
1026         default n
1027 choice
1028         prompt "L2 SRAM DCACHE policy"
1029         depends on BFIN_L2_DCACHEABLE
1030         default BFIN_L2_WRITEBACK
1031 config BFIN_L2_WRITEBACK
1032         bool "Write back"
1033
1034 config BFIN_L2_WRITETHROUGH
1035         bool "Write through"
1036 endchoice
1037
1038
1039 comment "Memory Protection Unit"
1040 config MPU
1041         bool "Enable the memory protection unit (EXPERIMENTAL)"
1042         default n
1043         help
1044           Use the processor's MPU to protect applications from accessing
1045           memory they do not own.  This comes at a performance penalty
1046           and is recommended only for debugging.
1047
1048 comment "Asynchronous Memory Configuration"
1049
1050 menu "EBIU_AMGCTL Global Control"
1051 config C_AMCKEN
1052         bool "Enable CLKOUT"
1053         default y
1054
1055 config C_CDPRIO
1056         bool "DMA has priority over core for ext. accesses"
1057         default n
1058
1059 config C_B0PEN
1060         depends on BF561
1061         bool "Bank 0 16 bit packing enable"
1062         default y
1063
1064 config C_B1PEN
1065         depends on BF561
1066         bool "Bank 1 16 bit packing enable"
1067         default y
1068
1069 config C_B2PEN
1070         depends on BF561
1071         bool "Bank 2 16 bit packing enable"
1072         default y
1073
1074 config C_B3PEN
1075         depends on BF561
1076         bool "Bank 3 16 bit packing enable"
1077         default n
1078
1079 choice
1080         prompt "Enable Asynchronous Memory Banks"
1081         default C_AMBEN_ALL
1082
1083 config C_AMBEN
1084         bool "Disable All Banks"
1085
1086 config C_AMBEN_B0
1087         bool "Enable Bank 0"
1088
1089 config C_AMBEN_B0_B1
1090         bool "Enable Bank 0 & 1"
1091
1092 config C_AMBEN_B0_B1_B2
1093         bool "Enable Bank 0 & 1 & 2"
1094
1095 config C_AMBEN_ALL
1096         bool "Enable All Banks"
1097 endchoice
1098 endmenu
1099
1100 menu "EBIU_AMBCTL Control"
1101 config BANK_0
1102         hex "Bank 0 (AMBCTL0.L)"
1103         default 0x7BB0
1104         help
1105           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1106           used to control the Asynchronous Memory Bank 0 settings.
1107
1108 config BANK_1
1109         hex "Bank 1 (AMBCTL0.H)"
1110         default 0x7BB0
1111         default 0x5558 if BF54x
1112         help
1113           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1114           used to control the Asynchronous Memory Bank 1 settings.
1115
1116 config BANK_2
1117         hex "Bank 2 (AMBCTL1.L)"
1118         default 0x7BB0
1119         help
1120           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1121           used to control the Asynchronous Memory Bank 2 settings.
1122
1123 config BANK_3
1124         hex "Bank 3 (AMBCTL1.H)"
1125         default 0x99B3
1126         help
1127           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1128           used to control the Asynchronous Memory Bank 3 settings.
1129
1130 endmenu
1131
1132 config EBIU_MBSCTLVAL
1133         hex "EBIU Bank Select Control Register"
1134         depends on BF54x
1135         default 0
1136
1137 config EBIU_MODEVAL
1138         hex "Flash Memory Mode Control Register"
1139         depends on BF54x
1140         default 1
1141
1142 config EBIU_FCTLVAL
1143         hex "Flash Memory Bank Control Register"
1144         depends on BF54x
1145         default 6
1146 endmenu
1147
1148 #############################################################################
1149 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1150
1151 config PCI
1152         bool "PCI support"
1153         depends on BROKEN
1154         help
1155           Support for PCI bus.
1156
1157 source "drivers/pci/Kconfig"
1158
1159 source "drivers/pcmcia/Kconfig"
1160
1161 source "drivers/pci/hotplug/Kconfig"
1162
1163 endmenu
1164
1165 menu "Executable file formats"
1166
1167 source "fs/Kconfig.binfmt"
1168
1169 endmenu
1170
1171 menu "Power management options"
1172
1173 source "kernel/power/Kconfig"
1174
1175 config ARCH_SUSPEND_POSSIBLE
1176         def_bool y
1177
1178 choice
1179         prompt "Standby Power Saving Mode"
1180         depends on PM
1181         default PM_BFIN_SLEEP_DEEPER
1182 config  PM_BFIN_SLEEP_DEEPER
1183         bool "Sleep Deeper"
1184         help
1185           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1186           power dissipation by disabling the clock to the processor core (CCLK).
1187           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1188           to 0.85 V to provide the greatest power savings, while preserving the
1189           processor state.
1190           The PLL and system clock (SCLK) continue to operate at a very low
1191           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1192           the SDRAM is put into Self Refresh Mode. Typically an external event
1193           such as GPIO interrupt or RTC activity wakes up the processor.
1194           Various Peripherals such as UART, SPORT, PPI may not function as
1195           normal during Sleep Deeper, due to the reduced SCLK frequency.
1196           When in the sleep mode, system DMA access to L1 memory is not supported.
1197
1198           If unsure, select "Sleep Deeper".
1199
1200 config  PM_BFIN_SLEEP
1201         bool "Sleep"
1202         help
1203           Sleep Mode (High Power Savings) - The sleep mode reduces power
1204           dissipation by disabling the clock to the processor core (CCLK).
1205           The PLL and system clock (SCLK), however, continue to operate in
1206           this mode. Typically an external event or RTC activity will wake
1207           up the processor. When in the sleep mode, system DMA access to L1
1208           memory is not supported.
1209
1210           If unsure, select "Sleep Deeper".
1211 endchoice
1212
1213 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1214         depends on PM
1215
1216 config PM_BFIN_WAKE_PH6
1217         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1218         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1219         default n
1220         help
1221           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1222
1223 config PM_BFIN_WAKE_GP
1224         bool "Allow Wake-Up from GPIOs"
1225         depends on PM && BF54x
1226         default n
1227         help
1228           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1229           (all processors, except ADSP-BF549). This option sets
1230           the general-purpose wake-up enable (GPWE) control bit to enable
1231           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1232           On ADSP-BF549 this option enables the the same functionality on the
1233           /MRXON pin also PH7.
1234
1235 endmenu
1236
1237 menu "CPU Frequency scaling"
1238
1239 source "drivers/cpufreq/Kconfig"
1240
1241 config BFIN_CPU_FREQ
1242         bool
1243         depends on CPU_FREQ
1244         select CPU_FREQ_TABLE
1245         default y
1246
1247 config CPU_VOLTAGE
1248         bool "CPU Voltage scaling"
1249         depends on EXPERIMENTAL
1250         depends on CPU_FREQ
1251         default n
1252         help
1253           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1254           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1255           manuals. There is a theoretical risk that during VDDINT transitions
1256           the PLL may unlock.
1257
1258 endmenu
1259
1260 source "net/Kconfig"
1261
1262 source "drivers/Kconfig"
1263
1264 source "drivers/firmware/Kconfig"
1265
1266 source "fs/Kconfig"
1267
1268 source "arch/blackfin/Kconfig.debug"
1269
1270 source "security/Kconfig"
1271
1272 source "crypto/Kconfig"
1273
1274 source "lib/Kconfig"