arch/blackfin/Kconfig

   1 #
   2 # For a description of the syntax of this configuration file,
   3 # see Documentation/kbuild/kconfig-language.txt.
   4 #
   5
   6 mainmenu "Blackfin Kernel Configuration"
   7
   8 config SYMBOL_PREFIX
   9         string
  10         default "_"
  11
  12 config MMU
  13         def_bool n
  14
  15 config FPU
  16         def_bool n
  17
  18 config RWSEM_GENERIC_SPINLOCK
  19         def_bool y
  20
  21 config RWSEM_XCHGADD_ALGORITHM
  22         def_bool n
  23
  24 config BLACKFIN
  25         def_bool y
  26         select HAVE_ARCH_KGDB
  27         select HAVE_ARCH_TRACEHOOK
  28         select HAVE_FUNCTION_GRAPH_TRACER
  29         select HAVE_FUNCTION_TRACER
  30         select HAVE_FUNCTION_TRACE_MCOUNT_TEST
  31         select HAVE_IDE
  32         select HAVE_KERNEL_GZIP if RAMKERNEL
  33         select HAVE_KERNEL_BZIP2 if RAMKERNEL
  34         select HAVE_KERNEL_LZMA if RAMKERNEL
  35         select HAVE_OPROFILE
  36         select ARCH_WANT_OPTIONAL_GPIOLIB
  37
  38 config GENERIC_CSUM
  39         def_bool y
  40
  41 config GENERIC_BUG
  42         def_bool y
  43         depends on BUG
  44
  45 config ZONE_DMA
  46         def_bool y
  47
  48 config GENERIC_FIND_NEXT_BIT
  49         def_bool y
  50
  51 config GENERIC_HARDIRQS
  52         def_bool y
  53
  54 config GENERIC_IRQ_PROBE
  55         def_bool y
  56
  57 config GENERIC_HARDIRQS_NO__DO_IRQ
  58         def_bool y
  59
  60 config GENERIC_GPIO
  61         def_bool y
  62
  63 config FORCE_MAX_ZONEORDER
  64         int
  65         default "14"
  66
  67 config GENERIC_CALIBRATE_DELAY
  68         def_bool y
  69
  70 config LOCKDEP_SUPPORT
  71         def_bool y
  72
  73 config STACKTRACE_SUPPORT
  74         def_bool y
  75
  76 config TRACE_IRQFLAGS_SUPPORT
  77         def_bool y
  78
  79 source "init/Kconfig"
  80
  81 source "kernel/Kconfig.preempt"
  82
  83 source "kernel/Kconfig.freezer"
  84
  85 menu "Blackfin Processor Options"
  86
  87 comment "Processor and Board Settings"
  88
  89 choice
  90         prompt "CPU"
  91         default BF533
  92
  93 config BF512
  94         bool "BF512"
  95         help
  96           BF512 Processor Support.
  97
  98 config BF514
  99         bool "BF514"
 100         help
 101           BF514 Processor Support.
 102
 103 config BF516
 104         bool "BF516"
 105         help
 106           BF516 Processor Support.
 107
 108 config BF518
 109         bool "BF518"
 110         help
 111           BF518 Processor Support.
 112
 113 config BF522
 114         bool "BF522"
 115         help
 116           BF522 Processor Support.
 117
 118 config BF523
 119         bool "BF523"
 120         help
 121           BF523 Processor Support.
 122
 123 config BF524
 124         bool "BF524"
 125         help
 126           BF524 Processor Support.
 127
 128 config BF525
 129         bool "BF525"
 130         help
 131           BF525 Processor Support.
 132
 133 config BF526
 134         bool "BF526"
 135         help
 136           BF526 Processor Support.
 137
 138 config BF527
 139         bool "BF527"
 140         help
 141           BF527 Processor Support.
 142
 143 config BF531
 144         bool "BF531"
 145         help
 146           BF531 Processor Support.
 147
 148 config BF532
 149         bool "BF532"
 150         help
 151           BF532 Processor Support.
 152
 153 config BF533
 154         bool "BF533"
 155         help
 156           BF533 Processor Support.
 157
 158 config BF534
 159         bool "BF534"
 160         help
 161           BF534 Processor Support.
 162
 163 config BF536
 164         bool "BF536"
 165         help
 166           BF536 Processor Support.
 167
 168 config BF537
 169         bool "BF537"
 170         help
 171           BF537 Processor Support.
 172
 173 config BF538
 174         bool "BF538"
 175         help
 176           BF538 Processor Support.
 177
 178 config BF539
 179         bool "BF539"
 180         help
 181           BF539 Processor Support.
 182
 183 config BF542_std
 184         bool "BF542"
 185         help
 186           BF542 Processor Support.
 187
 188 config BF542M
 189         bool "BF542m"
 190         help
 191           BF542 Processor Support.
 192
 193 config BF544_std
 194         bool "BF544"
 195         help
 196           BF544 Processor Support.
 197
 198 config BF544M
 199         bool "BF544m"
 200         help
 201           BF544 Processor Support.
 202
 203 config BF547_std
 204         bool "BF547"
 205         help
 206           BF547 Processor Support.
 207
 208 config BF547M
 209         bool "BF547m"
 210         help
 211           BF547 Processor Support.
 212
 213 config BF548_std
 214         bool "BF548"
 215         help
 216           BF548 Processor Support.
 217
 218 config BF548M
 219         bool "BF548m"
 220         help
 221           BF548 Processor Support.
 222
 223 config BF549_std
 224         bool "BF549"
 225         help
 226           BF549 Processor Support.
 227
 228 config BF549M
 229         bool "BF549m"
 230         help
 231           BF549 Processor Support.
 232
 233 config BF561
 234         bool "BF561"
 235         help
 236           BF561 Processor Support.
 237
 238 endchoice
 239
 240 config SMP
 241         depends on BF561
 242         select TICKSOURCE_CORETMR
 243         bool "Symmetric multi-processing support"
 244         ---help---
 245           This enables support for systems with more than one CPU,
 246           like the dual core BF561. If you have a system with only one
 247           CPU, say N. If you have a system with more than one CPU, say Y.
 248
 249           If you don't know what to do here, say N.
 250
 251 config NR_CPUS
 252         int
 253         depends on SMP
 254         default 2 if BF561
 255
 256 config HOTPLUG_CPU
 257         bool "Support for hot-pluggable CPUs"
 258         depends on SMP && HOTPLUG
 259         default y
 260
 261 config IRQ_PER_CPU
 262         bool
 263         depends on SMP
 264         default y
 265
 266 config HAVE_LEGACY_PER_CPU_AREA
 267         def_bool y
 268         depends on SMP
 269
 270 config BF_REV_MIN
 271         int
 272         default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
 273         default 2 if (BF537 || BF536 || BF534)
 274         default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
 275         default 4 if (BF538 || BF539)
 276
 277 config BF_REV_MAX
 278         int
 279         default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
 280         default 3 if (BF537 || BF536 || BF534 || BF54xM)
 281         default 5 if (BF561 || BF538 || BF539)
 282         default 6 if (BF533 || BF532 || BF531)
 283
 284 choice
 285         prompt "Silicon Rev"
 286         default BF_REV_0_0 if (BF51x || BF52x)
 287         default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
 288         default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
 289
 290 config BF_REV_0_0
 291         bool "0.0"
 292         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 293
 294 config BF_REV_0_1
 295         bool "0.1"
 296         depends on (BF51x || BF52x || (BF54x && !BF54xM))
 297
 298 config BF_REV_0_2
 299         bool "0.2"
 300         depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
 301
 302 config BF_REV_0_3
 303         bool "0.3"
 304         depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
 305
 306 config BF_REV_0_4
 307         bool "0.4"
 308         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 309
 310 config BF_REV_0_5
 311         bool "0.5"
 312         depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
 313
 314 config BF_REV_0_6
 315         bool "0.6"
 316         depends on (BF533 || BF532 || BF531)
 317
 318 config BF_REV_ANY
 319         bool "any"
 320
 321 config BF_REV_NONE
 322         bool "none"
 323
 324 endchoice
 325
 326 config BF53x
 327         bool
 328         depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
 329         default y
 330
 331 config MEM_GENERIC_BOARD
 332         bool
 333         depends on GENERIC_BOARD
 334         default y
 335
 336 config MEM_MT48LC64M4A2FB_7E
 337         bool
 338         depends on (BFIN533_STAMP)
 339         default y
 340
 341 config MEM_MT48LC16M16A2TG_75
 342         bool
 343         depends on (BFIN533_EZKIT || BFIN561_EZKIT \
 344                 || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM_E \
 345                 || BFIN537_BLUETECHNIX_CM_U || H8606_HVSISTEMAS \
 346                 || BFIN527_BLUETECHNIX_CM)
 347         default y
 348
 349 config MEM_MT48LC32M8A2_75
 350         bool
 351         depends on (BFIN518F_EZBRD || BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
 352         default y
 353
 354 config MEM_MT48LC8M32B2B5_7
 355         bool
 356         depends on (BFIN561_BLUETECHNIX_CM)
 357         default y
 358
 359 config MEM_MT48LC32M16A2TG_75
 360         bool
 361         depends on (BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN532_IP0X || BLACKSTAMP)
 362         default y
 363
 364 config MEM_MT48H32M16LFCJ_75
 365         bool
 366         depends on (BFIN526_EZBRD)
 367         default y
 368
 369 source "arch/blackfin/mach-bf518/Kconfig"
 370 source "arch/blackfin/mach-bf527/Kconfig"
 371 source "arch/blackfin/mach-bf533/Kconfig"
 372 source "arch/blackfin/mach-bf561/Kconfig"
 373 source "arch/blackfin/mach-bf537/Kconfig"
 374 source "arch/blackfin/mach-bf538/Kconfig"
 375 source "arch/blackfin/mach-bf548/Kconfig"
 376
 377 menu "Board customizations"
 378
 379 config CMDLINE_BOOL
 380         bool "Default bootloader kernel arguments"
 381
 382 config CMDLINE
 383         string "Initial kernel command string"
 384         depends on CMDLINE_BOOL
 385         default "console=ttyBF0,57600"
 386         help
 387           If you don't have a boot loader capable of passing a command line string
 388           to the kernel, you may specify one here. As a minimum, you should specify
 389           the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
 390
 391 config BOOT_LOAD
 392         hex "Kernel load address for booting"
 393         default "0x1000"
 394         range 0x1000 0x20000000
 395         help
 396           This option allows you to set the load address of the kernel.
 397           This can be useful if you are on a board which has a small amount
 398           of memory or you wish to reserve some memory at the beginning of
 399           the address space.
 400
 401           Note that you need to keep this value above 4k (0x1000) as this
 402           memory region is used to capture NULL pointer references as well
 403           as some core kernel functions.
 404
 405 config ROM_BASE
 406         hex "Kernel ROM Base"
 407         depends on ROMKERNEL
 408         default "0x20040040"
 409         range 0x20000000 0x20400000 if !(BF54x || BF561)
 410         range 0x20000000 0x30000000 if (BF54x || BF561)
 411         help
 412           Make sure your ROM base does not include any file-header
 413           information that is prepended to the kernel.
 414
 415           For example, the bootable U-Boot format (created with
 416           mkimage) has a 64 byte header (0x40).  So while the image
 417           you write to flash might start at say 0x20080000, you have
 418           to add 0x40 to get the kernel's ROM base as it will come
 419           after the header.
 420
 421 comment "Clock/PLL Setup"
 422
 423 config CLKIN_HZ
 424         int "Frequency of the crystal on the board in Hz"
 425         default "10000000" if BFIN532_IP0X
 426         default "11059200" if BFIN533_STAMP
 427         default "24576000" if PNAV10
 428         default "25000000" # most people use this
 429         default "27000000" if BFIN533_EZKIT
 430         default "30000000" if BFIN561_EZKIT
 431         help
 432           The frequency of CLKIN crystal oscillator on the board in Hz.
 433           Warning: This value should match the crystal on the board. Otherwise,
 434           peripherals won't work properly.
 435
 436 config BFIN_KERNEL_CLOCK
 437         bool "Re-program Clocks while Kernel boots?"
 438         default n
 439         help
 440           This option decides if kernel clocks are re-programed from the
 441           bootloader settings. If the clocks are not set, the SDRAM settings
 442           are also not changed, and the Bootloader does 100% of the hardware
 443           configuration.
 444
 445 config PLL_BYPASS
 446         bool "Bypass PLL"
 447         depends on BFIN_KERNEL_CLOCK
 448         default n
 449
 450 config CLKIN_HALF
 451         bool "Half Clock In"
 452         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 453         default n
 454         help
 455           If this is set the clock will be divided by 2, before it goes to the PLL.
 456
 457 config VCO_MULT
 458         int "VCO Multiplier"
 459         depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
 460         range 1 64
 461         default "22" if BFIN533_EZKIT
 462         default "45" if BFIN533_STAMP
 463         default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN527_EZKIT_V2 || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
 464         default "22" if BFIN533_BLUETECHNIX_CM
 465         default "20" if (BFIN537_BLUETECHNIX_CM_E || BFIN537_BLUETECHNIX_CM_U || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
 466         default "20" if BFIN561_EZKIT
 467         default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
 468         help
 469           This controls the frequency of the on-chip PLL. This can be between 1 and 64.
 470           PLL Frequency = (Crystal Frequency) * (this setting)
 471
 472 choice
 473         prompt "Core Clock Divider"
 474         depends on BFIN_KERNEL_CLOCK
 475         default CCLK_DIV_1
 476         help
 477           This sets the frequency of the core. It can be 1, 2, 4 or 8
 478           Core Frequency = (PLL frequency) / (this setting)
 479
 480 config CCLK_DIV_1
 481         bool "1"
 482
 483 config CCLK_DIV_2
 484         bool "2"
 485
 486 config CCLK_DIV_4
 487         bool "4"
 488
 489 config CCLK_DIV_8
 490         bool "8"
 491 endchoice
 492
 493 config SCLK_DIV
 494         int "System Clock Divider"
 495         depends on BFIN_KERNEL_CLOCK
 496         range 1 15
 497         default 5
 498         help
 499           This sets the frequency of the system clock (including SDRAM or DDR).
 500           This can be between 1 and 15
 501           System Clock = (PLL frequency) / (this setting)
 502
 503 choice
 504         prompt "DDR SDRAM Chip Type"
 505         depends on BFIN_KERNEL_CLOCK
 506         depends on BF54x
 507         default MEM_MT46V32M16_5B
 508
 509 config MEM_MT46V32M16_6T
 510         bool "MT46V32M16_6T"
 511
 512 config MEM_MT46V32M16_5B
 513         bool "MT46V32M16_5B"
 514 endchoice
 515
 516 choice
 517         prompt "DDR/SDRAM Timing"
 518         depends on BFIN_KERNEL_CLOCK
 519         default BFIN_KERNEL_CLOCK_MEMINIT_CALC
 520         help
 521           This option allows you to specify Blackfin SDRAM/DDR Timing parameters
 522           The calculated SDRAM timing parameters may not be 100%
 523           accurate - This option is therefore marked experimental.
 524
 525 config BFIN_KERNEL_CLOCK_MEMINIT_CALC
 526         bool "Calculate Timings (EXPERIMENTAL)"
 527         depends on EXPERIMENTAL
 528
 529 config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 530         bool "Provide accurate Timings based on target SCLK"
 531         help
 532           Please consult the Blackfin Hardware Reference Manuals as well
 533           as the memory device datasheet.
 534           http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 535 endchoice
 536
 537 menu "Memory Init Control"
 538         depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
 539
 540 config MEM_DDRCTL0
 541         depends on BF54x
 542         hex "DDRCTL0"
 543         default 0x0
 544
 545 config MEM_DDRCTL1
 546         depends on BF54x
 547         hex "DDRCTL1"
 548         default 0x0
 549
 550 config MEM_DDRCTL2
 551         depends on BF54x
 552         hex "DDRCTL2"
 553         default 0x0
 554
 555 config MEM_EBIU_DDRQUE
 556         depends on BF54x
 557         hex "DDRQUE"
 558         default 0x0
 559
 560 config MEM_SDRRC
 561         depends on !BF54x
 562         hex "SDRRC"
 563         default 0x0
 564
 565 config MEM_SDGCTL
 566         depends on !BF54x
 567         hex "SDGCTL"
 568         default 0x0
 569 endmenu
 570
 571 #
 572 # Max & Min Speeds for various Chips
 573 #
 574 config MAX_VCO_HZ
 575         int
 576         default 400000000 if BF512
 577         default 400000000 if BF514
 578         default 400000000 if BF516
 579         default 400000000 if BF518
 580         default 400000000 if BF522
 581         default 600000000 if BF523
 582         default 400000000 if BF524
 583         default 600000000 if BF525
 584         default 400000000 if BF526
 585         default 600000000 if BF527
 586         default 400000000 if BF531
 587         default 400000000 if BF532
 588         default 750000000 if BF533
 589         default 500000000 if BF534
 590         default 400000000 if BF536
 591         default 600000000 if BF537
 592         default 533333333 if BF538
 593         default 533333333 if BF539
 594         default 600000000 if BF542
 595         default 533333333 if BF544
 596         default 600000000 if BF547
 597         default 600000000 if BF548
 598         default 533333333 if BF549
 599         default 600000000 if BF561
 600
 601 config MIN_VCO_HZ
 602         int
 603         default 50000000
 604
 605 config MAX_SCLK_HZ
 606         int
 607         default 133333333
 608
 609 config MIN_SCLK_HZ
 610         int
 611         default 27000000
 612
 613 comment "Kernel Timer/Scheduler"
 614
 615 source kernel/Kconfig.hz
 616
 617 config GENERIC_CLOCKEVENTS
 618         bool "Generic clock events"
 619         default y
 620
 621 menu "Clock event device"
 622         depends on GENERIC_CLOCKEVENTS
 623 config TICKSOURCE_GPTMR0
 624         bool "GPTimer0"
 625         depends on !SMP
 626         select BFIN_GPTIMERS
 627
 628 config TICKSOURCE_CORETMR
 629         bool "Core timer"
 630         default y
 631 endmenu
 632
 633 menu "Clock souce"
 634         depends on GENERIC_CLOCKEVENTS
 635 config CYCLES_CLOCKSOURCE
 636         bool "CYCLES"
 637         default y
 638         depends on !BFIN_SCRATCH_REG_CYCLES
 639         depends on !SMP
 640         help
 641           If you say Y here, you will enable support for using the 'cycles'
 642           registers as a clock source.  Doing so means you will be unable to
 643           safely write to the 'cycles' register during runtime.  You will
 644           still be able to read it (such as for performance monitoring), but
 645           writing the registers will most likely crash the kernel.
 646
 647 config GPTMR0_CLOCKSOURCE
 648         bool "GPTimer0"
 649         select BFIN_GPTIMERS
 650         depends on !TICKSOURCE_GPTMR0
 651 endmenu
 652
 653 config ARCH_USES_GETTIMEOFFSET
 654         depends on !GENERIC_CLOCKEVENTS
 655         def_bool y
 656
 657 source kernel/time/Kconfig
 658
 659 comment "Misc"
 660
 661 choice
 662         prompt "Blackfin Exception Scratch Register"
 663         default BFIN_SCRATCH_REG_RETN
 664         help
 665           Select the resource to reserve for the Exception handler:
 666             - RETN: Non-Maskable Interrupt (NMI)
 667             - RETE: Exception Return (JTAG/ICE)
 668             - CYCLES: Performance counter
 669
 670           If you are unsure, please select "RETN".
 671
 672 config BFIN_SCRATCH_REG_RETN
 673         bool "RETN"
 674         help
 675           Use the RETN register in the Blackfin exception handler
 676           as a stack scratch register.  This means you cannot
 677           safely use NMI on the Blackfin while running Linux, but
 678           you can debug the system with a JTAG ICE and use the
 679           CYCLES performance registers.
 680
 681           If you are unsure, please select "RETN".
 682
 683 config BFIN_SCRATCH_REG_RETE
 684         bool "RETE"
 685         help
 686           Use the RETE register in the Blackfin exception handler
 687           as a stack scratch register.  This means you cannot
 688           safely use a JTAG ICE while debugging a Blackfin board,
 689           but you can safely use the CYCLES performance registers
 690           and the NMI.
 691
 692           If you are unsure, please select "RETN".
 693
 694 config BFIN_SCRATCH_REG_CYCLES
 695         bool "CYCLES"
 696         help
 697           Use the CYCLES register in the Blackfin exception handler
 698           as a stack scratch register.  This means you cannot
 699           safely use the CYCLES performance registers on a Blackfin
 700           board at anytime, but you can debug the system with a JTAG
 701           ICE and use the NMI.
 702
 703           If you are unsure, please select "RETN".
 704
 705 endchoice
 706
 707 endmenu
 708
 709
 710 menu "Blackfin Kernel Optimizations"
 711         depends on !SMP
 712
 713 comment "Memory Optimizations"
 714
 715 config I_ENTRY_L1
 716         bool "Locate interrupt entry code in L1 Memory"
 717         default y
 718         help
 719           If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
 720           into L1 instruction memory. (less latency)
 721
 722 config EXCPT_IRQ_SYSC_L1
 723         bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
 724         default y
 725         help
 726           If enabled, the entire ASM lowlevel exception and interrupt entry code
 727           (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
 728           (less latency)
 729
 730 config DO_IRQ_L1
 731         bool "Locate frequently called do_irq dispatcher function in L1 Memory"
 732         default y
 733         help
 734           If enabled, the frequently called do_irq dispatcher function is linked
 735           into L1 instruction memory. (less latency)
 736
 737 config CORE_TIMER_IRQ_L1
 738         bool "Locate frequently called timer_interrupt() function in L1 Memory"
 739         default y
 740         help
 741           If enabled, the frequently called timer_interrupt() function is linked
 742           into L1 instruction memory. (less latency)
 743
 744 config IDLE_L1
 745         bool "Locate frequently idle function in L1 Memory"
 746         default y
 747         help
 748           If enabled, the frequently called idle function is linked
 749           into L1 instruction memory. (less latency)
 750
 751 config SCHEDULE_L1
 752         bool "Locate kernel schedule function in L1 Memory"
 753         default y
 754         help
 755           If enabled, the frequently called kernel schedule is linked
 756           into L1 instruction memory. (less latency)
 757
 758 config ARITHMETIC_OPS_L1
 759         bool "Locate kernel owned arithmetic functions in L1 Memory"
 760         default y
 761         help
 762           If enabled, arithmetic functions are linked
 763           into L1 instruction memory. (less latency)
 764
 765 config ACCESS_OK_L1
 766         bool "Locate access_ok function in L1 Memory"
 767         default y
 768         help
 769           If enabled, the access_ok function is linked
 770           into L1 instruction memory. (less latency)
 771
 772 config MEMSET_L1
 773         bool "Locate memset function in L1 Memory"
 774         default y
 775         help
 776           If enabled, the memset function is linked
 777           into L1 instruction memory. (less latency)
 778
 779 config MEMCPY_L1
 780         bool "Locate memcpy function in L1 Memory"
 781         default y
 782         help
 783           If enabled, the memcpy function is linked
 784           into L1 instruction memory. (less latency)
 785
 786 config STRCMP_L1
 787         bool "locate strcmp function in L1 Memory"
 788         default y
 789         help
 790           If enabled, the strcmp function is linked
 791           into L1 instruction memory (less latency).
 792
 793 config STRNCMP_L1
 794         bool "locate strncmp function in L1 Memory"
 795         default y
 796         help
 797           If enabled, the strncmp function is linked
 798           into L1 instruction memory (less latency).
 799
 800 config STRCPY_L1
 801         bool "locate strcpy function in L1 Memory"
 802         default y
 803         help
 804           If enabled, the strcpy function is linked
 805           into L1 instruction memory (less latency).
 806
 807 config STRNCPY_L1
 808         bool "locate strncpy function in L1 Memory"
 809         default y
 810         help
 811           If enabled, the strncpy function is linked
 812           into L1 instruction memory (less latency).
 813
 814 config SYS_BFIN_SPINLOCK_L1
 815         bool "Locate sys_bfin_spinlock function in L1 Memory"
 816         default y
 817         help
 818           If enabled, sys_bfin_spinlock function is linked
 819           into L1 instruction memory. (less latency)
 820
 821 config IP_CHECKSUM_L1
 822         bool "Locate IP Checksum function in L1 Memory"
 823         default n
 824         help
 825           If enabled, the IP Checksum function is linked
 826           into L1 instruction memory. (less latency)
 827
 828 config CACHELINE_ALIGNED_L1
 829         bool "Locate cacheline_aligned data to L1 Data Memory"
 830         default y if !BF54x
 831         default n if BF54x
 832         depends on !BF531
 833         help
 834           If enabled, cacheline_aligned data is linked
 835           into L1 data memory. (less latency)
 836
 837 config SYSCALL_TAB_L1
 838         bool "Locate Syscall Table L1 Data Memory"
 839         default n
 840         depends on !BF531
 841         help
 842           If enabled, the Syscall LUT is linked
 843           into L1 data memory. (less latency)
 844
 845 config CPLB_SWITCH_TAB_L1
 846         bool "Locate CPLB Switch Tables L1 Data Memory"
 847         default n
 848         depends on !BF531
 849         help
 850           If enabled, the CPLB Switch Tables are linked
 851           into L1 data memory. (less latency)
 852
 853 config APP_STACK_L1
 854         bool "Support locating application stack in L1 Scratch Memory"
 855         default y
 856         help
 857           If enabled the application stack can be located in L1
 858           scratch memory (less latency).
 859
 860           Currently only works with FLAT binaries.
 861
 862 config EXCEPTION_L1_SCRATCH
 863         bool "Locate exception stack in L1 Scratch Memory"
 864         default n
 865         depends on !APP_STACK_L1
 866         help
 867           Whenever an exception occurs, use the L1 Scratch memory for
 868           stack storage.  You cannot place the stacks of FLAT binaries
 869           in L1 when using this option.
 870
 871           If you don't use L1 Scratch, then you should say Y here.
 872
 873 comment "Speed Optimizations"
 874 config BFIN_INS_LOWOVERHEAD
 875         bool "ins[bwl] low overhead, higher interrupt latency"
 876         default y
 877         help
 878           Reads on the Blackfin are speculative. In Blackfin terms, this means
 879           they can be interrupted at any time (even after they have been issued
 880           on to the external bus), and re-issued after the interrupt occurs.
 881           For memory - this is not a big deal, since memory does not change if
 882           it sees a read.
 883
 884           If a FIFO is sitting on the end of the read, it will see two reads,
 885           when the core only sees one since the FIFO receives both the read
 886           which is cancelled (and not delivered to the core) and the one which
 887           is re-issued (which is delivered to the core).
 888
 889           To solve this, interrupts are turned off before reads occur to
 890           I/O space. This option controls which the overhead/latency of
 891           controlling interrupts during this time
 892            "n" turns interrupts off every read
 893                 (higher overhead, but lower interrupt latency)
 894            "y" turns interrupts off every loop
 895                 (low overhead, but longer interrupt latency)
 896
 897           default behavior is to leave this set to on (type "Y"). If you are experiencing
 898           interrupt latency issues, it is safe and OK to turn this off.
 899
 900 endmenu
 901
 902 choice
 903         prompt "Kernel executes from"
 904         help
 905           Choose the memory type that the kernel will be running in.
 906
 907 config RAMKERNEL
 908         bool "RAM"
 909         help
 910           The kernel will be resident in RAM when running.
 911
 912 config ROMKERNEL
 913         bool "ROM"
 914         help
 915           The kernel will be resident in FLASH/ROM when running.
 916
 917 endchoice
 918
 919 source "mm/Kconfig"
 920
 921 config BFIN_GPTIMERS
 922         tristate "Enable Blackfin General Purpose Timers API"
 923         default n
 924         help
 925           Enable support for the General Purpose Timers API.  If you
 926           are unsure, say N.
 927
 928           To compile this driver as a module, choose M here: the module
 929           will be called gptimers.
 930
 931 choice
 932         prompt "Uncached DMA region"
 933         default DMA_UNCACHED_1M
 934 config DMA_UNCACHED_4M
 935         bool "Enable 4M DMA region"
 936 config DMA_UNCACHED_2M
 937         bool "Enable 2M DMA region"
 938 config DMA_UNCACHED_1M
 939         bool "Enable 1M DMA region"
 940 config DMA_UNCACHED_512K
 941         bool "Enable 512K DMA region"
 942 config DMA_UNCACHED_256K
 943         bool "Enable 256K DMA region"
 944 config DMA_UNCACHED_128K
 945         bool "Enable 128K DMA region"
 946 config DMA_UNCACHED_NONE
 947         bool "Disable DMA region"
 948 endchoice
 949
 950
 951 comment "Cache Support"
 952
 953 config BFIN_ICACHE
 954         bool "Enable ICACHE"
 955         default y
 956 config BFIN_EXTMEM_ICACHEABLE
 957         bool "Enable ICACHE for external memory"
 958         depends on BFIN_ICACHE
 959         default y
 960 config BFIN_L2_ICACHEABLE
 961         bool "Enable ICACHE for L2 SRAM"
 962         depends on BFIN_ICACHE
 963         depends on BF54x || BF561
 964         default n
 965
 966 config BFIN_DCACHE
 967         bool "Enable DCACHE"
 968         default y
 969 config BFIN_DCACHE_BANKA
 970         bool "Enable only 16k BankA DCACHE - BankB is SRAM"
 971         depends on BFIN_DCACHE && !BF531
 972         default n
 973 config BFIN_EXTMEM_DCACHEABLE
 974         bool "Enable DCACHE for external memory"
 975         depends on BFIN_DCACHE
 976         default y
 977 choice
 978         prompt "External memory DCACHE policy"
 979         depends on BFIN_EXTMEM_DCACHEABLE
 980         default BFIN_EXTMEM_WRITEBACK if !SMP
 981         default BFIN_EXTMEM_WRITETHROUGH if SMP
 982 config BFIN_EXTMEM_WRITEBACK
 983         bool "Write back"
 984         depends on !SMP
 985         help
 986           Write Back Policy:
 987             Cached data will be written back to SDRAM only when needed.
 988             This can give a nice increase in performance, but beware of
 989             broken drivers that do not properly invalidate/flush their
 990             cache.
 991
 992           Write Through Policy:
 993             Cached data will always be written back to SDRAM when the
 994             cache is updated.  This is a completely safe setting, but
 995             performance is worse than Write Back.
 996
 997           If you are unsure of the options and you want to be safe,
 998           then go with Write Through.
 999
1000 config BFIN_EXTMEM_WRITETHROUGH
1001         bool "Write through"
1002         help
1003           Write Back Policy:
1004             Cached data will be written back to SDRAM only when needed.
1005             This can give a nice increase in performance, but beware of
1006             broken drivers that do not properly invalidate/flush their
1007             cache.
1008
1009           Write Through Policy:
1010             Cached data will always be written back to SDRAM when the
1011             cache is updated.  This is a completely safe setting, but
1012             performance is worse than Write Back.
1013
1014           If you are unsure of the options and you want to be safe,
1015           then go with Write Through.
1016
1017 endchoice
1018
1019 config BFIN_L2_DCACHEABLE
1020         bool "Enable DCACHE for L2 SRAM"
1021         depends on BFIN_DCACHE
1022         depends on (BF54x || BF561) && !SMP
1023         default n
1024 choice
1025         prompt "L2 SRAM DCACHE policy"
1026         depends on BFIN_L2_DCACHEABLE
1027         default BFIN_L2_WRITEBACK
1028 config BFIN_L2_WRITEBACK
1029         bool "Write back"
1030
1031 config BFIN_L2_WRITETHROUGH
1032         bool "Write through"
1033 endchoice
1034
1035
1036 comment "Memory Protection Unit"
1037 config MPU
1038         bool "Enable the memory protection unit (EXPERIMENTAL)"
1039         default n
1040         help
1041           Use the processor's MPU to protect applications from accessing
1042           memory they do not own.  This comes at a performance penalty
1043           and is recommended only for debugging.
1044
1045 comment "Asynchronous Memory Configuration"
1046
1047 menu "EBIU_AMGCTL Global Control"
1048 config C_AMCKEN
1049         bool "Enable CLKOUT"
1050         default y
1051
1052 config C_CDPRIO
1053         bool "DMA has priority over core for ext. accesses"
1054         default n
1055
1056 config C_B0PEN
1057         depends on BF561
1058         bool "Bank 0 16 bit packing enable"
1059         default y
1060
1061 config C_B1PEN
1062         depends on BF561
1063         bool "Bank 1 16 bit packing enable"
1064         default y
1065
1066 config C_B2PEN
1067         depends on BF561
1068         bool "Bank 2 16 bit packing enable"
1069         default y
1070
1071 config C_B3PEN
1072         depends on BF561
1073         bool "Bank 3 16 bit packing enable"
1074         default n
1075
1076 choice
1077         prompt "Enable Asynchronous Memory Banks"
1078         default C_AMBEN_ALL
1079
1080 config C_AMBEN
1081         bool "Disable All Banks"
1082
1083 config C_AMBEN_B0
1084         bool "Enable Bank 0"
1085
1086 config C_AMBEN_B0_B1
1087         bool "Enable Bank 0 & 1"
1088
1089 config C_AMBEN_B0_B1_B2
1090         bool "Enable Bank 0 & 1 & 2"
1091
1092 config C_AMBEN_ALL
1093         bool "Enable All Banks"
1094 endchoice
1095 endmenu
1096
1097 menu "EBIU_AMBCTL Control"
1098 config BANK_0
1099         hex "Bank 0 (AMBCTL0.L)"
1100         default 0x7BB0
1101         help
1102           These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
1103           used to control the Asynchronous Memory Bank 0 settings.
1104
1105 config BANK_1
1106         hex "Bank 1 (AMBCTL0.H)"
1107         default 0x7BB0
1108         default 0x5558 if BF54x
1109         help
1110           These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
1111           used to control the Asynchronous Memory Bank 1 settings.
1112
1113 config BANK_2
1114         hex "Bank 2 (AMBCTL1.L)"
1115         default 0x7BB0
1116         help
1117           These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
1118           used to control the Asynchronous Memory Bank 2 settings.
1119
1120 config BANK_3
1121         hex "Bank 3 (AMBCTL1.H)"
1122         default 0x99B3
1123         help
1124           These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
1125           used to control the Asynchronous Memory Bank 3 settings.
1126
1127 endmenu
1128
1129 config EBIU_MBSCTLVAL
1130         hex "EBIU Bank Select Control Register"
1131         depends on BF54x
1132         default 0
1133
1134 config EBIU_MODEVAL
1135         hex "Flash Memory Mode Control Register"
1136         depends on BF54x
1137         default 1
1138
1139 config EBIU_FCTLVAL
1140         hex "Flash Memory Bank Control Register"
1141         depends on BF54x
1142         default 6
1143 endmenu
1144
1145 #############################################################################
1146 menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
1147
1148 config PCI
1149         bool "PCI support"
1150         depends on BROKEN
1151         help
1152           Support for PCI bus.
1153
1154 source "drivers/pci/Kconfig"
1155
1156 source "drivers/pcmcia/Kconfig"
1157
1158 source "drivers/pci/hotplug/Kconfig"
1159
1160 endmenu
1161
1162 menu "Executable file formats"
1163
1164 source "fs/Kconfig.binfmt"
1165
1166 endmenu
1167
1168 menu "Power management options"
1169
1170 source "kernel/power/Kconfig"
1171
1172 config ARCH_SUSPEND_POSSIBLE
1173         def_bool y
1174
1175 choice
1176         prompt "Standby Power Saving Mode"
1177         depends on PM
1178         default PM_BFIN_SLEEP_DEEPER
1179 config  PM_BFIN_SLEEP_DEEPER
1180         bool "Sleep Deeper"
1181         help
1182           Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
1183           power dissipation by disabling the clock to the processor core (CCLK).
1184           Furthermore, Standby sets the internal power supply voltage (VDDINT)
1185           to 0.85 V to provide the greatest power savings, while preserving the
1186           processor state.
1187           The PLL and system clock (SCLK) continue to operate at a very low
1188           frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
1189           the SDRAM is put into Self Refresh Mode. Typically an external event
1190           such as GPIO interrupt or RTC activity wakes up the processor.
1191           Various Peripherals such as UART, SPORT, PPI may not function as
1192           normal during Sleep Deeper, due to the reduced SCLK frequency.
1193           When in the sleep mode, system DMA access to L1 memory is not supported.
1194
1195           If unsure, select "Sleep Deeper".
1196
1197 config  PM_BFIN_SLEEP
1198         bool "Sleep"
1199         help
1200           Sleep Mode (High Power Savings) - The sleep mode reduces power
1201           dissipation by disabling the clock to the processor core (CCLK).
1202           The PLL and system clock (SCLK), however, continue to operate in
1203           this mode. Typically an external event or RTC activity will wake
1204           up the processor. When in the sleep mode, system DMA access to L1
1205           memory is not supported.
1206
1207           If unsure, select "Sleep Deeper".
1208 endchoice
1209
1210 comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
1211         depends on PM
1212
1213 config PM_BFIN_WAKE_PH6
1214         bool "Allow Wake-Up from on-chip PHY or PH6 GP"
1215         depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
1216         default n
1217         help
1218           Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
1219
1220 config PM_BFIN_WAKE_GP
1221         bool "Allow Wake-Up from GPIOs"
1222         depends on PM && BF54x
1223         default n
1224         help
1225           Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1226           (all processors, except ADSP-BF549). This option sets
1227           the general-purpose wake-up enable (GPWE) control bit to enable
1228           wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1229           On ADSP-BF549 this option enables the the same functionality on the
1230           /MRXON pin also PH7.
1231
1232 endmenu
1233
1234 menu "CPU Frequency scaling"
1235
1236 source "drivers/cpufreq/Kconfig"
1237
1238 config BFIN_CPU_FREQ
1239         bool
1240         depends on CPU_FREQ
1241         select CPU_FREQ_TABLE
1242         default y
1243
1244 config CPU_VOLTAGE
1245         bool "CPU Voltage scaling"
1246         depends on EXPERIMENTAL
1247         depends on CPU_FREQ
1248         default n
1249         help
1250           Say Y here if you want CPU voltage scaling according to the CPU frequency.
1251           This option violates the PLL BYPASS recommendation in the Blackfin Processor
1252           manuals. There is a theoretical risk that during VDDINT transitions
1253           the PLL may unlock.
1254
1255 endmenu
1256
1257 source "net/Kconfig"
1258
1259 source "drivers/Kconfig"
1260
1261 source "drivers/firmware/Kconfig"
1262
1263 source "fs/Kconfig"
1264
1265 source "arch/blackfin/Kconfig.debug"
1266
1267 source "security/Kconfig"
1268
1269 source "crypto/Kconfig"
1270
1271 source "lib/Kconfig"